diff options
Diffstat (limited to 'cpu/mpc824x')
| -rw-r--r-- | cpu/mpc824x/cpu.c | 12 | ||||
| -rw-r--r-- | cpu/mpc824x/cpu_init.c | 234 | ||||
| -rw-r--r-- | cpu/mpc824x/drivers/epic/epic1.c | 4 | ||||
| -rw-r--r-- | cpu/mpc824x/drivers/i2c/i2c.c | 4 | ||||
| -rw-r--r-- | cpu/mpc824x/interrupts.c | 4 | ||||
| -rw-r--r-- | cpu/mpc824x/start.S | 90 |
6 files changed, 174 insertions, 174 deletions
diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c index 0a45cc8..08f6a94 100644 --- a/cpu/mpc824x/cpu.c +++ b/cpu/mpc824x/cpu.c @@ -109,17 +109,17 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Trying to execute the next instruction at a non-existing address * should cause a machine check, resulting in reset */ -#ifdef CFG_RESET_ADDRESS - addr = CFG_RESET_ADDRESS; +#ifdef CONFIG_SYS_RESET_ADDRESS + addr = CONFIG_SYS_RESET_ADDRESS; #else /* - * note: when CFG_MONITOR_BASE points to a RAM address, - * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid + * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, + * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid * address. Better pick an address known to be invalid on - * your system and assign it to CFG_RESET_ADDRESS. + * your system and assign it to CONFIG_SYS_RESET_ADDRESS. * "(ulong)-1" used to be a good choice for many systems... */ - addr = CFG_MONITOR_BASE - sizeof (ulong); + addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); #endif ((void (*)(void)) addr) (); return 1; diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c index 7871031..395f776 100644 --- a/cpu/mpc824x/cpu_init.c +++ b/cpu/mpc824x/cpu_init.c @@ -25,32 +25,32 @@ #include <asm/processor.h> #include <mpc824x.h> -#ifndef CFG_BANK0_ROW -#define CFG_BANK0_ROW 0 +#ifndef CONFIG_SYS_BANK0_ROW +#define CONFIG_SYS_BANK0_ROW 0 #endif -#ifndef CFG_BANK1_ROW -#define CFG_BANK1_ROW 0 +#ifndef CONFIG_SYS_BANK1_ROW +#define CONFIG_SYS_BANK1_ROW 0 #endif -#ifndef CFG_BANK2_ROW -#define CFG_BANK2_ROW 0 +#ifndef CONFIG_SYS_BANK2_ROW +#define CONFIG_SYS_BANK2_ROW 0 #endif -#ifndef CFG_BANK3_ROW -#define CFG_BANK3_ROW 0 +#ifndef CONFIG_SYS_BANK3_ROW +#define CONFIG_SYS_BANK3_ROW 0 #endif -#ifndef CFG_BANK4_ROW -#define CFG_BANK4_ROW 0 +#ifndef CONFIG_SYS_BANK4_ROW +#define CONFIG_SYS_BANK4_ROW 0 #endif -#ifndef CFG_BANK5_ROW -#define CFG_BANK5_ROW 0 +#ifndef CONFIG_SYS_BANK5_ROW +#define CONFIG_SYS_BANK5_ROW 0 #endif -#ifndef CFG_BANK6_ROW -#define CFG_BANK6_ROW 0 +#ifndef CONFIG_SYS_BANK6_ROW +#define CONFIG_SYS_BANK6_ROW 0 #endif -#ifndef CFG_BANK7_ROW -#define CFG_BANK7_ROW 0 +#ifndef CONFIG_SYS_BANK7_ROW +#define CONFIG_SYS_BANK7_ROW 0 #endif -#ifndef CFG_DBUS_SIZE2 -#define CFG_DBUS_SIZE2 0 +#ifndef CONFIG_SYS_DBUS_SIZE2 +#define CONFIG_SYS_DBUS_SIZE2 0 #endif /* @@ -163,150 +163,150 @@ cpu_init_f (void) #endif CONFIG_WRITE_WORD(PICR2, val); - CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR); -#ifndef CFG_RAMBOOT - CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | - (CFG_BANK0_ROW) | - (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | - (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | - (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | - (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | - (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | - (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | - (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | - (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)); + CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); +#ifndef CONFIG_SYS_RAMBOOT + CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | + (CONFIG_SYS_BANK0_ROW) | + (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) | + (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) | + (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) | + (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) | + (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) | + (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) | + (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) | + (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)); #endif -#if defined(CFG_ASRISE) && defined(CFG_ASFALL) - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT | - CFG_ASRISE << MCCR2_ASRISE_SHIFT | - CFG_ASFALL << MCCR2_ASFALL_SHIFT); +#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL) + CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT | + CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT | + CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT); #else - CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT); + CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT); #endif #if defined(CONFIG_MPC8240) CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT) | - (CFG_RDLAT << MCCR3_RDLAT_SHIFT)); + (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | + (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)); #elif defined(CONFIG_MPC8245) CONFIG_WRITE_WORD(MCCR3, - (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | - (CFG_REFREC << MCCR3_REFREC_SHIFT)); + (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) | + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT)); #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif /* this is gross. We think these should all be the same, and various boards - * should define CFG_ACTORW to 0 if they don't want to set it, or even, if + * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if * its not set, we define it to zero in this file */ #if defined(CONFIG_CU824) || defined(CONFIG_PN62) CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | - CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | - (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) | - (((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); + (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | + (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | + CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | + (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) | + (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT)); #elif defined(CONFIG_MPC8240) CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | MCCR4_BIT21 | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | - (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) | - (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); + (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | + (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | + (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) | + (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); #elif defined(CONFIG_MPC8245) CONFIG_READ_WORD(MCCR1, val); val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */ CONFIG_WRITE_WORD(MCCR4, - (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | - (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | - (CFG_EXTROM ? MCCR4_EXTROM : 0) | - (CFG_REGDIMM ? MCCR4_REGDIMM : 0) | - (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | - ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | - (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) | - (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) | + (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | + (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | + (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) | + (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) | + (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) | + ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) | + (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) | + (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) | (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) | - (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) | - (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); + (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) | + (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT )); #else #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) #endif CONFIG_WRITE_WORD(MSAR1, - ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR1, - ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MSAR2, - ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMSAR2, - ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR1, - ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR1, - ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(MEAR2, - ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); + ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) | + (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)); CONFIG_WRITE_WORD(EMEAR2, - ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); - - CONFIG_WRITE_BYTE(ODCR, CFG_ODCR); -#ifdef CFG_DLL_MAX_DELAY - CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */ + ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) | + (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | + (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | + (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)); + + CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR); +#ifdef CONFIG_SYS_DLL_MAX_DELAY + CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */ #endif -#if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL) - CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL); +#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL) + CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL); #endif -#if defined(MIOCR2) && defined(CFG_SDRAM_DSCD) - CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */ +#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD) + CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */ #endif /* setup & hold time */ CONFIG_WRITE_BYTE(MBER, - CFG_BANK0_ENABLE | - (CFG_BANK1_ENABLE << 1) | - (CFG_BANK2_ENABLE << 2) | - (CFG_BANK3_ENABLE << 3) | - (CFG_BANK4_ENABLE << 4) | - (CFG_BANK5_ENABLE << 5) | - (CFG_BANK6_ENABLE << 6) | - (CFG_BANK7_ENABLE << 7)); - -#ifdef CFG_PGMAX - CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX); + CONFIG_SYS_BANK0_ENABLE | + (CONFIG_SYS_BANK1_ENABLE << 1) | + (CONFIG_SYS_BANK2_ENABLE << 2) | + (CONFIG_SYS_BANK3_ENABLE << 3) | + (CONFIG_SYS_BANK4_ENABLE << 4) | + (CONFIG_SYS_BANK5_ENABLE << 5) | + (CONFIG_SYS_BANK6_ENABLE << 6) | + (CONFIG_SYS_BANK7_ENABLE << 7)); + +#ifdef CONFIG_SYS_PGMAX + CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX); #endif /* ! Wait 200us before initialize other registers */ diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c index f89deed..ecbb42d 100644 --- a/cpu/mpc824x/drivers/epic/epic1.c +++ b/cpu/mpc824x/drivers/epic/epic1.c @@ -311,7 +311,7 @@ ULONG sysEUMBBARRead { ULONG temp; - temp = *(ULONG *) (CFG_EUMB_ADDR + regNum); + temp = *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum); return ( LONGSWAP(temp)); } @@ -331,7 +331,7 @@ void sysEUMBBARWrite ) { - *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal); + *(ULONG *) (CONFIG_SYS_EUMB_ADDR + regNum) = LONGSWAP(regVal); return ; } diff --git a/cpu/mpc824x/drivers/i2c/i2c.c b/cpu/mpc824x/drivers/i2c/i2c.c index 3add687..854345e 100644 --- a/cpu/mpc824x/drivers/i2c/i2c.c +++ b/cpu/mpc824x/drivers/i2c/i2c.c @@ -31,9 +31,9 @@ #ifdef CONFIG_HARD_I2C #include <i2c.h> -#define TIMEOUT (CFG_HZ/4) +#define TIMEOUT (CONFIG_SYS_HZ/4) -#define I2C_Addr ((unsigned *)(CFG_EUMB_ADDR + 0x3000)) +#define I2C_Addr ((unsigned *)(CONFIG_SYS_EUMB_ADDR + 0x3000)) #define I2CADR &I2C_Addr[0] #define I2CFDR &I2C_Addr[1] diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c index 4359ecc..139c52c 100644 --- a/cpu/mpc824x/interrupts.c +++ b/cpu/mpc824x/interrupts.c @@ -31,7 +31,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) { - *decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ; + *decrementer_count = (get_bus_freq (0) / 4) / CONFIG_SYS_HZ; /* * It's all broken at the moment and I currently don't need @@ -57,7 +57,7 @@ void external_interrupt (struct pt_regs *regs) { register unsigned long temp; - pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); + pci_readl (CONFIG_SYS_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp); sync (); /* i'm not convinced this is needed, but dink source has it */ temp &= 0xff; /*get vector */ diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 784edc3..b5d7eb1 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -157,8 +157,8 @@ in_flash: /* Allocate Initial RAM in data cache. */ - lis r3, CFG_INIT_RAM_ADDR@h - ori r3, r3, CFG_INIT_RAM_ADDR@l + lis r3, CONFIG_SYS_INIT_RAM_ADDR@h + ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l li r2, 128 mtctr r2 1: @@ -180,8 +180,8 @@ in_flash: * Thisk the stack pointer *somewhere* sensible. Doesnt * matter much where as we'll move it when we relocate */ - lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h - ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -475,21 +475,21 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ -#ifdef CFG_RAMBOOT - lis r4, CFG_SDRAM_BASE@h /* Source Address */ - ori r4, r4, CFG_SDRAM_BASE@l +#ifdef CONFIG_SYS_RAMBOOT + lis r4, CONFIG_SYS_SDRAM_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_SDRAM_BASE@l #else - lis r4, CFG_MONITOR_BASE@h /* Source Address */ - ori r4, r4, CFG_MONITOR_BASE@l + lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CONFIG_SYS_MONITOR_BASE@l #endif lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ /* * Fix GOT pointer: * - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address + * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address * * Offset: */ @@ -531,8 +531,8 @@ relocate_code: /* Unlock the data cache and invalidate locked area */ xor r0, r0, r0 mtspr 1011, r0 - lis r4, CFG_INIT_RAM_ADDR@h - ori r4, r4, CFG_INIT_RAM_ADDR@l + lis r4, CONFIG_SYS_INIT_RAM_ADDR@h + ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l li r0, 128 mtctr r0 41: @@ -709,66 +709,66 @@ trap_reloc: /* Setup the BAT registers. */ setup_bats: - lis r4, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - lis r3, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l + lis r4, CONFIG_SYS_IBAT0L@h + ori r4, r4, CONFIG_SYS_IBAT0L@l + lis r3, CONFIG_SYS_IBAT0U@h + ori r3, r3, CONFIG_SYS_IBAT0U@l mtspr IBAT0L, r4 mtspr IBAT0U, r3 isync - lis r4, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - lis r3, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l + lis r4, CONFIG_SYS_DBAT0L@h + ori r4, r4, CONFIG_SYS_DBAT0L@l + lis r3, CONFIG_SYS_DBAT0U@h + ori r3, r3, CONFIG_SYS_DBAT0U@l mtspr DBAT0L, r4 mtspr DBAT0U, r3 isync - lis r4, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - lis r3, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l + lis r4, CONFIG_SYS_IBAT1L@h + ori r4, r4, CONFIG_SYS_IBAT1L@l + lis r3, CONFIG_SYS_IBAT1U@h + ori r3, r3, CONFIG_SYS_IBAT1U@l mtspr IBAT1L, r4 mtspr IBAT1U, r3 isync - lis r4, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - lis r3, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l + lis r4, CONFIG_SYS_DBAT1L@h + ori r4, r4, CONFIG_SYS_DBAT1L@l + lis r3, CONFIG_SYS_DBAT1U@h + ori r3, r3, CONFIG_SYS_DBAT1U@l mtspr DBAT1L, r4 mtspr DBAT1U, r3 isync - lis r4, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - lis r3, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l + lis r4, CONFIG_SYS_IBAT2L@h + ori r4, r4, CONFIG_SYS_IBAT2L@l + lis r3, CONFIG_SYS_IBAT2U@h + ori r3, r3, CONFIG_SYS_IBAT2U@l mtspr IBAT2L, r4 mtspr IBAT2U, r3 isync - lis r4, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - lis r3, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l + lis r4, CONFIG_SYS_DBAT2L@h + ori r4, r4, CONFIG_SYS_DBAT2L@l + lis r3, CONFIG_SYS_DBAT2U@h + ori r3, r3, CONFIG_SYS_DBAT2U@l mtspr DBAT2L, r4 mtspr DBAT2U, r3 isync - lis r4, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - lis r3, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l + lis r4, CONFIG_SYS_IBAT3L@h + ori r4, r4, CONFIG_SYS_IBAT3L@l + lis r3, CONFIG_SYS_IBAT3U@h + ori r3, r3, CONFIG_SYS_IBAT3U@l mtspr IBAT3L, r4 mtspr IBAT3U, r3 isync - lis r4, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - lis r3, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l + lis r4, CONFIG_SYS_DBAT3L@h + ori r4, r4, CONFIG_SYS_DBAT3L@l + lis r3, CONFIG_SYS_DBAT3U@h + ori r3, r3, CONFIG_SYS_DBAT3U@l mtspr DBAT3L, r4 mtspr DBAT3U, r3 isync |