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Diffstat (limited to 'cpu/mpc8220')
-rw-r--r--cpu/mpc8220/cpu.c2
-rw-r--r--cpu/mpc8220/cpu_init.c64
-rw-r--r--cpu/mpc8220/dramSetup.c14
-rw-r--r--cpu/mpc8220/interrupts.c2
-rw-r--r--cpu/mpc8220/pci.c4
-rw-r--r--cpu/mpc8220/speed.c14
-rw-r--r--cpu/mpc8220/start.S34
7 files changed, 67 insertions, 67 deletions
diff --git a/cpu/mpc8220/cpu.c b/cpu/mpc8220/cpu.c
index be274cd..5b3fdd3 100644
--- a/cpu/mpc8220/cpu.c
+++ b/cpu/mpc8220/cpu.c
@@ -42,7 +42,7 @@ int checkcpu (void)
printf (CPU_ID_STR);
- printf (" (JTAG ID %08lx)", *(vu_long *) (CFG_MBAR + 0x50));
+ printf (" (JTAG ID %08lx)", *(vu_long *) (CONFIG_SYS_MBAR + 0x50));
printf (" at %s MHz\n", strmhz (buf, clock));
diff --git a/cpu/mpc8220/cpu_init.c b/cpu/mpc8220/cpu_init.c
index 0daac5b..8f52c7d 100644
--- a/cpu/mpc8220/cpu_init.c
+++ b/cpu/mpc8220/cpu_init.c
@@ -39,7 +39,7 @@ void cpu_init_f (void)
volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
/* Pointer is writable since we allocated a register for it */
- gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+ gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
@@ -49,54 +49,54 @@ void cpu_init_f (void)
portcfg->pcfg1 = 0;
portcfg->pcfg2 = 0;
portcfg->pcfg3 = 0;
- portcfg->pcfg2 = CFG_GP1_PORT2_CONFIG;
- portcfg->pcfg3 = CFG_PCI_PORT3_CONFIG | CFG_GP2_PORT3_CONFIG;
+ portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG;
+ portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG;
/*
* Flexbus Controller: configure chip selects and enable them
*/
-#if defined (CFG_CS0_BASE)
- flexbus->csar0 = CFG_CS0_BASE;
+#if defined (CONFIG_SYS_CS0_BASE)
+ flexbus->csar0 = CONFIG_SYS_CS0_BASE;
/* Sorcery-C can hang-up after CTRL reg initialization */
-#if defined (CFG_CS0_CTRL)
- flexbus->cscr0 = CFG_CS0_CTRL;
+#if defined (CONFIG_SYS_CS0_CTRL)
+ flexbus->cscr0 = CONFIG_SYS_CS0_CTRL;
#endif
- flexbus->csmr0 = ((CFG_CS0_MASK - 1) & 0xffff0000) | 1;
+ flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS1_BASE)
- flexbus->csar1 = CFG_CS1_BASE;
- flexbus->cscr1 = CFG_CS1_CTRL;
- flexbus->csmr1 = ((CFG_CS1_MASK - 1) & 0xffff0000) | 1;
+#if defined (CONFIG_SYS_CS1_BASE)
+ flexbus->csar1 = CONFIG_SYS_CS1_BASE;
+ flexbus->cscr1 = CONFIG_SYS_CS1_CTRL;
+ flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS2_BASE)
- flexbus->csar2 = CFG_CS2_BASE;
- flexbus->cscr2 = CFG_CS2_CTRL;
- flexbus->csmr2 = ((CFG_CS2_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS2_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS2_BASE)
+ flexbus->csar2 = CONFIG_SYS_CS2_BASE;
+ flexbus->cscr2 = CONFIG_SYS_CS2_CTRL;
+ flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS3_BASE)
- flexbus->csar3 = CFG_CS3_BASE;
- flexbus->cscr3 = CFG_CS3_CTRL;
- flexbus->csmr3 = ((CFG_CS3_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS3_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS3_BASE)
+ flexbus->csar3 = CONFIG_SYS_CS3_BASE;
+ flexbus->cscr3 = CONFIG_SYS_CS3_CTRL;
+ flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS4_BASE)
- flexbus->csar4 = CFG_CS4_BASE;
- flexbus->cscr4 = CFG_CS4_CTRL;
- flexbus->csmr4 = ((CFG_CS4_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS4_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS4_BASE)
+ flexbus->csar4 = CONFIG_SYS_CS4_BASE;
+ flexbus->cscr4 = CONFIG_SYS_CS4_CTRL;
+ flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
-#if defined (CFG_CS5_BASE)
- flexbus->csar5 = CFG_CS5_BASE;
- flexbus->cscr5 = CFG_CS5_CTRL;
- flexbus->csmr5 = ((CFG_CS5_MASK - 1) & 0xffff0000) | 1;
- portcfg->pcfg3 |= CFG_CS5_PORT3_CONFIG;
+#if defined (CONFIG_SYS_CS5_BASE)
+ flexbus->csar5 = CONFIG_SYS_CS5_BASE;
+ flexbus->cscr5 = CONFIG_SYS_CS5_CTRL;
+ flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1;
+ portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG;
__asm__ volatile ("sync");
#endif
diff --git a/cpu/mpc8220/dramSetup.c b/cpu/mpc8220/dramSetup.c
index 08e3172..52cf133 100644
--- a/cpu/mpc8220/dramSetup.c
+++ b/cpu/mpc8220/dramSetup.c
@@ -34,9 +34,9 @@ characteristics to initialize the dram on MPC8220
DECLARE_GLOBAL_DATA_PTR;
-#define SPD_SIZE CFG_SDRAM_SPD_SIZE
-#define DRAM_SPD (CFG_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
-#define TOTAL_BANK CFG_SDRAM_TOTAL_BANKS
+#define SPD_SIZE CONFIG_SYS_SDRAM_SPD_SIZE
+#define DRAM_SPD (CONFIG_SYS_SDRAM_SPD_I2C_ADDR)<<1 /* on Board SPD eeprom */
+#define TOTAL_BANK CONFIG_SYS_SDRAM_TOTAL_BANKS
int spd_status (volatile i2c8220_t * pi2c, u8 sta_bit, u8 truefalse)
{
@@ -103,7 +103,7 @@ int readSpdData (u8 * spdData)
/* Enable Port Configuration for SDA and SDL signals */
pcfg = (volatile pcfg8220_t *) (MMAP_PCFG);
__asm__ ("sync");
- pcfg->pcfg3 &= ~CFG_I2C_PORT3_CONFIG;
+ pcfg->pcfg3 &= ~CONFIG_SYS_I2C_PORT3_CONFIG;
__asm__ ("sync");
/* Points the structure to I2c mbar memory offset */
@@ -144,7 +144,7 @@ int readSpdData (u8 * spdData)
break;
}
- pi2cReg->adr = CFG_I2C_SLAVE<<1;
+ pi2cReg->adr = CONFIG_SYS_I2C_SLAVE<<1;
pi2cReg->cr = I2C_CTL_EN; /* Set Enable */
@@ -541,7 +541,7 @@ u32 dramSetup (void)
}
/* Set up the Drive Strength register */
- sysconf->sdramds = CFG_SDRAM_DRIVE_STRENGTH;
+ sysconf->sdramds = CONFIG_SYS_SDRAM_DRIVE_STRENGTH;
/* ********************** Cfg 1 ************************* */
@@ -679,7 +679,7 @@ u32 dramSetup (void)
/* Set up mode value for CAS latency */
-#if (CFG_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
+#if (CONFIG_SYS_SDRAM_CAS_LATENCY==5) /* CL=2.5 */
mode_value = (MODE_MODE | MODE_BURSTLEN (MODE_BURSTLEN_8) |
MODE_BT_SEQUENTIAL | MODE_CL (MODE_CL_2p5) | MODE_CMD);
#else
diff --git a/cpu/mpc8220/interrupts.c b/cpu/mpc8220/interrupts.c
index 036378c..78e9917 100644
--- a/cpu/mpc8220/interrupts.c
+++ b/cpu/mpc8220/interrupts.c
@@ -34,7 +34,7 @@
int interrupt_init_cpu (ulong * decrementer_count)
{
- *decrementer_count = get_tbclk () / CFG_HZ;
+ *decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
return (0);
}
diff --git a/cpu/mpc8220/pci.c b/cpu/mpc8220/pci.c
index 4ef214e..a78a828 100644
--- a/cpu/mpc8220/pci.c
+++ b/cpu/mpc8220/pci.c
@@ -33,8 +33,8 @@
#if defined(CONFIG_PCI)
/* System RAM mapped over PCI */
-#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define cfg_read(val, addr, type, op) *val = op((type)(addr));
diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c
index 200a762..c01ca0c 100644
--- a/cpu/mpc8220/speed.c
+++ b/cpu/mpc8220/speed.c
@@ -67,25 +67,25 @@ int get_clocks (void)
u32 hid1;
int i, size, pci2bus;
-#if !defined(CFG_MPC8220_CLKIN)
-#error clock measuring not implemented yet - define CFG_MPC8220_CLKIN
+#if !defined(CONFIG_SYS_MPC8220_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
#endif
- gd->inp_clk = CFG_MPC8220_CLKIN;
+ gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
/* Read XLB to PCI(INP) clock multiplier */
pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;
/* XLB bus clock */
- gd->bus_clk = CFG_MPC8220_CLKIN * pci2bus;
+ gd->bus_clk = CONFIG_SYS_MPC8220_CLKIN * pci2bus;
/* PCI clock is same as input clock */
- gd->pci_clk = CFG_MPC8220_CLKIN;
+ gd->pci_clk = CONFIG_SYS_MPC8220_CLKIN;
/* FlexBus is temporary set as the same as input clock */
/* will do dynamic in the future */
- gd->flb_clk = CFG_MPC8220_CLKIN;
+ gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
/* CPU Clock - Read HID1 */
asm volatile ("mfspr %0, 1009":"=r" (hid1):);
@@ -97,7 +97,7 @@ int get_clocks (void)
for (i = 0; i < size; i++)
if (hid1 == bus2core[i].hid1) {
gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
- gd->vco_clk = CFG_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+ gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
break;
}
diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S
index b5145ca..373be2c 100644
--- a/cpu/mpc8220/start.S
+++ b/cpu/mpc8220/start.S
@@ -105,16 +105,16 @@ boot_warm:
/* replace default MBAR base address from 0x80000000
to 0xf0000000 */
-#if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
- lis r3, CFG_MBAR@h
- ori r3, r3, CFG_MBAR@l
+#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
+ lis r3, CONFIG_SYS_MBAR@h
+ ori r3, r3, CONFIG_SYS_MBAR@l
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
mtspr SPRN_SPRG7W,r3
- lis r4, CFG_DEFAULT_MBAR@h
+ lis r4, CONFIG_SYS_DEFAULT_MBAR@h
stw r3, 0(r4)
-#endif /* CFG_DEFAULT_MBAR */
+#endif /* CONFIG_SYS_DEFAULT_MBAR */
/* Initialise the MPC8220 processor core */
/*--------------------------------------------------------------*/
@@ -125,9 +125,9 @@ boot_warm:
/*--------------------------------------------------------------*/
/* set up stack in on-chip SRAM */
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- ori r1, r3, CFG_INIT_SP_OFFSET
+ lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
+ ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
+ ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
li r0, 0 /* Make room for stack frame header and */
stwu r0, -4(r1) /* clear final stack frame so that */
@@ -361,13 +361,13 @@ init_8220_core:
/* HID0 also contains cache control */
/*--------------------------------------------------------------*/
- lis r3, CFG_HID0_INIT@h
- ori r3, r3, CFG_HID0_INIT@l
+ lis r3, CONFIG_SYS_HID0_INIT@h
+ ori r3, r3, CONFIG_SYS_HID0_INIT@l
SYNC
mtspr HID0, r3
- lis r3, CFG_HID0_FINAL@h
- ori r3, r3, CFG_HID0_FINAL@l
+ lis r3, CONFIG_SYS_HID0_FINAL@h
+ ori r3, r3, CONFIG_SYS_HID0_FINAL@l
SYNC
mtspr HID0, r3
@@ -458,7 +458,7 @@ init_8220_core:
.globl icache_enable
icache_enable:
lis r4, 0
- ori r4, r4, CFG_HID0_INIT /* set ICE & ICFI bit */
+ ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
/*
@@ -547,16 +547,16 @@ relocate_code:
mr r10, r5 /* Save copy of Destination Address */
mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
lwz r5, GOT(__init_end)
sub r5, r5, r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
*
- * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
*
* Offset:
*/
generated by cgit v1.1 at 2024-11-14 07:59:37 +0000