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-rw-r--r--cpu/mcf52x2/cpu.c18
-rw-r--r--cpu/mcf52x2/cpu_init.c493
-rw-r--r--cpu/mcf52x2/interrupts.c14
-rw-r--r--cpu/mcf52x2/speed.c12
-rw-r--r--cpu/mcf52x2/start.S79
5 files changed, 291 insertions, 325 deletions
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 2af31cb..32d6c40 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -32,6 +32,7 @@
#include <watchdog.h>
#include <command.h>
#include <asm/immap.h>
+#include <netdev.h>
#ifdef CONFIG_M5271
/*
@@ -65,11 +66,11 @@ int checkcpu(void)
if (cpu_model)
printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
- cpu_model, prn, strmhz(buf, CFG_CLK));
+ cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
else
printf("CPU: Unknown - Freescale ColdFire MCF5271 family"
" (PIN: 0x%x) rev. %hu, at %s MHz\n",
- pin, prn, strmhz(buf, CFG_CLK));
+ pin, prn, strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -173,7 +174,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wdog_wrrr =
- ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wdog_wcr = 0; /* reset watchdog counter */
puts("WATCHDOG:enabled\n");
@@ -201,7 +202,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5275 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
return 0;
};
@@ -235,7 +236,7 @@ int watchdog_init(void)
/* set timeout and enable watchdog */
wdt->wmr =
- ((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+ ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
wdt->wsr = 0x5555; /* reset watchdog counter */
wdt->wsr = 0xAAAA;
@@ -277,7 +278,7 @@ int checkcpu(void)
char buf[32];
printf("CPU: Freescale Coldfire MCF5249 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
return 0;
}
@@ -299,7 +300,7 @@ int checkcpu(void)
unsigned char resetsource = mbar_readLong(SIM_RSR);
printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n",
- strmhz(buf, CFG_CLK));
+ strmhz(buf, CONFIG_SYS_CLK));
if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
printf("Reset:%s%s\n",
@@ -328,11 +329,8 @@ int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
* int board_eth_init(bd_t *bis)
*/
-extern int mcffec_initialize(bd_t*);
-
int cpu_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
}
#endif
-
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 68aefe9..66f9164 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -36,6 +36,71 @@
#include <watchdog.h>
#include <asm/immap.h>
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
+#ifndef CONFIG_M5272
+/* Only 5272 Flexbus chipselect is different from the rest */
+void init_fbcs(void)
+{
+ volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+ && defined(CONFIG_SYS_CS0_CTRL))
+ fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+ fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+ fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+#else
+#warning "Chip Select 0 are not initialized/used"
+#endif
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+ && defined(CONFIG_SYS_CS1_CTRL))
+ fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+ fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+ fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+ && defined(CONFIG_SYS_CS2_CTRL))
+ fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+ fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+ fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+ && defined(CONFIG_SYS_CS3_CTRL))
+ fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+ fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+ fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+ && defined(CONFIG_SYS_CS4_CTRL))
+ fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+ fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+ fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+ && defined(CONFIG_SYS_CS5_CTRL))
+ fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+ fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+ fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
+ && defined(CONFIG_SYS_CS6_CTRL))
+ fbcs->csar6 = CONFIG_SYS_CS6_BASE;
+ fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
+ fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+#endif
+#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
+ && defined(CONFIG_SYS_CS7_CTRL))
+ fbcs->csar7 = CONFIG_SYS_CS7_BASE;
+ fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
+ fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+#endif
+}
+#endif
+
#if defined(CONFIG_M5253)
/*
* Breath some life into the CPU...
@@ -68,24 +133,16 @@ void cpu_init_f(void)
/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
- /*
- * Setup chip selects...
- */
-
- mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
- mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
- mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
-
- mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
- mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
- mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+ /* FlexBus Chipselect */
+ init_fbcs();
#ifdef CONFIG_FSL_I2C
- CFG_I2C_PINMUX_REG = CFG_I2C_PINMUX_REG & CFG_I2C_PINMUX_CLR;
- CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
-#ifdef CFG_I2C2_OFFSET
- CFG_I2C2_PINMUX_REG &= CFG_I2C2_PINMUX_CLR;
- CFG_I2C2_PINMUX_REG |= CFG_I2C2_PINMUX_SET;
+ CONFIG_SYS_I2C_PINMUX_REG =
+ CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
+#ifdef CONFIG_SYS_I2C2_OFFSET
+ CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
+ CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
#endif
#endif
@@ -102,7 +159,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:
@@ -121,6 +178,9 @@ void cpu_init_f(void)
mbar_writeShort(MCF_WTM_WCR, 0);
#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
+
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
@@ -138,7 +198,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
MCF_GPIO_PAR_UART_U0RXD);
@@ -153,6 +213,19 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ /* Enable Ethernet pins */
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+ } else {
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5272)
@@ -169,59 +242,59 @@ void cpu_init_f(void)
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- sysctrl->sc_scr = CFG_SCR;
- sysctrl->sc_spr = CFG_SPR;
+ sysctrl->sc_scr = CONFIG_SYS_SCR;
+ sysctrl->sc_spr = CONFIG_SYS_SPR;
/* Setup Ports: */
- gpio->gpio_pacnt = CFG_PACNT;
- gpio->gpio_paddr = CFG_PADDR;
- gpio->gpio_padat = CFG_PADAT;
- gpio->gpio_pbcnt = CFG_PBCNT;
- gpio->gpio_pbddr = CFG_PBDDR;
- gpio->gpio_pbdat = CFG_PBDAT;
- gpio->gpio_pdcnt = CFG_PDCNT;
+ gpio->gpio_pacnt = CONFIG_SYS_PACNT;
+ gpio->gpio_paddr = CONFIG_SYS_PADDR;
+ gpio->gpio_padat = CONFIG_SYS_PADAT;
+ gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
+ gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
+ gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
+ gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
/* Memory Controller: */
- csctrl->cs_br0 = CFG_BR0_PRELIM;
- csctrl->cs_or0 = CFG_OR0_PRELIM;
+ csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
+ csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
-#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- csctrl->cs_br1 = CFG_BR1_PRELIM;
- csctrl->cs_or1 = CFG_OR1_PRELIM;
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+ csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
+ csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
#endif
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- csctrl->cs_br2 = CFG_BR2_PRELIM;
- csctrl->cs_or2 = CFG_OR2_PRELIM;
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+ csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
+ csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
#endif
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- csctrl->cs_br3 = CFG_BR3_PRELIM;
- csctrl->cs_or3 = CFG_OR3_PRELIM;
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+ csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
+ csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
#endif
-#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- csctrl->cs_br4 = CFG_BR4_PRELIM;
- csctrl->cs_or4 = CFG_OR4_PRELIM;
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+ csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
+ csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
#endif
-#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- csctrl->cs_br5 = CFG_BR5_PRELIM;
- csctrl->cs_or5 = CFG_OR5_PRELIM;
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+ csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
+ csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
#endif
-#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- csctrl->cs_br6 = CFG_BR6_PRELIM;
- csctrl->cs_or6 = CFG_OR6_PRELIM;
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+ csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
+ csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
#endif
-#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- csctrl->cs_br7 = CFG_BR7_PRELIM;
- csctrl->cs_or7 = CFG_OR7_PRELIM;
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+ csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
+ csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
#endif
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -244,7 +317,7 @@ void uart_port_conf(void)
volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
@@ -255,6 +328,22 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ if (setclear) {
+ gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+ GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+ GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+ GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+ } else {
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5272) */
#if defined(CONFIG_M5275)
@@ -268,71 +357,25 @@ void uart_port_conf(void)
*/
void cpu_init_f(void)
{
- /* if we come from RAM we assume the CPU is
+ /*
+ * if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
- volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
- volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+ volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+ volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
/* Kill watchdog so we can initialize the PLL */
wdog_reg->wcr = 0;
- /* Memory Controller: */
- /* Flash */
- csctrl_reg->ar0 = CFG_AR0_PRELIM;
- csctrl_reg->cr0 = CFG_CR0_PRELIM;
- csctrl_reg->mr0 = CFG_MR0_PRELIM;
-
-#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
- csctrl_reg->ar1 = CFG_AR1_PRELIM;
- csctrl_reg->cr1 = CFG_CR1_PRELIM;
- csctrl_reg->mr1 = CFG_MR1_PRELIM;
-#endif
-
-#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
- csctrl_reg->ar2 = CFG_AR2_PRELIM;
- csctrl_reg->cr2 = CFG_CR2_PRELIM;
- csctrl_reg->mr2 = CFG_MR2_PRELIM;
-#endif
-
-#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
- csctrl_reg->ar3 = CFG_AR3_PRELIM;
- csctrl_reg->cr3 = CFG_CR3_PRELIM;
- csctrl_reg->mr3 = CFG_MR3_PRELIM;
-#endif
-
-#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
- csctrl_reg->ar4 = CFG_AR4_PRELIM;
- csctrl_reg->cr4 = CFG_CR4_PRELIM;
- csctrl_reg->mr4 = CFG_MR4_PRELIM;
-#endif
-
-#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
- csctrl_reg->ar5 = CFG_AR5_PRELIM;
- csctrl_reg->cr5 = CFG_CR5_PRELIM;
- csctrl_reg->mr5 = CFG_MR5_PRELIM;
-#endif
-
-#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
- csctrl_reg->ar6 = CFG_AR6_PRELIM;
- csctrl_reg->cr6 = CFG_CR6_PRELIM;
- csctrl_reg->mr6 = CFG_MR6_PRELIM;
-#endif
-
-#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
- csctrl_reg->ar7 = CFG_AR7_PRELIM;
- csctrl_reg->cr7 = CFG_CR7_PRELIM;
- csctrl_reg->mr7 = CFG_MR7_PRELIM;
-#endif
-
+ /* FlexBus Chipselect */
+ init_fbcs();
#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
#ifdef CONFIG_FSL_I2C
- CFG_I2C_PINMUX_REG &= CFG_I2C_PINMUX_CLR;
- CFG_I2C_PINMUX_REG |= CFG_I2C_PINMUX_SET;
+ CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
+ CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif
/* enable instruction cache now */
@@ -349,10 +392,10 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
- volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
gpio->par_uart |= UART0_ENABLE_MASK;
break;
@@ -364,6 +407,35 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ struct fec_info_s *info = (struct fec_info_s *) dev->priv;
+ volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+ if (setclear) {
+ /* Enable Ethernet pins */
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c |= 0x0F00;
+ gpio->par_fec0hl |= 0xC0;
+ } else {
+ gpio->par_feci2c |= 0x00A0;
+ gpio->par_fec1hl |= 0xC0;
+ }
+ } else {
+ if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
+ gpio->par_feci2c &= ~0x0F00;
+ gpio->par_fec0hl &= ~0xC0;
+ } else {
+ gpio->par_feci2c &= ~0x00A0;
+ gpio->par_fec1hl &= ~0xC0;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif /* #if defined(CONFIG_M5275) */
#if defined(CONFIG_M5282)
@@ -384,160 +456,50 @@ void cpu_init_f(void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
MCFCLOCK_SYNCR =
- MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
+ MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
-#ifdef CFG_PEPAR
- MCFGPIO_PEPAR = CFG_PEPAR;
-#endif
-#ifdef CFG_PFPAR
- MCFGPIO_PFPAR = CFG_PFPAR;
-#endif
-#ifdef CFG_PJPAR
- MCFGPIO_PJPAR = CFG_PJPAR;
+#ifdef CONFIG_SYS_PEPAR
+ MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
#endif
-#ifdef CFG_PSDPAR
- MCFGPIO_PSDPAR = CFG_PSDPAR;
+#ifdef CONFIG_SYS_PFPAR
+ MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
#endif
-#ifdef CFG_PASPAR
- MCFGPIO_PASPAR = CFG_PASPAR;
+#ifdef CONFIG_SYS_PJPAR
+ MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
#endif
-#ifdef CFG_PEHLPAR
- MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+#ifdef CONFIG_SYS_PSDPAR
+ MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
#endif
-#ifdef CFG_PQSPAR
- MCFGPIO_PQSPAR = CFG_PQSPAR;
+#ifdef CONFIG_SYS_PASPAR
+ MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
#endif
-#ifdef CFG_PTCPAR
- MCFGPIO_PTCPAR = CFG_PTCPAR;
+#ifdef CONFIG_SYS_PEHLPAR
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
#endif
-#ifdef CFG_PTDPAR
- MCFGPIO_PTDPAR = CFG_PTDPAR;
-#endif
-#ifdef CFG_PUAPAR
- MCFGPIO_PUAPAR = CFG_PUAPAR;
-#endif
-
-#ifdef CFG_DDRUA
- MCFGPIO_DDRUA = CFG_DDRUA;
-#endif
-
- /* This is probably a bad place to setup chip selects, but everyone
- else is doing it! */
-
-#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
- defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
-
- MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS0_WIDTH == 8)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS0_WIDTH == 16)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS0_WIDTH == 32)
-#define CFG_CS0_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+#ifdef CONFIG_SYS_PQSPAR
+ MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
#endif
- MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
- | CFG_CS0_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS0_RO != 0)
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
+#ifdef CONFIG_SYS_PTCPAR
+ MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
#endif
-#else
-#warning "Chip Select 0 are not initialized/used"
+#ifdef CONFIG_SYS_PTDPAR
+ MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
#endif
-
-#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
- defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
-
- MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS1_WIDTH == 8)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS1_WIDTH == 16)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS1_WIDTH == 32)
-#define CFG_CS1_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+#ifdef CONFIG_SYS_PUAPAR
+ MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
#endif
- MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
- | CFG_CS1_PS | MCFCSM_CSCR_AA;
-#if (CFG_CS1_RO != 0)
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 1 are not initialized/used"
+#ifdef CONFIG_SYS_DDRUA
+ MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
#endif
-#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
- defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
-
- MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS2_WIDTH == 8)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS2_WIDTH == 16)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS2_WIDTH == 32)
-#define CFG_CS2_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
-#endif
- MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
- | CFG_CS2_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS2_RO != 0)
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 2 are not initialized/used"
-#endif
-
-#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
- defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
-
- MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
-
-#if (CFG_CS3_WIDTH == 8)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_8
-#elif (CFG_CS3_WIDTH == 16)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_16
-#elif (CFG_CS3_WIDTH == 32)
-#define CFG_CS3_PS MCFCSM_CSCR_PS_32
-#else
-#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
-#endif
- MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
- | CFG_CS3_PS | MCFCSM_CSCR_AA;
-
-#if (CFG_CS3_RO != 0)
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
- | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
-#else
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
- | MCFCSM_CSMR_V;
-#endif
-#else
-#warning "Chip Select 3 are not initialized/used"
-#endif
+ /* FlexBus Chipselect */
+ init_fbcs();
#endif /* CONFIG_MONITOR_IS_IN_RAM */
@@ -556,7 +518,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
MCFGPIO_PUAPAR &= 0xFc;
MCFGPIO_PUAPAR |= 0x03;
@@ -571,6 +533,20 @@ void uart_port_conf(void)
break;
}
}
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+ if (setclear) {
+ MCFGPIO_PASPAR |= 0x0F00;
+ MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
+ } else {
+ MCFGPIO_PASPAR &= 0xF0FF;
+ MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
+ }
+ return 0;
+}
+#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_M5249)
@@ -589,12 +565,12 @@ void cpu_init_f(void)
* which is their primary function.
* ~Jeremy
*/
- mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
- mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
- mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
- mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
- mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
- mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
+ mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
+ mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
+ mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
+ mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
+ mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
/*
* dBug Compliance:
@@ -632,17 +608,8 @@ void cpu_init_f(void)
mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
- /*
- * Setup chip selects...
- */
-
- mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
- mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
- mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
-
- mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
- mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
- mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+ /* FlexBus Chipselect */
+ init_fbcs();
/* enable instruction cache now */
icache_enable();
@@ -659,7 +626,7 @@ int cpu_init_r(void)
void uart_port_conf(void)
{
/* Setup Ports: */
- switch (CFG_UART_PORT) {
+ switch (CONFIG_SYS_UART_PORT) {
case 0:
break;
case 1:
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index b8fb7bb..0181e4b 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -51,10 +51,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile intctrl_t *intp = (intctrl_t *) (CFG_INTR_BASE);
+ volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
- intp->int_icr1 |= CFG_TMRINTR_PRI;
+ intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5272 */
@@ -62,7 +62,7 @@ void dtimer_intr_setup(void)
#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
intp->imrl0 |= 0x1;
@@ -74,11 +74,11 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+ volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
+ intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
intp->imrl0 &= 0xFFFFFFFE;
- intp->imrl0 &= ~CFG_TMRINTR_MASK;
+ intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -95,7 +95,7 @@ int interrupt_init(void)
void dtimer_intr_setup(void)
{
mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
- mbar_writeByte(MCFSIM_TIMER2ICR, CFG_TMRINTR_PRI);
+ mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
}
#endif /* CONFIG_MCFTMR */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index 4cb8f93..fe51fb4 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -39,11 +39,11 @@ int get_clocks (void)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
-#ifndef CFG_PLL_BYPASS
+#ifndef CONFIG_SYS_PLL_BYPASS
#ifdef CONFIG_M5249
/* Setup the PLL to run at the specified speed */
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
@@ -51,7 +51,7 @@ int get_clocks (void)
#endif /* CONFIG_M5249 */
#ifdef CONFIG_M5253
- pllcr = CFG_PLLCR;
+ pllcr = CONFIG_SYS_PLLCR;
#endif /* CONFIG_M5253 */
cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
@@ -60,7 +60,7 @@ int get_clocks (void)
pllcr ^= 0x00000001; /* Set pll bypass to 1 */
mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CFG_PLL_BYPASS */
+#endif /* #ifndef CONFIG_SYS_PLL_BYPASS */
#endif /* CONFIG_M5249 || CONFIG_M5253 */
@@ -76,7 +76,7 @@ int get_clocks (void)
;
#endif
- gd->cpu_clk = CFG_CLK;
+ gd->cpu_clk = CONFIG_SYS_CLK;
#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
gd->bus_clk = gd->cpu_clk / 2;
#else
@@ -85,7 +85,7 @@ int get_clocks (void)
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
-#ifdef CFG_I2C2_OFFSET
+#ifdef CONFIG_SYS_I2C2_OFFSET
gd->i2c2_clk = gd->bus_clk;
#endif
#endif
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 2e8ecfb..ba6b884 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -22,6 +22,7 @@
*/
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#ifndef CONFIG_IDENT_STRING
@@ -56,7 +57,7 @@
_vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -103,9 +104,9 @@ _vectors:
.text
-#if defined(CFG_INT_FLASH_BASE) && \
+#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
(defined(CONFIG_M5282) || defined(CONFIG_M5281))
- #if (TEXT_BASE == CFG_INT_FLASH_BASE)
+ #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
.long 0xFFFFFFFF /* all sectors protected */
.long 0x00000000 /* supervisor/User restriction */
@@ -120,44 +121,44 @@ _start:
move.w #0x2700,%sr
#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
- move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
/*** The 5249 has MBAR2 as well ***/
-#ifdef CFG_MBAR2
- move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
+#ifdef CONFIG_SYS_MBAR2
+ move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */
movec %d0, #0xc0e /* Set MBAR2 */
#endif
- move.l #(CFG_INIT_RAM_ADDR + 1), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
movec %d0, %RAMBAR0
#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
/* Initialize IPSBAR */
- move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#if defined(CONFIG_M5282)
-#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
- move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
- move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
- move.l #(CFG_INIT_RAM_ADDR), %a2
+ move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
_copy_flash:
move.l (%a0)+, (%a2)+
cmp.l %a0, %a1
bgt.s _copy_flash
- jmp CFG_INIT_RAM_ADDR
+ jmp CONFIG_SYS_INIT_RAM_ADDR
_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
- move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
+ move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
jmp _after_flashbar_copy.L /* Force jump to absolute address */
_flashbar_setup_end:
@@ -165,9 +166,9 @@ _flashbar_setup_end:
_after_flashbar_copy:
#else
/* Setup code to initialize FLASHBAR, if start from external Memory */
- move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
+ move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
movec %d0, %FLASHBAR
-#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
+#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
#endif
#endif
@@ -175,22 +176,22 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
- move.l #CFG_INT_FLASH_BASE, %d0
+#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
+ move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
#else
- move.l #CFG_FLASH_BASE, %d0
+ move.l #CONFIG_SYS_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif
#ifdef CONFIG_M5275
/* Initialize IPSBAR */
- move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
+ move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
/* movec %d0, %MBAR */
/* Initialize RAMBAR: locate SRAM and validate it */
- move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
movec %d0, %RAMBAR1
#endif
@@ -204,7 +205,7 @@ _after_flashbar_copy:
#endif
/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
- move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
move.l #__got_start, %a5 /* put relocation table address to a5 */
@@ -235,7 +236,7 @@ relocate_code:
move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
move.l 16(%a6), %a0 /* Save copy of Destination Address */
- move.l #CFG_MONITOR_BASE, %a1
+ move.l #CONFIG_SYS_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
/* copy the code to RAM */
@@ -249,7 +250,7 @@ relocate_code:
* initialization, now running from RAM.
*/
move.l %a0, %a1
- add.l #(in_ram - CFG_MONITOR_BASE), %a1
+ add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
@@ -259,9 +260,9 @@ clear_bss:
* Now clear BSS segment
*/
move.l %a0, %a1
- add.l #(_sbss - CFG_MONITOR_BASE),%a1
+ add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a0, %d1
- add.l #(_ebss - CFG_MONITOR_BASE),%d1
+ add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
6:
clr.l (%a1)+
cmp.l %a1,%d1
@@ -271,11 +272,11 @@ clear_bss:
* fix got table in RAM
*/
move.l %a0, %a1
- add.l #(__got_start - CFG_MONITOR_BASE),%a1
+ add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
move.l %a1,%a5 /* * fix got pointer register a5 */
move.l %a0, %a2
- add.l #(__got_end - CFG_MONITOR_BASE),%a2
+ add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
7:
move.l (%a1),%d1
@@ -290,27 +291,27 @@ clear_bss:
/* quick and dirty */
move.l %a0,%d1
- add.l #(icache_state - CFG_MONITOR_BASE),%d1
+ add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
move.l %a0,%a1
- add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
- add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
move.l %a0,%a1
- add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
+ add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
move.l %d1,(%a1)
#endif
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
- add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+ add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
-#if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
- defined(CFG_HALT_BEFOR_RAM_JUMP)
+#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
+ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
halt
#endif
jsr (%a1)
@@ -344,14 +345,14 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
+ move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */
nop
- move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
moveq #1, %d0
move.l %d0, (%a1)
rts
@@ -474,6 +475,6 @@ dcache_status:
.globl version_string
version_string:
.ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
.ascii CONFIG_IDENT_STRING, "\0"
.align 4
generated by cgit v1.1 at 2024-11-22 19:04:29 +0000