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-rw-r--r--cpu/mcf52x2/cpu.c27
-rw-r--r--cpu/mcf52x2/cpu_init.c177
-rw-r--r--cpu/mcf52x2/fec.c27
-rw-r--r--cpu/mcf52x2/serial.c39
-rw-r--r--cpu/mcf52x2/start.S96
5 files changed, 334 insertions, 32 deletions
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 32a524f..8795bcc 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -2,6 +2,10 @@
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,7 +35,8 @@
#endif
#ifdef CONFIG_M5282
-
+#include <asm/m5282.h>
+#include <asm/immap_5282.h>
#endif
#ifdef CONFIG_M5249
@@ -75,7 +80,6 @@ int checkcpu(void) {
return 0;
};
-
#if defined(CONFIG_WATCHDOG)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset (void)
@@ -117,11 +121,26 @@ int watchdog_init (void)
#ifdef CONFIG_M5282
int checkcpu (void)
{
- puts ("CPU: MOTOROLA Coldfire MCF5282\n");
+ unsigned char resetsource;
+
+ printf ("CPU: MOTOROLA Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
+ MCFCCM_CIR>>8,MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
+ puts ("Reset: ");
+ resetsource = MCFRESET_RSR;
+ if (resetsource & MCFRESET_RSR_LOL) puts("Lose-of-lock ");
+ if (resetsource & MCFRESET_RSR_LOC) puts("Lose-of-clock ");
+ if (resetsource & MCFRESET_RSR_EXT) puts("external ");
+ if (resetsource & MCFRESET_RSR_POR) puts("Power-on ");
+ if (resetsource & MCFRESET_RSR_WDR) puts("Watchdog ");
+ if (resetsource & MCFRESET_RSR_SOFT) puts("Software ");
+ if (resetsource & MCFRESET_RSR_LVD) puts("Low-voltage ");
+ puts("\n");
return 0;
}
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) {
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
return 0;
};
#endif
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 350c431..0fa2ce2 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -2,6 +2,10 @@
* (C) Copyright 2003
* Josef Baumgartner <josef.baumgartner@telex.de>
*
+ * MCF5282 additionals
+ * (C) Copyright 2005
+ * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -135,7 +139,180 @@ int cpu_init_r (void)
*/
void cpu_init_f (void)
{
+#ifndef CONFIG_WATCHDOG
+ /* disable watchdog if we aren't using it */
+ MCFWTM_WCR = 0;
+#endif
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+ /* Set speed /PLL */
+ MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+
+ /* Set up the GPIO ports */
+#ifdef CFG_PEPAR
+ MCFGPIO_PEPAR = CFG_PEPAR;
+#endif
+#ifdef CFG_PFPAR
+ MCFGPIO_PFPAR = CFG_PFPAR;
+#endif
+#ifdef CFG_PJPAR
+ MCFGPIO_PJPAR = CFG_PJPAR;
+#endif
+#ifdef CFG_PSDPAR
+ MCFGPIO_PSDPAR = CFG_PSDPAR;
+#endif
+#ifdef CFG_PASPAR
+ MCFGPIO_PASPAR = CFG_PASPAR;
+#endif
+#ifdef CFG_PEHLPAR
+ MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+#endif
+#ifdef CFG_PQSPAR
+ MCFGPIO_PQSPAR = CFG_PQSPAR;
+#endif
+#ifdef CFG_PTCPAR
+ MCFGPIO_PTCPAR = CFG_PTCPAR;
+#endif
+#ifdef CFG_PTDPAR
+ MCFGPIO_PTDPAR = CFG_PTDPAR;
+#endif
+#ifdef CFG_PUAPAR
+ MCFGPIO_PUAPAR = CFG_PUAPAR;
+#endif
+
+#ifdef CFG_DDRUA
+ MCFGPIO_DDRUA = CFG_DDRUA;
+#endif
+
+ /* This is probably a bad place to setup chip selects, but everyone
+ else is doing it! */
+
+#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
+ defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
+ defined(CFG_CS0_WS)
+
+ MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
+
+ #if (CFG_CS0_WIDTH == 8)
+ #define CFG_CS0_PS MCFCSM_CSCR_PS_8
+ #elif (CFG_CS0_WIDTH == 16)
+ #define CFG_CS0_PS MCFCSM_CSCR_PS_16
+ #elif (CFG_CS0_WIDTH == 32)
+ #define CFG_CS0_PS MCFCSM_CSCR_PS_32
+ #else
+ #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+ #endif
+ MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
+ |CFG_CS0_PS
+ |MCFCSM_CSCR_AA;
+
+ #if (CFG_CS0_RO != 0)
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
+ |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
+ #else
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
+ #endif
+#else
+ #waring "Chip Select 0 are not initialized/used"
+#endif
+
+#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
+ defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
+ defined(CFG_CS1_WS)
+
+ MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
+
+ #if (CFG_CS1_WIDTH == 8)
+ #define CFG_CS1_PS MCFCSM_CSCR_PS_8
+ #elif (CFG_CS1_WIDTH == 16)
+ #define CFG_CS1_PS MCFCSM_CSCR_PS_16
+ #elif (CFG_CS1_WIDTH == 32)
+ #define CFG_CS1_PS MCFCSM_CSCR_PS_32
+ #else
+ #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+ #endif
+ MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
+ |CFG_CS1_PS
+ |MCFCSM_CSCR_AA;
+
+ #if (CFG_CS1_RO != 0)
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
+ |MCFCSM_CSMR_WP
+ |MCFCSM_CSMR_V;
+ #else
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
+ |MCFCSM_CSMR_V;
+ #endif
+#else
+ #warning "Chip Select 1 are not initialized/used"
+#endif
+
+#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
+ defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
+ defined(CFG_CS2_WS)
+
+ MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
+
+ #if (CFG_CS2_WIDTH == 8)
+ #define CFG_CS2_PS MCFCSM_CSCR_PS_8
+ #elif (CFG_CS2_WIDTH == 16)
+ #define CFG_CS2_PS MCFCSM_CSCR_PS_16
+ #elif (CFG_CS2_WIDTH == 32)
+ #define CFG_CS2_PS MCFCSM_CSCR_PS_32
+ #else
+ #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
+ #endif
+ MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
+ |CFG_CS2_PS
+ |MCFCSM_CSCR_AA;
+
+ #if (CFG_CS2_RO != 0)
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
+ |MCFCSM_CSMR_WP
+ |MCFCSM_CSMR_V;
+ #else
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
+ |MCFCSM_CSMR_V;
+ #endif
+#else
+ #warning "Chip Select 2 are not initialized/used"
+#endif
+
+#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
+ defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
+ defined(CFG_CS3_WS)
+
+ MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
+
+ #if (CFG_CS3_WIDTH == 8)
+ #define CFG_CS3_PS MCFCSM_CSCR_PS_8
+ #elif (CFG_CS3_WIDTH == 16)
+ #define CFG_CS3_PS MCFCSM_CSCR_PS_16
+ #elif (CFG_CS3_WIDTH == 32)
+ #define CFG_CS3_PS MCFCSM_CSCR_PS_32
+ #else
+ #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
+ #endif
+ MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
+ |CFG_CS3_PS
+ |MCFCSM_CSCR_AA;
+
+ #if (CFG_CS3_RO != 0)
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
+ |MCFCSM_CSMR_WP
+ |MCFCSM_CSMR_V;
+ #else
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
+ |MCFCSM_CSMR_V;
+ #endif
+#else
+ #warning "Chip Select 3 are not initialized/used"
+#endif
+
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
+ /* defer enabling cache until boot (see do_go) */
+ /* icache_enable(); */
}
/*
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index a5c50af..b8b82d0 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -200,7 +200,9 @@ int eth_rx (void)
int eth_init (bd_t * bd)
{
-
+#ifndef CFG_ENET_BD_BASE
+ DECLARE_GLOBAL_DATA_PTR;
+#endif
int i;
volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
@@ -242,9 +244,13 @@ int eth_init (bd_t * bd)
/* Clear multicast address hash table
*/
+#ifdef CONFIG_M5282
+ fecp->fec_ihash_table_high = 0;
+ fecp->fec_ihash_table_low = 0;
+#else
fecp->fec_hash_table_high = 0;
fecp->fec_hash_table_low = 0;
-
+#endif
/* Set maximum receive buffer size.
*/
fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
@@ -256,7 +262,16 @@ int eth_init (bd_t * bd)
txIdx = 0;
if (!rtx) {
+#ifdef CFG_ENET_BD_BASE
rtx = (RTXBD *) CFG_ENET_BD_BASE;
+#else
+ rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
+ (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
+ +0xFF)
+ & ~0xFF)
+ );
+ debug("set ENET_DB_BASE to %lX\n",(long) rtx);
+#endif
}
/*
@@ -294,11 +309,13 @@ int eth_init (bd_t * bd)
fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
#else /* Half duplex mode */
- fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
+ fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
+ fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
fecp->fec_x_cntrl = 0;
#endif
/* Set MII speed */
- fecp->fec_mii_speed = 0x0e;
+ fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
+ fecp->fec_mii_speed *= 2;
/* Configure port B for MII.
*/
@@ -402,7 +419,7 @@ static void mii_discover_phy (void)
*/
udelay (10000); /* wait 10ms */
}
- for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+ for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
#ifdef ET_DEBUG
printf ("PHY type 0x%x pass %d type ", phytype, pass);
diff --git a/cpu/mcf52x2/serial.c b/cpu/mcf52x2/serial.c
index 79628d0..fe412a0 100644
--- a/cpu/mcf52x2/serial.c
+++ b/cpu/mcf52x2/serial.c
@@ -65,6 +65,28 @@ void rs_serial_setbaudrate(int port,int baudrate)
uartp[MCFUART_UBG2] = ((int)clock & 0xff); /* set lsb baud */
uartp[MCFUART_UFPD] = ((int)fraction & 0xf); /* set baud fraction adjust */
#endif
+#if defined(CONFIG_M5282)
+ volatile unsigned char *uartp;
+ long clock;
+
+ switch (port)
+ {
+ case 1:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
+ break;
+ case 2:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
+ break;
+ default:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
+ }
+
+ clock = (long) CFG_CLK / ((long) 32 * baudrate); /* Set baud above */
+
+ uartp[MCFUART_UBG1] = (((int)clock >> 8) & 0xff); /* set msb baud */
+ uartp[MCFUART_UBG2] = ((int) clock & 0xff); /* set lsb baud */
+
+#endif
};
void rs_serial_init(int port,int baudrate)
@@ -74,10 +96,19 @@ void rs_serial_init(int port,int baudrate)
/*
* Reset UART, get it into known state...
*/
- if (port == 0)
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
- else
- uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
+ switch (port)
+ {
+ case 1:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE2);
+ break;
+ #if defined(CONFIG_M5282)
+ case 2:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE3);
+ break;
+ #endif
+ default:
+ uartp = (volatile unsigned char *) (CFG_MBAR + MCFUART_BASE1);
+ }
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETRX; /* reset RX */
uartp[MCFUART_UCR] = MCFUART_UCR_CMDRESETTX; /* reset TX */
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index b4926e2..9a13491 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -54,8 +54,12 @@
* These vectors are to catch any un-intended traps.
*/
_vectors:
-
-.long 0x00000000, _START
+ .long 0x00000000
+#ifndef CONFIG_M5282
+.long _START
+#else
+.long _start - TEXT_BASE
+#endif
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -96,20 +100,23 @@ _vectors:
.text
+
+#if defined(CFG_INT_FLASH_BASE) && \
+ (defined(CONFIG_M5282) || defined(CONFIG_M5281))
+ #if (TEXT_BASE == CFG_INT_FLASH_BASE)
+ .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
+ .long 0xFFFFFFFF /* all sectors protected */
+ .long 0x00000000 /* supervisor/User restriction */
+ .long 0x00000000 /* programm/data space restriction */
+ .long 0x00000000 /* Flash security */
+ #endif
+#endif
.globl _start
_start:
nop
nop
move.w #0x2700,%sr
- /* if we come from a pre-loader we have no exception table and
- * therefore no VBR to set
- */
-#if !defined(CONFIG_MONITOR_IS_IN_RAM)
- move.l #CFG_FLASH_BASE, %d0
- movec %d0, %VBR
-#endif
-
#if defined(CONFIG_M5272) || defined(CONFIG_M5249)
move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
move.c %d0, %MBAR
@@ -129,13 +136,43 @@ _start:
move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
move.l %d0, 0x40000000
+ /* Initialize RAMBAR1: locate SRAM and validate it */
+ move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
+ movec %d0, %RAMBAR1
+
+#if (TEXT_BASE == CFG_INT_FLASH_BASE)
+ /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
+
+ move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
+ move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
+ move.l #(CFG_INIT_RAM_ADDR), %a2
+_copy_flash:
+ move.l (%a0)+, (%a2)+
+ cmp.l %a0, %a1
+ bgt.s _copy_flash
+ jmp CFG_INIT_RAM_ADDR
+
+_flashbar_setup:
/* Initialize FLASHBAR: locate internal Flash and validate it */
move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
movec %d0, %RAMBAR0
+ jmp _after_flashbar_copy.L /* Force jump to absolute address */
+_flashbar_setup_end:
+ nop
+_after_flashbar_copy:
+#else
+ /* Setup code to initialize FLASHBAR, if start from external Memory */
+ move.l #(CFG_INT_FLASH_BASE + 0x21), %d0
+ movec %d0, %RAMBAR0
+#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
- /* Initialize RAMBAR1: locate SRAM and validate it */
- move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
- movec %d0, %RAMBAR1
+#endif
+ /* if we come from a pre-loader we have no exception table and
+ * therefore no VBR to set
+ */
+#if !defined(CONFIG_MONITOR_IS_IN_RAM)
+ move.l #CFG_FLASH_BASE, %d0
+ movec %d0, %VBR
#endif
/* invalidate and disable cache */
@@ -157,7 +194,6 @@ _start:
/* board_init_f() does not return
/*------------------------------------------------------------------------------*/
-
/*
* void relocate_code (addr_sp, gd, addr_moni)
*
@@ -180,7 +216,6 @@ relocate_code:
move.l #CFG_MONITOR_BASE, %a1
move.l #__init_end, %a2
move.l %a0, %a3
-
/* copy the code to RAM */
1:
move.l (%a1)+, (%a3)+
@@ -191,14 +226,14 @@ relocate_code:
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
- move.l %a0, %a1
+ move.l %a0, %a1
add.l #(in_ram - CFG_MONITOR_BASE), %a1
jmp (%a1)
in_ram:
clear_bss:
- /*
+ /*
* Now clear BSS segment
*/
move.l %a0, %a1
@@ -228,6 +263,23 @@ clear_bss:
cmp.l %a2, %a1
bne 7b
+#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
+ /* patch the 3 accesspoints to 3 ichache_state */
+ /* quick and dirty */
+
+ move.l %a0,%d1
+ add.l #(icache_state - CFG_MONITOR_BASE),%d1
+ move.l %a0,%a1
+ add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
+ move.l %d1,(%a1)
+ move.l %a0,%a1
+ add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
+ move.l %d1,(%a1)
+ move.l %a0,%a1
+ add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
+ move.l %d1,(%a1)
+#endif
+
/* calculate relative jump to board_init_r in ram */
move.l %a0, %a1
add.l #(board_init_r - CFG_MONITOR_BASE), %a1
@@ -235,6 +287,10 @@ clear_bss:
/* set parameters for board_init_r */
move.l %a0,-(%sp) /* dest_addr */
move.l %d0,-(%sp) /* gd */
+ #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
+ defined(CFG_HALT_BEFOR_RAM_JUMP)
+ halt
+ #endif
jsr (%a1)
/*------------------------------------------------------------------------------*/
@@ -289,6 +345,7 @@ icache_enable:
move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
movec %d0, %CACR /* Enable cache */
moveq #1, %d0
+icache_state_access_1:
move.l %d0, icache_state
rts
#endif
@@ -323,18 +380,19 @@ icache_disable:
movec %d0, %ACR0 /* Enable cache */
movec %d0, %ACR1 /* Enable cache */
moveq #0, %d0
+icache_state_access_2:
move.l %d0, icache_state
rts
.globl icache_status
icache_status:
+icache_state_access_3:
move.l icache_state, %d0
rts
.data
icache_state:
- .long 1
-
+ .long 0 /* cache is diabled on inirialization */
/*------------------------------------------------------------------------------*/
generated by cgit v1.1 at 2024-11-16 21:03:37 +0000