summaryrefslogtreecommitdiff
path: root/cpu/i386
diff options
context:
space:
mode:
Diffstat (limited to 'cpu/i386')
-rw-r--r--cpu/i386/Makefile2
-rw-r--r--cpu/i386/cpu.c4
-rw-r--r--cpu/i386/exceptions.c229
-rw-r--r--cpu/i386/interrupts.c426
-rw-r--r--cpu/i386/sc520/Makefile4
-rw-r--r--cpu/i386/sc520/sc520.c279
-rw-r--r--cpu/i386/sc520/sc520_pci.c171
-rw-r--r--cpu/i386/sc520/sc520_ssi.c92
-rw-r--r--cpu/i386/sc520/sc520_timer.c82
-rw-r--r--cpu/i386/start.S41
-rw-r--r--cpu/i386/timer.c211
11 files changed, 631 insertions, 910 deletions
diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index 761c4f6..e98bd3d 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o start16.o resetvec.o
-COBJS = serial.o interrupts.o cpu.o timer.o
+COBJS = serial.o interrupts.o exceptions.o cpu.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c
index b9af5f8..d91e33b 100644
--- a/cpu/i386/cpu.c
+++ b/cpu/i386/cpu.c
@@ -46,6 +46,10 @@ int cpu_init(void)
"orl $0x22, %eax\n" \
"movl %eax, %cr0\n" );
+ /* Initialize core interrupt and exception functionality of CPU */
+ cpu_init_interrupts ();
+ cpu_init_exceptions ();
+
return 0;
}
diff --git a/cpu/i386/exceptions.c b/cpu/i386/exceptions.c
new file mode 100644
index 0000000..bc3d434
--- /dev/null
+++ b/cpu/i386/exceptions.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/interrupt.h>
+
+asm (".globl exp_return\n"
+ "exp_return:\n"
+ " addl $12, %esp\n"
+ " pop %esp\n"
+ " popa\n"
+ " iret\n");
+
+char exception_stack[4096];
+
+/*
+ * For detailed description of each exception, refer to:
+ * Intel® 64 and IA-32 Architectures Software Developer's Manual
+ * Volume 1: Basic Architecture
+ * Order Number: 253665-029US, November 2008
+ * Table 6-1. Exceptions and Interrupts
+ */
+DECLARE_EXCEPTION(0, divide_error_entry);
+DECLARE_EXCEPTION(1, debug_entry);
+DECLARE_EXCEPTION(2, nmi_interrupt_entry);
+DECLARE_EXCEPTION(3, breakpoint_entry);
+DECLARE_EXCEPTION(4, overflow_entry);
+DECLARE_EXCEPTION(5, bound_range_exceeded_entry);
+DECLARE_EXCEPTION(6, invalid_opcode_entry);
+DECLARE_EXCEPTION(7, device_not_available_entry);
+DECLARE_EXCEPTION(8, double_fault_entry);
+DECLARE_EXCEPTION(9, coprocessor_segment_overrun_entry);
+DECLARE_EXCEPTION(10, invalid_tss_entry);
+DECLARE_EXCEPTION(11, segment_not_present_entry);
+DECLARE_EXCEPTION(12, stack_segment_fault_entry);
+DECLARE_EXCEPTION(13, general_protection_entry);
+DECLARE_EXCEPTION(14, page_fault_entry);
+DECLARE_EXCEPTION(15, reserved_exception_entry);
+DECLARE_EXCEPTION(16, floating_point_error_entry);
+DECLARE_EXCEPTION(17, alignment_check_entry);
+DECLARE_EXCEPTION(18, machine_check_entry);
+DECLARE_EXCEPTION(19, simd_floating_point_exception_entry);
+DECLARE_EXCEPTION(20, reserved_exception_entry);
+DECLARE_EXCEPTION(21, reserved_exception_entry);
+DECLARE_EXCEPTION(22, reserved_exception_entry);
+DECLARE_EXCEPTION(23, reserved_exception_entry);
+DECLARE_EXCEPTION(24, reserved_exception_entry);
+DECLARE_EXCEPTION(25, reserved_exception_entry);
+DECLARE_EXCEPTION(26, reserved_exception_entry);
+DECLARE_EXCEPTION(27, reserved_exception_entry);
+DECLARE_EXCEPTION(28, reserved_exception_entry);
+DECLARE_EXCEPTION(29, reserved_exception_entry);
+DECLARE_EXCEPTION(30, reserved_exception_entry);
+DECLARE_EXCEPTION(31, reserved_exception_entry);
+
+__isr__ reserved_exception_entry(int cause, int ip, int seg)
+{
+ printf("Reserved Exception %d at %04x:%08x\n", cause, seg, ip);
+}
+
+__isr__ divide_error_entry(int cause, int ip, int seg)
+{
+ printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ debug_entry(int cause, int ip, int seg)
+{
+ printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
+}
+
+__isr__ nmi_interrupt_entry(int cause, int ip, int seg)
+{
+ printf("NMI Interrupt at %04x:%08x\n", seg, ip);
+}
+
+__isr__ breakpoint_entry(int cause, int ip, int seg)
+{
+ printf("Breakpoint at %04x:%08x\n", seg, ip);
+}
+
+__isr__ overflow_entry(int cause, int ip, int seg)
+{
+ printf("Overflow at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ bound_range_exceeded_entry(int cause, int ip, int seg)
+{
+ printf("BOUND Range Exceeded at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ invalid_opcode_entry(int cause, int ip, int seg)
+{
+ printf("Invalid Opcode (UnDefined Opcode) at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ device_not_available_entry(int cause, int ip, int seg)
+{
+ printf("Device Not Available (No Math Coprocessor) at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ double_fault_entry(int cause, int ip, int seg)
+{
+ printf("Double fault at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ coprocessor_segment_overrun_entry(int cause, int ip, int seg)
+{
+ printf("Co-processor segment overrun at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ invalid_tss_entry(int cause, int ip, int seg)
+{
+ printf("Invalid TSS at %04x:%08x\n", seg, ip);
+}
+
+__isr__ segment_not_present_entry(int cause, int ip, int seg)
+{
+ printf("Segment Not Present at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ stack_segment_fault_entry(int cause, int ip, int seg)
+{
+ printf("Stack Segment Fault at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ general_protection_entry(int cause, int ip, int seg)
+{
+ printf("General Protection at %04x:%08x\n", seg, ip);
+}
+
+__isr__ page_fault_entry(int cause, int ip, int seg)
+{
+ printf("Page fault at %04x:%08x\n", seg, ip);
+ while(1);
+}
+
+__isr__ floating_point_error_entry(int cause, int ip, int seg)
+{
+ printf("Floating-Point Error (Math Fault) at %04x:%08x\n", seg, ip);
+}
+
+__isr__ alignment_check_entry(int cause, int ip, int seg)
+{
+ printf("Alignment check at %04x:%08x\n", seg, ip);
+}
+
+__isr__ machine_check_entry(int cause, int ip, int seg)
+{
+ printf("Machine Check at %04x:%08x\n", seg, ip);
+}
+
+__isr__ simd_floating_point_exception_entry(int cause, int ip, int seg)
+{
+ printf("SIMD Floating-Point Exception at %04x:%08x\n", seg, ip);
+}
+
+int cpu_init_exceptions(void)
+{
+ /* Just in case... */
+ disable_interrupts();
+
+ /* Setup exceptions */
+ set_vector(0x00, exp_0);
+ set_vector(0x01, exp_1);
+ set_vector(0x02, exp_2);
+ set_vector(0x03, exp_3);
+ set_vector(0x04, exp_4);
+ set_vector(0x05, exp_5);
+ set_vector(0x06, exp_6);
+ set_vector(0x07, exp_7);
+ set_vector(0x08, exp_8);
+ set_vector(0x09, exp_9);
+ set_vector(0x0a, exp_10);
+ set_vector(0x0b, exp_11);
+ set_vector(0x0c, exp_12);
+ set_vector(0x0d, exp_13);
+ set_vector(0x0e, exp_14);
+ set_vector(0x0f, exp_15);
+ set_vector(0x10, exp_16);
+ set_vector(0x11, exp_17);
+ set_vector(0x12, exp_18);
+ set_vector(0x13, exp_19);
+ set_vector(0x14, exp_20);
+ set_vector(0x15, exp_21);
+ set_vector(0x16, exp_22);
+ set_vector(0x17, exp_23);
+ set_vector(0x18, exp_24);
+ set_vector(0x19, exp_25);
+ set_vector(0x1a, exp_26);
+ set_vector(0x1b, exp_27);
+ set_vector(0x1c, exp_28);
+ set_vector(0x1d, exp_29);
+ set_vector(0x1e, exp_30);
+ set_vector(0x1f, exp_31);
+
+ /* It is now safe to enable interrupts */
+ enable_interrupts();
+
+ return 0;
+}
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c
index badb30b..063ea42 100644
--- a/cpu/i386/interrupts.c
+++ b/cpu/i386/interrupts.c
@@ -22,10 +22,6 @@
*/
#include <common.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/i8259.h>
-#include <asm/ibmpc.h>
#include <asm/interrupt.h>
@@ -41,361 +37,34 @@ struct idt_entry {
struct idt_entry idt[256];
-#define MAX_IRQ 16
-
-typedef struct irq_handler {
- struct irq_handler *next;
- interrupt_handler_t* isr_func;
- void *isr_data;
-} irq_handler_t;
-
-#define IRQ_DISABLED 1
-
-typedef struct {
- irq_handler_t *handler;
- unsigned long status;
-} irq_desc_t;
-
-static irq_desc_t irq_table[MAX_IRQ];
-
-asm ("irq_return:\n"
+asm (".globl irq_return\n"
+ "irq_return:\n"
" addl $4, %esp\n"
" popa\n"
" iret\n");
-asm ("exp_return:\n"
- " addl $12, %esp\n"
- " pop %esp\n"
- " popa\n"
- " iret\n");
-
-char exception_stack[4096];
-
-#define DECLARE_INTERRUPT(x) \
- asm(".globl irq_"#x"\n" \
- "irq_"#x":\n" \
- "pusha \n" \
- "pushl $"#x"\n" \
- "pushl $irq_return\n" \
- "jmp do_irq\n"); \
- void __attribute__ ((regparm(0))) irq_##x(void)
-
-#define DECLARE_EXCEPTION(x, f) \
- asm(".globl exp_"#x"\n" \
- "exp_"#x":\n" \
- "pusha \n" \
- "movl %esp, %ebx\n" \
- "movl $exception_stack, %eax\n" \
- "movl %eax, %esp \n" \
- "pushl %ebx\n" \
- "movl 32(%esp), %ebx\n" \
- "xorl %edx, %edx\n" \
- "movw 36(%esp), %dx\n" \
- "pushl %edx\n" \
- "pushl %ebx\n" \
- "pushl $"#x"\n" \
- "pushl $exp_return\n" \
- "jmp "#f"\n"); \
- void __attribute__ ((regparm(0))) exp_##x(void)
-
-DECLARE_EXCEPTION(0, divide_exception_entry); /* Divide exception */
-DECLARE_EXCEPTION(1, debug_exception_entry); /* Debug exception */
-DECLARE_EXCEPTION(2, nmi_entry); /* NMI */
-DECLARE_EXCEPTION(3, unknown_exception_entry); /* Breakpoint/Coprocessor Error */
-DECLARE_EXCEPTION(4, unknown_exception_entry); /* Overflow */
-DECLARE_EXCEPTION(5, unknown_exception_entry); /* Bounds */
-DECLARE_EXCEPTION(6, invalid_instruction_entry); /* Invalid instruction */
-DECLARE_EXCEPTION(7, unknown_exception_entry); /* Device not present */
-DECLARE_EXCEPTION(8, double_fault_entry); /* Double fault */
-DECLARE_EXCEPTION(9, unknown_exception_entry); /* Co-processor segment overrun */
-DECLARE_EXCEPTION(10, invalid_tss_exception_entry);/* Invalid TSS */
-DECLARE_EXCEPTION(11, seg_fault_entry); /* Segment not present */
-DECLARE_EXCEPTION(12, stack_fault_entry); /* Stack overflow */
-DECLARE_EXCEPTION(13, gpf_entry); /* GPF */
-DECLARE_EXCEPTION(14, page_fault_entry); /* PF */
-DECLARE_EXCEPTION(15, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(16, fp_exception_entry); /* Floating point */
-DECLARE_EXCEPTION(17, alignment_check_entry); /* alignment check */
-DECLARE_EXCEPTION(18, machine_check_entry); /* machine check */
-DECLARE_EXCEPTION(19, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(20, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(21, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(22, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(23, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(24, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(25, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(26, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(27, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(28, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(29, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(30, unknown_exception_entry); /* Reserved */
-DECLARE_EXCEPTION(31, unknown_exception_entry); /* Reserved */
-
-DECLARE_INTERRUPT(0);
-DECLARE_INTERRUPT(1);
-DECLARE_INTERRUPT(3);
-DECLARE_INTERRUPT(4);
-DECLARE_INTERRUPT(5);
-DECLARE_INTERRUPT(6);
-DECLARE_INTERRUPT(7);
-DECLARE_INTERRUPT(8);
-DECLARE_INTERRUPT(9);
-DECLARE_INTERRUPT(10);
-DECLARE_INTERRUPT(11);
-DECLARE_INTERRUPT(12);
-DECLARE_INTERRUPT(13);
-DECLARE_INTERRUPT(14);
-DECLARE_INTERRUPT(15);
-
void __attribute__ ((regparm(0))) default_isr(void);
asm ("default_isr: iret\n");
-void disable_irq(int irq)
-{
- if (irq >= MAX_IRQ) {
- return;
- }
- irq_table[irq].status |= IRQ_DISABLED;
-
-}
-
-void enable_irq(int irq)
-{
- if (irq >= MAX_IRQ) {
- return;
- }
- irq_table[irq].status &= ~IRQ_DISABLED;
-}
-
-/* masks one specific IRQ in the PIC */
-static void unmask_irq(int irq)
-{
- int imr_port;
-
- if (irq >= MAX_IRQ) {
- return;
- }
- if (irq > 7) {
- imr_port = SLAVE_PIC + IMR;
- } else {
- imr_port = MASTER_PIC + IMR;
- }
-
- outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
-}
-
-
-/* unmasks one specific IRQ in the PIC */
-static void mask_irq(int irq)
-{
- int imr_port;
-
- if (irq >= MAX_IRQ) {
- return;
- }
- if (irq > 7) {
- imr_port = SLAVE_PIC + IMR;
- } else {
- imr_port = MASTER_PIC + IMR;
- }
-
- outb(inb(imr_port)|(1<<(irq&7)), imr_port);
-}
-
-
-/* issue a Specific End Of Interrupt instruciton */
-static void specific_eoi(int irq)
-{
- /* If it is on the slave PIC this have to be performed on
- * both the master and the slave PICs */
- if (irq > 7) {
- outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
- irq = SEOI_IR2; /* also do IR2 on master */
- }
- outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
-}
-
-void __attribute__ ((regparm(0))) do_irq(int irq)
-{
-
- mask_irq(irq);
-
- if (irq_table[irq].status & IRQ_DISABLED) {
- unmask_irq(irq);
- specific_eoi(irq);
- return;
- }
-
-
- if (NULL != irq_table[irq].handler) {
- irq_handler_t *handler;
- for (handler = irq_table[irq].handler;
- NULL!= handler; handler = handler->next) {
- handler->isr_func(handler->isr_data);
- }
- } else {
- if ((irq & 7) != 7) {
- printf("Spurious irq %d\n", irq);
- }
- }
- unmask_irq(irq);
- specific_eoi(irq);
-}
-
-
-void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
-{
- printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
-}
-
-void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
-{
- printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
-{
- printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
-{
- printf("NMI Interrupt at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
-{
- printf("Invalid Instruction at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
-{
- printf("Double fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
-{
- printf("Invalid TSS at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
-{
- printf("Segmentation fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
-{
- printf("Stack fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
-{
- printf("General protection fault at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
-{
- printf("Page fault at %04x:%08x\n", seg, ip);
- while(1);
-}
-
-void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
-{
- printf("Floating point exception at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
-{
- printf("Alignment check at %04x:%08x\n", seg, ip);
-}
-
-void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
-{
- printf("Machine check exception at %04x:%08x\n", seg, ip);
-}
-
-
-void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
-{
- int status;
-
- if (ino>MAX_IRQ) {
- return;
- }
-
- if (NULL != irq_table[ino].handler) {
- return;
- }
-
- status = disable_interrupts();
- irq_table[ino].handler = malloc(sizeof(irq_handler_t));
- if (NULL == irq_table[ino].handler) {
- return;
- }
-
- memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
-
- irq_table[ino].handler->isr_func = func;
- irq_table[ino].handler->isr_data = pdata;
- if (status) {
- enable_interrupts();
- }
-
- unmask_irq(ino);
-
- return;
-}
-
-void irq_free_handler(int ino)
-{
- int status;
- if (ino>MAX_IRQ) {
- return;
- }
-
- status = disable_interrupts();
- mask_irq(ino);
- if (NULL == irq_table[ino].handler) {
- return;
- }
- free(irq_table[ino].handler);
- irq_table[ino].handler=NULL;
- if (status) {
- enable_interrupts();
- }
- return;
-}
-
-
asm ("idt_ptr:\n"
".word 0x800\n" /* size of the table 8*256 bytes */
".long idt\n" /* offset */
".word 0x18\n");/* data segment */
-void set_vector(int intnum, void *routine)
+void set_vector(u8 intnum, void *routine)
{
- idt[intnum].base_high = (u16)((u32)(routine)>>16);
- idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
+ idt[intnum].base_high = (u16)((u32)(routine + gd->reloc_off) >> 16);
+ idt[intnum].base_low = (u16)((u32)(routine + gd->reloc_off) & 0xffff);
}
-int interrupt_init(void)
+int cpu_init_interrupts(void)
{
int i;
/* Just in case... */
disable_interrupts();
- /* Initialize the IDT and stuff */
-
-
- memset(irq_table, 0, sizeof(irq_table));
-
/* Setup the IDT */
for (i=0;i<256;i++) {
idt[i].access = 0x8e;
@@ -406,89 +75,6 @@ int interrupt_init(void)
asm ("cs lidt idt_ptr\n");
- /* Setup exceptions */
- set_vector(0x00, exp_0);
- set_vector(0x01, exp_1);
- set_vector(0x02, exp_2);
- set_vector(0x03, exp_3);
- set_vector(0x04, exp_4);
- set_vector(0x05, exp_5);
- set_vector(0x06, exp_6);
- set_vector(0x07, exp_7);
- set_vector(0x08, exp_8);
- set_vector(0x09, exp_9);
- set_vector(0x0a, exp_10);
- set_vector(0x0b, exp_11);
- set_vector(0x0c, exp_12);
- set_vector(0x0d, exp_13);
- set_vector(0x0e, exp_14);
- set_vector(0x0f, exp_15);
- set_vector(0x10, exp_16);
- set_vector(0x11, exp_17);
- set_vector(0x12, exp_18);
- set_vector(0x13, exp_19);
- set_vector(0x14, exp_20);
- set_vector(0x15, exp_21);
- set_vector(0x16, exp_22);
- set_vector(0x17, exp_23);
- set_vector(0x18, exp_24);
- set_vector(0x19, exp_25);
- set_vector(0x1a, exp_26);
- set_vector(0x1b, exp_27);
- set_vector(0x1c, exp_28);
- set_vector(0x1d, exp_29);
- set_vector(0x1e, exp_30);
- set_vector(0x1f, exp_31);
-
-
- /* Setup interrupts */
- set_vector(0x20, irq_0);
- set_vector(0x21, irq_1);
- set_vector(0x23, irq_3);
- set_vector(0x24, irq_4);
- set_vector(0x25, irq_5);
- set_vector(0x26, irq_6);
- set_vector(0x27, irq_7);
- set_vector(0x28, irq_8);
- set_vector(0x29, irq_9);
- set_vector(0x2a, irq_10);
- set_vector(0x2b, irq_11);
- set_vector(0x2c, irq_12);
- set_vector(0x2d, irq_13);
- set_vector(0x2e, irq_14);
- set_vector(0x2f, irq_15);
- /* vectors 0x30-0x3f are reserved for irq 16-31 */
-
-
- /* Mask all interrupts */
- outb(0xff, MASTER_PIC + IMR);
- outb(0xff, SLAVE_PIC + IMR);
-
- /* Master PIC */
- outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
- outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
- outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
- outb(ICW4_PM, MASTER_PIC + ICW4);
-
- for (i=0;i<8;i++) {
- outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
- }
-
- /* Slave PIC */
- outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
- outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
- outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
- outb(ICW4_PM, SLAVE_PIC + ICW4);
-
- for (i=0;i<8;i++) {
- outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
- }
-
-
- /* enable cascade interrerupt */
- outb(0xfb, MASTER_PIC + IMR);
- outb(0xff, SLAVE_PIC + IMR);
-
/* It is now safe to enable interrupts */
enable_interrupts();
diff --git a/cpu/i386/sc520/Makefile b/cpu/i386/sc520/Makefile
index ddfec23..87835b2 100644
--- a/cpu/i386/sc520/Makefile
+++ b/cpu/i386/sc520/Makefile
@@ -32,6 +32,10 @@ include $(TOPDIR)/config.mk
LIB := $(obj)lib$(SOC).a
COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
+COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
+COBJS-$(CONFIG_PCI) += sc520_pci.o
+
SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c
index b958f8d..ae3b500 100644
--- a/cpu/i386/sc520/sc520.c
+++ b/cpu/i386/sc520/sc520.c
@@ -24,15 +24,8 @@
/* stuff specific for the sc520,
* but idependent of implementation */
-#include <config.h>
#include <common.h>
-#include <config.h>
-#include <pci.h>
-#ifdef CONFIG_SC520_SSI
-#include <asm/ic/ssi.h>
-#endif
#include <asm/io.h>
-#include <asm/pci.h>
#include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,13 +43,6 @@ DECLARE_GLOBAL_DATA_PTR;
*
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
- * void pci_sc520_init(struct pci_controller *hose)
- *
- * void reset_timer(void)
- * ulong get_timer(ulong base)
- * void set_timer(ulong t)
- * void udelay(unsigned long usec)
- *
*/
static u32 mmcr_base= 0xfffef000;
@@ -241,270 +227,7 @@ unsigned long init_sc520_dram(void)
return dram_present;
}
-
-#ifdef CONFIG_PCI
-
-
-static struct {
- u8 priority;
- u16 level_reg;
- u8 level_bit;
-} sc520_irq[] = {
- { SC520_IRQ0, SC520_MPICMODE, 0x01 },
- { SC520_IRQ1, SC520_MPICMODE, 0x02 },
- { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
- { SC520_IRQ3, SC520_MPICMODE, 0x08 },
- { SC520_IRQ4, SC520_MPICMODE, 0x10 },
- { SC520_IRQ5, SC520_MPICMODE, 0x20 },
- { SC520_IRQ6, SC520_MPICMODE, 0x40 },
- { SC520_IRQ7, SC520_MPICMODE, 0x80 },
-
- { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
- { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
- { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
- { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
- { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
- { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
- { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
- { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
-};
-
-
-/* The interrupt used for PCI INTA-INTD */
-int sc520_pci_ints[15] = {
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1
-};
-
-/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
-{
- int i;
-
-# if 1
- printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-#endif
- if (irq < 0 || irq > 15) {
- return -1; /* illegal irq */
- }
-
- if (pci_pin < 0 || pci_pin > 15) {
- return -1; /* illegal pci int pin */
- }
-
- /* first disable any non-pci interrupt source that use
- * this level */
- for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
- if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
- continue;
- }
- if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
- write_mmcr_byte(i, SC520_IRQ_DISABLED);
- }
- }
-
- /* Set the trigger to level */
- write_mmcr_byte(sc520_irq[irq].level_reg,
- read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
-
-
- if (pci_pin < 4) {
- /* PCI INTA-INTD */
- /* route the interrupt */
- write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-
-
- } else {
- /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
-
- /* also set the polarity in this case */
- write_mmcr_word(SC520_INTPINPOL,
- read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-
- }
-
- /* register the pin */
- sc520_pci_ints[pci_pin] = irq;
-
-
- return 0; /* OK */
-}
-
-void pci_sc520_init(struct pci_controller *hose)
-{
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region(hose->regions + 0,
- SC520_PCI_MEMORY_BUS,
- SC520_PCI_MEMORY_PHYS,
- SC520_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(hose->regions + 1,
- SC520_PCI_MEM_BUS,
- SC520_PCI_MEM_PHYS,
- SC520_PCI_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
- SC520_ISA_MEM_BUS,
- SC520_ISA_MEM_PHYS,
- SC520_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 3,
- SC520_PCI_IO_BUS,
- SC520_PCI_IO_PHYS,
- SC520_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
- SC520_ISA_IO_BUS,
- SC520_ISA_IO_PHYS,
- SC520_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 5;
-
- pci_setup_type1(hose,
- SC520_REG_ADDR,
- SC520_REG_DATA);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- /* enable target memory acceses on host brige */
- pci_write_config_word(0, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-}
-
-
-#endif
-
-#ifdef CONFIG_SYS_TIMER_SC520
-
-
-void reset_timer(void)
-{
- write_mmcr_word(SC520_GPTMR0CNT, 0);
- write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-
-}
-
-ulong get_timer(ulong base)
-{
- /* fixme: 30 or 33 */
- return read_mmcr_word(SC520_GPTMR0CNT) / 33;
-}
-
-void set_timer(ulong t)
-{
- /* FixMe: use two cascade coupled timers */
- write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
- write_mmcr_word(SC520_GPTMR0CNT, t*33);
- write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-}
-
-
-void udelay(unsigned long usec)
-{
- int m=0;
- long u;
-
- read_mmcr_word(SC520_SWTMRMILLI);
- read_mmcr_word(SC520_SWTMRMICRO);
-
-#if 0
- /* do not enable this line, udelay is used in the serial driver -> recursion */
- printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
-#endif
- while (1) {
-
- m += read_mmcr_word(SC520_SWTMRMILLI);
- u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
-
- if (usec <= u) {
- break;
- }
- }
-}
-
-#endif
-
-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
-{
- u8 temp=0;
-
- if (freq >= 8192) {
- temp |= CTL_CLK_SEL_4;
- } else if (freq >= 4096) {
- temp |= CTL_CLK_SEL_8;
- } else if (freq >= 2048) {
- temp |= CTL_CLK_SEL_16;
- } else if (freq >= 1024) {
- temp |= CTL_CLK_SEL_32;
- } else if (freq >= 512) {
- temp |= CTL_CLK_SEL_64;
- } else if (freq >= 256) {
- temp |= CTL_CLK_SEL_128;
- } else if (freq >= 128) {
- temp |= CTL_CLK_SEL_256;
- } else {
- temp |= CTL_CLK_SEL_512;
- }
-
- if (!lsb_first) {
- temp |= MSBF_ENB;
- }
-
- if (inv_clock) {
- temp |= CLK_INV_ENB;
- }
-
- if (inv_phase) {
- temp |= PHS_INV_ENB;
- }
-
- write_mmcr_byte(SC520_SSICTL, temp);
-
- return 0;
-}
-
-u8 ssi_txrx_byte(u8 data)
-{
- write_mmcr_byte(SC520_SSIXMIT, data);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- return read_mmcr_byte(SC520_SSIRCV);
-}
-
-
-void ssi_tx_byte(u8 data)
-{
- write_mmcr_byte(SC520_SSIXMIT, data);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
-}
-
-u8 ssi_rx_byte(void)
-{
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- return read_mmcr_byte(SC520_SSIRCV);
-}
-
-#ifdef CONFIG_SYS_RESET_SC520
+#ifdef CONFIG_SYS_SC520_RESET
void reset_cpu(ulong addr)
{
printf("Resetting using SC520 MMCR\n");
diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c
new file mode 100644
index 0000000..38b837e
--- /dev/null
+++ b/cpu/i386/sc520/sc520_pci.c
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+
+static struct {
+ u8 priority;
+ u16 level_reg;
+ u8 level_bit;
+} sc520_irq[] = {
+ { SC520_IRQ0, SC520_MPICMODE, 0x01 },
+ { SC520_IRQ1, SC520_MPICMODE, 0x02 },
+ { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
+ { SC520_IRQ3, SC520_MPICMODE, 0x08 },
+ { SC520_IRQ4, SC520_MPICMODE, 0x10 },
+ { SC520_IRQ5, SC520_MPICMODE, 0x20 },
+ { SC520_IRQ6, SC520_MPICMODE, 0x40 },
+ { SC520_IRQ7, SC520_MPICMODE, 0x80 },
+
+ { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
+ { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
+ { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
+ { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
+ { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
+ { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
+ { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
+ { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
+};
+
+
+/* The interrupt used for PCI INTA-INTD */
+int sc520_pci_ints[15] = {
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1
+};
+
+/* utility function to configure a pci interrupt */
+int pci_sc520_set_irq(int pci_pin, int irq)
+{
+ int i;
+
+# if 1
+ printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
+#endif
+ if (irq < 0 || irq > 15) {
+ return -1; /* illegal irq */
+ }
+
+ if (pci_pin < 0 || pci_pin > 15) {
+ return -1; /* illegal pci int pin */
+ }
+
+ /* first disable any non-pci interrupt source that use
+ * this level */
+ for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
+ if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
+ continue;
+ }
+ if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
+ write_mmcr_byte(i, SC520_IRQ_DISABLED);
+ }
+ }
+
+ /* Set the trigger to level */
+ write_mmcr_byte(sc520_irq[irq].level_reg,
+ read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
+
+
+ if (pci_pin < 4) {
+ /* PCI INTA-INTD */
+ /* route the interrupt */
+ write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
+
+
+ } else {
+ /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
+ write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
+
+ /* also set the polarity in this case */
+ write_mmcr_word(SC520_INTPINPOL,
+ read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
+
+ }
+
+ /* register the pin */
+ sc520_pci_ints[pci_pin] = irq;
+
+
+ return 0; /* OK */
+}
+
+void pci_sc520_init(struct pci_controller *hose)
+{
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* System memory space */
+ pci_set_region(hose->regions + 0,
+ SC520_PCI_MEMORY_BUS,
+ SC520_PCI_MEMORY_PHYS,
+ SC520_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ SC520_PCI_MEM_BUS,
+ SC520_PCI_MEM_PHYS,
+ SC520_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ SC520_ISA_MEM_BUS,
+ SC520_ISA_MEM_PHYS,
+ SC520_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ SC520_PCI_IO_BUS,
+ SC520_PCI_IO_PHYS,
+ SC520_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ SC520_ISA_IO_BUS,
+ SC520_ISA_IO_PHYS,
+ SC520_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_type1(hose,
+ SC520_REG_ADDR,
+ SC520_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* enable target memory acceses on host brige */
+ pci_write_config_word(0, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+}
diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c
new file mode 100644
index 0000000..dd667ca
--- /dev/null
+++ b/cpu/i386/sc520/sc520_ssi.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <asm/ic/ssi.h>
+#include <asm/ic/sc520.h>
+
+int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
+{
+ u8 temp=0;
+
+ if (freq >= 8192) {
+ temp |= CTL_CLK_SEL_4;
+ } else if (freq >= 4096) {
+ temp |= CTL_CLK_SEL_8;
+ } else if (freq >= 2048) {
+ temp |= CTL_CLK_SEL_16;
+ } else if (freq >= 1024) {
+ temp |= CTL_CLK_SEL_32;
+ } else if (freq >= 512) {
+ temp |= CTL_CLK_SEL_64;
+ } else if (freq >= 256) {
+ temp |= CTL_CLK_SEL_128;
+ } else if (freq >= 128) {
+ temp |= CTL_CLK_SEL_256;
+ } else {
+ temp |= CTL_CLK_SEL_512;
+ }
+
+ if (!lsb_first) {
+ temp |= MSBF_ENB;
+ }
+
+ if (inv_clock) {
+ temp |= CLK_INV_ENB;
+ }
+
+ if (inv_phase) {
+ temp |= PHS_INV_ENB;
+ }
+
+ write_mmcr_byte(SC520_SSICTL, temp);
+
+ return 0;
+}
+
+u8 ssi_txrx_byte(u8 data)
+{
+ write_mmcr_byte(SC520_SSIXMIT, data);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ return read_mmcr_byte(SC520_SSIRCV);
+}
+
+
+void ssi_tx_byte(u8 data)
+{
+ write_mmcr_byte(SC520_SSIXMIT, data);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
+}
+
+u8 ssi_rx_byte(void)
+{
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ return read_mmcr_byte(SC520_SSIRCV);
+}
diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c
new file mode 100644
index 0000000..2cb8656
--- /dev/null
+++ b/cpu/i386/sc520/sc520_timer.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* stuff specific for the sc520, but independent of implementation */
+
+#include <common.h>
+#include <asm/interrupt.h>
+#include <asm/ic/sc520.h>
+
+void sc520_timer_isr(void)
+{
+ /* Ack the GP Timer Interrupt */
+ write_mmcr_byte (SC520_GPTMRSTA, 0x02);
+}
+
+int timer_init(void)
+{
+ /* Map GP Timer 1 to Master PIC IR0 */
+ write_mmcr_byte (SC520_GPTMR1MAP, 0x01);
+
+ /* Disable GP Timers 1 & 2 - Allow configuration writes */
+ write_mmcr_word (SC520_GPTMR1CTL, 0x4000);
+ write_mmcr_word (SC520_GPTMR2CTL, 0x4000);
+
+ /* Reset GP Timers 1 & 2 */
+ write_mmcr_word (SC520_GPTMR1CNT, 0x0000);
+ write_mmcr_word (SC520_GPTMR2CNT, 0x0000);
+
+ /* Setup GP Timer 2 as a 100kHz (10us) prescaler */
+ write_mmcr_word (SC520_GPTMR2MAXCMPA, 83);
+ write_mmcr_word (SC520_GPTMR2CTL, 0xc001);
+
+ /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
+ write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
+ write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
+
+ /* Clear the GP Timers status register */
+ write_mmcr_byte (SC520_GPTMRSTA, 0x07);
+
+ /* Register the SC520 specific timer interrupt handler */
+ register_timer_isr (sc520_timer_isr);
+
+ /* Install interrupt handler for GP Timer 1 */
+ irq_install_handler (0, timer_isr, NULL);
+ unmask_irq (0);
+
+ return 0;
+}
+
+void udelay(unsigned long usec)
+{
+ int m = 0;
+ long u;
+
+ read_mmcr_word (SC520_SWTMRMILLI);
+ read_mmcr_word (SC520_SWTMRMICRO);
+
+ do {
+ m += read_mmcr_word (SC520_SWTMRMILLI);
+ u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000);
+ } while (u < usec);
+}
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index b6175b1..59089ef 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -173,7 +173,41 @@ bss_fail:
jmp die
bss_ok:
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ /* indicate progress */
+ movw $0x06, %ax
+ movl $.progress6, %ebp
+ jmp show_boot_progress_asm
+.progress6:
+
+ /* copy text section to ram, size must be 4-byte aligned */
+ movl $CONFIG_SYS_BL_START_RAM, %edi /* destination address */
+ movl $TEXT_BASE, %esi /* source address */
+ movl $_i386boot_text_size, %ecx /* number of bytes to copy */
+ movl %ecx, %eax
+ andl $3, %eax
+ jz text_copy /* Already 4-byte aligned */
+ subl $4, %eax /* Add extra bytes to size */
+ addl %eax, %ecx
+text_copy:
+ shrl $2, %ecx /* copy 4 byte each time */
+ cld
+ cmpl $0, %ecx
+ je text_ok
+text_segment:
+ movsl
+ loop text_segment
+ jmp text_ok
+text_fail:
+ /* indicate (lack of) progress */
+ movw $0x86, %ax
+ movl $.progress5a, %ebp
+ jmp show_boot_progress_asm
+.progress5a:
+ jmp die
+text_ok:
+#endif
wbinvd
@@ -183,7 +217,14 @@ bss_ok:
jmp show_boot_progress_asm
.progress4:
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
+ /* Jump to the RAM copy of start_i386boot */
+ movl $start_i386boot, %ebp
+ addl $(CONFIG_SYS_BL_START_RAM - TEXT_BASE), %ebp
+ call *%ebp /* Enter, U-boot! */
+#else
call start_i386boot /* Enter, U-boot! */
+#endif
/* indicate (lack of) progress */
movw $0x85, %ax
diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c
deleted file mode 100644
index 46db23f..0000000
--- a/cpu/i386/timer.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/i8254.h>
-#include <asm/ibmpc.h>
-
-
-static volatile unsigned long system_ticks;
-static int timer_init_done =0;
-
-static void timer_isr(void *unused)
-{
- system_ticks++;
-}
-
-unsigned long get_system_ticks(void)
-{
- return system_ticks;
-}
-
-#define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
-#define TIMER2_VALUE 0x0a8e /* 440Hz */
-
-int timer_init(void)
-{
- system_ticks = 0;
-
- irq_install_handler(0, timer_isr, NULL);
-
- /* initialize timer 0 and 2
- *
- * Timer 0 is used to increment system_tick 1000 times/sec
- * Timer 1 was used for DRAM refresh in early PC's
- * Timer 2 is used to drive the speaker
- * (to stasrt a beep: write 3 to port 0x61,
- * to stop it again: write 0)
- */
-
- outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
- outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0);
- outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0);
-
- outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
- outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2);
- outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2);
-
- timer_init_done = 1;
-
- return 0;
-}
-
-
-#ifdef CONFIG_SYS_TIMER_GENERIC
-
-/* the unit for these is CONFIG_SYS_HZ */
-
-/* FixMe: implement these */
-void reset_timer (void)
-{
- system_ticks = 0;
-}
-
-ulong get_timer (ulong base)
-{
- return (system_ticks - base);
-}
-
-void set_timer (ulong t)
-{
- system_ticks = t;
-}
-
-static u16 read_pit(void)
-{
- u8 low;
- outb(PIT_CMD_LATCH, PIT_BASE + PIT_COMMAND);
- low = inb(PIT_BASE + PIT_T0);
- return ((inb(PIT_BASE + PIT_T0) << 8) | low);
-}
-
-/* this is not very exact */
-void udelay (unsigned long usec)
-{
- int counter;
- int wraps;
-
- if (!timer_init_done) {
- return;
- }
- counter = read_pit();
- wraps = usec/1000;
- usec = usec%1000;
-
- usec*=1194;
- usec/=1000;
- usec+=counter;
- if (usec > 1194) {
- usec-=1194;
- wraps++;
- }
-
- while (1) {
- int new_count = read_pit();
-
- if (((new_count < usec) && !wraps) || wraps < 0) {
- break;
- }
-
- if (new_count > counter) {
- wraps--;
- }
- counter = new_count;
- }
-
-}
-
-#if 0
-/* this is a version with debug output */
-void _udelay (unsigned long usec)
-{
- int counter;
- int wraps;
-
- int usec1, usec2, usec3;
- int wraps1, wraps2, wraps3, wraps4;
- int ctr1, ctr2, ctr3, nct1, nct2;
- int i;
- usec1=usec;
- if (!timer_init_done) {
- return;
- }
- counter = read_pit();
- ctr1 = counter;
- wraps = usec/1000;
- usec = usec%1000;
-
- usec2 = usec;
- wraps1 = wraps;
-
- usec*=1194;
- usec/=1000;
- usec+=counter;
- if (usec > 1194) {
- usec-=1194;
- wraps++;
- }
-
- usec3 = usec;
- wraps2 = wraps;
-
- ctr2 = wraps3 = nct1 = 4711;
- ctr3 = wraps4 = nct2 = 4711;
- i=0;
- while (1) {
- int new_count = read_pit();
- i++;
- if ((new_count < usec && !wraps) || wraps < 0) {
- break;
- }
-
- if (new_count > counter) {
- wraps--;
- }
- if (ctr2==4711) {
- ctr2 = counter;
- wraps3 = wraps;
- nct1 = new_count;
- } else {
- ctr3 = counter;
- wraps4 = wraps;
- nct2 = new_count;
- }
-
- counter = new_count;
- }
-
- printf("udelay(%d)\n", usec1);
- printf("counter %d\n", ctr1);
- printf("1: wraps %d, usec %d\n", wraps1, usec2);
- printf("2: wraps %d, usec %d\n", wraps2, usec3);
- printf("new_count[0] %d counter %d wraps %d\n", nct1, ctr2, wraps3);
- printf("new_count[%d] %d counter %d wraps %d\n", i, nct2, ctr3, wraps4);
-
- printf("%d %d %d %d %d\n",
- read_pit(), read_pit(), read_pit(),
- read_pit(), read_pit());
-}
-#endif
-#endif
generated by cgit v1.1 at 2024-12-02 05:19:35 +0000