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-rw-r--r--cpu/i386/Makefile23
-rw-r--r--cpu/i386/sc520.c2
-rw-r--r--cpu/i386/sc520_asm.S12
3 files changed, 22 insertions, 15 deletions
diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index c44412a..cd46dea 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -1,4 +1,7 @@
#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
#
@@ -23,22 +26,26 @@
include $(TOPDIR)/config.mk
-LIB = lib$(CPU).a
+LIB = $(obj)lib$(CPU).a
START = start.o start16.o reset.o
COBJS = serial.o interrupts.o cpu.o timer.o sc520.o
-AOBJS = sc520_asm.o
+SOBJS = sc520_asm.o
-all: .depend $(START) $(LIB)
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+START := $(addprefix $(obj),$(START))
-$(LIB): $(COBJS) $(AOBJS)
- $(AR) crv $@ $(COBJS) $(AOBJS)
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
#########################################################################
-.depend: Makefile $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S)
- $(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) $(AOBJS:.o=.S) > $@
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
-sinclude .depend
+sinclude $(obj).depend
#########################################################################
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 1c4370b..d0a7341 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -149,7 +149,7 @@ unsigned long init_sc520_dram(void)
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
- * these refresh and delay values are better ? simply specified
+ * these refresh and delay values are better ? simply specified
* outright in the include/configs/{cfg} file since the HW designer
* simply dictates it.
*/
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index e1fa37a..8fc713d 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -462,7 +462,7 @@ emptybank:
#if defined CFG_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
+ movl $DRCTMCTL, %edi
movb $CFG_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
@@ -477,7 +477,7 @@ emptybank:
#ifdef CFG_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
#endif
movl $DRCCTL, %edi /* DRAM Control register */
@@ -537,7 +537,7 @@ bank0: movl (%edi), %eax
movl %eax, %ebx
-done:
+done:
movl %ebx, %eax
#if CFG_SDRAM_ECC_ENABLE
@@ -547,7 +547,7 @@ done:
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
jne out
shrl $1, %ecx
andl %ecx,%ecx
@@ -571,11 +571,11 @@ set_ecc:
/* enable NMI mapping for ECC */
movl $ECCINT, %edi
mov $0x10, %al
- movb %al, (%edi)
+ movb %al, (%edi)
/* Turn on ECC */
movl $ECCCTL, %edi
mov $0x05, %al
- movb %al, (%edi)
+ movb %al, (%edi)
#endif
out:
movl %ebx, %eax