diff options
Diffstat (limited to 'cpu/bf533')
| -rw-r--r-- | cpu/bf533/bf533_serial.h | 2 | ||||
| -rw-r--r-- | cpu/bf533/cache.S | 144 | ||||
| -rw-r--r-- | cpu/bf533/cplbhdlr.S | 33 | ||||
| -rw-r--r-- | cpu/bf533/cplbmgr.S | 88 | ||||
| -rw-r--r-- | cpu/bf533/cpu.c | 15 | ||||
| -rw-r--r-- | cpu/bf533/flush.S | 30 | ||||
| -rw-r--r-- | cpu/bf533/interrupt.S | 4 | ||||
| -rw-r--r-- | cpu/bf533/serial.c | 10 | ||||
| -rw-r--r-- | cpu/bf533/start.S | 10 |
9 files changed, 165 insertions, 171 deletions
diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index ec63a5e..d430e6c 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005 blackfin.uclinux.org * - * This file is based on + * This file is based on * bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver. * Copyright (C) 2003 Bas Vermeulen <bas@buyways.nl> * BuyWays B.V. (www.buyways.nl) diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index 1822d1f..8fac402 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -22,88 +22,88 @@ ENTRY(blackfin_icache_flush_range) ENTRY(blackfin_dcache_flush_range) R2 = -32; - R2 = R0 & R2; - P0 = R2; - P1 = R1; - CSYNC; + R2 = R0 & R2; + P0 = R2; + P1 = R1; + CSYNC; 1: - FLUSH[P0++]; - CC = P0 < P1(iu); - IF CC JUMP 1b(bp); - FLUSH[P0]; - SSYNC; - RTS; + FLUSH[P0++]; + CC = P0 < P1(iu); + IF CC JUMP 1b(bp); + FLUSH[P0]; + SSYNC; + RTS; ENTRY(_icache_invalidate) ENTRY(invalidate_entire_icache) - [--SP] = ( R7:5); - - P0.L = (IMEM_CONTROL & 0xFFFF); - P0.H = (IMEM_CONTROL >> 16); - R7 = [P0]; - - /* Clear the IMC bit , All valid bits in the instruction - * cache are set to the invalid state - */ - BITCLR(R7,IMC_P); - CLI R6; - SSYNC; /* SSYNC required before invalidating cache. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the instruction cache agian */ - R6 = (IMC | ENICPLB); - R7 = R7 | R6; - - CLI R6; - SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - ( R7:5) = [SP++]; - RTS; + [--SP] = ( R7:5); + + P0.L = (IMEM_CONTROL & 0xFFFF); + P0.H = (IMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the IMC bit , All valid bits in the instruction + * cache are set to the invalid state + */ + BITCLR(R7,IMC_P); + CLI R6; + SSYNC; /* SSYNC required before invalidating cache. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the instruction cache agian */ + R6 = (IMC | ENICPLB); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:5) = [SP++]; + RTS; /* Invalidate the Entire Data cache by * clearing DMC[1:0] bits */ ENTRY(invalidate_entire_dcache) ENTRY(_dcache_invalidate) - [--SP] = ( R7:6); - - P0.L = (DMEM_CONTROL & 0xFFFF); - P0.H = (DMEM_CONTROL >> 16); - R7 = [P0]; - - /* Clear the DMC[1:0] bits, All valid bits in the data - * cache are set to the invalid state - */ - BITCLR(R7,DMC0_P); - BITCLR(R7,DMC1_P); - CLI R6; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - /* Configures the data cache again */ - - R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - R7 = R7 | R6; - - CLI R6; - SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ - .align 8; - [P0] = R7; - SSYNC; - STI R6; - - ( R7:6) = [SP++]; - RTS; + [--SP] = ( R7:6); + + P0.L = (DMEM_CONTROL & 0xFFFF); + P0.H = (DMEM_CONTROL >> 16); + R7 = [P0]; + + /* Clear the DMC[1:0] bits, All valid bits in the data + * cache are set to the invalid state + */ + BITCLR(R7,DMC0_P); + BITCLR(R7,DMC1_P); + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + /* Configures the data cache again */ + + R6 = (ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + R7 = R7 | R6; + + CLI R6; + SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ + .align 8; + [P0] = R7; + SSYNC; + STI R6; + + ( R7:6) = [SP++]; + RTS; ENTRY(blackfin_dcache_invalidate_range) R2 = -32; diff --git a/cpu/bf533/cplbhdlr.S b/cpu/bf533/cplbhdlr.S index b5abbbc..61be5bb 100644 --- a/cpu/bf533/cplbhdlr.S +++ b/cpu/bf533/cplbhdlr.S @@ -1,9 +1,9 @@ -/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. +/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved. * * This file is subject to the terms and conditions of the GNU General Public - * License. + * License. * - * Blackfin BF533/2.6 support : LG Soft India + * Blackfin BF533/2.6 support : LG Soft India */ @@ -16,7 +16,7 @@ .text - + .globl _cplb_hdr; .type _cplb_hdr, STT_FUNC; .extern _cplb_mgr; @@ -76,19 +76,19 @@ is_icplb_miss: #if ( defined (CONFIG_BLKFIN_CACHE) || defined (CONFIG_BLKFIN_DCACHE)) #if ( defined (CONFIG_BLKFIN_CACHE) && !defined (CONFIG_BLKFIN_DCACHE)) - R1 = CPLB_ENABLE_ICACHE; + R1 = CPLB_ENABLE_ICACHE; #endif #if ( !defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) - R1 = CPLB_ENABLE_DCACHE; + R1 = CPLB_ENABLE_DCACHE; #endif #if ( defined (CONFIG_BLKFIN_CACHE) && defined (CONFIG_BLKFIN_DCACHE)) - R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; + R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE; #endif #else R1 = 0; #endif - [--SP] = RETS; + [--SP] = RETS; CALL _cplb_mgr; RETS = [SP++]; CC = R0 == 0; @@ -109,27 +109,27 @@ is_icplb_miss: RTS; unknown: - [--SP] = RETS; + [--SP] = RETS; CALL __unknown_exception_occurred; RETS = [SP++]; JUMP unknown; not_replaced: CC = R0 == CPLB_NO_UNLOCKED; IF !CC JUMP next_check; - [--SP] = RETS; + [--SP] = RETS; CALL __cplb_miss_all_locked; RETS = [SP++]; next_check: CC = R0 == CPLB_NO_ADDR_MATCH; IF !CC JUMP next_check2; - [--SP] = RETS; + [--SP] = RETS; CALL __cplb_miss_without_replacement; RETS = [SP++]; JUMP not_replaced; next_check2: CC = R0 == CPLB_PROT_VIOL; IF !CC JUMP strange_return_from_cplb_mgr; - [--SP] = RETS; + [--SP] = RETS; CALL __cplb_protection_violation; RETS = [SP++]; JUMP not_replaced; @@ -139,8 +139,8 @@ strange_return_from_cplb_mgr: JUMP strange_return_from_cplb_mgr; /************************************ - * Diagnostic exception handlers - */ + * Diagnostic exception handlers + */ __cplb_miss_all_locked: sp += -12; @@ -174,11 +174,11 @@ __unknown_exception_occurred: * other kinds of exceptions, you must replace the * default handler with your own, that handles all the * exceptions you will use. - * + * * Since there's nothing we can do, we just loop here * at what we hope is a suitably informative label. */ - + IDLE; do_not_know_what_to_do: CSYNC; @@ -191,4 +191,3 @@ do_not_know_what_to_do: panic_bfin: RTS; - diff --git a/cpu/bf533/cplbmgr.S b/cpu/bf533/cplbmgr.S index fc3e3a8..7a0b048 100644 --- a/cpu/bf533/cplbmgr.S +++ b/cpu/bf533/cplbmgr.S @@ -3,7 +3,7 @@ * * Blackfin BF533/2.6 support : LG Soft India * Modification: Dec 07 2004 - * 1. Correction in icheck_lock. Valid lock entries were + * 1. Correction in icheck_lock. Valid lock entries were * geting victimized, for instruction cplb replacement. * 2. Setup loop's are modified as now toolchain support's P Indexed * addressing @@ -18,15 +18,15 @@ * * Returns: * CPLB_RELOADED => Successfully updated CPLB table. - * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates - * that the CPLBs in the configuration tablei are badly + * CPLB_NO_UNLOCKED => All CPLBs are locked, so cannot be evicted.This indicates + * that the CPLBs in the configuration tablei are badly * configured, as this should never occur. - * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception, - * is not covered by any of the CPLBs in the configuration + * CPLB_NO_ADDR_MATCH => The address being accessed, that triggered the exception, + * is not covered by any of the CPLBs in the configuration * table. The application isi presumably misbehaving. - * CPLB_PROT_VIOL => The address being accessed, that triggered thei exception, - * was not a first-write to a clean Write Back Data page, - * and so presumably is a genuine violation of the page's + * CPLB_PROT_VIOL => The address being accessed, that triggered thei exception, + * was not a first-write to a clean Write Back Data page, + * and so presumably is a genuine violation of the page's * protection attributes. The application is misbehaving. */ #define ASSEMBLY @@ -35,9 +35,9 @@ #include <asm-blackfin/blackfin.h> #include <asm-blackfin/cplbtab.h> #include <asm-blackfin/cplb.h> - + .text - + .align 2; ENTRY(_cplb_mgr) @@ -51,8 +51,8 @@ ENTRY(_cplb_mgr) /* ICPLB Miss Exception. We need to choose one of the * currently-installed CPLBs, and replace it with one - * from the configuration table. - */ + * from the configuration table. + */ P4.L = (ICPLB_FAULT_ADDR & 0xFFFF); P4.H = (ICPLB_FAULT_ADDR >> 16); @@ -72,7 +72,7 @@ ENTRY(_cplb_mgr) isearch: R1 = [P0-0x100]; /* Address for this CPLB */ - + R0 = [P0++]; /* Info for this CPLB*/ CC = BITTST(R0,0); /* Is the CPLB valid?*/ IF !CC JUMP nomatch; /* Skip it, if not.*/ @@ -94,7 +94,7 @@ nomatch: isearch_done: I0 = R4; /* Fault address we'll search for*/ - + /* set up pointers */ P0.L = (ICPLB_DATA0 & 0xFFFF); P0.H = (ICPLB_DATA0 >> 16); @@ -138,7 +138,7 @@ ifound_victim: P3.H = ipdt_swapcount_table; P3 += -4; icount: - R2 = [P2]; /* address from config table */ + R2 = [P2]; /* address from config table */ P2 += 8; P3 += 8; CC = R2==-1; @@ -153,13 +153,13 @@ icount_done: #endif LC0=R3; LSETUP(is_move,ie_move) LC0; -is_move: +is_move: R0 = [P0]; [P0 - 4] = R0; R0 = [P0 - 0x100]; - [P0-0x104] = R0; + [P0-0x104] = R0; ie_move:P0+=4; - + /* We've made space in the ICPLB table, so that ICPLB15 * is now free to be overwritten. Next, we have to determine * which CPLB we need to install, from the configuration @@ -167,8 +167,8 @@ ie_move:P0+=4; * addresses and page-lengths from the config table, and * determining whether the fault address falls within that * range. - */ - + */ + P2.L = ipdt_table; P2.H = ipdt_table; #ifdef CONFIG_CPLB_INFO @@ -190,7 +190,7 @@ ie_move:P0+=4; */ R1 = ((16<<8)|2); -inext: R4 = [P2++]; /* address from config table */ +inext: R4 = [P2++]; /* address from config table */ R2 = [P2++]; /* data from config table */ #ifdef CONFIG_CPLB_INFO P3 += 8; @@ -201,7 +201,7 @@ inext: R4 = [P2++]; /* address from config table */ /* See if failed address > start address */ CC = R4 <= R0(IU); - IF !CC JUMP inext; + IF !CC JUMP inext; /* extract page size (17:16)*/ R3 = EXTRACT(R2, R1.L) (Z); @@ -250,17 +250,17 @@ inext: R4 = [P2++]; /* address from config table */ /* FAILED CASES*/ no_page_in_table: - ( R7:0,P5:0 ) = [SP++]; - R0 = CPLB_NO_ADDR_MATCH; - RTS; + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_ADDR_MATCH; + RTS; all_locked: - ( R7:0,P5:0 ) = [SP++]; - R0 = CPLB_NO_UNLOCKED; - RTS; + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_NO_UNLOCKED; + RTS; prot_violation: - ( R7:0,P5:0 ) = [SP++]; - R0 = CPLB_PROT_VIOL; - RTS; + ( R7:0,P5:0 ) = [SP++]; + R0 = CPLB_PROT_VIOL; + RTS; dcplb_write: @@ -275,7 +275,7 @@ dcplb_write: P4.H = (DCPLB_STATUS >> 16); P3.L = (DCPLB_DATA0 & 0xFFFF); P3.H = (DCPLB_DATA0 >> 16); - R5 = [P4]; + R5 = [P4]; /* A protection violation can be caused by more than just writes * to a clean WB page, so we have to ensure that: @@ -315,7 +315,7 @@ dcplb_write: R2 <<= R5; /* if was super, check write in super mode*/ R2 = R3 & R2; CC = R2 == 0; - IF CC JUMP prot_violation; + IF CC JUMP prot_violation; /* It's a genuine write-to-clean-page.*/ @@ -333,7 +333,7 @@ dcplb_miss_compare: * config table, that covers the faulting address. */ - P1.L = (DCPLB_DATA15 & 0xFFFF); + P1.L = (DCPLB_DATA15 & 0xFFFF); P1.H = (DCPLB_DATA15 >> 16); P4.L = (DCPLB_FAULT_ADDR & 0xFFFF); @@ -379,7 +379,7 @@ sdsearch2: CC = R2 == 0; /* If none are set, it'll do.*/ IF !CC JUMP skip_stack_check; - R2 = [P0 - 0x104]; /* R2 - PageStart */ + R2 = [P0 - 0x104]; /* R2 - PageStart */ P3.L = page_size_table; /* retrive end address */ P3.H = page_size_table; /* retrive end address */ R3 = 0x2; /* 0th - position, 2 bits -length */ @@ -392,13 +392,13 @@ sdsearch2: R7 = R7 << 0xA; /* in bytes * 1024*/ R7 = R2 + R7; /* R7 - PageEnd */ - R4 = SP; /* Test SP is in range */ + R4 = SP; /* Test SP is in range */ CC = R7 < R4; /* if PageEnd < SP */ IF CC JUMP dfound_victim; R3 = 0x284; /* stack length from start of trap till the point */ /* 20 stack locations for future modifications */ - R4 = R4 + R3; + R4 = R4 + R3; CC = R4 < R2; /* if SP + stacklen < PageStart */ IF CC JUMP dfound_victim; skip_stack_check: @@ -409,7 +409,7 @@ edsearch1: NOP; /* If we got here, we didn't find a DCPLB we considered * replacable, which means all of them were locked. */ - + JUMP all_locked; dfound_victim: @@ -450,14 +450,14 @@ dicount_done: CC = BITTST(R1, 7); /* Is it dirty?*/ IF !CC JUMP Ddoverwrite (BP); /* Nope.*/ CC = BITTST(R1, 14); /* Is it Write-Through?*/ - IF CC JUMP Ddoverwrite; /* Yep*/ + IF CC JUMP Ddoverwrite; /* Yep*/ /* This is a dirty page, so we need to flush all writes * that are pending on the page. */ /* Retrieve the page start address*/ - R0 = [P0 - 0x104]; + R0 = [P0 - 0x104]; [--sp] = rets; CALL dcplb_flush; /* R0==CPLB addr, R1==CPLB data*/ rets = [sp++]; @@ -467,7 +467,7 @@ Ddoverwrite: * overwrite it by moving all the following CPLBs * one space closer to the start. */ - + R1.L = ((DCPLB_DATA15+4) & 0xFFFF); /*DCPLB_DATA15+4*/ R1.H = ((DCPLB_DATA15+4) >> 16); R0 = P0; @@ -485,7 +485,7 @@ Ddoverwrite: ds_move: R0 = [P0++]; /* move data */ [P0 - 8] = R0; - R0 = [P0-0x104] /* move address */ + R0 = [P0-0x104] /* move address */ de_move: [P0-0x108] = R0; /* We've now made space in DCPLB15 for the new CPLB to be @@ -510,7 +510,7 @@ de_moved:NOP; /* An extraction pattern, to retrieve bits 17:16.*/ R1 = (16<<8)|2; -dnext: R4 = [P2++]; /* address */ +dnext: R4 = [P2++]; /* address */ R2 = [P2++]; /* data */ #ifdef CONFIG_CPLB_INFO P3 += 8; @@ -521,7 +521,7 @@ dnext: R4 = [P2++]; /* address */ /* See if failed address > start address */ CC = R4 <= R0(IU); - IF !CC JUMP dnext; + IF !CC JUMP dnext; /* extract page size (17:16)*/ R3 = EXTRACT(R2, R1.L) (Z); diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index 2c139f5..78e2b96 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -41,7 +41,7 @@ #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) -#define ANOMALY_05000158 0x200 +#define ANOMALY_05000158 0x200 #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) @@ -68,7 +68,7 @@ static unsigned int icplb_table[16][2]={ }; static unsigned int dcplb_table[16][2]={ - {0xFFA00000,L1_DMEMORY}, + {0xFFA00000,L1_DMEMORY}, {0x00000000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ {0x00400000,SDRAM_DKERNEL}, /*SDRAM_Page1*/ {0x07C00000,SDRAM_DKERNEL}, /*SDRAM_Page15*/ @@ -83,13 +83,9 @@ static unsigned int dcplb_table[16][2]={ {0x02800000,SDRAM_DGENERIC}, /*SDRAM_Page10*/ {0x02C00000,SDRAM_DGENERIC}, /*SDRAM_Page11*/ {0x03000000,SDRAM_DGENERIC}, /*SDRAM_Page12*/ - {0x20000000,SDRAM_EBIU}, /*For Network */ + {0x20000000,SDRAM_EBIU}, /*For Network */ }; - - - - int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { __asm__ __volatile__ @@ -121,7 +117,7 @@ void icache_enable(void) I0 = (unsigned int *)ICPLB_ADDR0; I1 = (unsigned int *)ICPLB_DATA0; - + for(i=0;i<16;i++){ *I0++ = icplb_table[i][0]; *I1++ = icplb_table[i][1]; @@ -166,13 +162,12 @@ void dcache_enable(void) *I1++ = dcplb_table[i][1]; } cli(); - temp = *(unsigned int *)DMEM_CONTROL; + temp = *(unsigned int *)DMEM_CONTROL; SSYNC(); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE |ENDCPLB |PORT_PREF0|temp; SSYNC(); sti(); } - void dcache_disable(void) { diff --git a/cpu/bf533/flush.S b/cpu/bf533/flush.S index 1f9ec98..9fbdefc 100644 --- a/cpu/bf533/flush.S +++ b/cpu/bf533/flush.S @@ -60,7 +60,7 @@ ENTRY(icplb_flush) [--SP] = LC1; [--SP] = LT1; [--SP] = LB1; - + /* If it's a 1K or 4K page, then it's quickest to * just systematically flush all the addresses in * the page, regardless of whether they're in the @@ -90,7 +90,7 @@ ENTRY(icplb_flush) R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/ R3.H = R4.L << 0 ; /* Save in extraction pattern for later deposit.*/ - + /* So: * R0 = Page start * R1 = Page length (actually, offset into size/prefix tables) @@ -101,7 +101,7 @@ ENTRY(icplb_flush) * sub-bank, looking for dirty, valid tags that match our * address prefix. */ - + P5.L = (ITEST_COMMAND & 0xFFFF); P5.H = (ITEST_COMMAND >> 16); P4.L = (ITEST_DATA0 & 0xFFFF); @@ -119,7 +119,7 @@ ENTRY(icplb_flush) * fetching tags, so we only have to set Set, Bank, * Sub-bank and Way. */ - + P2 = 4; LSETUP (ifs1, ife1) LC1 = P2; ifs1: P0 = 32; /* iterate over all sets*/ @@ -142,7 +142,7 @@ ifs0: R6 = R5 << 5; /* Combine set*/ IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/ /* Tag address matches against page, so this is an entry - * we must flush. + * we must flush. */ R7 >>= 10; /* Mask off the non-address bits*/ @@ -181,11 +181,11 @@ iflush_whole_page: IFLUSH [P0++]; /* because CSYNC can't end loops.*/ LSETUP (isall, ieall) LC0 = P1; isall:IFLUSH [P0++]; -ieall: NOP; +ieall: NOP; SSYNC; JUMP ifinished; -/* This is an external function being called by the user +/* This is an external function being called by the user * application through __flush_cache_all. Currently this function * serves the purpose of flushing all the pending writes in * in the data cache. @@ -222,7 +222,7 @@ skip: R6 += -1; /* This is an internal function to flush all pending * writes in the cache associated with a particular DCPLB. - * + * * R0 - page's start address * R1 - CPLB's data field. */ @@ -236,7 +236,7 @@ ENTRY(dcplb_flush) [--SP] = LC1; [--SP] = LT1; [--SP] = LB1; - + /* If it's a 1K or 4K page, then it's quickest to * just systematically flush all the addresses in * the page, regardless of whether they're in the @@ -250,9 +250,9 @@ ENTRY(dcplb_flush) /* We're only interested in the page's size, so extract * this from the CPLB (bits 17:16), and scale to give an - * offset into the page_size and page_prefix tables. + * offset into the page_size and page_prefix tables. */ - + R1 <<= 14; R1 >>= 30; R1 <<= 2; @@ -260,9 +260,9 @@ ENTRY(dcplb_flush) /* The page could be mapped into Bank A or Bank B, depending * on (a) whether both banks are configured as cache, and * (b) on whether address bit A[x] is set. x is determined - * by DCBS in DMEM_CONTROL + * by DCBS in DMEM_CONTROL */ - + R2 = 0; /* Default to Bank A (Bank B would be 1)*/ P0.L = (DMEM_CONTROL & 0xFFFF); @@ -303,7 +303,7 @@ bank_chosen: * sub-bank, looking for dirty, valid tags that match our * address prefix. */ - + P5.L = (DTEST_COMMAND & 0xFFFF); P5.H = (DTEST_COMMAND >> 16); P4.L = (DTEST_DATA0 & 0xFFFF); @@ -322,7 +322,7 @@ bank_chosen: * fetching tags, so we only have to set Set, Bank, * Sub-bank and Way. */ - + P2 = 2; LSETUP (fs1, fe1) LC1 = P2; fs1: P0 = 64; /* iterate over all sets*/ diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index b4d2579..e780dc6 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -240,7 +240,7 @@ evt_rst: sp += 12; _evt_rst_exit: - rtn; + rtn; irq_panic: r0 = IRQ_EVX; @@ -279,7 +279,7 @@ evt_evt7: evt_evt7_exit: RESTORE_CONTEXT - rti; + rti; .global evt_evt8 evt_evt8: diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 8f0cd16..84ae9d9 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -13,12 +13,12 @@ * Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com> * Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com> * Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com> - * + * * Based on code from 68328 version serial driver imlpementation which was: * Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu> * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com> * Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org> - * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> + * Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com> * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -178,9 +178,9 @@ static void local_put_char(char ch) save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)); - asm("csync;"); + /* Poll for TX Interruput */ + while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)); + asm("csync;"); *pUART_THR = ch; /* putc() */ diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 7414d88..6d58575 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -32,7 +32,7 @@ /* * Note: A change in this file subsequently requires a change in - * board/$(board_name)/config.mk for a valid u-boot.bin + * board/$(board_name)/config.mk for a valid u-boot.bin */ #define ASSEMBLY @@ -82,7 +82,7 @@ _stext: SSYNC; /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd + * DATA and Address resgister shall be zero'd * in initialization, after a reset state */ r1 = 0; /* Data registers zero'd */ @@ -99,7 +99,7 @@ _stext: p3 = 0; p4 = 0; p5 = 0; - + i0 = 0; /* DAG Registers zero'd */ i1 = 0; i2 = 0; @@ -242,9 +242,9 @@ loop1: r1 = [p1]; [p2] = r1; p3=0x4; - p1=p1+p3; + p1=p1+p3; p2=p2+p3; - r2=0x4; + r2=0x4; r0=r0-r2; cc=r0==0x0; if !cc jump loop1; |