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-rw-r--r--cpu/at91rm9200/Makefile43
-rw-r--r--cpu/at91rm9200/config.mk27
-rw-r--r--cpu/at91rm9200/cpu.c177
-rw-r--r--cpu/at91rm9200/interrupts.c236
-rw-r--r--cpu/at91rm9200/serial.c89
-rw-r--r--cpu/at91rm9200/start.S347
6 files changed, 919 insertions, 0 deletions
diff --git a/cpu/at91rm9200/Makefile b/cpu/at91rm9200/Makefile
new file mode 100644
index 0000000..0953c9f
--- /dev/null
+++ b/cpu/at91rm9200/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/at91rm9200/config.mk b/cpu/at91rm9200/config.mk
new file mode 100644
index 0000000..deb7f87
--- /dev/null
+++ b/cpu/at91rm9200/config.mk
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
diff --git a/cpu/at91rm9200/cpu.c b/cpu/at91rm9200/cpu.c
new file mode 100644
index 0000000..f41210b
--- /dev/null
+++ b/cpu/at91rm9200/cpu.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <AT91RM9200.h>
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1(void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+ /*printf("p15/c1 is = %08lx\n", value); */
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
+ /*printf("write %08lx to p15/c1\n", value); */
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ : "=r" (value)
+ :
+ : "memory");
+
+ read_p15_c1();
+}
+
+static void cp_delay(void)
+{
+ volatile int i;
+
+ /* copro seems to need some delay between reading and writing */
+ for (i=0; i<100; i++);
+}
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_IDC (1<<2) /* icache and/or dcache off/on */
+#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
+int cpu_init(void)
+{
+ /*
+ * setup up stack if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START = _armboot_end +
+ CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+ FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+ _armboot_real_end = FIQ_STACK_START + 4;
+#else
+ _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux(void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ * and we set the CPU-speed to 73 MHz - see start.S for details
+ */
+
+ disable_interrupts();
+ return 0;
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+
+#ifdef CFG_SOFT_RESET
+ extern void reset_cpu(ulong addr);
+
+ disable_interrupts();
+ reset_cpu(0);
+#else
+ AT91PS_USART us = AT91C_BASE_US1;
+ AT91PS_PIO pio = AT91C_BASE_PIOA;
+
+ /*shutdown the console to avoid strange chars during reset */
+ us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+
+ /* Clear PA19 to trigger the hard reset */
+ pio->PIO_CODR = 0x00080000;
+ pio->PIO_OER = 0x00080000;
+ pio->PIO_PER = 0x00080000;
+ /* Never reached */
+#endif
+ return 0;
+}
+
+void icache_enable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg | C1_IDC);
+}
+
+void icache_disable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg & ~C1_IDC);
+}
+
+int icache_status(void)
+{
+ return (read_p15_c1() & C1_IDC) != 0;
+ return 0;
+}
+
+void dcache_enable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg | C1_IDC);
+}
+
+void dcache_disable(void)
+{
+ ulong reg;
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg & ~C1_IDC);
+}
+
+int dcache_status(void)
+{
+ return (read_p15_c1() & C1_IDC) != 0;
+ return 0;
+}
diff --git a/cpu/at91rm9200/interrupts.c b/cpu/at91rm9200/interrupts.c
new file mode 100644
index 0000000..a14ef81
--- /dev/null
+++ b/cpu/at91rm9200/interrupts.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <AT91RM9200.h>
+#include <asm/proc-armv/ptrace.h>
+
+extern void reset_cpu(ulong addr);
+
+/* we always count down the max. */
+#define TIMER_LOAD_VAL 0xffff
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (tmr->TC_CV)
+AT91PS_TC tmr;
+
+
+
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+
+
+void bad_mode(void)
+{
+ panic("Resetting CPU ...\n");
+ reset_cpu(0);
+}
+
+void show_regs(struct pt_regs * regs)
+{
+ unsigned long flags;
+const char *processor_modes[]=
+{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
+ "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
+ "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+};
+
+ flags = condition_codes(regs);
+
+ printf("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer(regs),
+ regs->ARM_lr, regs->ARM_sp,
+ regs->ARM_ip, regs->ARM_fp);
+ printf("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9,
+ regs->ARM_r8);
+ printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6,
+ regs->ARM_r5, regs->ARM_r4);
+ printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2,
+ regs->ARM_r1, regs->ARM_r0);
+ printf("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c',
+ flags & CC_V_BIT ? 'V' : 'v');
+ printf(" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled(regs) ? "on" : "off",
+ fast_interrupts_enabled(regs) ? "on" : "off",
+ processor_modes[processor_mode(regs)],
+ thumb_mode(regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction(struct pt_regs *pt_regs)
+{
+ printf("undefined instruction\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_software_interrupt(struct pt_regs *pt_regs)
+{
+ printf("software interrupt\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_prefetch_abort(struct pt_regs *pt_regs)
+{
+ printf("prefetch abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_data_abort(struct pt_regs *pt_regs)
+{
+ printf("data abort\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_not_used(struct pt_regs *pt_regs)
+{
+ printf("not used\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_fiq(struct pt_regs *pt_regs)
+{
+ printf("fast interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+void do_irq(struct pt_regs *pt_regs)
+{
+ printf("interrupt request\n");
+ show_regs(pt_regs);
+ bad_mode();
+}
+
+static ulong timestamp;
+static ulong lastinc;
+
+int interrupt_init (void)
+{
+
+ tmr = AT91C_BASE_TC0;
+
+ /* enables TC1.0 clock */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */
+
+ *AT91C_TCB0_BCR = 0;
+ *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
+ tmr->TC_CCR = AT91C_TC_CLKDIS;
+ tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK; /* set to MCLK/2 */
+
+ tmr->TC_IDR = ~0ul;
+ tmr->TC_RC = TIMER_LOAD_VAL;
+ lastinc = TIMER_LOAD_VAL;
+ tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
+ timestamp = 0;
+ return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+ udelay_masked(usec);
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastinc = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = READ_TIMER;
+ if (now >= lastinc)
+ {
+ /* normal mode */
+ timestamp += now - lastinc;
+ } else {
+ /* we have an overflow ... */
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
+ }
+ lastinc = now;
+
+ return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 1000;
+
+ reset_timer_masked();
+
+ while(get_timer_masked() < tmo);
+ /*NOP*/;
+}
+
+
diff --git a/cpu/at91rm9200/serial.c b/cpu/at91rm9200/serial.c
new file mode 100644
index 0000000..565cd3d
--- /dev/null
+++ b/cpu/at91rm9200/serial.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <AT91RM9200.h>
+
+/* ggi thunder */
+AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+
+void serial_setbrg(void)
+ {
+ DECLARE_GLOBAL_DATA_PTR;
+ int baudrate;
+
+ if ((baudrate = gd->bd->bi_baudrate) <= 0)
+ baudrate = CONFIG_BAUDRATE;
+ us->US_BRGR = 33 /* AT91C_MASTER_CLOCK / baudrate / 16 */; /* hardcode so no __divsi3 */
+ }
+
+int serial_init(void)
+ {
+ /* make any port initializations specific to this port */
+ *AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */
+ *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */
+ serial_setbrg();
+
+ us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX;
+ us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+ us->US_MR = ( AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT );
+ us->US_IMR = ~0ul;
+ return (0);
+ }
+
+void serial_putc(const char c)
+ {
+ if (c == '\n')
+ serial_putc('\r');
+ while( (us->US_CSR & AT91C_US_TXRDY) == 0 )
+ ;
+ us->US_THR=c;
+ }
+
+void
+serial_puts (const char *s)
+ {
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+ }
+
+int serial_getc(void)
+ {
+ while( (us->US_CSR & AT91C_US_RXRDY) == 0 );
+ return us->US_RHR;
+ }
+
+int serial_tstc(void)
+ {
+ return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY);
+ }
diff --git a/cpu/at91rm9200/start.S b/cpu/at91rm9200/start.S
new file mode 100644
index 0000000..9b3e7aa
--- /dev/null
+++ b/cpu/at91rm9200/start.S
@@ -0,0 +1,347 @@
+/*
+ * armboot - Startup Code for ARM720 CPU-core
+ *
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+
+#include "config.h"
+#include "version.h"
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+ .word armboot_end_data
+/*
+ * Note: armboot_end is defined by the (board-dependent) linker script
+ */
+.globl _armboot_end
+_armboot_end:
+ .word armboot_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+ .word 0x0badc0de
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0x13
+ msr cpsr,r0
+
+ /*
+ * relocate exeception table
+ */
+ ldr r0, =_start
+ ldr r1, =0x0
+ mov r2, #16
+copyex:
+ subs r2, r2, #1
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ bne copyex
+
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+#ifdef CONFIG_INIT_CRITICAL
+ bl cpu_init_crit
+#endif
+
+ /* set up the stack */
+ ldr r0, _armboot_end
+ add r0, r0, #CONFIG_STACKSIZE
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+ ldr pc,_start_armboot
+
+_start_armboot: .word start_armboot
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ *************************************************************************
+ */
+
+cpu_init_crit:
+ # actually do nothing for now!
+ mov pc, lr
+
+
+
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+#define I_BIT 0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+
+ ldr r2, _armboot_end
+ add r2, r2, #CONFIG_STACKSIZE
+ sub r2, r2, #8
+ ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
+ add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
+ mov r0, sp
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} @ Calling r0-r12
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ @ Calling SP, LR
+ str lr, [r8, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r8, #4] @ Save CPSR
+ str r0, [r8, #8] @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_end @ setup our mode stack
+ add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
+ sub r13, r13, #8
+
+ str lr, [r13] @ save caller lr / spsr
+ mrs lr, spsr
+ str lr, [r13, #4]
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ msr spsr_c, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+ .align 5
+.globl reset_cpu
+reset_cpu:
+ mov pc, r0
generated by cgit v1.1 at 2024-11-21 22:19:12 +0000