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-rw-r--r--cpu/arm926ejs/davinci/Makefile2
-rw-r--r--cpu/arm926ejs/davinci/i2c.c334
-rw-r--r--cpu/arm926ejs/davinci/nand.c475
-rw-r--r--cpu/arm926ejs/omap/timer.c2
4 files changed, 2 insertions, 811 deletions
diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index 0f77f40..ed24e65 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
-COBJS = timer.o ether.o lxt972.o dp83848.o i2c.o nand.o
+COBJS = timer.o ether.o lxt972.o dp83848.o
SOBJS = lowlevel_init.o reset.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm926ejs/davinci/i2c.c b/cpu/arm926ejs/davinci/i2c.c
deleted file mode 100644
index 3ba20ef..0000000
--- a/cpu/arm926ejs/davinci/i2c.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * TI DaVinci (TMS320DM644x) I2C driver.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * --------------------------------------------------------
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#ifdef CONFIG_DRIVER_DAVINCI_I2C
-
-#include <i2c.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/i2c_defs.h>
-
-#define CHECK_NACK() \
- do {\
- if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
- REG(I2C_CON) = 0;\
- return(1);\
- }\
- } while (0)
-
-
-static int wait_for_bus(void)
-{
- int stat, timeout;
-
- REG(I2C_STAT) = 0xffff;
-
- for (timeout = 0; timeout < 10; timeout++) {
- if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
- REG(I2C_STAT) = 0xffff;
- return(0);
- }
-
- REG(I2C_STAT) = stat;
- udelay(50000);
- }
-
- REG(I2C_STAT) = 0xffff;
- return(1);
-}
-
-
-static int poll_i2c_irq(int mask)
-{
- int stat, timeout;
-
- for (timeout = 0; timeout < 10; timeout++) {
- udelay(1000);
- stat = REG(I2C_STAT);
- if (stat & mask) {
- return(stat);
- }
- }
-
- REG(I2C_STAT) = 0xffff;
- return(stat | I2C_TIMEOUT);
-}
-
-
-void flush_rx(void)
-{
- int dummy;
-
- while (1) {
- if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
- break;
-
- dummy = REG(I2C_DRR);
- REG(I2C_STAT) = I2C_STAT_RRDY;
- udelay(1000);
- }
-}
-
-
-void i2c_init(int speed, int slaveadd)
-{
- u_int32_t div, psc;
-
- if (REG(I2C_CON) & I2C_CON_EN) {
- REG(I2C_CON) = 0;
- udelay (50000);
- }
-
- psc = 2;
- div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
- REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
- REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
- REG(I2C_SCLH) = div - REG(I2C_SCLL);
-
- REG(I2C_OA) = slaveadd;
- REG(I2C_CNT) = 0;
-
- /* Interrupts must be enabled or I2C module won't work */
- REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
- I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
-
- /* Now enable I2C controller (get it out of reset) */
- REG(I2C_CON) = I2C_CON_EN;
-
- udelay(1000);
-}
-
-
-int i2c_probe(u_int8_t chip)
-{
- int rc = 1;
-
- if (chip == REG(I2C_OA)) {
- return(rc);
- }
-
- REG(I2C_CON) = 0;
- if (wait_for_bus()) {return(1);}
-
- /* try to read one byte from current (or only) address */
- REG(I2C_CNT) = 1;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
- udelay (50000);
-
- if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
- rc = 0;
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- } else {
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CON) |= I2C_CON_STP;
- udelay(20000);
- if (wait_for_bus()) {return(1);}
- }
-
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- return(rc);
-}
-
-
-int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
-{
- u_int32_t tmp;
- int i;
-
- if ((alen < 0) || (alen > 2)) {
- printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
- return(1);
- }
-
- if (wait_for_bus()) {return(1);}
-
- if (alen != 0) {
- /* Start address phase */
- tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
- REG(I2C_CNT) = alen;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
-
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- switch (alen) {
- case 2:
- /* Send address MSByte */
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = (addr >> 8) & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
- /* No break, fall through */
- case 1:
- /* Send address LSByte */
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = addr & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
-
- CHECK_NACK();
-
- if (!(tmp & I2C_STAT_ARDY)) {
- REG(I2C_CON) = 0;
- return(1);
- }
- }
- }
-
- /* Address phase is over, now read 'len' bytes and stop */
- tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
- REG(I2C_CNT) = len & 0xffff;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
-
- for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
-
- CHECK_NACK();
-
- if (tmp & I2C_STAT_RRDY) {
- buf[i] = REG(I2C_DRR);
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
- }
-
- tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- if (!(tmp & I2C_STAT_SCD)) {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- REG(I2C_CON) = 0;
-
- return(0);
-}
-
-
-int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
-{
- u_int32_t tmp;
- int i;
-
- if ((alen < 0) || (alen > 2)) {
- printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
- return(1);
- }
- if (len < 0) {
- printf("%s(): bogus length %x\n", __FUNCTION__, len);
- return(1);
- }
-
- if (wait_for_bus()) {return(1);}
-
- /* Start address phase */
- tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
- REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
- REG(I2C_SA) = chip;
- REG(I2C_CON) = tmp;
-
- switch (alen) {
- case 2:
- /* Send address MSByte */
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = (addr >> 8) & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
- /* No break, fall through */
- case 1:
- /* Send address LSByte */
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = addr & 0xff;
- } else {
- REG(I2C_CON) = 0;
- return(1);
- }
- }
-
- for (i = 0; i < len; i++) {
- tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- if (tmp & I2C_STAT_XRDY) {
- REG(I2C_DXR) = buf[i];
- } else {
- return(1);
- }
- }
-
- tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
-
- CHECK_NACK();
-
- if (!(tmp & I2C_STAT_SCD)) {
- REG(I2C_CON) = 0;
- return(1);
- }
-
- flush_rx();
- REG(I2C_STAT) = 0xffff;
- REG(I2C_CNT) = 0;
- REG(I2C_CON) = 0;
-
- return(0);
-}
-
-#endif /* CONFIG_DRIVER_DAVINCI_I2C */
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
deleted file mode 100644
index 014e2b0..0000000
--- a/cpu/arm926ejs/davinci/nand.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/*
- * NAND driver for TI DaVinci based boards.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
- */
-
-/*
- *
- * linux/drivers/mtd/nand/nand_davinci.c
- *
- * NAND Flash Driver
- *
- * Copyright (C) 2006 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- * ----------------------------------------------------------------------------
- *
- * Overview:
- * This is a device driver for the NAND flash device found on the
- * DaVinci board which utilizes the Samsung k9k2g08 part.
- *
- Modifications:
- ver. 1.0: Feb 2005, Vinod/Sudhakar
- -
- *
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_USE_NAND
-#if !defined(CONFIG_NAND_LEGACY)
-
-#include <nand.h>
-#include <asm/arch/nand_defs.h>
-#include <asm/arch/emif_defs.h>
-
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
-
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_CLE )
- IO_ADDR_W |= MASK_CLE;
- if ( ctrl & NAND_ALE )
- IO_ADDR_W |= MASK_ALE;
- this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-/* Set WP on deselect, write enable on select */
-static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
-{
-#define GPIO_SET_DATA01 0x01c67018
-#define GPIO_CLR_DATA01 0x01c6701c
-#define GPIO_NAND_WP (1 << 4)
-#ifdef SONATA_BOARD_GPIOWP
- if (chip < 0) {
- REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
- } else {
- REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
- }
-#endif
-}
-
-#ifdef CONFIG_SYS_NAND_HW_ECC
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-/* Linux-compatible ECC uses MTD defaults. */
-/* These layouts are not compatible with Linux or RBL/UBL. */
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
-static struct nand_ecclayout davinci_nand_ecclayout = {
- .eccbytes = 12,
- .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
- .oobfree = {
- {.offset = 2, .length = 6},
- {.offset = 12, .length = 12},
- {.offset = 28, .length = 12},
- {.offset = 44, .length = 12},
- {.offset = 60, .length = 4}
- }
-};
-#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
-static struct nand_ecclayout davinci_nand_ecclayout = {
- .eccbytes = 3,
- .eccpos = {0, 1, 2},
- .oobfree = {
- {.offset = 6, .length = 2},
- {.offset = 8, .length = 8}
- }
-};
-#else
-#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
-#endif
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-
-static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- emifregs emif_addr;
- int dummy;
-
- emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- dummy = emif_addr->NANDF1ECC;
- dummy = emif_addr->NANDF2ECC;
- dummy = emif_addr->NANDF3ECC;
- dummy = emif_addr->NANDF4ECC;
-
- emif_addr->NANDFCR |= (1 << 8);
-}
-
-static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
-{
- u_int32_t ecc = 0;
- emifregs emif_base_addr;
-
- emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- if (region == 1)
- ecc = emif_base_addr->NANDF1ECC;
- else if (region == 2)
- ecc = emif_base_addr->NANDF2ECC;
- else if (region == 3)
- ecc = emif_base_addr->NANDF3ECC;
- else if (region == 4)
- ecc = emif_base_addr->NANDF4ECC;
-
- return(ecc);
-}
-
-static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
-{
- u_int32_t tmp;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
- /*
- * This is not how you should read ECCs on large page Davinci devices.
- * The region parameter gets you ECCs for flash chips on different chip
- * selects, not the 4x512 byte pages in a 2048 byte page.
- *
- * Preserved for backwards compatibility though.
- */
-
- int region, n;
- struct nand_chip *this = mtd->priv;
-
- n = (this->ecc.size/512);
-
- region = 1;
- while (n--) {
- tmp = nand_davinci_readecc(mtd, region);
- *ecc_code++ = tmp;
- *ecc_code++ = tmp >> 16;
- *ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
- region++;
- }
-#else
- const int region = 1;
-
- tmp = nand_davinci_readecc(mtd, region);
-
- /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
- * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
- tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
-
- /* Invert so that erased block ECC is correct */
- tmp = ~tmp;
-
- *ecc_code++ = tmp;
- *ecc_code++ = tmp >> 8;
- *ecc_code++ = tmp >> 16;
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
- return(0);
-}
-
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
-static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
-{
- u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
-
- ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
- ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
- ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
-}
-
-static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
-{
- u_int32_t i;
- u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
- u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
- u_int8_t ecc_bit[24];
- u_int8_t ecc_sum = 0;
- u_int8_t find_bit = 0;
- u_int32_t find_byte = 0;
- int is_ecc_ff;
-
- is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
-
- nand_davinci_gen_true_ecc(ecc_nand);
- nand_davinci_gen_true_ecc(ecc_calc);
-
- for (i = 0; i <= 2; i++) {
- *(ecc_nand + i) = ~(*(ecc_nand + i));
- *(ecc_calc + i) = ~(*(ecc_calc + i));
- }
-
- for (i = 0; i < 8; i++) {
- tmp0_bit[i] = *ecc_nand % 2;
- *ecc_nand = *ecc_nand / 2;
- }
-
- for (i = 0; i < 8; i++) {
- tmp1_bit[i] = *(ecc_nand + 1) % 2;
- *(ecc_nand + 1) = *(ecc_nand + 1) / 2;
- }
-
- for (i = 0; i < 8; i++) {
- tmp2_bit[i] = *(ecc_nand + 2) % 2;
- *(ecc_nand + 2) = *(ecc_nand + 2) / 2;
- }
-
- for (i = 0; i < 8; i++) {
- comp0_bit[i] = *ecc_calc % 2;
- *ecc_calc = *ecc_calc / 2;
- }
-
- for (i = 0; i < 8; i++) {
- comp1_bit[i] = *(ecc_calc + 1) % 2;
- *(ecc_calc + 1) = *(ecc_calc + 1) / 2;
- }
-
- for (i = 0; i < 8; i++) {
- comp2_bit[i] = *(ecc_calc + 2) % 2;
- *(ecc_calc + 2) = *(ecc_calc + 2) / 2;
- }
-
- for (i = 0; i< 6; i++)
- ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
-
- for (i = 0; i < 8; i++)
- ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
-
- for (i = 0; i < 8; i++)
- ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
-
- ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
- ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
-
- for (i = 0; i < 24; i++)
- ecc_sum += ecc_bit[i];
-
- switch (ecc_sum) {
- case 0:
- /* Not reached because this function is not called if
- ECC values are equal */
- return 0;
- case 1:
- /* Uncorrectable error */
- MTDDEBUG (MTD_DEBUG_LEVEL0,
- "ECC UNCORRECTED_ERROR 1\n");
- return(-1);
- case 12:
- /* Correctable error */
- find_byte = (ecc_bit[23] << 8) +
- (ecc_bit[21] << 7) +
- (ecc_bit[19] << 6) +
- (ecc_bit[17] << 5) +
- (ecc_bit[15] << 4) +
- (ecc_bit[13] << 3) +
- (ecc_bit[11] << 2) +
- (ecc_bit[9] << 1) +
- ecc_bit[7];
-
- find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
-
- MTDDEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC "
- "error at offset: %d, bit: %d\n",
- find_byte, find_bit);
-
- page_data[find_byte] ^= (1 << find_bit);
-
- return(0);
- default:
- if (is_ecc_ff) {
- if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
- return(0);
- }
- MTDDEBUG (MTD_DEBUG_LEVEL0,
- "UNCORRECTED_ERROR default\n");
- return(-1);
- }
-}
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
-
-static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
-{
- struct nand_chip *this = mtd->priv;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
- int block_count = 0, i, rc;
-
- block_count = (this->ecc.size/512);
- for (i = 0; i < block_count; i++) {
- if (memcmp(read_ecc, calc_ecc, 3) != 0) {
- rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
- if (rc < 0) {
- return(rc);
- }
- }
- read_ecc += 3;
- calc_ecc += 3;
- dat += 512;
- }
-#else
- u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
- (read_ecc[2] << 16);
- u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
- (calc_ecc[2] << 16);
- u_int32_t diff = ecc_calc ^ ecc_nand;
-
- if (diff) {
- if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
- /* Correctable error */
- if ((diff >> (12 + 3)) < this->ecc.size) {
- uint8_t find_bit = 1 << ((diff >> 12) & 7);
- uint32_t find_byte = diff >> (12 + 3);
-
- dat[find_byte] ^= find_bit;
- MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
- "bit ECC error at offset: %d, bit: "
- "%d\n", find_byte, find_bit);
- return 1;
- } else {
- return -1;
- }
- } else if (!(diff & (diff - 1))) {
- /* Single bit ECC error in the ECC itself,
- nothing to fix */
- MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
- "ECC.\n");
- return 1;
- } else {
- /* Uncorrectable error */
- MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
- return -1;
- }
- }
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
- return(0);
-}
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-
-static int nand_davinci_dev_ready(struct mtd_info *mtd)
-{
- emifregs emif_addr;
-
- emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- return(emif_addr->NANDFSR & 0x1);
-}
-
-static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
-{
- while(!nand_davinci_dev_ready(mtd)) {;}
- *NAND_CE0CLE = NAND_STATUS;
- return(*NAND_CE0DATA);
-}
-
-static void nand_flash_init(void)
-{
- u_int32_t acfg1 = 0x3ffffffc;
- u_int32_t acfg2 = 0x3ffffffc;
- u_int32_t acfg3 = 0x3ffffffc;
- u_int32_t acfg4 = 0x3ffffffc;
- emifregs emif_regs;
-
- /*------------------------------------------------------------------*
- * NAND FLASH CHIP TIMEOUT @ 459 MHz *
- * *
- * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
- * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
- * *
- *------------------------------------------------------------------*/
- acfg1 = 0
- | (0 << 31 ) /* selectStrobe */
- | (0 << 30 ) /* extWait */
- | (1 << 26 ) /* writeSetup 10 ns */
- | (3 << 20 ) /* writeStrobe 40 ns */
- | (1 << 17 ) /* writeHold 10 ns */
- | (1 << 13 ) /* readSetup 10 ns */
- | (5 << 7 ) /* readStrobe 60 ns */
- | (1 << 4 ) /* readHold 10 ns */
- | (3 << 2 ) /* turnAround ?? ns */
- | (0 << 0 ) /* asyncSize 8-bit bus */
- ;
-
- emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
-
- emif_regs->AWCCR |= 0x10000000;
- emif_regs->AB1CR = acfg1; /* 0x08244128 */;
- emif_regs->AB2CR = acfg2;
- emif_regs->AB3CR = acfg3;
- emif_regs->AB4CR = acfg4;
- emif_regs->NANDFCR = 0x00000101;
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
- nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
- nand->chip_delay = 0;
- nand->select_chip = nand_davinci_select_chip;
-#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
- nand->options = NAND_USE_FLASH_BBT;
-#endif
-#ifdef CONFIG_SYS_NAND_HW_ECC
- nand->ecc.mode = NAND_ECC_HW;
-#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
- nand->ecc.layout = &davinci_nand_ecclayout;
-#ifdef CONFIG_SYS_NAND_LARGEPAGE
- nand->ecc.size = 2048;
- nand->ecc.bytes = 12;
-#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
-#else
-#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
-#endif
-#else
- nand->ecc.size = 512;
- nand->ecc.bytes = 3;
-#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
- nand->ecc.calculate = nand_davinci_calculate_ecc;
- nand->ecc.correct = nand_davinci_correct_data;
- nand->ecc.hwctl = nand_davinci_enable_hwecc;
-#else
- nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* CONFIG_SYS_NAND_HW_ECC */
-
- /* Set address of hardware control function */
- nand->cmd_ctrl = nand_davinci_hwcontrol;
-
- nand->dev_ready = nand_davinci_dev_ready;
- nand->waitfunc = nand_davinci_waitfunc;
-
- nand_flash_init();
-
- return(0);
-}
-
-#else
-#error "U-Boot legacy NAND support not available for DaVinci chips"
-#endif
-#endif /* CONFIG_SYS_USE_NAND */
diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
index 49e74ab..bedc2e7 100644
--- a/cpu/arm926ejs/omap/timer.c
+++ b/cpu/arm926ejs/omap/timer.c
@@ -52,7 +52,7 @@ int timer_init (void)
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
generated by cgit v1.1 at 2024-11-22 10:28:01 +0000