diff options
Diffstat (limited to 'cpu/arm926ejs')
| -rw-r--r-- | cpu/arm926ejs/mx28/Makefile | 47 | ||||
| -rw-r--r-- | cpu/arm926ejs/mx28/config.mk | 2 | ||||
| -rw-r--r-- | cpu/arm926ejs/mx28/reset.S | 43 | ||||
| -rw-r--r-- | cpu/arm926ejs/mx28/spi.c | 255 | ||||
| -rw-r--r-- | cpu/arm926ejs/mx28/timer.c | 245 |
5 files changed, 592 insertions, 0 deletions
diff --git a/cpu/arm926ejs/mx28/Makefile b/cpu/arm926ejs/mx28/Makefile new file mode 100644 index 0000000..3b23886 --- /dev/null +++ b/cpu/arm926ejs/mx28/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o spi.o +SOBJS = reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx28/config.mk b/cpu/arm926ejs/mx28/config.mk new file mode 100644 index 0000000..b524ad1 --- /dev/null +++ b/cpu/arm926ejs/mx28/config.mk @@ -0,0 +1,2 @@ +PLATFORM_CPPFLAGS += -march=armv5te +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,)
\ No newline at end of file diff --git a/cpu/arm926ejs/mx28/reset.S b/cpu/arm926ejs/mx28/reset.S new file mode 100644 index 0000000..324c384 --- /dev/null +++ b/cpu/arm926ejs/mx28/reset.S @@ -0,0 +1,43 @@ +/* + * Processor reset for Freescale MX28 SoC. + * + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * ----------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.globl reset_cpu +reset_cpu: + ldr r0, POWER_CHARGE + mov r1, #0x0 + str r1, [r0] + ldr r0, POWER_MINPWR + str r1, [r0] + ldr r0, CLKCTRL_RESET + mov r1, #0x1 + str r1, [r0] +_loop_forever: + b _loop_forever + +POWER_MINPWR: + .word 0x80044020 +POWER_CHARGE: + .word 0x80044030 +CLKCTRL_RESET: + .word 0x80040120 + diff --git a/cpu/arm926ejs/mx28/spi.c b/cpu/arm926ejs/mx28/spi.c new file mode 100644 index 0000000..cad2569 --- /dev/null +++ b/cpu/arm926ejs/mx28/spi.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2008 Embedded Alley Solutions Inc. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Freescale MX28 SSP/SPI driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <asm/arch/spi.h> + +#define SPI_NUM_BUSES 2 +#define SPI_NUM_SLAVES 3 + +/* Initalized in spi_init() depending on SSP port configuration */ +static unsigned long ssp_bases[SPI_NUM_BUSES]; + +/* Set in spi_set_cfg() depending on which SSP port is being used */ +static unsigned long ssp_base = SSP1_BASE; + +/* + * Init SSP port: SSP1 (@bus = 0) or SSP2 (@bus == 1) + */ +static void ssp_spi_init(unsigned int bus) +{ + u32 spi_div; + u32 val = 0; + + if (bus >= SPI_NUM_BUSES) { + printf("SPI bus %d doesn't exist\n", bus); + return; + } + + ssp_base = ssp_bases[bus]; + + /* Reset block */ + + /* Clear SFTRST */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_SFTRST) + ; + + /* Clear CLKGATE */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE); + + /* Set SFTRST and wait until CLKGATE is set */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + while (!(REG_RD(ssp_base + SSP_CTRL0) & CTRL0_CLKGATE)) + ; + + /* Clear SFTRST and CLKGATE */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_SFTRST); + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_CLKGATE); + + /* + * Set CLK to desired value + */ + + spi_div = ((CONFIG_SSP_CLK>>1) + CONFIG_SPI_CLK - 1) / CONFIG_SPI_CLK; + val = (2 << TIMING_CLOCK_DIVIDE) | ((spi_div - 1) << TIMING_CLOCK_RATE); + REG_WR(ssp_base + SSP_TIMING, val); + + /* Set transfer parameters */ + + /* Set SSP SPI Master mode and word length to 8 bit */ + REG_WR(ssp_base + SSP_CTRL1, WORD_LENGTH8 | SSP_MODE_SPI); + + /* Set BUS_WIDTH to 1 bit and XFER_COUNT to 1 byte */ + REG_WR(ssp_base + SSP_CTRL0, + BUS_WIDTH_SPI1 | (0x1 << CTRL0_XFER_COUNT)); + + /* + * Set BLOCK_SIZE and BLOCK_COUNT to 0, so that XFER_COUNT + * reflects number of bytes to send. Disalbe other bits as + * well + */ + REG_WR(ssp_base + SSP_CMD0, 0x0); +} + +/* + * Init SSP ports, must be called first and only once + */ +void spi_init(void) +{ +#ifdef CONFIG_SPI_SSP1 + ssp_bases[0] = SSP1_BASE; + ssp_spi_init(0); +#endif + +#ifdef CONFIG_SPI_SSP2 + ssp_bases[1] = SSP2_BASE; + ssp_spi_init(1); +#endif +} + +void spi_set_cfg(unsigned int bus, unsigned int cs, unsigned long mode) +{ + u32 clr_mask = 0; + u32 set_mask = 0; + + if (bus >= SPI_NUM_BUSES || cs >= SPI_NUM_SLAVES) { + printf("SPI device %d:%d doesn't exist", bus, cs); + return; + } + + if (ssp_bases[bus] == 0) { + printf("SSP port %d isn't in SPI mode\n", bus + 1); + return; + } + + /* Set SSP port to use */ + ssp_base = ssp_bases[bus]; + + /* Set phase and polarity: HW_SSP_CTRL1 */ + if (mode & SPI_PHASE) + set_mask |= CTRL1_PHASE; + else + clr_mask |= CTRL1_PHASE; + + if (mode & SPI_POLARITY) + set_mask |= CTRL1_POLARITY; + else + clr_mask |= CTRL1_POLARITY; + + REG_SET(ssp_base + SSP_CTRL1, set_mask); + REG_CLR(ssp_base + SSP_CTRL1, clr_mask); + + /* Set SSn number: HW_SSP_CTRL0 */ + REG_CLR(ssp_base + SSP_CTRL0, SPI_CS_CLR_MASK); + + switch (cs) { + case 0: + set_mask = SPI_CS0; + break; + case 1: + set_mask = SPI_CS1; + break; + case 2: + set_mask = SPI_CS2; + break; + } + + REG_SET(ssp_base + SSP_CTRL0, set_mask); +} + +/* Read single data byte */ +static unsigned char spi_read(void) +{ + unsigned char b = 0; + + /* Set XFER_LENGTH to 1 */ + REG_CLR(ssp_base + SSP_CTRL0, 0xffff); + REG_SET(ssp_base + SSP_CTRL0, 1); + + /* Enable READ mode */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_READ); + + /* Set RUN bit */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN); + + + /* Set transfer */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER); + + while (REG_RD(ssp_base + SSP_STATUS) & STATUS_FIFO_EMPTY) + ; + + /* Read data byte */ + b = REG_RD(ssp_base + SSP_DATA) & 0xff; + + /* Wait until RUN bit is cleared */ + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN) + ; + + return b; +} + +/* Write single data byte */ +static void spi_write(unsigned char b) +{ + /* Set XFER_LENGTH to 1 */ + REG_CLR(ssp_base + SSP_CTRL0, 0xffff); + REG_SET(ssp_base + SSP_CTRL0, 1); + + /* Enable WRITE mode */ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_READ); + + /* Set RUN bit */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_RUN); + + /* Write data byte */ + REG_WR(ssp_base + SSP_DATA, b); + + /* Set transfer */ + REG_SET(ssp_base + SSP_CTRL0, CTRL0_DATA_XFER); + + /* Wait until RUN bit is cleared */ + while (REG_RD(ssp_base + SSP_CTRL0) & CTRL0_RUN) + ; +} + +static void spi_lock_cs(void) +{ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC); + REG_SET(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS); +} + +static void spi_unlock_cs(void) +{ + REG_CLR(ssp_base + SSP_CTRL0, CTRL0_LOCK_CS); + REG_SET(ssp_base + SSP_CTRL0, CTRL0_IGNORE_CRC); +} + +void spi_txrx(const char *dout, unsigned int tx_len, char *din, + unsigned int rx_len, unsigned long flags) +{ + int i; + + if (tx_len == 0 && rx_len == 0) + return; + + if (flags & SPI_START) + spi_lock_cs(); + + for (i = 0; i < tx_len; i++) { + + /* Check if it is last data byte to transfer */ + if (flags & SPI_STOP && rx_len == 0 && i == tx_len - 1) + spi_unlock_cs(); + + spi_write(dout[i]); + } + + for (i = 0; i < rx_len; i++) { + + /* Check if it is last data byte to transfer */ + if (flags & SPI_STOP && i == rx_len - 1) + spi_unlock_cs(); + + din[i] = spi_read(); + } +} diff --git a/cpu/arm926ejs/mx28/timer.c b/cpu/arm926ejs/mx28/timer.c new file mode 100644 index 0000000..ffad4d8 --- /dev/null +++ b/cpu/arm926ejs/mx28/timer.c @@ -0,0 +1,245 @@ +/* + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/mx28.h> +#include <asm/arch/timrot.h> + +#define CONFIG_USE_TIMER0 + +#if defined(CONFIG_USE_TIMER0) +#define TIMCTRL TIMCTRL0 +#define TIMCOUNT TIMCOUNT0 +#elif defined(CONFIG_USE_TIMER1) +#define TIMCTRL TIMCTRL1 +#define TIMCOUNT TIMCOUNT1 +#elif defined(CONFIG_USE_TIMER2) +#define TIMCTRL TIMCTRL2 +#define TIMCOUNT TIMCOUNT2 +#elif defined(CONFIG_USE_TIMER3) +#define TIMCTRL TIMCTRL3 +#define TIMCOUNT TIMCOUNT3 +#else +#error "Define which STMP378x timer to use" +#endif + +#define TIMER_LOAD_VAL 0x0000ffff + +/* macro to read the 16 bit timer */ +#define READ_TIMER ((REG_RD(TIMROT_BASE + TIMCOUNT) & 0xffff0000) >> 16) + +static ulong timestamp; +static ulong lastdec; + +int timer_init(void) +{ + u32 val; + + /* + * Reset Timers and Rotary Encoder module + */ + + /* Clear SFTRST */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); + while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31)) + ; + + /* Clear CLKGATE */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); + + /* Set SFTRST and wait until CLKGATE is set */ + REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31); + while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30))) + ; + + /* Clear SFTRST and CLKGATE */ + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31); + REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30); + + /* + * Now initialize timer + */ + + /* Set fixed_count to 0 */ + REG_WR(TIMROT_BASE + TIMCOUNT, 0); + + /* set UPDATE bit and 1Khz frequency */ + REG_WR(TIMROT_BASE + TIMCTRL, + TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ); + + /* Set fixed_count to maximal value */ + REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay(unsigned long usec) +{ + ulong tmo, tmp; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer(0); + /* get current timestamp */ + if ((tmo + tmp + 1) < tmp) + /* if setting this fordward will roll time stamp */ + reset_timer_masked(); + /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; + /* else, set advancing stamp wake up time */ + + while (get_timer_masked() < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; + /* move stamp fordward with absoulte diff ticks */ + } else { + /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll + * and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now + 1; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked(unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { + /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; + /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; + /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; + /* finish normalize. */ + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked() + tmo; + + do { + ulong now = get_timer_masked(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} |