1 files changed, 75 insertions, 0 deletions
diff --git a/cpu/arm926ejs/at91/at91sam9261_spi.c b/cpu/arm926ejs/at91/at91sam9261_spi.c
new file mode 100644
index 0000000..f70320d
--- /dev/null
+++ b/cpu/arm926ejs/at91/at91sam9261_spi.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_gpio_output(AT91_PIN_PA3, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_gpio_output(AT91_PIN_PA4, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_gpio_output(AT91_PIN_PA5, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_gpio_output(AT91_PIN_PA6, 1);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_set_A_periph(AT91_PIN_PB30, 0);	/* SPI1_MISO */
+	at91_set_A_periph(AT91_PIN_PB31, 0);	/* SPI1_MOSI */
+	at91_set_A_periph(AT91_PIN_PB29, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_gpio_output(AT91_PIN_PB28, 1);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_gpio_output(AT91_PIN_PA24, 1);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_gpio_output(AT91_PIN_PA25, 1);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_gpio_output(AT91_PIN_PA26, 1);
+	}
+}