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Diffstat (limited to 'cpu/arm720t/cpu.c')
-rw-r--r--cpu/arm720t/cpu.c58
1 files changed, 11 insertions, 47 deletions
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 8166982..d178e41 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -34,6 +34,7 @@
#include <command.h>
#include <clps7111.h>
#include <asm/hardware.h>
+#include <asm/system.h>
int cpu_init (void)
{
@@ -98,33 +99,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
- unsigned long value;
-
- __asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
- /* printf("p15/c1 is = %08lx\n", value); */
- return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
- /* printf("write %08lx to p15/c1\n", value); */
- __asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
- :
- : "r" (value)
- : "memory");
-
- read_p15_c1();
-}
-
static void cp_delay (void)
{
volatile int i;
@@ -133,60 +107,50 @@ static void cp_delay (void)
for (i = 0; i < 100; i++);
}
-/* See also ARM Ref. Man. */
-#define C1_MMU (1<<0) /* mmu off/on */
-#define C1_ALIGN (1<<1) /* alignment faults off/on */
-#define C1_IDC (1<<2) /* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
-#define C1_SYS_PROT (1<<8) /* system protection */
-#define C1_ROM_PROT (1<<9) /* ROM protection */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-
void icache_enable (void)
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = get_cr ();
cp_delay ();
- write_p15_c1 (reg | C1_IDC);
+ set_cr (reg | CR_C);
}
void icache_disable (void)
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = get_cr ();
cp_delay ();
- write_p15_c1 (reg & ~C1_IDC);
+ set_cr (reg & ~CR_C);
}
int icache_status (void)
{
- return (read_p15_c1 () & C1_IDC) != 0;
+ return (get_cr () & CR_C) != 0;
}
void dcache_enable (void)
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = get_cr ();
cp_delay ();
- write_p15_c1 (reg | C1_IDC);
+ set_cr (reg | CR_C);
}
void dcache_disable (void)
{
ulong reg;
- reg = read_p15_c1 ();
+ reg = get_cr ();
cp_delay ();
- write_p15_c1 (reg & ~C1_IDC);
+ set_cr (reg & ~CR_C);
}
int dcache_status (void)
{
- return (read_p15_c1 () & C1_IDC) != 0;
+ return (get_cr () & CR_C) != 0;
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific cache setup for IntegratorAP/CM720T as yet */