diff options
Diffstat (limited to 'cpu/arm1176')
| -rw-r--r-- | cpu/arm1176/cpu.c | 103 | ||||
| -rw-r--r-- | cpu/arm1176/s3c64xx/cpu_init.S | 7 |
2 files changed, 2 insertions, 108 deletions
diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index 1e94f7d..bfa4378 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -34,55 +34,10 @@ #include <common.h> #include <command.h> #include <s3c6400.h> +#include <asm/system.h> static void cache_flush (void); -/* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1 (void) -{ - unsigned long value; - - __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); - return value; -} - -/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1 (unsigned long value) -{ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); - - read_p15_c1(); -} - -static void cp_delay (void) -{ - volatile int i; - - /* Many OMAP regs need at least 2 nops */ - for (i = 0; i < 100; i++) - __asm__ __volatile__("nop\n"); -} - -/* See also ARM Ref. Man. */ -#define C1_MMU (1 << 0) /* mmu off/on */ -#define C1_ALIGN (1 << 1) /* alignment faults off/on */ -#define C1_DC (1 << 2) /* dcache off/on */ -#define C1_WB (1 << 3) /* merging write buffer on/off */ -#define C1_BIG_ENDIAN (1 << 7) /* big endian off/on */ -#define C1_SYS_PROT (1 << 8) /* system protection */ -#define C1_ROM_PROT (1 << 9) /* ROM protection */ -#define C1_IC (1 << 12) /* icache off/on */ -#define C1_HIGH_VECTORS (1 << 13) /* location of vectors: low/high */ -#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ - int cpu_init (void) { return 0; @@ -102,6 +57,7 @@ int cleanup_before_linux (void) /* turn off I/D-cache */ icache_disable(); dcache_disable(); + /* flush I/D-cache */ cache_flush(); return 0; @@ -123,61 +79,6 @@ void reset_cpu (ulong ignored) /*NOTREACHED*/ } -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - disable_interrupts (); - reset_cpu (0); - /*NOTREACHED*/ - return 0; -} - -void icache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); -} - -void icache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); -} - -int icache_status (void) -{ - return (read_p15_c1 () & C1_IC) != 0; -} - -/* It makes no sense to use the dcache if the MMU is not enabled */ -void dcache_enable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg | C1_DC); -} - -void dcache_disable (void) -{ - ulong reg; - - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_DC); -} - -int dcache_status (void) -{ - return (read_p15_c1 () & C1_DC) != 0; -} - /* flush I/D-cache */ static void cache_flush (void) { diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S index 08bda99..32bb467 100644 --- a/cpu/arm1176/s3c64xx/cpu_init.S +++ b/cpu/arm1176/s3c64xx/cpu_init.S @@ -28,13 +28,6 @@ .globl mem_ctrl_asm_init mem_ctrl_asm_init: - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #0xd - str r1, [r0] - /* DMC1 base address 0x7e001000 */ ldr r0, =ELFIN_DMC1_BASE |