diff options
Diffstat (limited to 'common')
| -rw-r--r-- | common/cmd_jffs2.c | 10 | ||||
| -rw-r--r-- | common/cmd_nand.c | 3 | ||||
| -rw-r--r-- | common/hush.c | 18 | ||||
| -rw-r--r-- | common/miiphybb.c | 328 | ||||
| -rw-r--r-- | common/miiphyutil.c | 8 |
5 files changed, 200 insertions, 167 deletions
diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 16f5b7a..7ab6e9c 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -1810,7 +1810,7 @@ int do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return !(size > 0); } - return 0; + return 1; } /** @@ -1846,9 +1846,9 @@ int do_jffs2_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ret = jffs2_1pass_ls(part, filename); } - return (ret == 1); + return ret ? 0 : 1; } - return 0; + return 1; } /** @@ -1884,9 +1884,9 @@ int do_jffs2_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ret = jffs2_1pass_info(part); } - return (ret == 1); + return ret ? 0 : 1; } - return 0; + return 1; } /* command line only */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 4499917..5648ab2 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -225,10 +225,11 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CFG_NAND_SKIP_BAD_DOT_I /* need ".i" same as ".jffs2s" for compatibility with older units (esd) */ /* ".i" for image -> read skips bad block (no 0xff) */ - else if (cmdtail && !strcmp(cmdtail, ".i")) + else if (cmdtail && !strcmp(cmdtail, ".i")) { cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ if (cmd & NANDRW_READ) cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ + } #endif /* CFG_NAND_SKIP_BAD_DOT_I */ else if (cmdtail) { printf ("Usage:\n%s\n", cmdtp->usage); diff --git a/common/hush.c b/common/hush.c index 47680ed..eb7f7f1 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1022,12 +1022,30 @@ static void get_user_input(struct in_str *i) int n; static char the_command[CFG_CBSIZE]; +#ifdef CONFIG_BOOT_RETRY_TIME +# ifdef CONFIG_RESET_TO_RETRY + extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); +# else +# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" +# endif + reset_cmd_timeout(); +#endif i->__promptme = 1; if (i->promptmode == 1) { n = readline(CFG_PROMPT); } else { n = readline(CFG_PROMPT_HUSH_PS2); } +#ifdef CONFIG_BOOT_RETRY_TIME + if (n == -2) { + puts("\nTimeout waiting for command\n"); +# ifdef CONFIG_RESET_TO_RETRY + do_reset(NULL, 0, 0, NULL); +# else +# error "This currently only works with CONFIG_RESET_TO_RETRY enabled" +# endif + } +#endif if (n == -1 ) { flag_repeat = 0; i->__promptme = 0; diff --git a/common/miiphybb.c b/common/miiphybb.c index b4cbb70..b6af88f 100644 --- a/common/miiphybb.c +++ b/common/miiphybb.c @@ -38,72 +38,79 @@ * Utility to send the preamble, address, and register (common to read * and write). */ -static void miiphy_pre(char read, - unsigned char addr, - unsigned char reg) +static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { - int j; /* counter */ - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); - - /* - * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. - * The IEEE spec says this is a PHY optional requirement. The AMD - * 79C874 requires one after power up and one after a MII communications - * error. This means that we are doing more preambles than we need, - * but it is safer and will be much more robust. - */ - - MDIO_ACTIVE; - MDIO(1); - for(j = 0; j < 32; j++) - { - MDC(0); - MIIDELAY; - MDC(1); - MIIDELAY; - } - - /* send the start bit (01) and the read opcode (10) or write (10) */ - MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY; - MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY; - MDC(0); MDIO(read); MIIDELAY; MDC(1); MIIDELAY; - MDC(0); MDIO(!read); MIIDELAY; MDC(1); MIIDELAY; - - /* send the PHY address */ - for(j = 0; j < 5; j++) - { - MDC(0); - if((addr & 0x10) == 0) - { - MDIO(0); - } - else - { - MDIO(1); - } - MIIDELAY; - MDC(1); - MIIDELAY; - addr <<= 1; - } - - /* send the register address */ - for(j = 0; j < 5; j++) - { - MDC(0); - if((reg & 0x10) == 0) - { - MDIO(0); - } - else - { - MDIO(1); - } - MIIDELAY; - MDC(1); - MIIDELAY; - reg <<= 1; - } + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + /* + * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. + * The IEEE spec says this is a PHY optional requirement. The AMD + * 79C874 requires one after power up and one after a MII communications + * error. This means that we are doing more preambles than we need, + * but it is safer and will be much more robust. + */ + + MDIO_ACTIVE; + MDIO (1); + for (j = 0; j < 32; j++) { + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + } + + /* send the start bit (01) and the read opcode (10) or write (10) */ + MDC (0); + MDIO (0); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (1); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (read); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (!read); + MIIDELAY; + MDC (1); + MIIDELAY; + + /* send the PHY address */ + for (j = 0; j < 5; j++) { + MDC (0); + if ((addr & 0x10) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + addr <<= 1; + } + + /* send the register address */ + for (j = 0; j < 5; j++) { + MDC (0); + if ((reg & 0x10) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + reg <<= 1; + } } @@ -114,66 +121,63 @@ static void miiphy_pre(char read, * Returns: * 0 on success */ -int miiphy_read(unsigned char addr, - unsigned char reg, - unsigned short *value) +int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value) { - short rdreg; /* register working value */ - int j; /* counter */ - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); - - miiphy_pre(1, addr, reg); - - /* tri-state our MDIO I/O pin so we can read */ - MDC(0); - MDIO_TRISTATE; - MIIDELAY; - MDC(1); - MIIDELAY; - - /* check the turnaround bit: the PHY should be driving it to zero */ - if(MDIO_READ != 0) - { - /* puts ("PHY didn't drive TA low\n"); */ - for(j = 0; j < 32; j++) - { - MDC(0); - MIIDELAY; - MDC(1); - MIIDELAY; - } - return(-1); - } - - MDC(0); - MIIDELAY; - - /* read 16 bits of register data, MSB first */ - rdreg = 0; - for(j = 0; j < 16; j++) - { - MDC(1); - MIIDELAY; - rdreg <<= 1; - rdreg |= MDIO_READ; - MDC(0); - MIIDELAY; - } - - MDC(1); - MIIDELAY; - MDC(0); - MIIDELAY; - MDC(1); - MIIDELAY; - - *value = rdreg; + short rdreg; /* register working value */ + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + miiphy_pre (1, addr, reg); + + /* tri-state our MDIO I/O pin so we can read */ + MDC (0); + MDIO_TRISTATE; + MIIDELAY; + MDC (1); + MIIDELAY; + + /* check the turnaround bit: the PHY should be driving it to zero */ + if (MDIO_READ != 0) { + /* puts ("PHY didn't drive TA low\n"); */ + for (j = 0; j < 32; j++) { + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + } + return (-1); + } + + MDC (0); + MIIDELAY; + + /* read 16 bits of register data, MSB first */ + rdreg = 0; + for (j = 0; j < 16; j++) { + MDC (1); + MIIDELAY; + rdreg <<= 1; + rdreg |= MDIO_READ; + MDC (0); + MIIDELAY; + } + + MDC (1); + MIIDELAY; + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + *value = rdreg; #ifdef DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); + printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); #endif - return 0; + return 0; } @@ -184,47 +188,51 @@ int miiphy_read(unsigned char addr, * Returns: * 0 on success */ -int miiphy_write(unsigned char addr, - unsigned char reg, - unsigned short value) +int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value) { - int j; /* counter */ - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, MDIO_PORT); - - miiphy_pre(0, addr, reg); - - /* send the turnaround (10) */ - MDC(0); MDIO(1); MIIDELAY; MDC(1); MIIDELAY; - MDC(0); MDIO(0); MIIDELAY; MDC(1); MIIDELAY; - - /* write 16 bits of register data, MSB first */ - for(j = 0; j < 16; j++) - { - MDC(0); - if((value & 0x00008000) == 0) - { - MDIO(0); - } - else - { - MDIO(1); - } - MIIDELAY; - MDC(1); - MIIDELAY; - value <<= 1; - } - - /* - * Tri-state the MDIO line. - */ - MDIO_TRISTATE; - MDC(0); - MIIDELAY; - MDC(1); - MIIDELAY; - - return 0; + int j; /* counter */ +#ifndef CONFIG_EP8248 + volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT); +#endif + + miiphy_pre (0, addr, reg); + + /* send the turnaround (10) */ + MDC (0); + MDIO (1); + MIIDELAY; + MDC (1); + MIIDELAY; + MDC (0); + MDIO (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + /* write 16 bits of register data, MSB first */ + for (j = 0; j < 16; j++) { + MDC (0); + if ((value & 0x00008000) == 0) { + MDIO (0); + } else { + MDIO (1); + } + MIIDELAY; + MDC (1); + MIIDELAY; + value <<= 1; + } + + /* + * Tri-state the MDIO line. + */ + MDIO_TRISTATE; + MDC (0); + MIIDELAY; + MDC (1); + MIIDELAY; + + return 0; } #endif /* CONFIG_BITBANGMII */ diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 2b0dcf4..13b9c65 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -93,7 +93,13 @@ int miiphy_reset (unsigned char addr) unsigned short reg; int loop_cnt; - if (miiphy_write (addr, PHY_BMCR, 0x8000) != 0) { + if (miiphy_read (addr, PHY_BMCR, ®) != 0) { +#ifdef DEBUG + printf ("PHY status read failed\n"); +#endif + return (-1); + } + if (miiphy_write (addr, PHY_BMCR, reg | 0x8000) != 0) { #ifdef DEBUG puts ("PHY reset failed\n"); #endif |