diff options
Diffstat (limited to 'board')
30 files changed, 781 insertions, 251 deletions
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 694bd74..41fa3e1 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 + * (C) Copyright 2009-2010 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -28,13 +28,13 @@ #include <common.h> #include <asm/arch/at91sam9263.h> -#include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <netdev.h> @@ -52,10 +52,10 @@ int get_hw_rev(void) if (hw_rev >= 0) return hw_rev; - hw_rev = at91_get_gpio_value(AT91_PIN_PB19); - hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; if (hw_rev == 15) hw_rev = 0; @@ -67,44 +67,44 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | -#endif - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { + at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + /* Configure SMC EBI1_CS0 for EtherCAT */ - at91_sys_write(AT91_SMC1_SETUP(0), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC1_PULSE(0), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9)); - at91_sys_write(AT91_SMC1_CYCLE(0), - AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), + &smc1->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | + AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), + &smc1->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), + &smc1->cs[0].cycle); /* * Configure behavior at external wait signal, byte-select mode, 16 bit * data bus width, none data float wait states and TDF optimization */ - at91_sys_write(AT91_SMC1_MODE(0), - AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | - AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | - AT91_SMC_TDFMODE); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | + AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | + AT91_SMC_MODE_TDF, &smc1->cs[0].mode); /* Configure RDY/BSY */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ + at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ } int dram_init(void) @@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); #endif return rc; } @@ -175,7 +176,7 @@ int checkboard(void) gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; puts("Board: EtherCAN/2 Gateway"); /* switch on LED1D */ - at91_set_gpio_output(AT91_PIN_PB12, 1); + at91_set_pio_output(AT91_PIO_PORTB, 12, 1); break; default: /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ @@ -222,8 +223,9 @@ u32 get_board_rev(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - char *str; - char buf[32]; + char *str; + char buf[32]; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* * Normally the processor clock has a divisor of 2. @@ -231,10 +233,9 @@ int misc_init_r(void) * Check the user has set environment mdiv to 4 to change the divisor. */ if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { - at91_sys_write(AT91_PMC_MCKR, - (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) | - AT91SAM9_PMC_MDIV_4); - at91_clock_init(0); + writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | + AT91SAM9_PMC_MDIV_4, &pmc->mckr); + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", @@ -247,10 +248,14 @@ int misc_init_r(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Peripheral Clock Enable Register */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + writel(1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE | + 1 << AT91SAM9263_ID_UHP, + &pmc->pcer); /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); @@ -271,5 +276,8 @@ int board_init(void) #ifdef CONFIG_AT91_CAN at91_can_hw_init(); #endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif return 0; } diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S index 7f0686c..1a11eee 100644 --- a/board/espt/lowlevel_init.S +++ b/board/espt/lowlevel_init.S @@ -206,26 +206,31 @@ PKDR_A: .long 0xFFEF0034 /* GPIO Set data */ PADR_D: .long 0x00000000 -PACR_D: .long 0x00001400 +PACR_D: .word 0x1400 +.align 2 PBDR_D: .long 0x00000000 -PBCR_D: .long 0x0000555A +PBCR_D: .word 0x555A +.align 2 PCDR_D: .long 0x00000000 -PCCR_D: .long 0x00005555 +PCCR_D: .word 0x5555 +.align 2 PDDR_D: .long 0x00000000 -PDCR_D: .long 0x00000155 -PECR_D: .long 0x00000000 -PFCR_D: .long 0x00000000 -PGCR_D: .long 0x00000000 -PHCR_D: .long 0x00000000 -PICR_D: .long 0x00000800 +PDCR_D: .word 0x0155 +PECR_D: .word 0x0000 +PFCR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PICR_D: .word 0x0800 PJDR_D: .long 0x00000006 -PJCR_D: .long 0x00005A57 +PJCR_D: .word 0x5A57 +.align 2 PKDR_D: .long 0x00000000 -PKCR_D: .long 0x0000FFF9 -PLCR_D: .long 0x0000C330 -PMCR_D: .long 0x0000FFFF -PNCR_D: .long 0x00000242 -POCR_D: .long 0x00000000 +PKCR_D: .word 0xFFF9 +.align 2 +PLCR_D: .word 0xC330 +PMCR_D: .word 0xFFFF +PNCR_D: .word 0x0242 +POCR_D: .word 0x0000 /* Pin Select */ PSEL0_A: .long 0xFFEF0070 @@ -233,11 +238,12 @@ PSEL1_A: .long 0xFFEF0072 PSEL2_A: .long 0xFFEF0074 PSEL3_A: .long 0xFFEF0076 PSEL4_A: .long 0xFFEF0078 -PSEL0_D: .long 0x0001 -PSEL1_D: .long 0x2400 -PSEL2_D: .long 0x0000 -PSEL3_D: .long 0x2421 -PSEL4_D: .long 0x0000 +PSEL0_D: .word 0x0001 +PSEL1_D: .word 0x2400 +PSEL2_D: .word 0x0000 +PSEL3_D: .word 0x2421 +PSEL4_D: .word 0x0000 +.align 2 MMSEL_A: .long 0xFE600020 BCR_A: .long 0xFF801000 diff --git a/board/eukrea/cpuat91/cpuat91.c b/board/eukrea/cpuat91/cpuat91.c index 0017962..cd4d42c 100644 --- a/board/eukrea/cpuat91/cpuat91.c +++ b/board/eukrea/cpuat91/cpuat91.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Eukrea Electromatique <www.eukrea.com> + * (C) Copyright 2006-2010 Eukrea Electromatique <www.eukrea.com> * Eric Benard <eric@eukrea.com> * based on at91rm9200dk.c which is : * (C) Copyright 2002 @@ -27,13 +27,11 @@ #include <common.h> #include <netdev.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <ks8721.h> -#endif +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_pmc.h> DECLARE_GLOBAL_DATA_PTR; @@ -61,31 +59,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_DRIVER_ETHER) -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = ks8721_initphy; - p_phyops->IsPhyConnected = ks8721_isphyconnected; - p_phyops->GetLinkSpeed = ks8721_getlinkspeed; - p_phyops->AutoNegotiate = ks8721_autonegotiate; -} - -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ #ifdef CONFIG_DRIVER_AT91EMAC - int board_eth_init(bd_t *bis) { int rc = 0; @@ -93,3 +67,20 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +#ifdef CONFIG_SOFT_I2C +void i2c_init_board(void) +{ + u32 pin; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + + writel(1 << AT91_ID_PIOA, &pmc->pcer); + pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); +} +#endif diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3cdefb3..48d95d6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> #include <netdev.h> +#include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> @@ -120,28 +121,6 @@ int board_early_init_r(void) set_liodns(); setup_portals(); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - return 0; } @@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_SRIO1 + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_1); + } else { + printf (" SRIO1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ +#endif + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_2); + } else { + printf (" SRIO2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ +#endif + /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 82b2b4f..18adf2f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -66,11 +66,19 @@ typedef struct { * seem reliable, but errors will appear when memory intensive * program is run. */ /* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][20] = { +const board_specific_parameters_t board_specific_parameters[][30] = { { /* memory controller 0 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, @@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = { /* memory controller 1 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 30d640f..9a1b075 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = { {550, 680, 1, 4, 0x1f, 3, 0}, {681, 850, 1, 4, 0x1f, 4, 0} #else - { 0, 850, 2, 4, 0x1f, 4, 0}, + { 0, 850, 2, 6, 0x1f, 4, 0}, { 0, 850, 1, 4, 0x1f, 4, 0} #endif }, @@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x7; + popts->wrlvl_start = 0x8; /* Rtt and Rtt_WR override */ popts->rtt_override = 1; popts->rtt_override_value = DDR3_RTT_120_OHM; diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index e6eee9b..aeb0fcc 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 5f02bd4..0f7a892 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -82,10 +82,10 @@ lowlevel_init: /* * PLL Settings */ -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 /* start counting at zero */ -WTCSR_D: .long 0xA507 /* divide by 4096 */ - +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 /* start counting at zero */ +WTCSR_D: .word 0xA507 /* divide by 4096 */ +.align 2 /* * Spansion S29GL256N11 @ 48 MHz */ diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S index 7593811..3df25b6 100644 --- a/board/ms7720se/lowlevel_init.S +++ b/board/ms7720se/lowlevel_init.S @@ -114,10 +114,10 @@ FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ WTCNT_A: .long 0xA415FF84 WTCSR_A: .long 0xA415FF86 UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 -WTCSR_D: .long 0xA506 -UCLKCR_D: .long 0xA5C0 +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 +WTCSR_D: .word 0xA506 +UCLKCR_D: .word 0xA5C0 #define BSC_BASE 0xA4FD0000 CMNCR_A: .long BSC_BASE @@ -164,7 +164,8 @@ SDCR_D1: .long 0x00000011 RTCSR_D: .long 0xA55A0010 RTCNT_D: .long 0xA55A001F RTCOR_D: .long 0xA55A001F -SDMR3_D: .long 0x0000 +SDMR3_D: .word 0x0000 +.align 2 SDCR_D2: .long 0x00000811 #define PFC_BASE 0xA4050100 @@ -178,15 +179,16 @@ PTCR_A: .long PFC_BASE + 0x1E PVCR_A: .long PFC_BASE + 0x22 PSELA_A: .long PFC_BASE + 0x24 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PPCR_D: .long 0x00AA -PTCR_D: .long 0x0280 -PVCR_D: .long 0x0000 -PSELA_D: .long 0x0000 +PCCR_D: .word 0x0000 +PDCR_D: .word 0x0000 +PECR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PPCR_D: .word 0x00AA +PTCR_D: .word 0x0280 +PVCR_D: .word 0x0000 +PSELA_D: .word 0x0000 +.align 2 CCR_A: .long 0xFFFFFFEC !CCR_D: .long 0x0000000D diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 5e09a39..3041e64 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -120,13 +120,14 @@ CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R - .long 0x00000e1a /* 12:3:3 */ + .word 0x0e1a /* 12:3:3 */ #else /* CONFIG_CPU_TYPE_R */ #ifdef CONFIG_GOOD_SESH4 - .long 0x00000e13 /* 6:2:1 */ + .word 0x00e13 /* 6:2:1 */ #else - .long 0x00000e23 /* 6:1:1 */ + .word 0x00e23 /* 6:1:1 */ #endif +.align 2 #endif /* CONFIG_CPU_TYPE_R */ BCR1_A: .long BCR1 @@ -140,15 +141,19 @@ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR3_A: .long WCR3 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ RTCSR_A: .long RTCSR -RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ +RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ +.align 2 RTCNT_A: .long RTCNT -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR -RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ +RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ +.align 2 SDMR3_A: .long SDMR3_ADDRESS SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE RFCR_A: .long RFCR -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ +.align 2 diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 9a6cd1b..358cc54 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 1881e65..542601a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index ad058ca..bd16786 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 0daf25a..04cfef1 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -119,15 +119,16 @@ lowlevel_init: DRVCRA_A: .long DRVCRA DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 +DRVCRA_D: .word 0x4555 +DRVCRB_D: .word 0x0005 RWTCSR_A: .long RWTCSR RWTCNT_A: .long RWTCNT FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 +RWTCSR_D1: .word 0xa507 +RWTCSR_D2: .word 0xa504 +RWTCNT_D: .word 0x5a00 +.align 2 FRQCR_D: .long 0x0b04474a SBSC_SDCR_A: .long SBSC_SDCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 76d3cfc..f3392f0 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -94,11 +94,14 @@ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .word 0xA534 /* RTCOR Write Code */ +.align 2 RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +RTCSR_D: .word 0xA510 /* RTCSR Write Code */ +.align 2 SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D0: .long 0x55 SDMR3_D1: .long 0x00 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 7b9ecd8..30ef5ab 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -73,7 +73,7 @@ init_bsc_cs0: write32 CMNCR_A, CMNCR_D - write32 SC0BCR_A, SC0BCR_D + write32 CS0BCR_A, CS0BCR_D write32 CS0WCR_A, CS0WCR_D @@ -122,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -190,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 3747bf6..5b18200 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -266,8 +266,8 @@ SDR4_D: .long 0x00000300 SDMR00308_D: .long 0x00000000 SDMR00B08_D: .long 0x00000000 SDMR02000_D: .long 0x00000000 -PSEL0_D: .long 0x00000001 -PSEL1_D: .long 0x00000244 +PSEL0_D: .word 0x00000001 +PSEL1_D: .word 0x00000244 SR_MASK_D: .long 0xEFFFFF0F WDTST_D: .long 0x5A000FFF WDTCSR_D: .long 0xA5000000 diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 40d9b08..86f6783 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -68,22 +68,22 @@ lowlevel_init: wait_timer WAIT_200US /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D write16 PHCR_A, PHCR_D write16 PJCR_A, PJCR_D write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D + write16 PLCR_A, PXCR_D write16 PMCR_A, PMCR_D write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D write8 PEPUPR_A, PEPUPR_D write8 PHPUPR_A, PHPUPR_D @@ -179,22 +179,14 @@ lbsc_end: .align 4 /*------- GPIO -------*/ -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 PEPUPR_D: .long 0xff PHPUPR_D: .long 0x00 @@ -203,10 +195,10 @@ PKPUPR_D: .long 0x00 PLPUPR_D: .long 0x00 PMPUPR_D: .long 0xfc PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 #define GPIO_BASE 0xffe70000 PACR_A: .long GPIO_BASE + 0x00 diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 060d5d1..4336729 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -67,7 +67,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1); + gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -80,11 +80,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2); + gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE); + gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X); + gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0); diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 4b72992..62737ab 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -51,7 +51,7 @@ lowlevel_init: ldr r7, =S5PC100_GPIO_BASE ldr r8, =S5PC100_GPIO_BASE /* Read CPU ID */ - ldr r2, =S5PC1XX_PRO_ID + ldr r2, =S5PC110_PRO_ID ldr r0, [r2] mov r1, #0x00010000 and r0, r0, r1 @@ -377,7 +377,7 @@ lockloop: * void system_clock_init(void) */ system_clock_init: - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Check S5PC100 */ cmp r7, r8 @@ -437,7 +437,7 @@ system_clock_init: ldr r1, =0x3ff03ff str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 32572c5..30d0d06 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -131,7 +131,7 @@ wakeup_reset: * void system_clock_init(void) */ system_clock_init: - ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x00011110 diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index c25869e..501855e 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -35,7 +35,8 @@ void onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); struct samsung_onenand *onenand; int value; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index fb466c6..31e8d9e 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -38,10 +38,10 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100644 index 0000000..87d2234 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100644 index 0000000..c661f0b --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100644 index 0000000..04d2f9d --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,170 @@ +/* + * (c) 2010 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mb86r0x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) + MB86R0x_CCNT_BASE; + + /* We select mode 0 for group 2 and mode 1 for group 4 */ + writel(0x00000010, &ccnt->cmux_md); + + gd->flags = 0; + gd->bd->bi_arch_number = MACH_TYPE_JADECPU; + gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; + + icache_enable(); + + return 0; +} + +static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, + unsigned long pwm_base) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; + const char *e; + + writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); + + e = getenv(pwm_opts); + if (e != NULL) { + const char *s; + uint32_t freq, init; + + freq = 0; + init = 0; + + s = strchr(e, 'f'); + if (s != NULL) + freq = simple_strtol(s + 2, NULL, 0); + + s = strchr(e, 'i'); + if (s != NULL) + init = simple_strtol(s + 2, NULL, 0); + + if (freq > 0) { + writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, + &pwm->bcr); + writel(1002, &pwm->tpr); + writel(1, &pwm->pr); + writel(init * 10 + 1, &pwm->dr); + writel(1, &pwm->cr); + writel(1, &pwm->sr); + } + } +} + +int board_late_init(void) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + uint32_t in_word; + +#ifdef CONFIG_VIDEO_MB86R0xGDC + /* Check if we have valid display settings and turn on power if so */ + /* Display 0 */ + if (getenv("gs_dsp_0_param") || getenv("videomode")) + setup_display_power((1 << 3), "gs_dsp_0_pwm", + MB86R0x_PWM0_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); + + /* Display 1 */ + if (getenv("gs_dsp_1_param") || getenv("videomode1")) + setup_display_power((1 << 4), "gs_dsp_1_pwm", + MB86R0x_PWM1_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); +#endif /* CONFIG_VIDEO_MB86R0xGDC */ + + /* 5V enable */ + writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); + writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); + + /* We have special boot options if told by GPIOs */ + in_word = readl(&gpio->gpdr1); + + if ((in_word & 0xC0) == 0xC0) { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + setenv("preboot", "run gs_slow_boot"); + } else if ((in_word & 0xC0) != 0) { + setenv("stdout", "vga"); + setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" + "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" + "bootelf 0x40000000; bootelf 0x10080000"); + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + if (getenv("gs_devel")) { + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("gs_bootcmd", "bootelf 0x10080000"); + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +/* + * DRAM configuration + */ +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100644 index 0000000..5ad4dce --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,265 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/mb86r0x.h> +#include <asm/arch/asm-offsets.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/* + * Initialize Clock Reset Generator (CRG) + */ + + ldr r0, =MB86R0x_CRG_BASE + + /* Not change the initial value that is set by external pin.*/ +WAIT_PLL: + ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ + tst r2, #MB86R0x_CRG_CRPR_PLLRDY + beq WAIT_PLL + + /* Set clock gate control */ + ldr r1, =CONFIG_SYS_CRG_CRHA_INIT + str r1, [r0, #CRG_CRHA] + ldr r1, =CONFIG_SYS_CRG_CRPA_INIT + str r1, [r0, #CRG_CRPA] + ldr r1, =CONFIG_SYS_CRG_CRPB_INIT + str r1, [r0, #CRG_CRPB] + ldr r1, =CONFIG_SYS_CRG_CRHB_INIT + str r1, [r0, #CRG_CRHB] + ldr r1, =CONFIG_SYS_CRG_CRAM_INIT + str r1, [r0, #CRG_CRAM] + +/* + * Initialize External Bus Interface + */ + ldr r0, =MB86R0x_MEMC_BASE + + ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT + str r1, [r0, #MEMC_MCFMODE0] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT + str r1, [r0, #MEMC_MCFMODE2] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT + str r1, [r0, #MEMC_MCFMODE4] + + ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT + str r1, [r0, #MEMC_MCFTIM0] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT + str r1, [r0, #MEMC_MCFTIM2] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT + str r1, [r0, #MEMC_MCFTIM4] + + ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT + str r1, [r0, #MEMC_MCFAREA0] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT + str r1, [r0, #MEMC_MCFAREA2] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT + str r1, [r0, #MEMC_MCFAREA4] + +/* + * Initialize DDR2 Controller + */ + + /* Wait for PLL LOCK up time or more */ + wait_timer 20 + + /* + * (2) Initialize DDRIF + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT + strh r1, [r0, #DDR2_DRIMS] + + /* + * (3) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (4) IRESET/IUSRRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 + str r1, [r0, #CCNT_CDCRC] + + /* + * (5) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (6) IDLLRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 + str r1, [r0, #CCNT_CDCRC] + + /* + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) + */ + wait_timer 33536 + + /* + * (9) MCKE ON + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT + strh r1, [r0, #DDR2_DRCA] + ldr r1, =MB86R0x_DDR2_DRCI_INIT + strh r1, [r0, #DDR2_DRIC] + + /* + * (10) Initialize SDRAM + */ + + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 67 /* 400ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 18 /* 105ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 /* MRS to OCD: 200clock */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT + strh r1, [r0, #DDR2_DRCM] + + ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT + strh r1, [r0, #DDR2_DRCST1] + + ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT + strh r1, [r0, #DDR2_DRCST2] + + ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT + strh r1, [r0, #DDR2_DRCR] + + ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT + strh r1, [r0, #DDR2_DRCF] + + ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT + strh r1, [r0, #DDR2_DRASR] + + /* + * (11) ODT setting + */ + ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT + strh r1, [r0, #DDR2_DROBS] + ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT + strh r1, [r0, #DDR2_DROABA] + ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT + strh r1, [r0, #DDR2_DRIBSODT1] + + /* + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode + */ + ldr r1, =CONFIG_SYS_DDR2_DROS_INIT + strh r1, [r0, #DDR2_DROS] + ldr r1, =MB86R0x_DDR2_DRCI_NORMAL + strh r1, [r0, #DDR2_DRIC] + + mov pc, lr diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 8ba1b19..2272ff0 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -101,7 +101,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |