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-rw-r--r--board/tqc/tqm85xx/law.c29
-rw-r--r--board/tqc/tqm85xx/tlb.c97
2 files changed, 122 insertions, 4 deletions
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index 914ce68..b4e663b 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -30,6 +30,8 @@
/*
* LAW(Local Access Window) configuration:
*
+ * Standard mapping:
+ *
* 0x0000_0000 0x7fff_ffff DDR 2G
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M
@@ -37,22 +39,41 @@
* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M
* 0xef00_0000 0xefff_ffff PCI express IO 16M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M
+ *
+ * Big FLASH mapping:
+ *
+ * 0x0000_0000 0x7fff_ffff DDR 2G
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xa000_ffff CCSR 1M
+ * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M
+ * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M
+ * 0xaf00_0000 0xafff_ffff PCI express IO 16M
+ * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M
+ * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G
*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
+#ifdef CONFIG_TQM_BIGFLASH
+#define LAW_3_SIZE LAW_SIZE_1G
+#define LAW_5_SIZE LAW_SIZE_256M
+#else
+#define LAW_3_SIZE LAW_SIZE_128M
+#define LAW_5_SIZE LAW_SIZE_512M
+#endif
+
struct law_entry law_table[] = {
SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#ifdef CONFIG_PCIE1
- SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
#else /* !CONFIG_PCIE1 */
- SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+ SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
#endif /* CONFIG_PCIE1 */
#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 7f4efc1..380448a 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -44,6 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
+#ifndef CONFIG_TQM_BIGFLASH
/*
* TLB 0, 1: 128M Non-cacheable, guarded
* 0xf8000000 128M FLASH
@@ -146,6 +147,102 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */
+#else /* CONFIG_TQM_BIGFLASH */
+
+ /*
+ * TLB 0,1,2,3: 1G Non-cacheable, guarded
+ * 0xc0000000 1G FLASH
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
+ CFG_FLASH_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
+ CFG_FLASH_BASE + 0x20000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 1, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
+ CFG_FLASH_BASE + 0x30000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 4: 256M Non-cacheable, guarded
+ * 0x80000000 256M PCI1 MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLB 5: 256M Non-cacheable, guarded
+ * 0x90000000 256M PCI1 MEM Second half
+ */
+ SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
+ CFG_PCI1_MEM_PHYS + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xc0000000 256M PCI express MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
+ /*
+ * TLB 6: 256M Non-cacheable, guarded
+ * 0xb0000000 256M Rapid IO MEM First half
+ */
+ SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+#endif /* CONFIG_PCIE */
+
+ /*
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xa0000000 1M CCSRBAR
+ * 0xa2000000 16M PCI1 IO
+ * 0xa3000000 16M CAN and NAND Flash
+ */
+ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
+ * 0x00000000 512M DDR System memory
+ * Without SPD EEPROM configured DDR, this must be setup manually.
+ * Make sure the TLB count at the top of this table is correct.
+ * Likely it needs to be increased by two for these entries.
+ */
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
+ CFG_DDR_SDRAM_BASE + 0x10000000,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+ /*
+ * TLB 10: 16M Non-cacheable, guarded
+ * 0xaf000000 16M PCI express IO
+ */
+ SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+ MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
+#endif /* CONFIG_TQM_BIGFLASH */
};
int num_tlb_entries = ARRAY_SIZE (tlb_table);