diff options
Diffstat (limited to 'board')
6 files changed, 282 insertions, 39 deletions
diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig b/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig index 51bc6d9..517846f 100644 --- a/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/Kconfig @@ -9,4 +9,15 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ul_14x14_ddr3_arm2" +config MX6UL_DDR3_ARM2_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config MX6UL_DDR3_ARM2_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. endif diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg b/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg index a099b71..4e93368 100644 --- a/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/imximage.cfg @@ -21,9 +21,9 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ -#ifdef CONFIG_SYS_BOOT_QSPI +#ifdef CONFIG_QSPI_BOOT BOOT_FROM qspi -#elif defined(CONFIG_SYS_BOOT_EIMNOR) +#elif defined(CONFIG_NOR_BOOT) BOOT_FROM nor #else BOOT_FROM sd diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c index 7d30ac9..ab98321 100644 --- a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <asm/imx-common/video.h> DECLARE_GLOBAL_DATA_PTR; @@ -80,7 +80,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC and EEPROM */ struct i2c_pads_info i2c_pad_info1 = { @@ -154,7 +154,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { }; #endif -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -163,7 +163,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), #ifdef CONFIG_MX6UL_DDR3_ARM2_USDHC2_REWORK -#if defined(CONFIG_SYS_USE_EIMNOR) || defined(CONFIG_SYS_USE_SPINOR) +#if defined(CONFIG_MTD_NOR_FLASH) || defined(CONFIG_MXC_SPI) #error "Pin conflicts!" #endif /* conflict with eimnor/spinor */ @@ -186,7 +186,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { }; #endif -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_CMD_NAND static iomux_v3_cfg_t const nand_pads[] = { MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), @@ -224,7 +224,7 @@ static void setup_gpmi_nand(void) } #endif -#ifdef CONFIG_SYS_USE_SPINOR +#ifdef CONFIG_MXC_SPI /* pin conflicts with eim nor */ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -238,6 +238,7 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { static void setup_spinor(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); gpio_direction_output(IMX_GPIO_NR(4, 26), 0); } @@ -247,7 +248,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif -#ifdef CONFIG_SYS_USE_EIMNOR +#ifdef CONFIG_MTD_NOR_FLASH /* pin conflicts with nand usdhc2 lcd enet */ static iomux_v3_cfg_t const eimnor_pads[] = { MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), @@ -389,12 +390,14 @@ static void setup_iomux_fec(int fec_id) if (fec_id == 0) { imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); gpio_direction_output(IMX_GPIO_NR(5, 2), 0); udelay(50); gpio_direction_output(IMX_GPIO_NR(5, 2), 1); } else { imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); gpio_direction_output(IMX_GPIO_NR(5, 4), 0); udelay(50); gpio_direction_output(IMX_GPIO_NR(5, 4), 1); @@ -407,8 +410,9 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_SYS_USE_QSPI +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) @@ -430,13 +434,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; +#endif int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - +#endif /* Set the clock */ enable_qspi_clk(0); @@ -452,7 +458,7 @@ static struct fsl_esdhc_cfg usdhc_cfg[2] = { #else {USDHC1_BASE_ADDR, 0, 4}, #endif -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) {USDHC2_BASE_ADDR, 0, 4}, #endif }; @@ -492,7 +498,7 @@ int board_mmc_getcd(struct mmc *mmc) ret = !gpio_get_value(USDHC1_CD_GPIO); #endif break; -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) case USDHC2_BASE_ADDR: ret = !gpio_get_value(USDHC2_CD_GPIO); break; @@ -521,17 +527,22 @@ int board_mmc_init(bd_t *bis) #else imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); gpio_direction_input(USDHC1_CD_GPIO); #endif usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); gpio_direction_output(USDHC1_VSELECT, 0); gpio_direction_output(USDHC1_PWR_GPIO, 1); break; -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) case 1: imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_input(USDHC2_CD_GPIO); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); @@ -598,11 +609,12 @@ struct lcd_panel_info_t { void do_enable_parallel_lcd(struct display_info_t const *dev) { - enable_lcdif_clock(dev->bus); + enable_lcdif_clock(dev->bus, 1); imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); /* Set Brightness to high */ @@ -811,6 +823,105 @@ void ldo_mode_set(int ldo_bypass) } } #endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + #endif int board_early_init_f(void) @@ -837,7 +948,7 @@ int board_init(void) * DNP. */ -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif @@ -845,19 +956,19 @@ int board_init(void) setup_fec(CONFIG_FEC_ENET_DEV); #endif -#ifdef CONFIG_SYS_USE_SPINOR +#ifdef CONFIG_MXC_SPI setup_spinor(); #endif -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_CMD_NAND setup_gpmi_nand(); #endif -#ifdef CONFIG_SYS_USE_EIMNOR +#ifdef CONFIG_MTD_NOR_FLASH setup_eimnor(); #endif -#ifdef CONFIG_SYS_USE_QSPI +#ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig b/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig index 4f6e61a..e902da4 100644 --- a/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/Kconfig @@ -9,4 +9,13 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ul_14x14_lpddr2_arm2" +config MX6UL_LPDDR2_ARM2_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. + endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg b/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg index 083f864..0a084ce 100644 --- a/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/imximage.cfg @@ -21,9 +21,9 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ -#ifdef CONFIG_SYS_BOOT_QSPI +#ifdef CONFIG_QSPI_BOOT BOOT_FROM qspi -#elif defined(CONFIG_SYS_BOOT_EIMNOR) +#elif defined(CONFIG_NOR_BOOT) BOOT_FROM nor #else BOOT_FROM sd diff --git a/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c index b815f2a..9da8155 100644 --- a/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c +++ b/board/freescale/mx6ul_14x14_lpddr2_arm2/mx6ul_14x14_lpddr2_arm2.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <asm/imx-common/video.h> DECLARE_GLOBAL_DATA_PTR; @@ -80,7 +80,7 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* I2C1 for PMIC and EEPROM */ struct i2c_pads_info i2c_pad_info1 = { @@ -120,7 +120,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -137,7 +137,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) #ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK static iomux_v3_cfg_t const usdhc2_pads[] = { @@ -179,7 +179,7 @@ static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { #endif #endif -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_CMD_NAND static iomux_v3_cfg_t const nand_pads[] = { MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), @@ -217,7 +217,7 @@ static void setup_gpmi_nand(void) } #endif -#ifdef CONFIG_SYS_USE_SPINOR +#ifdef CONFIG_MXC_SPI /* pin conflicts with eim nor */ static iomux_v3_cfg_t const ecspi2_pads[] = { MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -231,6 +231,7 @@ static iomux_v3_cfg_t const ecspi2_pads[] = { static void setup_spinor(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 22), "escpi cs"); gpio_direction_output(IMX_GPIO_NR(4, 22), 0); } @@ -240,7 +241,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs) } #endif -#ifdef CONFIG_SYS_USE_EIMNOR +#ifdef CONFIG_MTD_NOR_FLASH /* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */ static iomux_v3_cfg_t const eimnor_pads[] = { MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), @@ -354,12 +355,14 @@ static void setup_iomux_fec(int fec_id) if (fec_id == 0) { imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + gpio_request(IMX_GPIO_NR(5, 4), "fec1 reset"); gpio_direction_output(IMX_GPIO_NR(5, 4), 0); udelay(50); gpio_direction_output(IMX_GPIO_NR(5, 4), 1); } else { imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); + gpio_request(IMX_GPIO_NR(5, 2), "fec2 reset"); gpio_direction_output(IMX_GPIO_NR(5, 2), 0); udelay(50); gpio_direction_output(IMX_GPIO_NR(5, 2), 1); @@ -372,8 +375,9 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -#ifdef CONFIG_SYS_USE_QSPI +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) @@ -395,13 +399,15 @@ static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), }; +#endif int board_qspi_init(void) { +#ifndef CONFIG_DM_SPI /* Set the iomux */ imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); - +#endif /* Set the clock */ enable_qspi_clk(0); @@ -410,7 +416,7 @@ int board_qspi_init(void) #endif #ifdef CONFIG_FSL_ESDHC -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC1_BASE_ADDR, 0, 1}, {USDHC2_BASE_ADDR, 0, 8}, @@ -436,7 +442,7 @@ int board_mmc_getcd(struct mmc *mmc) case USDHC1_BASE_ADDR: ret = !gpio_get_value(USDHC1_CD_GPIO); break; -#if !defined(CONFIG_SYS_USE_NAND) +#if !defined(CONFIG_CMD_NAND) case USDHC2_BASE_ADDR: #ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK ret = !gpio_get_value(USDHC2_CD_GPIO); @@ -465,8 +471,10 @@ int board_mmc_init(bd_t *bis) case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); gpio_direction_output(USDHC1_PWR_GPIO, 1); break; #if !defined(CONFIG_SYS_USE_NAND) @@ -474,12 +482,15 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_MX6UL_LPDDR2_ARM2_USDHC2_REWORK imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_input(USDHC2_CD_GPIO); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); #else imx_iomux_v3_setup_multiple_pads( usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_output(USDHC2_PWR_GPIO, 1); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); #endif @@ -547,14 +558,16 @@ struct lcd_panel_info_t { void do_enable_parallel_lcd(struct display_info_t const *dev) { - enable_lcdif_clock(dev->bus); + enable_lcdif_clock(dev->bus, 1); imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(4, 16), "backlight"); gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); } @@ -754,6 +767,105 @@ void ldo_mode_set(int ldo_bypass) } } #endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 1.3V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + #endif int board_early_init_f(void) @@ -768,7 +880,7 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_MXC +#ifdef CONFIG_SYS_I2C setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif @@ -776,15 +888,15 @@ int board_init(void) setup_fec(CONFIG_FEC_ENET_DEV); #endif -#ifdef CONFIG_SYS_USE_SPINOR +#ifdef CONFIG_MXC_SPI setup_spinor(); #endif -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_CMD_NAND setup_gpmi_nand(); #endif -#ifdef CONFIG_SYS_USE_EIMNOR +#ifdef CONFIG_MTD_NOR_FLASH /* * This function should be invoked after setup_fec, * because ENET2_RX_ER conflicts. However, we rarely need @@ -794,7 +906,7 @@ int board_init(void) setup_eimnor(); #endif -#ifdef CONFIG_SYS_USE_QSPI +#ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif |