diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc8315erdb/mpc8315erdb.c | 39 | ||||
| -rw-r--r-- | board/freescale/mpc8349emds/mpc8349emds.c | 9 | ||||
| -rw-r--r-- | board/freescale/mpc8349emds/pci.c | 414 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/Makefile (renamed from board/mvblm7/Makefile) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/config.mk (renamed from board/mvblm7/config.mk) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/fpga.c (renamed from board/mvblm7/fpga.c) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/fpga.h (renamed from board/mvblm7/fpga.h) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/mvblm7.c (renamed from board/mvblm7/mvblm7.c) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/mvblm7.h (renamed from board/mvblm7/mvblm7.h) | 0 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/mvblm7_autoscript (renamed from board/mvblm7/mvblm7_autoscript) | 10 | ||||
| -rw-r--r-- | board/matrix_vision/mvblm7/pci.c (renamed from board/mvblm7/pci.c) | 0 |
11 files changed, 157 insertions, 315 deletions
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 7af36dd..3eecee2 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -25,9 +25,8 @@ #include <common.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> -#endif +#include <fdt_support.h> #include <pci.h> #include <mpc83xx.h> @@ -122,11 +121,47 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) +void fdt_tsec1_fixup(void *fdt, bd_t *bd) +{ + char *mpc8315erdb = getenv("mpc8315erdb"); + const char disabled[] = "disabled"; + const char *path; + int ret; + + if (!mpc8315erdb) + return; + + if (!strcmp(mpc8315erdb, "tsec1")) { + return; + } else if (strcmp(mpc8315erdb, "ulpi")) { + printf("WARNING: wrong `mpc8315erdb' environment " + "variable specified: `%s'. Should be `ulpi' " + "or `tsec1'.\n", mpc8315erdb); + return; + } + + ret = fdt_path_offset(fdt, "/aliases"); + if (ret < 0) { + printf("WARNING: can't find /aliases node\n"); + return; + } + + path = fdt_getprop(fdt, ret, "ethernet0", NULL); + if (!path) { + printf("WARNING: can't find ethernet0 alias\n"); + return; + } + + do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif + fdt_fixup_dr_usb(blob, bd); + fdt_tsec1_fixup(blob, bd); } #endif diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 9a312c3..4c04f2c 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -165,6 +165,15 @@ int fixed_sdram(void) int checkboard (void) { + /* + * Warning: do not read the BCSR registers here + * + * There is a timing bug in the 8349E and 8349EA BCSR code + * version 1.2 (read from BCSR 11) that will cause the CFI + * flash initialization code to overwrite BCSR 0, disabling + * the serial ports and gigabit ethernet + */ + puts("Board: Freescale MPC8349EMDS\n"); return 0; } diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index ecc67b6..9c19e30 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -20,58 +20,63 @@ */ #include <asm/mmu.h> +#include <asm/io.h> #include <common.h> -#include <asm/global_data.h> +#include <mpc83xx.h> #include <pci.h> -#include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - +#include <asm/fsl_i2c.h> DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PCI -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349emds_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } +static struct pci_region pci1_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM }, - {} }; -#endif -static struct pci_controller pci_hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - } +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { + { + bus_start: CFG_PCI2_MEM_BASE, + phys_start: CFG_PCI2_MEM_PHYS, + size: CFG_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI2_IO_BASE, + phys_start: CFG_PCI2_IO_PHYS, + size: CFG_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CFG_PCI2_MMIO_BASE, + phys_start: CFG_PCI2_MMIO_PHYS, + size: CFG_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/************************************************************************** - * - * pib_init() -- initialize the PCA9555PW IO expander on the PIB board - * - */ -void -pib_init(void) +#ifndef CONFIG_PCISLAVE +void pib_init(void) { u8 val8, orig_i2c_bus; /* @@ -128,299 +133,86 @@ pib_init(void) i2c_set_bus_num(orig_i2c_bus); } -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ -void -pci_init_board(void) +void pci_init_board(void) { - volatile immap_t * immr; - volatile clk83xx_t * clk; - volatile law83xx_t * pci_law; - volatile pot83xx_t * pci_pot; - volatile pcictrl83xx_t * pci_ctrl; - volatile pciconf83xx_t * pci_conf; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller * hose; - - immr = (immap_t *)CFG_IMMR; - clk = (clk83xx_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif + /* initialize the PCA9555PW IO expander on the PIB board */ pib_init(); - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); + /* Enable all 8 PCI_CLK_OUTPUTS */ clk->occr = 0xff000000; udelay(2000); - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; - udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; ++i) - udelay (1000); - } - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, - CFG_PCI1_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + udelay(2000); -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); #endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, - CFG_PCI2_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; +} - pci_setup_indirect(hose, - (CFG_IMMR+0x8380), - (CFG_IMMR+0x8384)); +#else +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; - pci_register_hose(hose); + /* Enable all 8 PCI_CLK_OUTPUTS */ + clk->occr = 0xff000000; + udelay(2000); - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif + udelay(2000); + mpc83xx_pci_init(1, reg, 0); + + /* Configure PCI Inbound Translation Windows (3 1MB windows) */ + pci_ctrl->pitar0 = 0x0; + pci_ctrl->pibar0 = 0x0; + pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + pci_ctrl->pitar1 = 0x0; + pci_ctrl->pibar1 = 0x0; + pci_ctrl->piebar1 = 0x0; + pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + pci_ctrl->pitar2 = 0x0; + pci_ctrl->pibar2 = 0x0; + pci_ctrl->piebar2 = 0x0; + pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); } +#endif /* CONFIG_PCISLAVE */ -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#endif - } -} -#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/board/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index cfbecfb..cfbecfb 100644 --- a/board/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile diff --git a/board/mvblm7/config.mk b/board/matrix_vision/mvblm7/config.mk index 1d85f4f..1d85f4f 100644 --- a/board/mvblm7/config.mk +++ b/board/matrix_vision/mvblm7/config.mk diff --git a/board/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c index a60af01..a60af01 100644 --- a/board/mvblm7/fpga.c +++ b/board/matrix_vision/mvblm7/fpga.c diff --git a/board/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h index 19277eb..19277eb 100644 --- a/board/mvblm7/fpga.h +++ b/board/matrix_vision/mvblm7/fpga.h diff --git a/board/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index b07f913..b07f913 100644 --- a/board/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c diff --git a/board/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h index 03e9f41..03e9f41 100644 --- a/board/mvblm7/mvblm7.h +++ b/board/matrix_vision/mvblm7/mvblm7.h diff --git a/board/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/mvblm7_autoscript index ec6e34e..6f9357f 100644 --- a/board/mvblm7/mvblm7_autoscript +++ b/board/matrix_vision/mvblm7/mvblm7_autoscript @@ -5,11 +5,17 @@ setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} setenv ramkernel setenv kernel_boot \${loadaddr} setenv flashkernel setenv kernel_boot \${mv_kernel_addr} setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam bootdtb +setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +if test ${console} = yes; +then +setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 +else +setenv addcons setenv bootargs \${bootargs} console=tty0 +fi setenv set_static_ip setenv ipaddr \${static_ipaddr} setenv set_static_nm setenv netmask \${static_netmask} setenv set_static_gw setenv gatewayip \${static_gateway} @@ -24,7 +30,7 @@ then then echo "=== bootp succeeded -> netboot ===" run set_ip - run getdtb rundtb bootfromnet ramparam bootdtb + run getdtb rundtb bootfromnet ramparam addcons bootdtb else echo "=== netboot failed ===" fi diff --git a/board/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index ef34a6b..ef34a6b 100644 --- a/board/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c |