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-rw-r--r--board/BuS/eb_cpux9k2/config.mk1
-rw-r--r--board/BuS/eb_cpux9k2/cpux9k2.c7
-rw-r--r--board/LaCie/edminiv2/config.mk3
-rw-r--r--board/atmel/at91rm9200ek/Makefile5
-rw-r--r--board/atmel/at91rm9200ek/at91rm9200ek.c60
-rw-r--r--board/atmel/at91rm9200ek/config.mk3
-rw-r--r--board/atmel/at91rm9200ek/led.c58
-rw-r--r--board/atmel/at91rm9200ek/mux.c38
-rw-r--r--board/balloon3/Makefile47
-rw-r--r--board/balloon3/balloon3.c238
-rw-r--r--board/colibri_pxa270/colibri_pxa270.c33
-rw-r--r--board/cradle/cradle.c5
-rw-r--r--board/cradle/lowlevel_init.S4
-rw-r--r--board/csb226/csb226.c13
-rw-r--r--board/delta/delta.c37
-rw-r--r--board/delta/nand.c110
-rw-r--r--board/freescale/mx51evk/mx51evk.c2
-rw-r--r--board/innokom/innokom.c14
-rw-r--r--board/karo/tx25/config.mk2
-rw-r--r--board/logicpd/imx27lite/config.mk4
-rw-r--r--board/logicpd/imx31_litekit/config.mk2
-rw-r--r--board/logicpd/imx31_litekit/imx31_litekit.c10
-rw-r--r--board/palmld/Makefile49
-rw-r--r--board/palmld/config.mk1
-rw-r--r--board/palmld/lowlevel_init.S (renamed from board/zipitz2/lowlevel_init.S)9
-rw-r--r--board/palmld/palmld.c69
-rw-r--r--board/palmld/u-boot.lds (renamed from board/vpac270/u-boot.lds)7
-rw-r--r--board/palmtc/Makefile49
-rw-r--r--board/palmtc/config.mk1
-rw-r--r--board/palmtc/lowlevel_init.S (renamed from board/vpac270/lowlevel_init.S)3
-rw-r--r--board/palmtc/palmtc.c (renamed from board/atmel/at91rm9200ek/partition.c)61
-rw-r--r--board/palmtc/u-boot.lds (renamed from board/atmel/at91rm9200ek/misc.c)50
-rw-r--r--board/pxa255_idp/pxa_idp.c27
-rw-r--r--board/trizepsiv/conxs.c35
-rw-r--r--board/ttcontrol/vision2/vision2.c2
-rw-r--r--board/vpac270/Makefile17
-rw-r--r--board/vpac270/config.mk1
-rw-r--r--board/vpac270/vpac270.c92
-rw-r--r--board/wepep250/wepep250.c11
-rw-r--r--board/zipitz2/Makefile10
-rw-r--r--board/zipitz2/config.mk1
-rw-r--r--board/zipitz2/zipitz2.c57
-rw-r--r--board/zylonite/nand.c110
43 files changed, 898 insertions, 460 deletions
diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk
deleted file mode 100644
index e554a45..0000000
--- a/board/BuS/eb_cpux9k2/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x23f00000
diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index bbceaf3..fe62a0f 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -66,7 +66,7 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
@@ -134,9 +134,8 @@ void reset_phy(void)
int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size =
- get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
index d07642f..2ffd125 100644
--- a/board/LaCie/edminiv2/config.mk
+++ b/board/LaCie/edminiv2/config.mk
@@ -24,4 +24,5 @@
# MA 02110-1301 USA
#
-CONFIG_SYS_TEXT_BASE = 0x00100000
+# TEXT_BASE must equal the intended FLASH location of u-boot.
+CONFIG_SYS_TEXT_BASE = 0xfff90000
diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile
index 500ce72..96a0f05 100644
--- a/board/atmel/at91rm9200ek/Makefile
+++ b/board/atmel/at91rm9200ek/Makefile
@@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
-COBJS-y += misc.o
-ifdef CONFIG_HAS_DATAFLASH
-COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
-COBJS-y += partition.o
-endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c
index 570a09a..d242583 100644
--- a/board/atmel/at91rm9200ek/at91rm9200ek.c
+++ b/board/atmel/at91rm9200ek/at91rm9200ek.c
@@ -1,4 +1,8 @@
/*
+ * (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
+ *
+ * derived from previous work
+ *
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
@@ -23,78 +27,44 @@
*/
#include <common.h>
-#include <exports.h>
#include <netdev.h>
-#include <asm/arch/AT91RM9200.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
-#if defined(CONFIG_DRIVER_ETHER)
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-int board_init (void)
+int board_init(void)
{
- /* Enable Ctrlc */
- console_init_f ();
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
- writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
-
- /*
- * memory and cpu-speed are setup before relocation
- * so we do _nothing_ here
- */
+ writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
return 0;
}
-#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
-/*
- * Name:
- * at91rm9200_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
- * None
- * Return value:
- * None
- */
-void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
-{
- p_phyops->Init = dm9161_InitPhy;
- p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
- p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
- p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
-}
-#endif
-
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
- int rc = 0;
- rc = at91emac_register(bis, 0);
- return rc;
+ return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
diff --git a/board/atmel/at91rm9200ek/config.mk b/board/atmel/at91rm9200ek/config.mk
index 2077692..c7323fe 100644
--- a/board/atmel/at91rm9200ek/config.mk
+++ b/board/atmel/at91rm9200ek/config.mk
@@ -1 +1,2 @@
-CONFIG_SYS_TEXT_BASE = 0x21f00000
+# currently only NOR flash booting is supported
+CONFIG_SYS_TEXT_BASE = 0x10000000
diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c
index 9464952..8d512e0 100644
--- a/board/atmel/at91rm9200ek/led.c
+++ b/board/atmel/at91rm9200ek/led.c
@@ -3,6 +3,9 @@
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
+ * (C) Copyright 2010
+ * Andreas Bießmann <andreas.devel@gmail.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -23,67 +26,62 @@
*/
#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pmc.h>
-#define GREEN_LED AT91C_PIO_PB0
-#define YELLOW_LED AT91C_PIO_PB1
-#define RED_LED AT91C_PIO_PB2
+/* bit mask in PIO port B */
+#define GREEN_LED (1<<0)
+#define YELLOW_LED (1<<1)
+#define RED_LED (1<<2)
void green_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_CODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(GREEN_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(YELLOW_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
-
- writel(RED_LED, PIOB->PIO_SODR);
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
+ writel(RED_LED, &pio->piob.sodr);
}
-
void coloured_LED_init (void)
{
- AT91PS_PIO PIOB = AT91C_BASE_PIOB;
- AT91PS_PMC PMC = AT91C_BASE_PMC;
+ at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
- writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
+ writel(1 << AT91_ID_PIOB, &pmc->pcer);
+
/* Disable peripherals on LEDs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
- writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
+ writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}
diff --git a/board/atmel/at91rm9200ek/mux.c b/board/atmel/at91rm9200ek/mux.c
deleted file mode 100644
index bdd44e8..0000000
--- a/board/atmel/at91rm9200ek/mux.c
+++ /dev/null
@@ -1,38 +0,0 @@
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
-#include <dataflash.h>
-
-int AT91F_GetMuxStatus(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
-
- if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
- return 1;
-
- return 0;
-}
-
-void AT91F_SelectMMC(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Set Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
-}
-
-void AT91F_SelectSPI(void)
-{
- /* Set in PIO mode */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
- /* Configure in output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
- /* Clear Output */
- writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
-}
diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile
new file mode 100644
index 0000000..7db615e
--- /dev/null
+++ b/board/balloon3/Makefile
@@ -0,0 +1,47 @@
+#
+# Balloon3 Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := balloon3.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c
new file mode 100644
index 0000000..26e34e9
--- /dev/null
+++ b/board/balloon3/balloon3.c
@@ -0,0 +1,238 @@
+/*
+ * Balloon3 Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <spartan3.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void balloon3_init_fpga(void);
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ /* arch number of vpac270 */
+ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Init the FPGA */
+ balloon3_init_fpga();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_stuart_device;
+}
+
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+}
+
+#ifdef CONFIG_CMD_USB
+int usb_board_init(void)
+{
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
+
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
+
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
+
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
+
+ /* Clear any OTG Pin Hold */
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
+
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
+
+ /* Set port power control mask bits, only 3 ports. */
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
+
+ /* enable port 2 */
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
+
+ return 0;
+}
+
+void usb_board_init_fail(void)
+{
+ return;
+}
+
+void usb_board_stop(void)
+{
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+ udelay(11);
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
+
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
+ udelay(10);
+
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
+
+ return;
+}
+#endif
+
+#if defined(CONFIG_FPGA)
+/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */
+int fpga_pgm_fn(int nassert, int nflush, int cookie)
+{
+ if (nassert)
+ writel(0x80, GPCR3);
+ else
+ writel(0x80, GPSR3);
+ if (nflush)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+ return nassert;
+}
+
+/* Check GPIO83 -- INITB */
+int fpga_init_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x80000);
+}
+
+/* Check GPIO84 -- BUSY */
+int fpga_busy_fn(int cookie)
+{
+ return !(readl(GPLR2) & 0x100000);
+}
+
+/* Check GPIO111 -- DONE */
+int fpga_done_fn(int cookie)
+{
+ return readl(GPLR3) & 0x8000;
+}
+
+/* Configure GPIO104 as GPIO and deassert it */
+int fpga_pre_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
+ writel(0x100, GPCR3);
+ return 0;
+}
+
+/* Configure GPIO104 as nSKTSEL */
+int fpga_post_config_fn(int cookie)
+{
+ writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
+ return 0;
+}
+
+/* Toggle RDnWR */
+int fpga_wr_fn(int nassert_write, int flush, int cookie)
+{
+ udelay(1000);
+
+ if (nassert_write)
+ writel(0x100, GPCR3);
+ else
+ writel(0x100, GPSR3);
+
+ return nassert_write;
+}
+
+/* Write program to the FPGA */
+int fpga_wdata_fn(uchar data, int flush, int cookie)
+{
+ writeb(data, 0x10f00000);
+ return 0;
+}
+
+/* Toggle Clock pin -- NO-OP */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+/* Toggle ChipSelect pin -- NO-OP */
+int fpga_cs_fn(int assert_clk, int flush, int cookie)
+{
+ return assert_clk;
+}
+
+Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
+ fpga_pre_config_fn,
+ fpga_pgm_fn,
+ fpga_init_fn,
+ NULL, /* err */
+ fpga_done_fn,
+ fpga_clk_fn,
+ fpga_cs_fn,
+ fpga_wr_fn,
+ NULL, /* rdata */
+ fpga_wdata_fn,
+ fpga_busy_fn,
+ NULL, /* abort */
+ fpga_post_config_fn,
+};
+
+Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
+ (void *)&balloon3_fpga_fns, 0);
+
+/* Initialize the FPGA */
+void balloon3_init_fpga(void)
+{
+ fpga_init();
+ fpga_add(fpga_xilinx, &fpga);
+}
+#else
+void balloon3_init_fpga(void) {}
+#endif /* CONFIG_FPGA */
diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c
index 84ec38e..8aa7067 100644
--- a/board/colibri_pxa270/colibri_pxa270.c
+++ b/board/colibri_pxa270/colibri_pxa270.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -65,28 +66,30 @@ int dram_init (void)
#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
while (UHCHR & UHCHR_FSBIR);
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -98,14 +101,14 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c
index 21eb655..c4a93f9 100644
--- a/board/cradle/cradle.c
+++ b/board/cradle/cradle.c
@@ -28,6 +28,7 @@
#include <asm/arch/pxa-regs.h>
#include <common.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -92,8 +93,8 @@ set_led (int led, int color)
int shift = led * 2;
unsigned long mask = 0x3 << shift;
- CRADLE_LED_CLR_REG = mask; /* clear bits */
- CRADLE_LED_SET_REG = (color << shift); /* set bits */
+ writel(mask, GPCR2); /* clear bits */
+ writel((color << shift), GPSR2); /* set bits */
udelay (5000);
}
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
index 6b5cfb9..39964b6 100644
--- a/board/cradle/lowlevel_init.S
+++ b/board/cradle/lowlevel_init.S
@@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
.endm
.macro SET_LED val
- ldr r6, =CRADLE_LED_CLR_REG
+ ldr r6, =GPCR2
ldr r7, =0
str r7, [r6]
- ldr r6, =CRADLE_LED_SET_REG
+ ldr r6, =GPSR2
ldr r7, =\val
str r7, [r6]
.endm
diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c
index 0a6c13d..6eed9ad 100644
--- a/board/csb226/csb226.c
+++ b/board/csb226/csb226.c
@@ -26,6 +26,7 @@
#include <common.h>
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
switch(led) {
case 0: if (state==1) {
- GPCR0 |= CSB226_USER_LED0;
+ writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED0;
+ writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0);
}
break;
case 1: if (state==1) {
- GPCR0 |= CSB226_USER_LED1;
+ writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED1;
+ writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0);
}
break;
case 2: if (state==1) {
- GPCR0 |= CSB226_USER_LED2;
+ writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0);
} else if (state==0) {
- GPSR0 |= CSB226_USER_LED2;
+ writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0);
}
break;
}
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 68c39d2..df23076 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -28,6 +28,7 @@
#include <malloc.h>
#include <command.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd";
static void get_pressed_keys(uchar *s)
{
unsigned long val;
- val = GPLR3;
+ val = readl(GPLR3);
if(val & (1<<31))
*s++ = KEYBD_KP_DKIN0;
@@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s)
static void keys_init()
{
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Configure GPIOs */
- GPIO127 = 0xa840; /* KP_DKIN0 */
- GPIO114 = 0xa840; /* KP_DKIN1 */
- GPIO125 = 0xa840; /* KP_DKIN2 */
- GPIO118 = 0xa840; /* KP_DKIN5 */
+ writel(0xa840, GPIO127); /* KP_DKIN0 */
+ writel(0xa840, GPIO114); /* KP_DKIN1 */
+ writel(0xa840, GPIO125); /* KP_DKIN2 */
+ writel(0xa840, GPIO118); /* KP_DKIN5 */
/* Configure GPIOs as inputs */
- GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
- GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
+ writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3);
+ writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3);
udelay(100);
}
@@ -283,11 +284,11 @@ int dram_init (void)
void i2c_init_board()
{
- CKENB |= (CKENB_4_I2C);
+ writel(readl(CKENB) | (CKENB_4_I2C), CKENB);
/* setup I2C GPIO's */
- GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
- GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
+ writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */
+ writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */
}
/* initialize the DA9030 Power Controller */
@@ -295,20 +296,20 @@ static void init_DA9030()
{
uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
- CKENB |= CKENB_7_GPIO;
+ writel(readl(CKENB) | CKENB_7_GPIO, CKENB);
udelay(100);
/* Rising Edge on EXTON to reset DA9030 */
- GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */
- GPDR0 |= (1<<17); /* GPIO17 is output */
- GSDR0 = (1<<17);
- GPCR0 = (1<<17); /* drive GPIO17 low */
- GPSR0 = (1<<17); /* drive GPIO17 high */
+ writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */
+ writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */
+ writel((1<<17), GSDR0);
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
+ writel((1<<17), GPSR0); /* drive GPIO17 high */
#if CONFIG_SYS_DA9030_EXTON_DELAY
udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */
#endif
- GPCR0 = (1<<17); /* drive GPIO17 low */
+ writel((1<<17), GPCR0); /* drive GPIO17 low */
/* reset the watchdog and go active (0xec) */
val = (SYS_CONTROL_A_HWRES_ENABLE |
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 85a6ba2..119a587 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -26,6 +26,7 @@
#include <nand.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
#ifdef CONFIG_SYS_DFC_DEBUG1
# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -120,7 +121,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -166,8 +167,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -202,14 +203,14 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event)
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -243,11 +244,11 @@ static void dfc_new_cmd(void)
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xfff, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -372,36 +373,36 @@ static void dfc_gpio_init(void)
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1, GPIO4);
+
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
+
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand)
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand)
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand)
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand)
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 84386e6..c8d7d39 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -23,7 +23,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/iomux.h>
#include <asm/errno.h>
#include <asm/arch/sys_proto.h>
diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c
index 3412f10..2c51125 100644
--- a/board/innokom/innokom.c
+++ b/board/innokom/innokom.c
@@ -27,6 +27,7 @@
#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -48,20 +49,21 @@ int i2c_init_board(void)
/* disable I2C controller first, otherwhise it thinks we want to */
/* talk to the slave port... */
- icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE);
+ icr = readl(ICR);
+ writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR);
/* set gpio pin low _before_ we change direction to output */
- GPCR(70) = GPIO_bit(70);
+ writel(GPIO_bit(70), GPCR(70));
/* now toggle between output=low and high-impedance */
for (i = 0; i < 20; i++) {
- GPDR(70) |= GPIO_bit(70); /* output */
+ writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */
udelay(10);
- GPDR(70) &= ~GPIO_bit(70); /* input */
+ writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */
udelay(10);
}
- ICR = icr;
+ writel(icr, ICR);
return 0;
}
@@ -76,7 +78,7 @@ int misc_init_r(void)
char *str;
/* determine if the software update key is pressed during startup */
- if (GPLR0 & 0x00000800) {
+ if (readl(GPLR0) & 0x00000800) {
printf("using bootcmd_normal (sw-update button not pressed)\n");
str = getenv("bootcmd_normal");
} else {
diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk
index 4283c3e..18b2883 100644
--- a/board/karo/tx25/config.mk
+++ b/board/karo/tx25/config.mk
@@ -1,5 +1,5 @@
ifdef CONFIG_NAND_SPL
CONFIG_SYS_TEXT_BASE = 0x810c0000
else
-CONFIG_SYS_TEXT_BASE = 0x81fc0000
+CONFIG_SYS_TEXT_BASE = 0x81200000
endif
diff --git a/board/logicpd/imx27lite/config.mk b/board/logicpd/imx27lite/config.mk
index 7f22154..018d920 100644
--- a/board/logicpd/imx27lite/config.mk
+++ b/board/logicpd/imx27lite/config.mk
@@ -1 +1,5 @@
+# with relocation CONFIG_SYS_TEXT_BASE can be anything, and making it 0
+# makes relative and absolute relocation fixups interchangeable.
+#CONFIG_SYS_TEXT_BASE = 0
+
CONFIG_SYS_TEXT_BASE = 0xc0000000
diff --git a/board/logicpd/imx31_litekit/config.mk b/board/logicpd/imx31_litekit/config.mk
index 0131edf..a7887ba 100644
--- a/board/logicpd/imx31_litekit/config.mk
+++ b/board/logicpd/imx31_litekit/config.mk
@@ -1 +1 @@
-CONFIG_SYS_TEXT_BASE = 0x87f00000
+CONFIG_SYS_TEXT_BASE = 0xa0000000
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 2ac622d..a07ba0e 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -31,12 +31,18 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init (void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
+void
+dram_init_banksize (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
int board_init (void)
{
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
diff --git a/board/palmld/Makefile b/board/palmld/Makefile
new file mode 100644
index 0000000..bcb014d
--- /dev/null
+++ b/board/palmld/Makefile
@@ -0,0 +1,49 @@
+#
+# Palm LifeDrive Support
+#
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := palmld.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/palmld/config.mk b/board/palmld/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/palmld/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/zipitz2/lowlevel_init.S b/board/palmld/lowlevel_init.S
index 82a52e8..e3382ee 100644
--- a/board/zipitz2/lowlevel_init.S
+++ b/board/palmld/lowlevel_init.S
@@ -1,9 +1,8 @@
/*
- * Aeronix Zipit Z2 Lowlevel Hardware Initialization
+ * Palm LifeDrive Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
- *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,6 +30,12 @@
.globl lowlevel_init
lowlevel_init:
pxa_gpio_setup
+
+ /* Enable GPIO reset */
+ ldr r0, =PCFR
+ mov r1, #0x30
+ str r1, [r0]
+
pxa_wait_ticks 0x8000
pxa_mem_setup
pxa_wakeup
diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c
new file mode 100644
index 0000000..4f0087e
--- /dev/null
+++ b/board/palmld/palmld.c
@@ -0,0 +1,69 @@
+/*
+ * Palm LifeDrive Support
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMLD;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x7, PWM_CTRL0);
+ writel(0x16c, PWM_PERVAL0);
+ writel(0x11a, PWM_PWDUTY0);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ info->portwidth = FLASH_CFI_16BIT;
+ info->chipwidth = FLASH_CFI_BY16;
+ info->interface = FLASH_CFI_X16;
+ return 1;
+}
diff --git a/board/vpac270/u-boot.lds b/board/palmld/u-boot.lds
index 58c371d..fb4358b 100644
--- a/board/vpac270/u-boot.lds
+++ b/board/palmld/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -36,7 +36,7 @@ SECTIONS
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : { *(.data) }
@@ -44,12 +44,13 @@ SECTIONS
. = ALIGN(4);
.got : { *(.got) }
+ . = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
- .bss : { *(.bss) }
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
}
diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile
new file mode 100644
index 0000000..20ac4e1
--- /dev/null
+++ b/board/palmtc/Makefile
@@ -0,0 +1,49 @@
+#
+# Palm Tungsten|C Support
+#
+# Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := palmtc.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk
new file mode 100644
index 0000000..1d650ac
--- /dev/null
+++ b/board/palmtc/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xa1000000
diff --git a/board/vpac270/lowlevel_init.S b/board/palmtc/lowlevel_init.S
index ec0d12c..74050dc 100644
--- a/board/vpac270/lowlevel_init.S
+++ b/board/palmtc/lowlevel_init.S
@@ -1,9 +1,8 @@
/*
- * Voipac PXA270 Lowlevel Hardware Initialization
+ * Palm Tungsten|C Lowlevel Hardware Initialization
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
- *
* See file CREDITS for list of people who contributed to this
* project.
*
diff --git a/board/atmel/at91rm9200ek/partition.c b/board/palmtc/palmtc.c
index 990cbcf..04cb33e 100644
--- a/board/atmel/at91rm9200ek/partition.c
+++ b/board/palmtc/palmtc.c
@@ -1,4 +1,7 @@
/*
+ * Palm Tungsten|C Support
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -14,25 +17,43 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
*/
+
#include <common.h>
-#include <config.h>
-#include <asm/hardware.h>
-#include <dataflash.h>
-
-AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
-
-struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
- {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
-};
-
-/*define the area offsets*/
-dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
- {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
- {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
- {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
- {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
- {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
-};
+#include <command.h>
+#include <serial.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ /* Arch number of Palm Tungsten|C */
+ gd->bd->bi_arch_number = MACH_TYPE_PALMTC;
+
+ /* Adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ /* Set PWM for LCD */
+ writel(0x5f, PWM_CTRL1);
+ writel(0x3ff, PWM_PERVAL1);
+ writel(892, PWM_PWDUTY1);
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_ffuart_device;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
diff --git a/board/atmel/at91rm9200ek/misc.c b/board/palmtc/u-boot.lds
index 81de32f..fb4358b 100644
--- a/board/atmel/at91rm9200ek/misc.c
+++ b/board/palmtc/u-boot.lds
@@ -1,7 +1,6 @@
/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,29 +21,36 @@
* MA 02111-1307 USA
*/
-#include <common.h>
-#include <asm/arch/AT91RM9200.h>
-#include <at91rm9200_net.h>
-#include <dm9161.h>
-#include <net.h>
-
-int board_late_init(void)
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
{
- DECLARE_GLOBAL_DATA_PTR;
+ . = 0x00000000;
- /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
- eth_init(gd->bd);
- return 0;
-}
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-/* checks if addr is in RAM */
-int addr2ram(ulong addr)
-{
- int result = 0;
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
- if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
- result = 1;
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
- return result;
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
+ _end = .;
}
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index a54a95d..4ab8bd4 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -33,6 +33,7 @@
#include <common.h>
#include <netdev.h>
#include <command.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -56,14 +57,14 @@ int board_init (void)
/* set PWM for LCD */
/* a value that works is 60Hz, 77% duty cycle */
- CKEN |= CKEN0_PWM0;
- PWM_CTRL0 = 0x3f;
- PWM_PERVAL0 = 0x3ff;
- PWM_PWDUTY0 = 792;
+ writel(readl(CKEN) | CKEN0_PWM0, CKEN);
+ writel(0x3f, PWM_CTRL0);
+ writel(0x3ff, PWM_PERVAL0);
+ writel(792, PWM_PWDUTY0);
/* clear reset to AC97 codec */
- CKEN |= CKEN2_AC97;
- GCR = GCR_COLD_RST;
+ writel(readl(CKEN) | CKEN2_AC97, CKEN);
+ writel(GCR_COLD_RST, GCR);
/* enable LCD backlight */
/* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */
@@ -102,11 +103,11 @@ int dram_init (void)
void delay_c(void)
{
/* reset OSCR to 0 */
- OSCR = 0;
- while(OSCR > 0x10000)
+ writel(0, OSCR);
+ while (readl(OSCR) > 0x10000)
;
- while(OSCR < 0xd4000)
+ while (readl(OSCR) < 0xd4000)
;
}
@@ -114,12 +115,12 @@ void blink_c(void)
{
int led_bit = (1<<10);
- GPDR0 = led_bit;
- GPCR0 = led_bit;
+ writel(led_bit, GPDR0);
+ writel(led_bit, GPCR0);
delay_c();
- GPSR0 = led_bit;
+ writel(led_bit, GPSR0);
delay_c();
- GPCR0 = led_bit;
+ writel(led_bit, GPCR0);
}
int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 8c11456..0c67367 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -34,6 +34,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -44,7 +45,7 @@ extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
-#if CONFIG_POLARIS
+#if CONFIG_MK_POLARIS
#define BOOT_CONSOLE "serial_stuart"
#else
#define BOOT_CONSOLE "serial_ffuart"
@@ -57,25 +58,27 @@ extern struct serial_device serial_stuart_device;
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(RH_A_NPS);
- UHCRHDA |= RH_A_PSM;
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
return 0;
}
@@ -87,14 +90,14 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index c991ee2..ce4cb78 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -26,7 +26,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#include <asm/arch/mx51_pins.h>
+#include <asm/arch/mx5x_pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <mxc_gpio.h>
diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile
index c6f4c7c..c359917 100644
--- a/board/vpac270/Makefile
+++ b/board/vpac270/Makefile
@@ -1,10 +1,7 @@
-
#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Voipac PXA270 Support
#
-# See file CREDITS for list of people who contributed to this
-# project.
+# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -27,17 +24,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := vpac270.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/vpac270/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 18e47e2..43bbdff 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -1,16 +1,7 @@
/*
- * (C) Copyright 2004
- * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ * Voipac PXA270 Support
*
- * (C) Copyright 2002
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -31,29 +22,24 @@
#include <common.h>
#include <asm/arch/hardware.h>
#include <netdev.h>
+#include <serial.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
-/* ------------------------------------------------------------------------- */
-
/*
* Miscelaneous platform dependent initialisations
*/
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-struct serial_device *default_serial_console (void)
+int board_init(void)
{
- return &serial_ffuart_device;
-}
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
-int board_init (void)
-{
/* memory and cpu-speed are setup before relocation */
/* so we do _nothing_ here */
- /* arch number of vpac270 */
+ /* Arch number of vpac270 */
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
/* adress of boot parameters */
@@ -62,41 +48,58 @@ int board_init (void)
return 0;
}
-int dram_init (void)
+struct serial_device *default_serial_console(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ return &serial_ffuart_device;
+}
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- return 0;
+#ifdef CONFIG_RAM_256M
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
}
+#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(0x200);
- UHCRHDA |= 0x100;
+ writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
+ writel(readl(UHCRHDA) | 0x100, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
/* enable port 2 */
- UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+ writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
+ UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
return 0;
}
@@ -108,17 +111,18 @@ void usb_board_init_fail(void)
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
+#endif
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c
index fe4b6a9..6e41ea6 100644
--- a/board/wepep250/wepep250.c
+++ b/board/wepep250/wepep250.c
@@ -22,6 +22,7 @@
#include <common.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,13 +34,13 @@ int board_init (void)
* Setup GPIO stuff to get serial working
*/
#if defined( CONFIG_FFUART )
- GPDR1 = 0x80;
- GAFR1_L = 0x8010;
+ writel(0x80, GPDR1);
+ writel(0x8010, GAFR1_L);
#elif defined( CONFIG_BTUART )
- GPDR1 = 0x800;
- GAFR1_L = 0x900000;
+ writel(0x800, GPDR1);
+ writel(0x900000, GAFR1_L);
#endif
- PSSR = 0x20;
+ writel(0x20, PSSR);
return 0;
}
diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile
index 2673835..8d452de 100644
--- a/board/zipitz2/Makefile
+++ b/board/zipitz2/Makefile
@@ -29,17 +29,15 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := zipitz2.o
-SOBJS := lowlevel_init.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
- rm -f $(SOBJS) $(OBJS)
+ rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk
deleted file mode 100644
index 0f10662..0000000
--- a/board/zipitz2/config.mk
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0xa1000000
diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c
index 14d1d76..9e6a0d5 100644
--- a/board/zipitz2/zipitz2.c
+++ b/board/zipitz2/zipitz2.c
@@ -28,6 +28,7 @@
#include <serial.h>
#include <asm/arch/hardware.h>
#include <spi.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -43,10 +44,11 @@ inline void lcd_start(void) {};
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
- /* arch number of Lubbock-Board */
+ /* arch number of Z2 */
gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
/* adress of boot parameters */
@@ -58,24 +60,23 @@ int board_init (void)
return 0;
}
-int board_late_init(void)
+struct serial_device *default_serial_console (void)
{
- setenv("stdout", "serial");
- setenv("stderr", "serial");
- return 0;
+ return &serial_stuart_device;
}
-struct serial_device *default_serial_console (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
{
- return &serial_stuart_device;
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
}
-int dram_init (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
}
#ifdef CONFIG_CMD_SPI
@@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set)
{
/* GPIO 13 */
if (set)
- GPSR0 = (1 << 13);
+ writel((1 << 13), GPSR0);
else
- GPCR0 = (1 << 13);
+ writel((1 << 13), GPCR0);
}
void zipitz2_spi_scl(int set)
{
/* GPIO 22 */
if (set)
- GPCR0 = (1 << 22);
+ writel((1 << 22), GPCR0);
else
- GPSR0 = (1 << 22);
+ writel((1 << 22), GPSR0);
}
unsigned char zipitz2_spi_read(void)
{
/* GPIO 40 */
- return !!(GPLR1 & (1 << 8));
+ return !!(readl(GPLR1) & (1 << 8));
}
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
@@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
void spi_cs_activate(struct spi_slave *slave)
{
/* GPIO 88 low */
- GPCR2 = (1 << 24);
+ writel((1 << 24), GPCR2);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
/* GPIO 88 high */
- GPSR2 = (1 << 24);
+ writel((1 << 24), GPSR2);
}
@@ -176,20 +177,20 @@ void lcd_start(void)
unsigned char dummy[3] = { 0, 0, 0 };
/* PWM2 AF */
- GAFR0_L |= 0x00800000;
+ writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
/* Enable clock to all PWM */
- CKEN |= 0x3;
+ writel(readl(CKEN) | 0x3, CKEN);
/* Configure PWM2 */
- PWM_CTRL2 = 0x4f;
- PWM_PWDUTY2 = 0x2ff;
- PWM_PERVAL2 = 792;
+ writel(0x4f, PWM_CTRL2);
+ writel(0x2ff, PWM_PWDUTY2);
+ writel(792, PWM_PERVAL2);
/* Toggle the reset pin to reset the LCD */
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(100000);
- GPCR0 = (1 << 19);
+ writel((1 << 19), GPCR0);
udelay(20000);
- GPSR0 = (1 << 19);
+ writel((1 << 19), GPSR0);
udelay(20000);
/* Program the LCD init sequence */
@@ -208,6 +209,6 @@ void lcd_start(void)
udelay(lcd_data[i].mdelay * 1000);
}
- GPSR0 = (1 << 11);
+ writel((1 << 11), GPSR0);
}
#endif
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 7cad1ac..71d18a6 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -21,6 +21,7 @@
*/
#include <common.h>
+#include <asm/io.h>
#if defined(CONFIG_CMD_NAND)
@@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- NDDB = *long_buf;
+ writel(*long_buf, NDDB);
}
}
if(rest) {
@@ -125,7 +126,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
if(bytes_multi) {
for(i=0; i<bytes_multi; i+=4) {
long_buf = (unsigned long*) &buf[i];
- *long_buf = NDDB;
+ *long_buf = readl(NDDB);
}
}
@@ -171,8 +172,8 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
unsigned long dummy;
if(bytes_read < 0) {
- read_buf = NDDB;
- dummy = NDDB;
+ read_buf = readl(NDDB);
+ dummy = readl(NDDB);
bytes_read = 0;
}
byte = (unsigned char) (read_buf>>(8 * bytes_read++));
@@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd)
/* calculate delta between OSCR values start and now */
static unsigned long get_delta(unsigned long start)
{
- unsigned long cur = OSCR;
+ unsigned long cur = readl(OSCR);
if(cur < start) /* OSCR overflowed */
return (cur + (start^0xffffffff));
@@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
/* delay function, this doesn't belong here */
static void wait_us(unsigned long us)
{
- unsigned long start = OSCR;
+ unsigned long start = readl(OSCR);
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
@@ -207,14 +208,14 @@ static void wait_us(unsigned long us)
static void dfc_clear_nddb(void)
{
- NDCR &= ~NDCR_ND_RUN;
+ writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR);
wait_us(CONFIG_SYS_NAND_OTHER_TO);
}
/* wait_event with timeout */
static unsigned long dfc_wait_event(unsigned long event)
{
- unsigned long ndsr, timeout, start = OSCR;
+ unsigned long ndsr, timeout, start = readl(OSCR);
if(!event)
return 0xff000000;
@@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event)
* OSCR_CLK_FREQ, 1000);
while(1) {
- ndsr = NDSR;
+ ndsr = readl(NDSR);
if(ndsr & event) {
- NDSR |= event;
+ writel(readl(NDSR) | event, NDSR);
break;
}
if(get_delta(start) > timeout) {
@@ -248,11 +249,11 @@ static void dfc_new_cmd(void)
while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
/* Clear NDSR */
- NDSR = 0xFFF;
+ writel(0xFFF, NDSR);
/* set NDCR[NDRUN] */
- if(!(NDCR & NDCR_ND_RUN))
- NDCR |= NDCR_ND_RUN;
+ if (!(readl(NDCR) & NDCR_ND_RUN))
+ writel(readl(NDCR) | NDCR_ND_RUN, NDCR);
status = dfc_wait_event(NDSR_WRCMDREQ);
@@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
}
write_cmd:
- NDCB0 = ndcb0;
- NDCB0 = ndcb1;
- NDCB0 = ndcb2;
+ writel(ndcb0, NDCB0);
+ writel(ndcb1, NDCB0);
+ writel(ndcb2, NDCB0);
/* wait_event: */
dfc_wait_event(event);
@@ -377,36 +378,36 @@ static void dfc_gpio_init(void)
DFC_DEBUG2("Setting up DFC GPIO's.\n");
/* no idea what is done here, see zylonite.c */
- GPIO4 = 0x1;
-
- DF_ALE_WE1 = 0x00000001;
- DF_ALE_WE2 = 0x00000001;
- DF_nCS0 = 0x00000001;
- DF_nCS1 = 0x00000001;
- DF_nWE = 0x00000001;
- DF_nRE = 0x00000001;
- DF_IO0 = 0x00000001;
- DF_IO8 = 0x00000001;
- DF_IO1 = 0x00000001;
- DF_IO9 = 0x00000001;
- DF_IO2 = 0x00000001;
- DF_IO10 = 0x00000001;
- DF_IO3 = 0x00000001;
- DF_IO11 = 0x00000001;
- DF_IO4 = 0x00000001;
- DF_IO12 = 0x00000001;
- DF_IO5 = 0x00000001;
- DF_IO13 = 0x00000001;
- DF_IO6 = 0x00000001;
- DF_IO14 = 0x00000001;
- DF_IO7 = 0x00000001;
- DF_IO15 = 0x00000001;
-
- DF_nWE = 0x1901;
- DF_nRE = 0x1901;
- DF_CLE_NOE = 0x1900;
- DF_ALE_WE1 = 0x1901;
- DF_INT_RnB = 0x1900;
+ writel(0x1, GPIO4);
+
+ writel(0x00000001, DF_ALE_nWE1);
+ writel(0x00000001, DF_ALE_nWE2);
+ writel(0x00000001, DF_nCS0);
+ writel(0x00000001, DF_nCS1);
+ writel(0x00000001, DF_nWE);
+ writel(0x00000001, DF_nRE);
+ writel(0x00000001, DF_IO0);
+ writel(0x00000001, DF_IO8);
+ writel(0x00000001, DF_IO1);
+ writel(0x00000001, DF_IO9);
+ writel(0x00000001, DF_IO2);
+ writel(0x00000001, DF_IO10);
+ writel(0x00000001, DF_IO3);
+ writel(0x00000001, DF_IO11);
+ writel(0x00000001, DF_IO4);
+ writel(0x00000001, DF_IO12);
+ writel(0x00000001, DF_IO5);
+ writel(0x00000001, DF_IO13);
+ writel(0x00000001, DF_IO6);
+ writel(0x00000001, DF_IO14);
+ writel(0x00000001, DF_IO7);
+ writel(0x00000001, DF_IO15);
+
+ writel(0x1901, DF_nWE);
+ writel(0x1901, DF_nRE);
+ writel(0x1900, DF_CLE_nOE);
+ writel(0x1901, DF_ALE_nWE1);
+ writel(0x1900, DF_INT_RnB);
}
/*
@@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand)
dfc_gpio_init();
/* turn on the NAND Controller Clock (104 MHz @ D0) */
- CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+ writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA);
#undef CONFIG_SYS_TIMING_TIGHT
#ifndef CONFIG_SYS_TIMING_TIGHT
@@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand)
tRP_high = 0;
}
- NDTR0CS0 = (tCH << 19) |
+ writel((tCH << 19) |
(tCS << 16) |
(tWH << 11) |
(tWP << 8) |
(tRP_high << 6) |
(tRH << 3) |
- (tRP << 0);
+ (tRP << 0),
+ NDTR0CS0);
- NDTR1CS0 = (tR << 16) |
+ writel((tR << 16) |
(tWHR << 4) |
- (tAR << 0);
+ (tAR << 0),
+ NDTR1CS0);
/* If it doesn't work (unlikely) think about:
* - ecc enable
@@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand)
*/
/* NDCR_NCSX | /\* Chip select busy don't care *\/ */
- NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ writel(NDCR_SPARE_EN | /* use the spare area */
NDCR_DWIDTH_C | /* 16bit DFC data bus width */
NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
(2 << 16) | /* read id count = 7 ???? mk@tbd */
@@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand)
NDCR_SBERRM | /* single bit error ir masked */
NDCR_WRDREQM | /* write data request ir masked */
NDCR_RDDREQM | /* read data request ir masked */
- NDCR_WRCMDREQM); /* write command request ir masked */
+ NDCR_WRCMDREQM, /* write command request ir masked */
+ NDCR);
/* wait 10 us due to cmd buffer clear reset */