diff options
Diffstat (limited to 'board')
41 files changed, 4500 insertions, 126 deletions
diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig new file mode 100644 index 0000000..e2cd9f0 --- /dev/null +++ b/board/bluewater/gurnard/Kconfig @@ -0,0 +1,12 @@ +if TARGET_GURNARD + +config SYS_BOARD + default "gurnard" + +config SYS_VENDOR + default "bluewater" + +config SYS_CONFIG_NAME + default "snapper9g45" + +endif diff --git a/board/bluewater/gurnard/MAINTAINERS b/board/bluewater/gurnard/MAINTAINERS new file mode 100644 index 0000000..5e546d4 --- /dev/null +++ b/board/bluewater/gurnard/MAINTAINERS @@ -0,0 +1,6 @@ +GURNARD BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/bluewater/gurnard/ +F: include/configs/snapper9g45.h +F: configs/gurnard_defconfig diff --git a/board/bluewater/gurnard/Makefile b/board/bluewater/gurnard/Makefile new file mode 100644 index 0000000..f646d35 --- /dev/null +++ b/board/bluewater/gurnard/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2011 Bluewater Systems +# Ryan Mallon <ryan@bluewatersys.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += gurnard.o diff --git a/board/bluewater/gurnard/gurnard.c b/board/bluewater/gurnard/gurnard.c new file mode 100644 index 0000000..2a36d29 --- /dev/null +++ b/board/bluewater/gurnard/gurnard.c @@ -0,0 +1,449 @@ +/* + * Bluewater Systems Snapper 9260/9G20 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud <andre@bluewatersys.com> + * Author: Ryan Mallon <ryan@bluewatersys.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <atmel_lcd.h> +#include <atmel_lcdc.h> +#include <atmel_mci.h> +#include <dm.h> +#include <lcd.h> +#include <net.h> +#ifndef CONFIG_DM_ETH +#include <netdev.h> +#endif +#include <spi.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_emac.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_rtc.h> +#include <asm/arch/at91_sck.h> +#include <asm/arch/atmel_serial.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <dm/uclass-internal.h> + +#ifdef CONFIG_GURNARD_SPLASH +#include "splash_logo.h" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* IO Expander pins */ +#define IO_EXP_ETH_RESET (0 << 1) +#define IO_EXP_ETH_POWER (1 << 1) + +#ifdef CONFIG_MACB +static void gurnard_macb_hw_init(void) +{ + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + + at91_periph_clk_enable(ATMEL_ID_EMAC); + + /* + * Enable pull-up on: + * RXDV (PA12) => MODE0 - PHY also has pull-up + * ERX0 (PA13) => MODE1 - PHY also has pull-up + * ERX1 (PA15) => MODE2 - PHY also has pull-up + */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->puer); + + at91_phy_reset(); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_CMD_NAND +static int gurnard_nand_hw_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + ulong flags; + int ret; + + /* Enable CS3 as NAND/SmartMedia */ + setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); +#ifdef CONFIG_SYS_NAND_DBW_16 + flags = AT91_SMC_MODE_DBW_16; +#else + flags = AT91_SMC_MODE_DBW_8; +#endif + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + flags | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + ret = gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy"); + if (ret) + return ret; + gpio_direction_input(CONFIG_SYS_NAND_READY_PIN); + + /* Enable NandFlash */ + ret = gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce"); + if (ret) + return ret; + gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + + return 0; +} +#endif + +#ifdef CONFIG_GURNARD_SPLASH +static void lcd_splash(int width, int height) +{ + u16 colour; + int x, y; + u16 *base_addr = (u16 *)gd->video_bottom; + + memset(base_addr, 0xff, width * height * 2); + /* + * Blit the logo to the center of the screen + */ + for (y = 0; y < BMP_LOGO_HEIGHT; y++) { + for (x = 0; x < BMP_LOGO_WIDTH; x++) { + int posx, posy; + colour = bmp_logo_palette[bmp_logo_bitmap[ + y * BMP_LOGO_WIDTH + x]]; + posx = x + (width - BMP_LOGO_WIDTH) / 2; + posy = y; + base_addr[posy * width + posx] = colour; + } + } +} +#endif + +#ifdef CONFIG_DM_VIDEO +static void at91sam9g45_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + at91_periph_clk_enable(ATMEL_ID_LCDC); +} +#endif + +#ifdef CONFIG_GURNARD_FPGA +/** + * Initialise the memory bus settings so that we can talk to the + * memory mapped FPGA + */ +static int fpga_hw_init(void) +{ + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + int i; + + setbits_le32(&matrix->ebicsa, AT91_MATRIX_EBI_CS1A_SDRAMC); + + at91_set_a_periph(2, 4, 0); /* EBIA21 */ + at91_set_a_periph(2, 5, 0); /* EBIA22 */ + at91_set_a_periph(2, 6, 0); /* EBIA23 */ + at91_set_a_periph(2, 7, 0); /* EBIA24 */ + at91_set_a_periph(2, 12, 0); /* EBIA25 */ + for (i = 15; i <= 31; i++) /* EBINWAIT & EBID16 - 31 */ + at91_set_a_periph(2, i, 0); + + /* configure SMC cs0 for FPGA access timing */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(2) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(2), + &smc->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(5) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6), + &smc->cs[0].cycle); + writel(AT91_SMC_MODE_BAT | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_32 | + AT91_SMC_MODE_TDF | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[0].mode); + + /* Do a write to within EBI_CS1 to enable the SDCK */ + writel(0, ATMEL_BASE_CS1); + + return 0; +} +#endif + +#ifdef CONFIG_CMD_USB + +#define USB0_ENABLE_PIN AT91_PIN_PB22 +#define USB1_ENABLE_PIN AT91_PIN_PB23 + +void gurnard_usb_init(void) +{ + at91_set_gpio_output(USB0_ENABLE_PIN, 1); + at91_set_gpio_value(USB0_ENABLE_PIN, 0); + at91_set_gpio_output(USB1_ENABLE_PIN, 1); + at91_set_gpio_value(USB1_ENABLE_PIN, 0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int cpu_mmc_init(bd_t *bis) +{ + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + +static void gurnard_enable_console(int enable) +{ + at91_set_gpio_output(AT91_PIN_PB14, 1); + at91_set_gpio_value(AT91_PIN_PB14, enable ? 0 : 1); +} + +void at91sam9g45_slowclock_init(void) +{ + /* + * On AT91SAM9G45 revC CPUs, the slow clock can be based on an + * internal impreciseRC oscillator or an external 32kHz oscillator. + * Switch to the latter. + */ + unsigned i, tmp; + ulong *reg = (ulong *)ATMEL_BASE_SCKCR; + + tmp = readl(reg); + if ((tmp & AT91SAM9G45_SCKCR_OSCSEL) == AT91SAM9G45_SCKCR_OSCSEL_RC) { + timer_init(); + tmp |= AT91SAM9G45_SCKCR_OSC32EN; + writel(tmp, reg); + for (i = 0; i < 1200; i++) + udelay(1000); + tmp |= AT91SAM9G45_SCKCR_OSCSEL_32; + writel(tmp, reg); + udelay(200); + tmp &= ~AT91SAM9G45_SCKCR_RCEN; + writel(tmp, reg); + } +} + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + gurnard_enable_console(1); + + return 0; +} + +int board_init(void) +{ + const char *rev_str; +#ifdef CONFIG_CMD_NAND + int ret; +#endif + + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIODE); + + at91sam9g45_slowclock_init(); + + /* + * Clear the RTC IDR to disable all IRQs. Avoid issues when Linux + * boots with spurious IRQs. + */ + writel(0xffffffff, AT91_RTC_IDR); + + /* Make sure that the reset signal is attached properly */ + setbits_le32(AT91_ASM_RSTC_MR, AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN); + + gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + ret = gurnard_nand_hw_init(); + if (ret) + return ret; +#endif +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4); +#endif + +#ifdef CONFIG_MACB + gurnard_macb_hw_init(); +#endif + +#ifdef CONFIG_GURNARD_FPGA + fpga_hw_init(); +#endif + +#ifdef CONFIG_CMD_USB + gurnard_usb_init(); +#endif + +#ifdef CONFIG_CMD_MMC + at91_set_A_periph(AT91_PIN_PA12, 0); + at91_set_gpio_output(AT91_PIN_PA8, 1); + at91_set_gpio_value(AT91_PIN_PA8, 0); + at91_mci_hw_init(); +#endif + +#ifdef CONFIG_DM_VIDEO + at91sam9g45_lcd_hw_init(); + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ + + /* Select the second timing index for board rev 2 */ + rev_str = getenv("board_rev"); + if (rev_str && !strncmp(rev_str, "2", 1)) { + struct udevice *dev; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + if (dev) { + struct atmel_lcd_platdata *plat = dev_get_platdata(dev); + + plat->timing_index = 1; + } + } +#endif + + return 0; +} + +int board_late_init(void) +{ + u_int8_t env_enetaddr[8]; + char *env_str; + char *end; + int i; + + /* + * Set MAC address so we do not need to init Ethernet before Linux + * boot + */ + env_str = getenv("ethaddr"); + if (env_str) { + struct at91_emac *emac = (struct at91_emac *)ATMEL_BASE_EMAC; + /* Parse MAC address */ + for (i = 0; i < 6; i++) { + env_enetaddr[i] = env_str ? + simple_strtoul(env_str, &end, 16) : 0; + if (env_str) + env_str = (*end) ? end+1 : end; + } + + /* Set hardware address */ + writel(env_enetaddr[0] | env_enetaddr[1] << 8 | + env_enetaddr[2] << 16 | env_enetaddr[3] << 24, + &emac->sa2l); + writel((env_enetaddr[4] | env_enetaddr[5] << 8), &emac->sa2h); + + printf("MAC: %s\n", getenv("ethaddr")); + } else { + /* Not set in environment */ + printf("MAC: not set\n"); + } +#ifdef CONFIG_GURNARD_SPLASH + lcd_splash(480, 272); +#endif + + return 0; +} + +#ifndef CONFIG_DM_ETH +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0); +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +void reset_phy(void) +{ +} + +/* This breaks the Ethernet MAC at present */ +void enable_caches(void) +{ + dcache_enable(); +} + +/* SPI chip select control - only used for FPGA programming */ +#ifdef CONFIG_ATMEL_SPI + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* We don't use chipselects for FPGA programming */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* We don't use chipselects for FPGA programming */ +} +#endif /* CONFIG_ATMEL_SPI */ + +static struct atmel_serial_platdata at91sam9260_serial_plat = { + .base_addr = ATMEL_BASE_DBGU, +}; + +U_BOOT_DEVICE(at91sam9260_serial) = { + .name = "serial_atmel", + .platdata = &at91sam9260_serial_plat, +}; diff --git a/board/bluewater/gurnard/splash_logo.h b/board/bluewater/gurnard/splash_logo.h new file mode 100644 index 0000000..fb87dea --- /dev/null +++ b/board/bluewater/gurnard/splash_logo.h @@ -0,0 +1,2619 @@ +/* generated by ppm_logo (c) 2004 by Andre Renaud from logo_gurnard_small.ppm*/ +#ifndef __BMP_LOGO_H__ +#define __BMP_LOGO_H__ +#define BMP_LOGO_WIDTH 187 +#define BMP_LOGO_HEIGHT 139 +#define BMP_LOGO_COLORS 255 +#define BMP_LOGO_OFFSET 50 + +unsigned short bmp_logo_palette[] = { + 0xb61a, 0x9d78, 0xdefc, 0xffff, 0x7455, 0x32b1, 0xb5fa, 0xe75e, + 0xffdf, 0xc65b, 0x9538, 0xd6dc, 0xce9b, 0xf7df, 0xadb9, 0x84d7, + 0xffff, 0xffff, 0xffdf, 0x5bb4, 0x4b11, 0x3ad1, 0xf7bf, 0xf7bf, + 0xffff, 0xffff, 0xf79e, 0xef9e, 0x6c35, 0xef7e, 0xe75d, 0xdf1d, + 0xdf1c, 0xf7df, 0xde9a, 0xed96, 0xe6fb, 0xdb4d, 0xc945, 0xe410, + 0xffdf, 0xc965, 0xc986, 0xd2aa, 0xe451, 0xed14, 0xef5d, 0xffbe, + 0xffff, 0xef3c, }; + +unsigned char bmp_logo_bitmap[] = { + 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, + 0x0001, 0x0001, 0x0001, 0x0002, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0004, 0x0005, 0x0005, + 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, + 0x0006, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, + 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 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+ 0x0005, 0x0005, 0x0005, 0x0005, 0x0005, 0x0004, 0x0023, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, 0x002d, + 0x002d, 0x0022, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x0003, 0x001f, + 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, + 0x000e, 0x000e, 0x0009, }; +#endif diff --git a/board/broadcom/bcm23550_w1d/Kconfig b/board/broadcom/bcm23550_w1d/Kconfig new file mode 100644 index 0000000..007a127 --- /dev/null +++ b/board/broadcom/bcm23550_w1d/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BCM23550_W1D + +config SYS_BOARD + default "bcm23550_w1d" + +config SYS_VENDOR + default "broadcom" + +config SYS_SOC + default "bcm235xx" + +config SYS_CONFIG_NAME + default "bcm23550_w1d" + +endif diff --git a/board/broadcom/bcm23550_w1d/MAINTAINERS b/board/broadcom/bcm23550_w1d/MAINTAINERS new file mode 100644 index 0000000..fdaa539 --- /dev/null +++ b/board/broadcom/bcm23550_w1d/MAINTAINERS @@ -0,0 +1,6 @@ +BCM23550_W1D BOARD +M: Steve Rae <srae@broadcom.com> +S: Maintained +F: board/broadcom/bcm23550_w1d/ +F: include/configs/bcm23550_w1d.h +F: configs/bcm23550_w1d_defconfig diff --git a/board/broadcom/bcm23550_w1d/Makefile b/board/broadcom/bcm23550_w1d/Makefile new file mode 100644 index 0000000..76bd032 --- /dev/null +++ b/board/broadcom/bcm23550_w1d/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2013 Broadcom Corporation. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += bcm23550_w1d.o diff --git a/board/broadcom/bcm23550_w1d/bcm23550_w1d.c b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c new file mode 100644 index 0000000..0cb059f --- /dev/null +++ b/board/broadcom/bcm23550_w1d/bcm23550_w1d.c @@ -0,0 +1,120 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <mmc.h> +#include <asm/kona-common/kona_sdhci.h> +#include <asm/kona-common/clk.h> +#include <asm/arch/sysmap.h> + +#include <usb.h> +#include <usb/dwc2_udc.h> +#include <g_dnl.h> + +#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 +#define SECWATCHDOG_SDOGCR_EN_SHIFT 27 +#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 +#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 +#define SECWATCHDOG_SDOGCR_LD_SHIFT 0 + +#ifndef CONFIG_USB_SERIALNO +#define CONFIG_USB_SERIALNO "1234567890" +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * board_init - early hardware init + */ +int board_init(void) +{ + printf("Relocation Offset is: %08lx\n", gd->reloc_off); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + clk_init(); + + return 0; +} + +/* + * misc_init_r - miscellaneous platform dependent initializations + */ +int misc_init_r(void) +{ + return 0; +} + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + +#ifdef CONFIG_KONA_SDHCI +/* + * mmc_init - Initializes mmc + */ +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + + /* Register eMMC - SDIO2 */ + ret = kona_sdhci_init(1, 400000, 0); + if (ret) + return ret; + + /* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */ + ret = kona_sdhci_init(3, 400000, 0); + return ret; +} +#endif + +#ifdef CONFIG_USB_GADGET +static struct dwc2_plat_otg_data bcm_otg_data = { + .regs_otg = HSOTG_BASE_ADDR +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("%s: performing dwc2_udc_probe\n", __func__); + return dwc2_udc_probe(&bcm_otg_data); +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + debug("%s\n", __func__); + if (!getenv("serial#")) + g_dnl_set_serialnumber(CONFIG_USB_SERIALNO); + return 0; +} + +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + debug("%s\n", __func__); + return 1; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + debug("%s\n", __func__); + return 0; +} +#endif diff --git a/board/dbau1x00/MAINTAINERS b/board/dbau1x00/MAINTAINERS index b94ed81..21853ed 100644 --- a/board/dbau1x00/MAINTAINERS +++ b/board/dbau1x00/MAINTAINERS @@ -1,6 +1,6 @@ DBAU1X00 BOARD -M: Thomas Lange <thomas@corelatus.se> -S: Maintained +#M: - +S: Orphan (since 2016-06) F: board/dbau1x00/ F: include/configs/dbau1x00.h F: configs/dbau1000_defconfig diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 33ad7dc..95ff68b 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -20,6 +20,7 @@ #include "ls2080aqds_qixis.h" +#define MC_BOOT_ENV_VAR "mcinitcmd" #ifdef CONFIG_FSL_MC_ENET /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. @@ -714,6 +715,7 @@ void ls2080a_handle_phy_interface_xsgmii(int i) int board_eth_init(bd_t *bis) { int error; + char *mc_boot_env_var; #ifdef CONFIG_FSL_MC_ENET struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -781,6 +783,9 @@ int board_eth_init(bd_t *bis) } } + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); error = cpu_eth_init(bis); if (hwconfig_f("xqsgmii", env_hwconfig)) { diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 479f689..7d95deb 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -26,6 +26,7 @@ #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a +#define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) @@ -80,6 +81,8 @@ int checkboard(void) puts("PromJet\n"); else if (sw == 0x9) puts("NAND\n"); + else if (sw == 0xf) + puts("QSPI\n"); else if (sw == 0x15) printf("IFCCard\n"); else @@ -207,6 +210,15 @@ int board_init(void) else config_board_mux(MUX_TYPE_SDHC); +#if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI) + val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); + + if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) + QIXIS_WRITE(brdcfg[9], + (QIXIS_READ(brdcfg[9]) & 0xf8) | + FSL_QIXIS_BRDCFG9_QSPI); +#endif + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif @@ -218,7 +230,14 @@ int board_init(void) int board_early_init_f(void) { +#ifdef CONFIG_SYS_I2C_EARLY_INIT + i2c_early_init_f(); +#endif fsl_lsch3_early_init_f(); +#ifdef CONFIG_FSL_QSPI + /* input clk: 1/2 platform clk, output: input/20 */ + out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); +#endif return 0; } diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 58ea746..799799c 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,9 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define MC_BOOT_ENV_VAR "mcinitcmd" int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) + char *mc_boot_env_var; int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; @@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis) } } + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index c2e9c57..d63a979 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -321,39 +321,6 @@ static void setup_gpmi_nand(void) } #endif -int mx6_rgmii_rework(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - mx6_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - static void setup_fec(void) { if (is_mx6dqp()) { @@ -625,9 +592,9 @@ int board_late_init(void) if (is_mx6dqp()) setenv("board_rev", "MX6QP"); - else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + else if (is_mx6dq()) setenv("board_rev", "MX6Q"); - else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + else if (is_mx6sdl()) setenv("board_rev", "MX6DL"); #endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 2319354..0cf6809 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -177,13 +177,27 @@ static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const bl_pads[] = { MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static void enable_backlight(void) +{ + imx_iomux_v3_setup_multiple_pads(bl_pads, ARRAY_SIZE(bl_pads)); + gpio_direction_output(DISP0_PWR_EN, 1); +} + static void enable_rgb(struct display_info_t const *dev) { imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); - gpio_direction_output(DISP0_PWR_EN, 1); + enable_backlight(); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + enable_backlight(); } static struct i2c_pads_info i2c_pad_info1 = { @@ -370,7 +384,7 @@ struct display_info_t const displays[] = {{ .addr = 0, .pixfmt = IPU_PIX_FMT_RGB666, .detect = NULL, - .enable = NULL, + .enable = enable_lvds, .mode = { .name = "Hannstar-XGA", .refresh = 60, @@ -649,9 +663,9 @@ int board_late_init(void) if (is_mx6dqp()) setenv("board_rev", "MX6QP"); - else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + else if (is_mx6dq()) setenv("board_rev", "MX6Q"); - else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO)) + else if (is_mx6sdl()) setenv("board_rev", "MX6DL"); #endif diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index f1915a8..256d602 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -230,14 +230,14 @@ int board_mmc_init(bd_t *bis) printf("Warning: you configured more USDHC controllers" "(%d) than supported by the board\n", i + 1); return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) { - printf("Warning: failed to initialize " - "mmc dev %d\n", i); - return ret; - } + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize " + "mmc dev %d\n", i); + return ret; + } } return 0; diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 88d3fbd..92c9211 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -66,7 +66,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IOX_SDI IMX_GPIO_NR(5, 10) #define IOX_STCP IMX_GPIO_NR(5, 7) #define IOX_SHCP IMX_GPIO_NR(5, 11) -#define IOX_OE IMX_GPIO_NR(5, 18) +#define IOX_OE IMX_GPIO_NR(5, 8) static iomux_v3_cfg_t const iox_pads[] = { /* IOX_SDI */ @@ -117,7 +117,7 @@ static enum qn_level seq[3][2] = { static enum qn_func qn_output[8] = { qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, - qn_disable, qn_enable + qn_disable, qn_disable }; static void iox74lv_init(void) @@ -154,8 +154,6 @@ static void iox74lv_init(void) * shift register will be output to pins */ gpio_direction_output(IOX_STCP, 1); - - gpio_direction_output(IOX_OE, 1); }; #ifdef CONFIG_SYS_I2C_MXC @@ -305,7 +303,7 @@ static void setup_iomux_uart(void) #define QSPI_PAD_CTRL1 \ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) static iomux_v3_cfg_t const quadspi_pads[] = { MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index c3062f1..1f4fc03 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -171,7 +171,7 @@ static enum qn_level seq[3][2] = { static enum qn_func qn_output[8] = { qn_disable, qn_reset, qn_reset, qn_reset, qn_reset, qn_reset, qn_enable, - qn_enable + qn_disable }; static void iox74lv_init(void) diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig new file mode 100644 index 0000000..e71dfc4 --- /dev/null +++ b/board/freescale/s32v234evb/Kconfig @@ -0,0 +1,23 @@ +if TARGET_S32V234EVB + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "s32v234evb" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "s32v234" + +config SYS_CONFIG_NAME + string + default "s32v234evb" + +endif diff --git a/board/freescale/s32v234evb/MAINTAINERS b/board/freescale/s32v234evb/MAINTAINERS new file mode 100644 index 0000000..62b2e1b --- /dev/null +++ b/board/freescale/s32v234evb/MAINTAINERS @@ -0,0 +1,8 @@ +S32V234 Evaluation BOARD +M: Eddy PetriÈ™or <eddy.petrisor@gmail.com> +S: Maintained +F: arch/arm/cpu/armv8/s32v234/ +F: arch/arm/include/asm/arch-s32v234/ +F: board/freescale/s32v234evb/ +F: include/configs/s32v234evb.h +F: configs/s32v234evb_defconfig diff --git a/board/freescale/s32v234evb/Makefile b/board/freescale/s32v234evb/Makefile new file mode 100644 index 0000000..69e6d3e --- /dev/null +++ b/board/freescale/s32v234evb/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2013-2015, Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := clock.o +obj-y += lpddr2.o +obj-y += s32v234evb.o + +######################################################################### diff --git a/board/freescale/s32v234evb/clock.c b/board/freescale/s32v234evb/clock.c new file mode 100644 index 0000000..d218c21 --- /dev/null +++ b/board/freescale/s32v234evb/clock.c @@ -0,0 +1,344 @@ +/* + * (C) Copyright 2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mc_cgm_regs.h> +#include <asm/arch/mc_me_regs.h> +#include <asm/arch/clock.h> + +/* + * Select the clock reference for required pll. + * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. + * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) + */ +static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) +{ + u32 clk_src; + u32 pll_idx; + volatile struct src *src = (struct src *)SRC_SOC_BASE_ADDR; + + /* select the pll clock source */ + switch (refclk_freq) { + case FIRC_CLK_FREQ: + clk_src = SRC_GPR1_FIRC_CLK_SOURCE; + break; + case XOSC_CLK_FREQ: + clk_src = SRC_GPR1_XOSC_CLK_SOURCE; + break; + default: + /* The clock frequency for the source clock is unknown */ + return -1; + } + /* + * The hardware definition is not uniform, it has to calculate again + * the recurrence formula. + */ + switch (pll) { + case PERIPH_PLL: + pll_idx = 3; + break; + case ENET_PLL: + pll_idx = 1; + break; + case DDR_PLL: + pll_idx = 2;; + break; + default: + pll_idx = pll; + } + + writel(readl(&src->gpr1) | SRC_GPR1_PLL_SOURCE(pll_idx, clk_src), + &src->gpr1); + + return 0; +} + +static void entry_to_target_mode(u32 mode) +{ + writel(mode | MC_ME_MCTL_KEY, MC_ME_MCTL); + writel(mode | MC_ME_MCTL_INVERTEDKEY, MC_ME_MCTL); + while ((readl(MC_ME_GS) & MC_ME_GS_S_MTRANS) != 0x00000000) ; +} + +/* + * Program the pll according to the input parameters. + * pll - ARM_PLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_PLL. + * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ) + * freq - expected output frequency for PHY0 + * freq1 - expected output frequency for PHY1 + * dfs_nr - number of DFS modules for current PLL + * dfs - array with the activation dfs field, mfn and mfi + * plldv_prediv - divider of clkfreq_ref + * plldv_mfd - loop multiplication factor divider + * pllfd_mfn - numerator loop multiplication factor divider + * Please consult the PLLDIG chapter of platform manual + * before to use this function. + *) + */ +static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, + u32 dfs_nr, u32 dfs[][DFS_PARAMS_Nr], u32 plldv_prediv, + u32 plldv_mfd, u32 pllfd_mfn) +{ + u32 i, rfdphi1, rfdphi, dfs_on = 0, fvco; + + /* + * This formula is from platform reference manual (Rev. 1, 6/2015), PLLDIG chapter. + */ + fvco = + (refclk_freq / plldv_prediv) * (plldv_mfd + + pllfd_mfn / (float)20480); + + /* + * VCO should have value in [ PLL_MIN_FREQ, PLL_MAX_FREQ ]. Please consult + * the platform DataSheet in order to determine the allowed values. + */ + + if (fvco < PLL_MIN_FREQ || fvco > PLL_MAX_FREQ) { + return -1; + } + + if (select_pll_source_clk(pll, refclk_freq) < 0) { + return -1; + } + + rfdphi = fvco / freq0; + + rfdphi1 = (freq1 == 0) ? 0 : fvco / freq1; + + writel(PLLDIG_PLLDV_RFDPHI1_SET(rfdphi1) | + PLLDIG_PLLDV_RFDPHI_SET(rfdphi) | + PLLDIG_PLLDV_PREDIV_SET(plldv_prediv) | + PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); + + writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | + PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); + + /* switch on the pll in current mode */ + writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), + MC_ME_RUNn_MC(0)); + + entry_to_target_mode(MC_ME_MCTL_RUN0); + + /* Only ARM_PLL, ENET_PLL and DDR_PLL */ + if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { + /* DFS clk enable programming */ + writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll)); + + writel(DFS_DLLPRG1_CPICTRL_SET(0x5) | + DFS_DLLPRG1_VSETTLCTRL_SET(0x1) | + DFS_DLLPRG1_CALBYPEN_SET(0x0) | + DFS_DLLPRG1_DACIN_SET(0x1) | DFS_DLLPRG1_LCKWT_SET(0x0) | + DFS_DLLPRG1_V2IGC_SET(0x5), DFS_DLLPRG1(pll)); + + for (i = 0; i < dfs_nr; i++) { + if (dfs[i][0]) { + writel(DFS_DVPORTn_MFI_SET(dfs[i][2]) | + DFS_DVPORTn_MFN_SET(dfs[i][1]), + DFS_DVPORTn(pll, i)); + dfs_on |= (dfs[i][0] << i); + } + } + + writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET, + DFS_CTRL(pll)); + writel(readl(DFS_PORTRESET(pll)) & + ~DFS_PORTRESET_PORTRESET_SET(dfs_on), + DFS_PORTRESET(pll)); + while ((readl(DFS_PORTSR(pll)) & dfs_on) != dfs_on) ; + } + + entry_to_target_mode(MC_ME_MCTL_RUN0); + + return 0; + +} + +static void aux_source_clk_config(uintptr_t cgm_addr, u8 ac, u32 source) +{ + /* select the clock source */ + writel(MC_CGM_ACn_SEL_SET(source), CGM_ACn_SC(cgm_addr, ac)); +} + +static void aux_div_clk_config(uintptr_t cgm_addr, u8 ac, u8 dc, u32 divider) +{ + /* set the divider */ + writel(MC_CGM_ACn_DCm_DE | MC_CGM_ACn_DCm_PREDIV(divider), + CGM_ACn_DCm(cgm_addr, ac, dc)); +} + +static void setup_sys_clocks(void) +{ + + /* set ARM PLL DFS 1 as SYSCLK */ + writel((readl(MC_ME_RUNn_MC(0)) & ~MC_ME_RUNMODE_MC_SYSCLK_MASK) | + MC_ME_RUNMODE_MC_SYSCLK(0x2), MC_ME_RUNn_MC(0)); + + entry_to_target_mode(MC_ME_MCTL_RUN0); + + /* select sysclks ARMPLL, ARMPLLDFS2, ARMPLLDFS3 */ + writel(MC_ME_RUNMODE_SEC_CC_I_SYSCLK + (0x2, + MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET) | + MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, + MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET) + | MC_ME_RUNMODE_SEC_CC_I_SYSCLK(0x2, + MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET), + MC_ME_RUNn_SEC_CC_I(0)); + + /* setup the sys clock divider for CORE_CLK (1000MHz) */ + writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), + CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)); + + /* setup the sys clock divider for CORE2_CLK (500MHz) */ + writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), + CGM_SC_DCn(MC_CGM1_BASE_ADDR, 1)); + /* setup the sys clock divider for SYS3_CLK (266 MHz) */ + writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x0), + CGM_SC_DCn(MC_CGM0_BASE_ADDR, 0)); + + /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ + writel(MC_CGM_SC_DCn_DE | MC_CGM_SC_DCn_PREDIV(0x1), + CGM_SC_DCn(MC_CGM0_BASE_ADDR, 1)); + + entry_to_target_mode(MC_ME_MCTL_RUN0); + +} + +static void setup_aux_clocks(void) +{ + /* + * setup the aux clock divider for PERI_CLK + * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) + */ + aux_source_clk_config(MC_CGM0_BASE_ADDR, 5, MC_CGM_ACn_SEL_PERPLLDIVX); + aux_div_clk_config(MC_CGM0_BASE_ADDR, 5, 0, 4); + + /* setup the aux clock divider for LIN_CLK (40MHz) */ + aux_source_clk_config(MC_CGM0_BASE_ADDR, 3, MC_CGM_ACn_SEL_PERPLLDIVX); + aux_div_clk_config(MC_CGM0_BASE_ADDR, 3, 0, 1); + + /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ + aux_source_clk_config(MC_CGM0_BASE_ADDR, 7, MC_CGM_ACn_SEL_ENETPLL); + aux_div_clk_config(MC_CGM0_BASE_ADDR, 7, 1, 9); + + /* setup the aux clock divider for ENET_CLK (50MHz) */ + aux_source_clk_config(MC_CGM2_BASE_ADDR, 2, MC_CGM_ACn_SEL_ENETPLL); + aux_div_clk_config(MC_CGM2_BASE_ADDR, 2, 0, 9); + + /* setup the aux clock divider for SDHC_CLK (50 MHz). */ + aux_source_clk_config(MC_CGM0_BASE_ADDR, 15, MC_CGM_ACn_SEL_ENETPLL); + aux_div_clk_config(MC_CGM0_BASE_ADDR, 15, 0, 9); + + /* setup the aux clock divider for DDR_CLK (533MHz) and APEX_SYS_CLK (266MHz) */ + aux_source_clk_config(MC_CGM0_BASE_ADDR, 8, MC_CGM_ACn_SEL_DDRPLL); + aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 0, 0); + /* setup the aux clock divider for DDR4_CLK (133,25MHz) */ + aux_div_clk_config(MC_CGM0_BASE_ADDR, 8, 1, 3); + + entry_to_target_mode(MC_ME_MCTL_RUN0); + +} + +static void enable_modules_clock(void) +{ + /* PIT0 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL58); + /* PIT1 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL170); + /* LINFLEX0 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL83); + /* LINFLEX1 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL188); + /* ENET */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL50); + /* SDHC */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL93); + /* IIC0 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL81); + /* IIC1 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL184); + /* IIC2 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL186); + /* MMDC0 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL54); + /* MMDC1 */ + writeb(MC_ME_PCTLn_RUNPCm(0), MC_ME_PCTL162); + + entry_to_target_mode(MC_ME_MCTL_RUN0); +} + +void clock_init(void) +{ + unsigned int arm_dfs[ARM_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { + {ARM_PLL_PHI1_DFS1_EN, ARM_PLL_PHI1_DFS1_MFN, + ARM_PLL_PHI1_DFS1_MFI}, + {ARM_PLL_PHI1_DFS2_EN, ARM_PLL_PHI1_DFS2_MFN, + ARM_PLL_PHI1_DFS2_MFI}, + {ARM_PLL_PHI1_DFS3_EN, ARM_PLL_PHI1_DFS3_MFN, + ARM_PLL_PHI1_DFS3_MFI} + }; + + unsigned int enet_dfs[ENET_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { + {ENET_PLL_PHI1_DFS1_EN, ENET_PLL_PHI1_DFS1_MFN, + ENET_PLL_PHI1_DFS1_MFI}, + {ENET_PLL_PHI1_DFS2_EN, ENET_PLL_PHI1_DFS2_MFN, + ENET_PLL_PHI1_DFS2_MFI}, + {ENET_PLL_PHI1_DFS3_EN, ENET_PLL_PHI1_DFS3_MFN, + ENET_PLL_PHI1_DFS3_MFI}, + {ENET_PLL_PHI1_DFS4_EN, ENET_PLL_PHI1_DFS4_MFN, + ENET_PLL_PHI1_DFS4_MFI} + }; + + unsigned int ddr_dfs[DDR_PLL_PHI1_DFS_Nr][DFS_PARAMS_Nr] = { + {DDR_PLL_PHI1_DFS1_EN, DDR_PLL_PHI1_DFS1_MFN, + DDR_PLL_PHI1_DFS1_MFI}, + {DDR_PLL_PHI1_DFS2_EN, DDR_PLL_PHI1_DFS2_MFN, + DDR_PLL_PHI1_DFS2_MFI}, + {DDR_PLL_PHI1_DFS3_EN, DDR_PLL_PHI1_DFS3_MFN, + DDR_PLL_PHI1_DFS3_MFI} + }; + + writel(MC_ME_RUN_PCn_DRUN | MC_ME_RUN_PCn_RUN0 | MC_ME_RUN_PCn_RUN1 | + MC_ME_RUN_PCn_RUN2 | MC_ME_RUN_PCn_RUN3, MC_ME_RUN_PCn(0)); + + /* turn on FXOSC */ + writel(MC_ME_RUNMODE_MC_MVRON | MC_ME_RUNMODE_MC_XOSCON | + MC_ME_RUNMODE_MC_FIRCON | MC_ME_RUNMODE_MC_SYSCLK(0x1), + MC_ME_RUNn_MC(0)); + + entry_to_target_mode(MC_ME_MCTL_RUN0); + + program_pll(ARM_PLL, XOSC_CLK_FREQ, ARM_PLL_PHI0_FREQ, + ARM_PLL_PHI1_FREQ, ARM_PLL_PHI1_DFS_Nr, arm_dfs, + ARM_PLL_PLLDV_PREDIV, ARM_PLL_PLLDV_MFD, ARM_PLL_PLLDV_MFN); + + setup_sys_clocks(); + + program_pll(PERIPH_PLL, XOSC_CLK_FREQ, PERIPH_PLL_PHI0_FREQ, + PERIPH_PLL_PHI1_FREQ, PERIPH_PLL_PHI1_DFS_Nr, NULL, + PERIPH_PLL_PLLDV_PREDIV, PERIPH_PLL_PLLDV_MFD, + PERIPH_PLL_PLLDV_MFN); + + program_pll(ENET_PLL, XOSC_CLK_FREQ, ENET_PLL_PHI0_FREQ, + ENET_PLL_PHI1_FREQ, ENET_PLL_PHI1_DFS_Nr, enet_dfs, + ENET_PLL_PLLDV_PREDIV, ENET_PLL_PLLDV_MFD, + ENET_PLL_PLLDV_MFN); + + program_pll(DDR_PLL, XOSC_CLK_FREQ, DDR_PLL_PHI0_FREQ, + DDR_PLL_PHI1_FREQ, DDR_PLL_PHI1_DFS_Nr, ddr_dfs, + DDR_PLL_PLLDV_PREDIV, DDR_PLL_PLLDV_MFD, DDR_PLL_PLLDV_MFN); + + program_pll(VIDEO_PLL, XOSC_CLK_FREQ, VIDEO_PLL_PHI0_FREQ, + VIDEO_PLL_PHI1_FREQ, VIDEO_PLL_PHI1_DFS_Nr, NULL, + VIDEO_PLL_PLLDV_PREDIV, VIDEO_PLL_PLLDV_MFD, + VIDEO_PLL_PLLDV_MFN); + + setup_aux_clocks(); + + enable_modules_clock(); + +} diff --git a/board/freescale/s32v234evb/lpddr2.c b/board/freescale/s32v234evb/lpddr2.c new file mode 100644 index 0000000..ecc0842 --- /dev/null +++ b/board/freescale/s32v234evb/lpddr2.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/siul.h> +#include <asm/arch/lpddr2.h> +#include <asm/arch/mmdc.h> + +volatile int mscr_offset_ck0; + +void lpddr2_config_iomux(uint8_t module) +{ + int i; + + switch (module) { + case DDR0: + mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); + writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); + + writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); + writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); + + writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); + writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); + + for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) + writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) + writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR0_A0; i <= _DDR0_A9; i++) + writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR0_D0; i <= _DDR0_D31; i++) + writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); + break; + case DDR1: + writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); + + writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); + writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); + + writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); + writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); + + for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) + writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) + writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR1_A0; i <= _DDR1_A9; i++) + writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); + + for (i = _DDR1_D0; i <= _DDR1_D31; i++) + writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); + break; + } +} + +void config_mmdc(uint8_t module) +{ + unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; + + writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); + + writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); + writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); + writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); + writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); + writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); + writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); + writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); + writel(_MDCTL, mmdc_addr + MMDC_MDCTL); + + writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); + + while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { + } + + writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); + + /* Perform ZQ calibration */ + writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); + writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); + while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { + } + + /* Enable MMDC with CS0 */ + writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); + + /* Complete the initialization sequence as defined by JEDEC */ + writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); + writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); + writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); + writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); + + /* Set the amount of DRAM */ + /* Set DQS settings based on board type */ + + switch (module) { + case MMDC0: + writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); + writel(MMDC_MPRDDLCTL_MODULE0_VALUE, + mmdc_addr + MMDC_MPRDDLCTL); + writel(MMDC_MPWRDLCTL_MODULE0_VALUE, + mmdc_addr + MMDC_MPWRDLCTL); + writel(MMDC_MPDGCTRL0_MODULE0_VALUE, + mmdc_addr + MMDC_MPDGCTRL0); + writel(MMDC_MPDGCTRL1_MODULE0_VALUE, + mmdc_addr + MMDC_MPDGCTRL1); + break; + case MMDC1: + writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); + writel(MMDC_MPRDDLCTL_MODULE1_VALUE, + mmdc_addr + MMDC_MPRDDLCTL); + writel(MMDC_MPWRDLCTL_MODULE1_VALUE, + mmdc_addr + MMDC_MPWRDLCTL); + writel(MMDC_MPDGCTRL0_MODULE1_VALUE, + mmdc_addr + MMDC_MPDGCTRL0); + writel(MMDC_MPDGCTRL1_MODULE1_VALUE, + mmdc_addr + MMDC_MPDGCTRL1); + break; + } + + writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); + writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); + writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); + writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); + writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); + +} diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c new file mode 100644 index 0000000..3100f09 --- /dev/null +++ b/board/freescale/s32v234evb/s32v234evb.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/siul.h> +#include <asm/arch/lpddr2.h> +#include <asm/arch/clock.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +void setup_iomux_ddr(void) +{ + lpddr2_config_iomux(DDR0); + lpddr2_config_iomux(DDR1); + +} + +void ddr_phy_init(void) +{ +} + +void ddr_ctrl_init(void) +{ + config_mmdc(0); + config_mmdc(1); +} + +int dram_init(void) +{ + setup_iomux_ddr(); + + ddr_ctrl_init(); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static void setup_iomux_uart(void) +{ + /* Muxing for linflex */ + /* Replace the magic values after bringup */ + + /* set TXD - MSCR[12] PA12 */ + writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD)); + + /* set RXD - MSCR[11] - PA11 */ + writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD)); + + /* set RXD - IMCR[200] - 200 */ + writel(SIUL2_UART_IMCR_RXD, SIUL2_IMCRn(SIUL2_UART0_IMCR_RXD_PAD)); +} + +static void setup_iomux_enet(void) +{ +} + +static void setup_iomux_i2c(void) +{ +} + +#ifdef CONFIG_SYS_USE_NAND +void setup_iomux_nfc(void) +{ +} +#endif + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {USDHC_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + /* eSDHC1 is always present */ + return 1; +} + +int board_mmc_init(bd_t * bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_USDHC_CLK); + + /* Set iomux PADS for USDHC */ + + /* PK6 pad: uSDHC clk */ + writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150)); + writel(0x3, SIUL2_MSCRn(902)); + + /* PK7 pad: uSDHC CMD */ + writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151)); + writel(0x3, SIUL2_MSCRn(901)); + + /* PK8 pad: uSDHC DAT0 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152)); + writel(0x3, SIUL2_MSCRn(903)); + + /* PK9 pad: uSDHC DAT1 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153)); + writel(0x3, SIUL2_MSCRn(904)); + + /* PK10 pad: uSDHC DAT2 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154)); + writel(0x3, SIUL2_MSCRn(905)); + + /* PK11 pad: uSDHC DAT3 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155)); + writel(0x3, SIUL2_MSCRn(906)); + + /* PK15 pad: uSDHC DAT4 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159)); + writel(0x3, SIUL2_MSCRn(907)); + + /* PL0 pad: uSDHC DAT5 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160)); + writel(0x3, SIUL2_MSCRn(908)); + + /* PL1 pad: uSDHC DAT6 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161)); + writel(0x3, SIUL2_MSCRn(909)); + + /* PL2 pad: uSDHC DAT7 */ + writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162)); + writel(0x3, SIUL2_MSCRn(910)); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +static void mscm_init(void) +{ + struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR; + int i; + + for (i = 0; i < MSCM_IRSPRC_NUM; i++) + writew(MSCM_IRSPRC_CPn_EN, &mscmir->irsprc[i]); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_early_init_f(void) +{ + clock_init(); + mscm_init(); + + setup_iomux_uart(); + setup_iomux_enet(); + setup_iomux_i2c(); +#ifdef CONFIG_SYS_USE_NAND + setup_iomux_nfc(); +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: s32v234evb\n"); + + return 0; +} diff --git a/board/freescale/s32v234evb/s32v234evb.cfg b/board/freescale/s32v234evb/s32v234evb.cfg new file mode 100644 index 0000000..6017a40 --- /dev/null +++ b/board/freescale/s32v234evb/s32v234evb.cfg @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013-2015, Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include <asm/imx-common/imximage.cfg> + +/* image version */ +IMAGE_VERSION 2 +BOOT_FROM sd + + +/* + * Boot Device : one of qspi, sd: + * qspi: flash_offset: 0x1000 + * sd/mmc: flash_offset: 0x1000 + */ + + +#ifdef CONFIG_SECURE_BOOT +SECURE_BOOT +#endif diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README index 9418907..f3f8998 100644 --- a/board/gateworks/gw_ventana/README +++ b/board/gateworks/gw_ventana/README @@ -173,13 +173,8 @@ OS load time which defeats the purpose of Falcon mode in the first place. The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel) based on the return value of the spl_start_uboot() function. While often this can simply be the state of a GPIO based pushbutton or DIP switch, for -Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if -set to '1' will choose to boot the OS rather than U-Boot. While the choice -of adding env support to the SPL adds a little bit of time to the boot -process as well as (significant really) SPL code space this was deemed most -flexible as within the large variety of Gateworks Ventana boards not all of -them have a user pushbutton and that pushbutton may be configured as a hard -reset per user configuration. +Gateworks Ventana, we use an EEPROM register on i2c-0 at 0x50:0x00: +set to '0' will choose to boot to U-Boot and otherwise it will boot to OS. To use Falcon mode it is required that you first 'prepare' the 'args' data that is stored on your boot medium along with the kernel (which can be any @@ -235,8 +230,8 @@ using rootfs (ubi), kernel (uImage), and dtb from the network: # flash args (at 17MB) Ventana > nand erase.part args && nand write 18000000 args 100000 - # set boot_os env var to enable booting to Linux - Ventana > setenv boot_os 1 && saveenv + # set i2c register 0x50:0x00=0 to boot to Linux + Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1 Be sure to adjust 'bootargs' above to your OS needs (this will be different for various distros such as OpenWrt, Yocto, Android, etc). You can use the @@ -309,8 +304,8 @@ out in U-Boot and use the following to enable Falcon mode: # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors) Ventana > mmc write 18000000 0x800 0x800 - # set boot_os to enable falcon mode - Ventana > setenv boot_os 1 && saveenv + # set i2c register 0x50:0x00=0 to boot to Linux + Ventana > i2c dev 0 && i2c mw 0x50 0x00.0 0 1 Be sure to adjust 'bootargs' above to your OS needs (this will be different for various distros such as OpenWrt, Yocto, Android, etc). You can use the diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index a20190e..929dde9 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -132,10 +132,10 @@ void setup_ventana_i2c(void) /* common to add baseboards */ static iomux_v3_cfg_t const gw_gpio_pads[] = { - /* MSATA_EN */ - IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* RS232_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), }; /* prototype */ @@ -183,6 +183,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -212,6 +214,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* CAN_STBY */ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* USB_HUBRST# */ @@ -241,6 +245,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* CAN_STBY */ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), /* PANLEDG# */ @@ -283,6 +289,8 @@ static iomux_v3_cfg_t const gw551x_gpio_pads[] = { }; static iomux_v3_cfg_t const gw552x_gpio_pads[] = { + /* MSATA_EN */ + IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* USBOTG_SEL */ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), /* USB_HUBRST# */ @@ -310,6 +318,20 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = { IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; +static iomux_v3_cfg_t const gw553x_gpio_pads[] = { + /* PANLEDG# */ + IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), + /* PANLEDR# */ + IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), + + /* VID_PWR */ + IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + /* * Board Specific GPIO @@ -445,6 +467,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .vidin_en = IMX_GPIO_NR(3, 31), .usb_sel = IMX_GPIO_NR(1, 2), .wdis = IMX_GPIO_NR(7, 12), + .msata_en = GP_MSATA_SEL, }, /* GW53xx */ @@ -489,6 +512,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .gps_shdn = IMX_GPIO_NR(1, 27), .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), + .msata_en = GP_MSATA_SEL, }, /* GW54xx */ @@ -535,6 +559,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), .wdis = IMX_GPIO_NR(5, 17), + .msata_en = GP_MSATA_SEL, }, /* GW551x */ @@ -602,6 +627,47 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_rst = IMX_GPIO_NR(1, 29), .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), + .msata_en = GP_MSATA_SEL, + }, + + /* GW553x */ + { + .gpio_pads = gw553x_gpio_pads, + .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 4, + .leds = { + IMX_GPIO_NR(4, 10), + IMX_GPIO_NR(4, 11), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .vidin_en = IMX_GPIO_NR(5, 20), + .wdis = IMX_GPIO_NR(7, 12), }, }; @@ -616,10 +682,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); gpio_direction_output(GP_USB_OTG_PWR, 0); - /* MSATA Enable - default to PCI */ - gpio_request(GP_MSATA_SEL, "msata_en"); - gpio_direction_output(GP_MSATA_SEL, 0); - /* RS232_EN# */ gpio_request(GP_RS232_EN, "rs232_en"); gpio_direction_output(GP_RS232_EN, 0); @@ -649,6 +711,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) } } + /* MSATA Enable - default to PCI */ + if (gpio_cfg[board].msata_en) { + gpio_request(gpio_cfg[board].msata_en, "msata_en"); + gpio_direction_output(gpio_cfg[board].msata_en, 0); + } + /* Expansion Mezzanine IO */ if (gpio_cfg[board].mezz_pwren) { gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); @@ -700,6 +768,11 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_request(gpio_cfg[board].wdis, "wlan_dis"); gpio_direction_output(gpio_cfg[board].wdis, 1); } + + /* sense vselect pin to see if we support uhs-i */ + gpio_request(GP_SD3_VSELECT, "sd3_vselect"); + gpio_direction_input(GP_SD3_VSELECT); + gpio_cfg[board].usd_vsel = !gpio_get_value(GP_SD3_VSELECT); } /* setup GPIO pinmux and default configuration per baseboard and env */ @@ -718,10 +791,9 @@ void setup_board_gpio(int board, struct ventana_board_info *info) gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); /* MSATA Enable */ - if (is_cpu_type(MXC_CPU_MX6Q) && - test_bit(EECONFIG_SATA, info->config)) { + if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { gpio_direction_output(GP_MSATA_SEL, - (hwconfig("msata")) ? 1 : 0); + (hwconfig("msata")) ? 1 : 0); } /* USBOTG Select (PCISKT or FrontPanel) */ @@ -760,8 +832,13 @@ void setup_board_gpio(int board, struct ventana_board_info *info) ctrl); gpio_requestf(cfg->gpio_param, "dio%d", i); gpio_direction_input(cfg->gpio_param); - } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && + } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_padmux) { + if (!cfg->pwm_param) { + printf("DIO%d: Error: pwm config invalid\n", + i); + continue; + } if (!quiet) printf("DIO%d: pwm%d\n", i, cfg->pwm_param); imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | @@ -770,8 +847,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info) } if (!quiet) { - if (is_cpu_type(MXC_CPU_MX6Q) && - (test_bit(EECONFIG_SATA, info->config))) { + if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { printf("MSATA: %s\n", (hwconfig("msata") ? "enabled" : "disabled")); } diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 28f5816..d037767 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -17,6 +17,7 @@ #define GP_SD3_CD IMX_GPIO_NR(7, 0) #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) +#define GP_SD3_VSELECT IMX_GPIO_NR(6, 14) #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ @@ -76,6 +77,8 @@ struct ventana { int pcie_sson; int usb_sel; int wdis; + int msata_en; + bool usd_vsel; }; extern struct ventana gpio_cfg[GW_UNKNOWN]; diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index ba15969..1382e5d 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -87,6 +87,9 @@ read_eeprom(int bus, struct ventana_board_info *info) } else if (info->model[4] == '2') { type = GW552x; break; + } else if (info->model[4] == '3') { + type = GW553x; + break; } /* fall through */ default: @@ -100,43 +103,12 @@ read_eeprom(int bus, struct ventana_board_info *info) /* list of config bits that the bootloader will remove from dtb if not set */ struct ventana_eeprom_config econfig[] = { { "eth0", "ethernet0", EECONFIG_ETH0 }, - { "eth1", "ethernet1", EECONFIG_ETH1 }, - { "sata", "ahci0", EECONFIG_SATA }, - { "pcie", NULL, EECONFIG_PCIE}, - { "lvds0", NULL, EECONFIG_LVDS0 }, - { "lvds1", NULL, EECONFIG_LVDS1 }, { "usb0", NULL, EECONFIG_USB0 }, { "usb1", NULL, EECONFIG_USB1 }, { "mmc0", NULL, EECONFIG_SD0 }, { "mmc1", NULL, EECONFIG_SD1 }, { "mmc2", NULL, EECONFIG_SD2 }, { "mmc3", NULL, EECONFIG_SD3 }, - { "uart0", NULL, EECONFIG_UART0 }, - { "uart1", NULL, EECONFIG_UART1 }, - { "uart2", NULL, EECONFIG_UART2 }, - { "uart3", NULL, EECONFIG_UART3 }, - { "uart4", NULL, EECONFIG_UART4 }, - { "ipu0", NULL, EECONFIG_IPU0 }, - { "ipu1", NULL, EECONFIG_IPU1 }, - { "can0", NULL, EECONFIG_FLEXCAN }, - { "i2c0", NULL, EECONFIG_I2C0 }, - { "i2c1", NULL, EECONFIG_I2C1 }, - { "i2c2", NULL, EECONFIG_I2C2 }, - { "vpu", NULL, EECONFIG_VPU }, - { "csi0", NULL, EECONFIG_CSI0 }, - { "csi1", NULL, EECONFIG_CSI1 }, - { "spi0", NULL, EECONFIG_ESPCI0 }, - { "spi1", NULL, EECONFIG_ESPCI1 }, - { "spi2", NULL, EECONFIG_ESPCI2 }, - { "spi3", NULL, EECONFIG_ESPCI3 }, - { "spi4", NULL, EECONFIG_ESPCI4 }, - { "spi5", NULL, EECONFIG_ESPCI5 }, - { "gps", "pps", EECONFIG_GPS }, - { "hdmi_in", NULL, EECONFIG_HDMI_IN }, - { "hdmi_out", NULL, EECONFIG_HDMI_OUT }, - { "cvbs_in", NULL, EECONFIG_VID_IN }, - { "cvbs_out", NULL, EECONFIG_VID_OUT }, - { "nand", NULL, EECONFIG_NAND }, { /* Sentinel */ } }; diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 3febd12..2ca6d5c 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -11,6 +11,7 @@ #include <i2c.h> #include <linux/ctype.h> +#include "ventana_eeprom.h" #include "gsc.h" /* @@ -70,6 +71,8 @@ static void read_hwmon(const char *name, uint reg, uint size) puts("fRD\n"); } else { ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); + if (reg == GSC_HWMON_TEMP && ui > 0x8000) + ui -= 0xffff; if (ui == 0xffffff) puts("invalid\n"); else @@ -79,7 +82,6 @@ static void read_hwmon(const char *name, uint reg, uint size) int gsc_info(int verbose) { - const char *model = getenv("model"); unsigned char buf[16]; i2c_set_bus_num(0); @@ -96,6 +98,12 @@ int gsc_info(int verbose) gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &buf[GSC_SC_STATUS], 1); } + if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) { + int ui = buf[0] | buf[1]<<8; + if (ui > 0x8000) + ui -= 0xffff; + printf(" board temp at %dC", ui / 10); + } puts("\n"); if (!verbose) return CMD_RET_SUCCESS; @@ -109,10 +117,11 @@ int gsc_info(int verbose) read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); - read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); + if (strncasecmp((const char*) ventana_info.model, "GW553", 5)) + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); - switch (model[3]) { + switch (ventana_info.model[3]) { case '1': /* GW51xx */ read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ break; @@ -160,6 +169,48 @@ int gsc_boot_wd_disable(void) } #ifdef CONFIG_CMD_GSC +static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + unsigned char reg; + unsigned long secs = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + secs = simple_strtoul(argv[1], NULL, 10); + printf("GSC Sleeping for %ld seconds\n", secs); + + i2c_set_bus_num(0); + reg = (secs >> 24) & 0xff; + if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1)) + goto error; + reg = (secs >> 16) & 0xff; + if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1)) + goto error; + reg = (secs >> 8) & 0xff; + if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1)) + goto error; + reg = secs & 0xff; + if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1)) + goto error; + if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + goto error; + reg |= (1 << 2); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + goto error; + reg &= ~(1 << 2); + reg |= 0x3; + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + goto error; + + return CMD_RET_SUCCESS; + +error: + printf("i2c error\n"); + return CMD_RET_FAILURE; +} + static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned char reg; @@ -206,13 +257,15 @@ static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strcasecmp(argv[1], "wd") == 0) return do_gsc_wd(cmdtp, flag, --argc, ++argv); + else if (strcasecmp(argv[1], "sleep") == 0) + return do_gsc_sleep(cmdtp, flag, --argc, ++argv); return CMD_RET_USAGE; } U_BOOT_CMD( gsc, 4, 1, do_gsc, "GSC configuration", - "[wd enable [30|60]]|[wd disable]\n" + "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n" ); #endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index e2eeef3..70395ac 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -21,6 +21,7 @@ #include <asm/io.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> +#include <hwconfig.h> #include <i2c.h> #include <fdt_support.h> #include <fsl_esdhc.h> @@ -59,8 +60,7 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - /* CD */ - IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; /* ENET */ @@ -266,7 +266,9 @@ int board_phy_config(struct phy_device *phydev) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FEC_MXC - if (board_type != GW551x && board_type != GW552x) { + struct ventana_board_info *info = &ventana_info; + + if (test_bit(EECONFIG_ETH0, info->config)) { setup_iomux_enet(GP_PHY_RST); cpu_eth_init(bis); } @@ -317,6 +319,8 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[2]); /* Enable Backlight */ + gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); + gpio_direction_output(IMX_GPIO_NR(1, 10), 0); gpio_request(IMX_GPIO_NR(1, 18), "bklt_en"); SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 18), 1); @@ -456,8 +460,7 @@ static void setup_display(void) <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); - /* Backlight CABEN on LVDS connector */ - gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio"); + /* LVDS Backlight GPIO on LVDS connector - output low */ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); gpio_direction_output(IMX_GPIO_NR(1, 10), 0); } @@ -697,7 +700,9 @@ int misc_init_r(void) setenv("model_base", str); sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file1", fdt); - if (board_type != GW551x && board_type != GW552x) + if (board_type != GW551x && + board_type != GW552x && + board_type != GW553x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; @@ -776,6 +781,27 @@ static int ft_sethdmiinfmt(void *blob, char *mode) return 0; } +/* enable a property of a node if the node is found */ +static inline void ft_enable_path(void *blob, const char *path) +{ + int i = fdt_path_offset(blob, path); + if (i >= 0) { + debug("enabling %s\n", path); + fdt_status_okay(blob, i); + } +} + +/* remove a property of a node if the node is found */ +static inline void ft_delprop_path(void *blob, const char *path, + const char *name) +{ + int i = fdt_path_offset(blob, path); + if (i) { + debug("removing %s/%s\n", path, name); + fdt_delprop(blob, i, name); + } +} + /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -879,6 +905,11 @@ int ft_board_setup(void *blob, bd_t *bd) range[1] = cpu_to_fdt32(23); } } + + /* these have broken usd_vsel */ + if (strstr((const char *)info->model, "SP318-B") || + strstr((const char *)info->model, "SP331-B")) + gpio_cfg[board_type].usd_vsel = 0; } /* @@ -919,6 +950,32 @@ int ft_board_setup(void *blob, bd_t *bd) ft_sethdmiinfmt(blob, "yuv422bt656"); } + /* Configure DIO */ + for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) { + struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i]; + char arg[10]; + + sprintf(arg, "dio%d", i); + if (!hwconfig(arg)) + continue; + if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param) + { + char path[48]; + sprintf(path, "/soc/aips-bus@02000000/pwm@%08x", + 0x02080000 + (0x4000 * (cfg->pwm_param - 1))); + printf(" Enabling pwm%d for DIO%d\n", + cfg->pwm_param, i); + ft_enable_path(blob, path); + } + } + + /* remove no-1-8-v if UHS-I support is present */ + if (gpio_cfg[board_type].usd_vsel) { + debug("Enabling UHS-I support\n"); + ft_delprop_path(blob, "/soc/aips-bus@02100000/usdhc@02198000", + "no-1-8-v"); + } + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 0a6ad47..e7f699a 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -15,6 +15,7 @@ #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/mxc_i2c.h> #include <environment.h> +#include <i2c.h> #include <spl.h> #include "gsc.h" @@ -189,6 +190,20 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { .trasmin = 3500, }; +/* MT41K512M16HA-125 (8Gb density) */ +static struct mx6_ddr3_cfg mt41k512m16ha_125 = { + .mem_speed = 1600, + .density = 8, + .width = 16, + .banks = 8, + .rowaddr = 16, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + /* * calibration - these are the various CPU/DDR3 combinations we support */ @@ -340,6 +355,19 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { .p1_mpwrdlctl = 0X40304239, }; +static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x002A0025, + .p0_mpwldectrl1 = 0x003A002A, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43430356, + .p0_mpdgctrl1 = 0x033C0335, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4B373F42, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x303E3C36, +}; + static void spl_dram_init(int width, int size_mb, int board_model) { struct mx6_ddr3_cfg *mem = NULL; @@ -419,6 +447,11 @@ static void spl_dram_init(int width, int size_mb, int board_model) else calib = &mx6sdl_256x32_mmdc_calib; debug("4gB density\n"); + } else if (width == 32 && size_mb == 2048) { + mem = &mt41k512m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_512x32_mmdc_calib; + debug("8gB density\n"); } else if (width == 64 && size_mb == 512) { mem = &mt41k64m16jt_125; debug("1gB density\n"); @@ -526,9 +559,6 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - - /* disable boot watchdog */ - gsc_boot_wd_disable(); } /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ @@ -560,7 +590,7 @@ void spl_board_init(void) /* return 1 if we wish to boot to uboot vs os (falcon mode) */ int spl_start_uboot(void) { - int ret = 1; + unsigned char ret = 1; debug("%s\n", __func__); #ifdef CONFIG_SPL_ENV_SUPPORT @@ -569,7 +599,14 @@ int spl_start_uboot(void) debug("boot_os=%s\n", getenv("boot_os")); if (getenv_yesno("boot_os") == 1) ret = 0; +#else + /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */ + i2c_set_bus_num(0); + gsc_i2c_read(0x50, 0x0, 1, &ret, 1); #endif + if (!ret) + gsc_boot_wd_disable(); + debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); return ret; } diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index daff375..9ffad58 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -111,6 +111,7 @@ enum { GW54xx, GW551x, GW552x, + GW553x, GW_UNKNOWN, GW_BADCRC, }; diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index ff8f4d7..d45ed44 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -601,6 +601,8 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#ifdef CONFIG_VIDEO_IPUV3 /* We need at least 200ms between power on and backlight on * as per specifications from CHI MEI */ mdelay(250); @@ -615,6 +617,7 @@ int board_late_init(void) gpio_direction_output(LVDS_BACKLIGHT_GP, 1); pwm_enable(0); +#endif return 0; } diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c index 84ee2bf..a5e774b 100644 --- a/board/synopsys/axs101/axs101.c +++ b/board/synopsys/axs101/axs101.c @@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr) writel(addr, (void __iomem *)RESET_VECTOR_ADDR); /* Make sure other cores see written value in memory */ - flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int)); + flush_dcache_all(); } void smp_kick_all_cpus(void) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index bde5ac7..f005762 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -850,7 +850,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm")) + if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) return 0; else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) return 0; diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig index 87654f9..cead0f4 100644 --- a/board/ti/am57xx/Kconfig +++ b/board/ti/am57xx/Kconfig @@ -1,4 +1,4 @@ -if TARGET_BEAGLE_X15 +if TARGET_AM57XX_EVM config SYS_BOARD default "am57xx" diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index ccf97b2..08cf14d 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -736,3 +736,17 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (board_is_x15() && !strcmp(name, "am57xx-beagle-x15")) + return 0; + else if (board_is_am572x_evm() && !strcmp(name, "am57xx-beagle-x15")) + return 0; + else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) + return 0; + else + return -1; +} +#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 3fbbc9b..0394e4e 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -305,6 +305,82 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) } } +struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS6, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS7, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS8, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + +struct vcores_data dra722_volts = { + .mpu.value = VDD_MPU_DRA7, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS65917_REG_ADDR_SMPS1, + .mpu.pmic = &tps659038, + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, + + .core.value = VDD_CORE_DRA7, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS65917_REG_ADDR_SMPS2, + .core.pmic = &tps659038, + + /* + * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x + * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. + */ + .gpu.value = VDD_GPU_DRA7, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS65917_REG_ADDR_SMPS3, + .gpu.pmic = &tps659038, + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, + + .eve.value = VDD_EVE_DRA7, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS65917_REG_ADDR_SMPS3, + .eve.pmic = &tps659038, + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, + + .iva.value = VDD_IVA_DRA7, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS65917_REG_ADDR_SMPS3, + .iva.pmic = &tps659038, + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, +}; + /** * @brief board_init * @@ -390,6 +466,21 @@ void do_board_detect(void) } #endif /* CONFIG_SPL_BUILD */ +void vcores_init(void) +{ + if (board_is_dra74x_evm()) { + *omap_vcores = &dra752_volts; + } else if (board_is_dra72x_evm()) { + *omap_vcores = &dra722_volts; + } else { + /* If EEPROM is not populated */ + if (is_dra72x()) + *omap_vcores = &dra722_volts; + else + *omap_vcores = &dra752_volts; + } +} + void set_muxconf_regs(void) { do_set_mux32((*ctrl)->control_padconf_core_base, diff --git a/board/warp7/README b/board/warp7/README new file mode 100644 index 0000000..60339da --- /dev/null +++ b/board/warp7/README @@ -0,0 +1,63 @@ +How to Update U-Boot on Warp7 board +---------------------------------- + +Required software on the host PC: + +- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader + +- dfu-util: http://dfu-util.sourceforge.net/releases/ (if you are in a +Debian distribution then you can get it via libdfu-dev package) + +- libusb: http://libusb.org/ (if you are in a Debian distribution +then you can get it via libusb-dev and libusb-1.0-0-dev) + +In U-Boot folder, build U-Boot for Warp7: + +$ make mrproper +$ make warp7_config +$ make + +This will generate the U-Boot binary called u-boot.imx. + +Put warp7 board in USB download mode: + +Remove the CPU board from the base board then put switch 2 in the upper +position + +Connect a USB to serial adapter between the host PC and warp7 + +Connect a USB cable between the OTG warp7 port and the host PC + +Copy u-boot.imx to the imx_usb_loader folder. + +Load u-boot.imx via USB: + +$ sudo ./imx_usb u-boot.imx + +Then U-Boot should start and its messages will appear in the console program. + +Open a terminal program such as minicom + +Use the default environment variables: + +=> env default -f -a +=> saveenv + +Run the DFU command: +=> dfu 0 mmc 0 + +Transfer u-boot.imx that will be flashed into the eMMC: + +$ sudo dfu-util -D u-boot.imx -a boot + +Then on the U-Boot prompt the following message should be seen after a +successful upgrade: + +#DOWNLOAD ... OK +Ctrl+C to exit ... + +Remove power from the warp7 board. + +Put warp7 board into normal boot mode (put the switch 2 in the lower position) + +Power up the board and the new updated U-Boot should boot from eMMC diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 8c5bf9a..27e31f3 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -32,6 +32,10 @@ int dram_init(void) return 0; } +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -100,3 +104,20 @@ int board_usb_phy_mode(int port) { return USB_INIT_DEVICE; } + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + return 0; +} |