diff options
Diffstat (limited to 'board')
79 files changed, 3261 insertions, 664 deletions
diff --git a/board/Marvell/db-88f6720/MAINTAINERS b/board/Marvell/db-88f6720/MAINTAINERS new file mode 100644 index 0000000..a27d1c2 --- /dev/null +++ b/board/Marvell/db-88f6720/MAINTAINERS @@ -0,0 +1,6 @@ +DB_88F6720 BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/Marvell/db-88f6720/ +F: include/configs/db-88f6720.h +F: configs/db-88f6720_defconfig diff --git a/board/Marvell/db-88f6720/Makefile b/board/Marvell/db-88f6720/Makefile new file mode 100644 index 0000000..7a5b512 --- /dev/null +++ b/board/Marvell/db-88f6720/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2016 Stefan Roese <sr@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := db-88f6720.o diff --git a/board/Marvell/db-88f6720/db-88f6720.c b/board/Marvell/db-88f6720/db-88f6720.c new file mode 100644 index 0000000..b6e00f3 --- /dev/null +++ b/board/Marvell/db-88f6720/db-88f6720.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720 + */ +#define DB_88F6720_MPP0_7 0x00020020 /* SPI */ +#define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */ +#define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/ +#define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/ +#define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */ +#define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */ +#define DB_88F6720_MPP48_55 0x22222222 /* GE0 */ +#define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */ +#define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/ + +#define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF +#define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF +#define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF +#define DB_88F6720_GPP_OUT_VAL_LOW 0x0 +#define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */ +#define DB_88F6720_GPP_OUT_VAL_HIGH 0x0 +#define DB_88F6720_GPP_POL_LOW 0x0 +#define DB_88F6720_GPP_POL_MID 0x0 +#define DB_88F6720_GPP_POL_HIGH 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00); + writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04); + writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08); + writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c); + writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10); + writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14); + writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18); + writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c); + writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20); + + /* Configure GPIO */ + /* Set GPP Out value */ + writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); + + /* Set GPP Polarity */ + writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Marvell DB-88F6720\n"); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in controller(s) come first */ + return pci_eth_init(bis); +} diff --git a/board/Marvell/db-88f6720/kwbimage.cfg b/board/Marvell/db-88f6720/kwbimage.cfg new file mode 100644 index 0000000..1f748db --- /dev/null +++ b/board/Marvell/db-88f6720/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese <sr@denx.de> +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068 diff --git a/board/Marvell/db-88f6820-gp/binary.0 b/board/Marvell/db-88f6820-gp/binary.0 deleted file mode 100644 index 57a4cbf..0000000 --- a/board/Marvell/db-88f6820-gp/binary.0 +++ /dev/null @@ -1,16 +0,0 @@ --------- -WARNING: --------- -This file should contain the bin_hdr generated by the original Marvell -U-Boot implementation. As this is currently not included in this -U-Boot version, we have added this placeholder, so that the U-Boot -image can be generated without errors. - -If you have a known to be working bin_hdr for your board, then you -just need to replace this text file here with the binary header -and recompile U-Boot. - -In a few weeks, mainline U-Boot will get support to generate the -bin_hdr with the DDR training code itself. By implementing this code -as SPL U-Boot. Then this file will not be needed any more and will -get removed. diff --git a/board/amazon/kc1/kc1.c b/board/amazon/kc1/kc1.c index ca63af8..469a83e 100644 --- a/board/amazon/kc1/kc1.c +++ b/board/amazon/kc1/kc1.c @@ -88,10 +88,11 @@ int misc_init_r(void) char reboot_mode[2] = { 0 }; u32 data = 0; u32 value; + int rc; /* Reboot mode */ - omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); + rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); /* USB ID pin pull-up indicates factory (fastboot) cable detection. */ gpio_request(KC1_GPIO_USB_ID, "USB_ID"); @@ -101,18 +102,7 @@ int misc_init_r(void) if (value) reboot_mode[0] = 'b'; - if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { - if (reboot_mode[0] == 'o') - twl6030_power_off(); - - if (!getenv("reboot-mode")) - setenv("reboot-mode", (char *)reboot_mode); - - omap_reboot_mode_clear(); - } else { - /* Reboot mode garbage may still be valid, so clear it. */ - omap_reboot_mode_clear(); - + if (rc < 0 || reboot_mode[0] == 'o') { /* * When not rebooting, valid power on reasons are either the * power button, charger plug or USB plug. @@ -126,6 +116,13 @@ int misc_init_r(void) twl6030_power_off(); } + if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { + if (!getenv("reboot-mode")) + setenv("reboot-mode", (char *)reboot_mode); + } + + omap_reboot_mode_clear(); + /* Serial number */ omap_die_id_serial(); diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 104d71f..a3a56ca 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -31,7 +31,7 @@ #include <i2c.h> #include <input.h> #include <netdev.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) diff --git a/board/denx/m53evk/m53evk.c b/board/denx/m53evk/m53evk.c index 5dd6cdd..934f009 100644 --- a/board/denx/m53evk/m53evk.c +++ b/board/denx/m53evk/m53evk.c @@ -22,7 +22,7 @@ #include <spl.h> #include <fsl_esdhc.h> #include <asm/gpio.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <linux/fb.h> #include <ipu_pixfmt.h> diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index dfa3e21..cefe3cc 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -8,7 +8,7 @@ #include <command.h> #include <fsl_validate.h> -static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, +int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (fsl_check_boot_mode_secure() == 0) { @@ -29,6 +29,8 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, char *hash_str = NULL; uintptr_t haddr; int ret; + uintptr_t img_addr = 0; + char buf[20]; if (argc < 2) return cmd_usage(cmdtp); @@ -43,7 +45,15 @@ static int do_esbc_validate(cmd_tbl_t *cmdtp, int flag, int argc, * part of header. So, the function is called * by passing this argument as 0. */ - ret = fsl_secboot_validate(haddr, hash_str, 0); + ret = fsl_secboot_validate(haddr, hash_str, &img_addr); + + /* Need to set "img_addr" even if validation failure. + * Required when SB_EN in RCW set and non-fatal error + * to continue U-Boot + */ + sprintf(buf, "%lx", img_addr); + setenv("img_addr", buf); + if (ret) return 1; diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 8fd6dd6..64e4e30 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, }; static u8 hash_val[SHA256_BYTES]; + +#ifdef CONFIG_ESBC_HDR_LS +/* New Barker Code for LS ESBC Header */ +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; +#else static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; +#endif void branch_to_self(void) __attribute__ ((noreturn)); @@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr) /* This function checks srk_table_flag in header and set/reset srk_flag.*/ static u32 check_srk(struct fsl_secboot_img_priv *img) { +#ifdef CONFIG_ESBC_HDR_LS + /* In LS, No SRK Flag as SRK is always present*/ + return 1; +#else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) return 1; return 0; +#endif } /* This function returns ospr's key_revoc values.*/ @@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) } #endif +#ifndef CONFIG_ESBC_HDR_LS static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; @@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) return 0; } +#endif /* CONFIG_ESBC_HDR_LS */ #if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) @@ -312,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void) printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); } /* @@ -342,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void) printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + } else { change_sec_mon_state(HPSR_SSM_ST_TRUST, HPSR_SSM_ST_NON_SECURE); @@ -388,6 +406,7 @@ void fsl_secboot_handle_error(int error) case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: + case ERROR_KEY_TABLE_NOT_FOUND: #ifdef CONFIG_KEY_REVOCATION case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: @@ -536,15 +555,22 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) if (!key_hash && check_ie(img)) key_hash = 1; #endif - if (!key_hash) +#ifndef CONFIG_ESBC_HDR_LS +/* No single key support in LS ESBC header */ + if (!key_hash) { ret = algo->hash_update(algo, ctx, img->img_key, img->hdr.key_len, 0); + key_hash = 1; + } +#endif if (ret) return ret; + if (!key_hash) + return ERROR_KEY_TABLE_NOT_FOUND; /* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, - (u8 *)img->img_addr, img->img_size, 1); + (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); if (ret) return ret; @@ -620,14 +646,11 @@ static void construct_img_encoded_hash_second(struct fsl_secboot_img_priv *img) */ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) { - char buf[20]; struct fsl_secboot_img_hdr *hdr = &img->hdr; void *esbc = (u8 *)(uintptr_t)img->ehdrloc; u8 *k, *s; u32 ret = 0; -#ifdef CONFIG_KEY_REVOCATION -#endif int key_found = 0; /* check barker code */ @@ -637,17 +660,14 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) /* If Image Address is not passed as argument to function, * then Address and Size must be read from the Header. */ - if (img->img_addr == 0) { + if (*(img->img_addr_ptr) == 0) { #ifdef CONFIG_ESBC_ADDR_64BIT - img->img_addr = hdr->pimg64; + *(img->img_addr_ptr) = hdr->pimg64; #else - img->img_addr = hdr->pimg; + *(img->img_addr_ptr) = hdr->pimg; #endif } - sprintf(buf, "%lx", img->img_addr); - setenv("img_addr", buf); - if (!hdr->img_size) return ERROR_ESBC_CLIENT_HEADER_IMG_SIZE; @@ -671,13 +691,17 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) key_found = 1; } #endif - +#ifndef CONFIG_ESBC_HDR_LS +/* Single Key Feature not available in LS ESBC Header */ if (key_found == 0) { ret = read_validate_single_key(img); if (ret != 0) return ret; key_found = 1; } +#endif + if (!key_found) + return ERROR_KEY_TABLE_NOT_FOUND; /* check signaure */ if (get_key_len(img) == 2 * hdr->sign_len) { @@ -691,10 +715,12 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) } memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); - +/* No SG support in LS-CH3 */ +#ifndef CONFIG_ESBC_HDR_LS /* No SG support */ if (hdr->sg_flag) return ERROR_ESBC_CLIENT_HEADER_SG; +#endif /* modulus most significant bit should be set */ k = (u8 *)&img->img_key; @@ -784,9 +810,17 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img) return 0; } - +/* haddr - Address of the header of image to be validated. + * arg_hash_str - Option hash string. If provided, this + * overides the key hash in the SFP fuses. + * img_addr_ptr - Optional pointer to address of image to be validated. + * If non zero addr, this overides the addr of image in header, + * otherwise updated to image addr in header. + * Acts as both input and output of function. + * This pointer shouldn't be NULL. + */ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, - uintptr_t img_addr) + uintptr_t *img_addr_ptr) { struct ccsr_sfp_regs *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR); ulong hash[SHA256_BYTES/sizeof(ulong)]; @@ -839,7 +873,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, /* Update the information in Private Struct */ hdr = &img->hdr; img->ehdrloc = haddr; - img->img_addr = img_addr; + img->img_addr_ptr = img_addr_ptr; esbc = (u8 *)img->ehdrloc; memcpy(hdr, esbc, sizeof(struct fsl_secboot_img_hdr)); diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 1bd65a8..2f29795 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -10,6 +10,8 @@ #include <asm/io.h> #ifdef CONFIG_LS1043A #include <asm/arch/immap_lsch2.h> +#elif defined(CONFIG_FSL_LSCH3) +#include <asm/arch/immap_lsch3.h> #else #include <asm/immap_85xx.h> #endif @@ -285,7 +287,7 @@ static int set_voltage(int i2caddress, int vdd) int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); -#ifdef CONFIG_LS1043A +#if defined(CONFIG_LS1043A) || defined(CONFIG_FSL_LSCH3) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = @@ -362,7 +364,11 @@ int adjust_vdd(ulong vdd_override) } /* get the voltage ID from fuse status register */ +#ifdef CONFIG_FSL_LSCH3 + fusesr = in_le32(&gur->dcfg_fusesr); +#else fusesr = in_be32(&gur->dcfg_fusesr); +#endif /* * VID is used according to the table below * --------------------------------------- @@ -387,6 +393,13 @@ int adjust_vdd(ulong vdd_override) vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) & FSL_CHASSIS2_DCFG_FUSESR_VID_MASK; } +#elif defined(CONFIG_FSL_LSCH3) + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } #else vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; @@ -454,6 +467,9 @@ int adjust_vdd(ulong vdd_override) exit: if (re_enable) enable_interrupts(); + + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + return ret; } @@ -469,7 +485,7 @@ static int print_vdd(void) ret = find_ir_chip_on_i2c(); if (ret < 0) { printf("VID: Could not find voltage regulator on I2C.\n"); - return -1; + goto exit; } else { i2caddress = ret; debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); @@ -481,11 +497,14 @@ static int print_vdd(void) vdd_last = read_voltage(i2caddress); if (vdd_last < 0) { printf("VID: Couldn't read sensor abort VID adjustment\n"); - return -1; + goto exit; } printf("VID: Core voltage is at %d mV\n", vdd_last); +exit: + i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); + + return ret < 0 ? -1 : 0; - return 0; } static int do_vdd_override(cmd_tbl_t *cmdtp, diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 67b4afe..bf26376 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -176,9 +176,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5G SGMII interface */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 1000; + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(1000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for 2.5G SGMII */ @@ -241,9 +241,9 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && port == FM1_10GEC1) { /* XFI interface */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; + f_link.phy_id = cpu_to_fdt32(port); + f_link.duplex = cpu_to_fdt32(1); + f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; /* no PHY for XFI */ diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index a72fe52..fba6b88 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -170,8 +170,7 @@ void board_retimer_init(void) u8 reg; /* Retimer is connected to I2C1_CH7_CH5 */ - reg = I2C_MUX_CH7; - i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); + select_i2c_ch_pca9547(I2C_MUX_CH7); reg = I2C_MUX_CH5; i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); @@ -219,6 +218,9 @@ void board_retimer_init(void) i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); + + /* Return the default channel */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); } int board_early_init_f(void) diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS index 975ea2d..c8dac99 100644 --- a/board/freescale/ls2080a/MAINTAINERS +++ b/board/freescale/ls2080a/MAINTAINERS @@ -6,5 +6,3 @@ F: include/configs/ls2080a_emu.h F: configs/ls2080a_emu_defconfig F: include/configs/ls2080a_simu.h F: configs/ls2080a_simu_defconfig -F: configs/ls2085a_emu_defconfig -F: configs/ls2085a_simu_defconfig diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 56c5d96..1827ddc 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 7bce8b0..00337d7 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -42,7 +42,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); @@ -87,14 +87,14 @@ void fdt_fixup_board_enet(void *fdt) { int offset; - offset = fdt_path_offset(fdt, "/fsl-mc"); + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); /* * TODO: Remove this when backward compatibility - * with old DT node (fsl,dprc@0) is no longer needed. + * with old DT node (/fsl-mc) is no longer needed. */ if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + offset = fdt_path_offset(fdt, "/fsl-mc"); if (offset < 0) { printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 6f99ad0..7d3bfc8 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -6,5 +6,8 @@ F: board/freescale/ls2080a/ls2080aqds.c F: include/configs/ls2080aqds.h F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig -F: configs/ls2085aqds_defconfig -F: configs/ls2085aqds_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.jain@nxp.freescale.com> +S: Maintained +F: configs/ls2080aqds_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 9fb5e11..fcb0366 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 42ff743..33ad7dc 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -548,12 +548,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 2: /* Slot housing a SGMII riser card? */ @@ -562,12 +556,6 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT2; bus = mii_dev_for_muxval(EMI1_SLOT2); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; @@ -606,12 +594,6 @@ serdes2: dpmac_info[dpmac_id].board_mux = EMI1_SLOT4; bus = mii_dev_for_muxval(EMI1_SLOT4); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - phy_config(dpmac_info[dpmac_id].phydev); break; case 5: break; @@ -679,13 +661,6 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) dpmac_info[dpmac_id].board_mux = EMI1_SLOT1; bus = mii_dev_for_muxval(EMI1_SLOT1); wriop_set_mdio(dpmac_id, bus); - dpmac_info[dpmac_id].phydev = phy_connect( - dpmac_info[dpmac_id].bus, - dpmac_info[dpmac_id].phy_addr, - NULL, - dpmac_info[dpmac_id].enet_if); - - phy_config(dpmac_info[dpmac_id].phydev); break; case 3: break; diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index aa256a2..b3bd40a 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -19,6 +19,7 @@ #include <rtc.h> #include <asm/arch/soc.h> #include <hwconfig.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -227,7 +228,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); @@ -248,7 +249,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif @@ -258,10 +261,10 @@ void fdt_fixup_board_enet(void *fdt) { int offset; - offset = fdt_path_offset(fdt, "/fsl-mc"); + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + offset = fdt_path_offset(fdt, "/fsl-mc"); if (offset < 0) { printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index c9f3459..5562917 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -6,5 +6,8 @@ F: board/freescale/ls2080a/ls2080ardb.c F: include/configs/ls2080ardb.h F: configs/ls2080ardb_defconfig F: configs/ls2080ardb_nand_defconfig -F: configs/ls2085ardb_defconfig -F: configs/ls2085ardb_nand_defconfig + +LS2080A_SECURE_BOOT BOARD +M: Saksham Jain <saksham.jain@nxp.freescale.com> +S: Maintained +F: configs/ls2080ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 6c19173..a04d21b 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -7,6 +7,7 @@ #include <common.h> #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> +#include <asm/arch/soc.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -201,22 +202,24 @@ void dram_init_banksize(void) } #ifdef CONFIG_SYS_DP_DDR_BASE_PHY - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, CONFIG_DP_DDR_CTRL, CONFIG_DP_DDR_NUM_CTRLS, CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } } #endif } diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index db50e4e..58ea746 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,42 +20,6 @@ DECLARE_GLOBAL_DATA_PTR; -int load_firmware_cortina(struct phy_device *phy_dev) -{ - if (phy_dev->drv->config) - return phy_dev->drv->config(phy_dev); - - return 0; -} - -void load_phy_firmware(void) -{ - int i; - u8 phy_addr; - struct phy_device *phy_dev; - struct mii_dev *dev; - phy_interface_t interface; - - /*Initialize and upload firmware for all the PHYs*/ - for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { - interface = wriop_get_enet_if(i); - if (interface == PHY_INTERFACE_MODE_XGMII) { - dev = wriop_get_mdio(i); - phy_addr = wriop_get_phy_address(i); - phy_dev = phy_find_by_mask(dev, 1 << phy_addr, - interface); - if (!phy_dev) { - printf("No phydev for phyaddr %d\n", phy_addr); - continue; - } - - /*Flash firmware for All CS4340 PHYS */ - if (phy_dev->phy_id == PHY_UID_CS4340) - load_firmware_cortina(phy_dev); - } - } -} - int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) @@ -125,9 +89,6 @@ int board_eth_init(bd_t *bis) } } - /* Load CORTINA CS4340 PHY firmware */ - load_phy_firmware(); - cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c63b639..fb39af6 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -18,9 +18,11 @@ #include <environment.h> #include <i2c.h> #include <asm/arch/soc.h> +#include <fsl_sec.h> #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#include "../common/vid.h" #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -122,6 +124,11 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int i2c_multiplexer_select_vid_channel(u8 channel) +{ + return select_i2c_ch_pca9547(channel); +} + int config_board_mux(int ctrl_type) { u8 reg5; @@ -149,6 +156,7 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; u32 val; init_final_memctl_regs(); @@ -170,6 +178,9 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); + /* invert AQR405 IRQ pins polarity */ + out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); + return 0; } @@ -184,6 +195,9 @@ int misc_init_r(void) if (hwconfig("sdhc")) config_board_mux(MUX_TYPE_SDHC); + if (adjust_vdd(0)) + printf("Warning: Adjusting core voltage failed.\n"); + return 0; } @@ -193,7 +207,7 @@ void detail_board_ddr_info(void) print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); print_ddr_info(0); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - if (gd->bd->bi_dram[2].size) { + if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { puts("\nDP-DDR "); print_size(gd->bd->bi_dram[2].size, ""); print_ddr_info(CONFIG_DP_DDR_CTRL); @@ -214,7 +228,9 @@ int arch_misc_init(void) #ifdef CONFIG_FSL_DEBUG_SERVER debug_server_init(); #endif - +#ifdef CONFIG_FSL_CAAM + sec_init(); +#endif return 0; } #endif @@ -224,10 +240,10 @@ void fdt_fixup_board_enet(void *fdt) { int offset; - offset = fdt_path_offset(fdt, "/fsl-mc"); + offset = fdt_path_offset(fdt, "/soc/fsl-mc"); if (offset < 0) - offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + offset = fdt_path_offset(fdt, "/fsl-mc"); if (offset < 0) { printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index c7c21f3..2ea5346 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -20,7 +20,7 @@ #include <power/pmic.h> #include <fsl_pmic.h> #include <mc13892.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index f440ce6..f1915a8 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index a240982..886373c 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -28,7 +28,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> #include <pca953x.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 41319c6..25e009e 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -27,7 +27,7 @@ #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 98d5675..88d3fbd 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -27,7 +27,7 @@ #include <power/pfuze3000_pmic.h> #include "../common/pfuze.h" #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 4d0b195..c3062f1 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -24,7 +24,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/arch/crm_regs.h> #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index d35aee0..54e7f63 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -12,6 +12,16 @@ #include <errno.h> #include <i2c.h> +#define DP501_I2C_ADDR 0x08 + +#ifdef CONFIG_SYS_DP501_I2C +int dp501_i2c[] = CONFIG_SYS_DP501_I2C; +#endif + +#ifdef CONFIG_SYS_DP501_BASE +int dp501_base[] = CONFIG_SYS_DP501_BASE; +#endif + static void dp501_setbits(u8 addr, u8 reg, u8 mask) { u8 val; @@ -125,3 +135,24 @@ void dp501_powerdown(u8 addr) { dp501_setbits(addr, 0x0a, 0x30); /* power down encoder, standby mode */ } + + +int dp501_probe(unsigned screen, bool power) +{ +#ifdef CONFIG_SYS_DP501_BASE + uint8_t dp501_addr = dp501_base[screen]; +#else + uint8_t dp501_addr = DP501_I2C_ADDR; +#endif + +#ifdef CONFIG_SYS_DP501_I2C + i2c_set_bus_num(dp501_i2c[screen]); +#endif + + if (i2c_probe(dp501_addr)) + return -1; + + dp501_powerup(dp501_addr); + + return 0; +} diff --git a/board/gdsys/common/dp501.h b/board/gdsys/common/dp501.h index 8dc3215..b98b54e 100644 --- a/board/gdsys/common/dp501.h +++ b/board/gdsys/common/dp501.h @@ -26,5 +26,6 @@ void dp501_powerup(u8 addr); void dp501_powerdown(u8 addr); +int dp501_probe(unsigned screen, bool power); #endif diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 7444bee..4e292f5 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -24,8 +24,6 @@ #define SIL1178_MASTER_I2C_ADDRESS 0x38 #define SIL1178_SLAVE_I2C_ADDRESS 0x39 -#define DP501_I2C_ADDR 0x08 - #define PIXCLK_640_480_60 25180000 #define MAX_X_CHARS 53 #define MAX_Y_CHARS 26 @@ -78,14 +76,6 @@ int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C; int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C; #endif -#ifdef CONFIG_SYS_DP501_I2C -int dp501_i2c[] = CONFIG_SYS_DP501_I2C; -#endif - -#ifdef CONFIG_SYS_DP501_BASE -int dp501_base[] = CONFIG_SYS_DP501_BASE; -#endif - #ifdef CONFIG_SYS_MPC92469AC static void mpc92469ac_calc_parameters(unsigned int fout, unsigned int *post_div, unsigned int *feedback_div) @@ -317,13 +307,6 @@ int osd_probe(unsigned screen) int old_bus = i2c_get_bus_num(); bool pixclock_present = false; bool output_driver_present = false; -#ifdef CONFIG_SYS_DP501_I2C -#ifdef CONFIG_SYS_DP501_BASE - uint8_t dp501_addr = dp501_base[screen]; -#else - uint8_t dp501_addr = DP501_I2C_ADDR; -#endif -#endif OSD_GET_REG(0, version, &version); OSD_GET_REG(0, features, &features); @@ -393,11 +376,8 @@ int osd_probe(unsigned screen) #endif #ifdef CONFIG_SYS_DP501_I2C - i2c_set_bus_num(dp501_i2c[screen]); - if (!i2c_probe(dp501_addr)) { - dp501_powerup(dp501_addr); + if (!dp501_probe(screen, true)) output_driver_present = true; - } #endif if (!output_driver_present) diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index ef5b6c0..eee582b 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -24,6 +24,7 @@ #include "../common/adv7611.h" #include "../common/ch7301.h" +#include "../common/dp501.h" #include "../common/ioep-fpga.h" #include "../common/mclink.h" #include "../common/osd.h" @@ -127,7 +128,10 @@ int last_stage_init(void) int slaves; unsigned int k; unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; +#ifdef CONFIG_STRIDER_CPU + unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; +#endif bool hw_type_cat = pca9698_get_value(0x20, 18); bool ch0_sgmii2_present = false; @@ -135,17 +139,25 @@ int last_stage_init(void) pca9698_direction_output(0x20, 8, 0); /* Turn on Parade DP501 */ - pca9698_direction_output(0x20, 9, 1); + pca9698_direction_output(0x20, 10, 1); ch0_sgmii2_present = !pca9698_get_value(0x20, 37); /* wait for FPGA done, then reset FPGA */ - for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { unsigned int ctr = 0; + unsigned char *mclink_controllers = mclink_controllers_dvi; +#ifdef CONFIG_STRIDER_CPU + if (i2c_probe(mclink_controllers[k])) { + mclink_controllers = mclink_controllers_dp; + if (i2c_probe(mclink_controllers[k])) + continue; + } +#else if (i2c_probe(mclink_controllers[k])) continue; - +#endif while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { udelay(100000); @@ -192,6 +204,7 @@ int last_stage_init(void) #ifdef CONFIG_STRIDER_CPU ch7301_probe(0, false); + dp501_probe(0, false); #endif if (slaves <= 0) @@ -199,6 +212,14 @@ int last_stage_init(void) mclink_fpgacount = slaves; +#ifdef CONFIG_STRIDER_CPU + /* get ADV7611 out of reset, power up DP501, give some time to wakeup */ + for (k = 1; k <= slaves; ++k) + FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ + + udelay(500000); +#endif + for (k = 1; k <= slaves; ++k) { ioep_fpga_print_info(k); #ifdef CONFIG_STRIDER_CON @@ -206,10 +227,10 @@ int last_stage_init(void) osd_probe(k); #endif #ifdef CONFIG_STRIDER_CPU - FPGA_SET_REG(k, extended_control, 0); /* enable video in*/ if (!adv7611_probe(k)) printf(" Advantiv ADV7611 HDMI Receiver\n"); ch7301_probe(k, false); + dp501_probe(k, false); #endif if (hw_type_cat) { miiphy_register(bb_miiphy_buses[k].name, diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 1edc807..3b484a9 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -77,7 +77,7 @@ static const struct pl01x_serial_platdata serial_platdata = { #elif CONFIG_CONS_INDEX == 4 .base = HI6220_UART3_BASE, #else -#error "Unsuported console index value." +#error "Unsupported console index value." #endif .type = TYPE_PL011, .clock = 19200000 diff --git a/board/lge/sniper/Kconfig b/board/lg/sniper/Kconfig index f7a682e..3f18d21 100644 --- a/board/lge/sniper/Kconfig +++ b/board/lg/sniper/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "sniper" config SYS_VENDOR - default "lge" + default "lg" config SYS_CONFIG_NAME default "sniper" diff --git a/board/lge/sniper/MAINTAINERS b/board/lg/sniper/MAINTAINERS index 0e7baa5..7226b09 100644 --- a/board/lge/sniper/MAINTAINERS +++ b/board/lg/sniper/MAINTAINERS @@ -1,6 +1,6 @@ SNIPER BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained -F: board/lge/sniper/ +F: board/lg/sniper/ F: include/configs/sniper.h F: configs/sniper_defconfig diff --git a/board/lge/sniper/Makefile b/board/lg/sniper/Makefile index f32a481..f32a481 100644 --- a/board/lge/sniper/Makefile +++ b/board/lg/sniper/Makefile diff --git a/board/lge/sniper/sniper.c b/board/lg/sniper/sniper.c index 29a7045..0662449 100644 --- a/board/lge/sniper/sniper.c +++ b/board/lg/sniper/sniper.c @@ -94,6 +94,7 @@ int misc_init_r(void) char reboot_mode[2] = { 0 }; unsigned char keys[3]; unsigned char data = 0; + int rc; /* Power button reset init */ @@ -109,22 +110,14 @@ int misc_init_r(void) /* Reboot mode */ - omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); + rc = omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); if (keys[0]) reboot_mode[0] = 'r'; else if (keys[1]) reboot_mode[0] = 'b'; - if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { - if (!getenv("reboot-mode")) - setenv("reboot-mode", (char *)reboot_mode); - - omap_reboot_mode_clear(); - } else { - /* Reboot mode garbage may still be valid, so clear it. */ - omap_reboot_mode_clear(); - + if (rc < 0 || reboot_mode[0] == 'o') { /* * When not rebooting, valid power on reasons are either the * power button, charger plug or USB plug. @@ -138,6 +131,13 @@ int misc_init_r(void) twl4030_power_off(); } + if (reboot_mode[0] > 0 && isascii(reboot_mode[0])) { + if (!getenv("reboot-mode")) + setenv("reboot-mode", (char *)reboot_mode); + } + + omap_reboot_mode_clear(); + /* Serial number */ omap_die_id_serial(); @@ -160,6 +160,19 @@ void get_board_serial(struct tag_serialnr *serialnr) omap_die_id_get_board_serial(serialnr); } +void reset_misc(void) +{ + char reboot_mode[2] = { 0 }; + + /* + * Valid resets must contain the reboot mode magic, but we must not + * override it when set previously (e.g. reboot to bootloader). + */ + + omap_reboot_mode(reboot_mode, sizeof(reboot_mode)); + omap_reboot_mode_store(reboot_mode); +} + int fb_set_reboot_flag(void) { return omap_reboot_mode_store("b"); diff --git a/board/lge/sniper/sniper.h b/board/lg/sniper/sniper.h index 0f81c43..0f81c43 100644 --- a/board/lge/sniper/sniper.h +++ b/board/lg/sniper/sniper.h diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 5590be1..8399407 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -52,7 +52,7 @@ * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They * will be inserted after the appropriate (depending the interval setting) skeleton TD. * If an interrupt has been detected the dev->irqhandler is called. The status and number - * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the + * of transferred bytes is stored in dev->irq_status resp. dev->irq_act_len. If the * dev->irqhandler returns 0, the interrupt TD is removed and disabled. If an 1 is returned, * the interrupt TD will be reactivated. * @@ -156,7 +156,7 @@ unsigned long usb_uhci_td_stat(unsigned long status) return result; } -/* get the status and the transfered len of a td chain. +/* get the status and the transferred len of a td chain. * called from the completion handler */ int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) @@ -177,7 +177,7 @@ int usb_get_td_status(uhci_td_t *td,struct usb_device *dev) (((info >> 21) & 0x7ff)!= 0x7ff) && (temp & 0x7FF)!=0x7ff) { /* if not setup and not null data pack */ - dev->act_len+=(temp & 0x7FF) + 1; /* the transfered len is act_len + 1 */ + dev->act_len+=(temp & 0x7FF) + 1; /* the transferred len is act_len + 1 */ } if(stat) { /* status no ok */ dev->status=stat; @@ -533,7 +533,7 @@ void usb_check_int_chain(void) if((td->dev_ptr!=0L) && !(status & TD_CTRL_ACTIVE)) { /* td is not active and a device is assigned -> call irqhandler */ dev=(struct usb_device *)td->dev_ptr; - dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transfered length */ + dev->irq_act_len=((status & 0x7FF)==0x7FF) ? 0 : (status & 0x7FF) + 1; /* transferred length */ dev->irq_status=usb_uhci_td_stat(status); /* get status */ res=dev->irq_handle(dev); /* call irqhandler */ if(res==1) { diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig new file mode 100644 index 0000000..03bd7ae --- /dev/null +++ b/board/qualcomm/dragonboard410c/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DRAGONBOARD410C + +config SYS_BOARD + default "dragonboard410c" + +config SYS_VENDOR + default "qualcomm" + +config SYS_SOC + default "apq8016" + +config SYS_CONFIG_NAME + default "dragonboard410c" + +endif diff --git a/board/qualcomm/dragonboard410c/MAINTAINERS b/board/qualcomm/dragonboard410c/MAINTAINERS new file mode 100644 index 0000000..65cb47c --- /dev/null +++ b/board/qualcomm/dragonboard410c/MAINTAINERS @@ -0,0 +1,6 @@ +DRAGONBOARD410C BOARD +M: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> +S: Maintained +F: board/qualcomm/dragonboard410c/ +F: include/configs/dragonboard410c.h +F: configs/dragonboard410c_defconfig diff --git a/board/qualcomm/dragonboard410c/Makefile b/board/qualcomm/dragonboard410c/Makefile new file mode 100644 index 0000000..cd67808 --- /dev/null +++ b/board/qualcomm/dragonboard410c/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := dragonboard410c.o +extra-y += head.o diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c new file mode 100644 index 0000000..1fa5664 --- /dev/null +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -0,0 +1,131 @@ +/* + * Board init file for Dragonboard 410C + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <usb.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + + +int board_prepare_usb(enum usb_init_type type) +{ + static struct udevice *pmic_gpio; + static struct gpio_desc hub_reset, usb_sel; + int ret = 0, node; + + if (!pmic_gpio) { + ret = uclass_get_device_by_name(UCLASS_GPIO, + "pm8916_gpios@c000", + &pmic_gpio); + if (ret < 0) { + printf("Failed to find pm8916_gpios@c000 node.\n"); + return ret; + } + } + + /* Try to request gpios needed to start usb host on dragonboard */ + if (!dm_gpio_is_valid(&hub_reset)) { + node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset, + "usb_hub_reset_pm"); + if (node < 0) { + printf("Failed to find usb_hub_reset_pm dt node.\n"); + return node; + } + ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, + &hub_reset, 0); + if (ret < 0) { + printf("Failed to request usb_hub_reset_pm gpio.\n"); + return ret; + } + } + + if (!dm_gpio_is_valid(&usb_sel)) { + node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset, + "usb_sw_sel_pm"); + if (node < 0) { + printf("Failed to find usb_sw_sel_pm dt node.\n"); + return 0; + } + ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, + &usb_sel, 0); + if (ret < 0) { + printf("Failed to request usb_sw_sel_pm gpio.\n"); + return ret; + } + } + + if (type == USB_INIT_HOST) { + /* Start USB Hub */ + dm_gpio_set_dir_flags(&hub_reset, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + mdelay(100); + /* Switch usb to host connectors */ + dm_gpio_set_dir_flags(&usb_sel, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + mdelay(100); + } else { /* Device */ + /* Disable hub */ + dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT); + /* Switch back to device connector */ + dm_gpio_set_dir_flags(&usb_sel, GPIOD_IS_OUT); + } + + return 0; +} + +int board_init(void) +{ + return 0; +} + +/* Check for vol- button - if pressed - stop autoboot */ +int misc_init_r(void) +{ + struct udevice *pon; + struct gpio_desc resin; + int node, ret; + + ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8916_pon@800", &pon); + if (ret < 0) { + printf("Failed to find PMIC pon node. Check device tree\n"); + return 0; + } + + node = fdt_subnode_offset(gd->fdt_blob, pon->of_offset, "key_vol_down"); + if (node < 0) { + printf("Failed to find key_vol_down node. Check device tree\n"); + return 0; + } + + if (gpio_request_by_name_nodev(gd->fdt_blob, node, "gpios", 0, &resin, + 0)) { + printf("Failed to request key_vol_down button.\n"); + return 0; + } + + if (dm_gpio_get_value(&resin)) { + setenv("bootdelay", "-1"); + printf("Power button pressed - dropping to console.\n"); + } + + return 0; +} diff --git a/board/qualcomm/dragonboard410c/head.S b/board/qualcomm/dragonboard410c/head.S new file mode 100644 index 0000000..ba29b12 --- /dev/null +++ b/board/qualcomm/dragonboard410c/head.S @@ -0,0 +1,34 @@ +/* + * ARM64 header for proper chain-loading with Little Kernel. + * + * Little Kernel shipped with Dragonboard410C boots standard Linux images for + * ARM64. This file adds header that is required to boot U-Boot properly. + * + * For details see: + * https://www.kernel.org/doc/Documentation/arm64/booting.txt + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +.global _arm64_header +_arm64_header: + b _start + .word 0 + /* Image load offset from start of RAM, little-endian */ + .quad CONFIG_SYS_TEXT_BASE-PHYS_SDRAM_1 + /* Effective size of kernel image, little-endian */ + .quad 0 /* 0x60000 - ignored */ + /* Informative flags, little-endian */ + .quad 0 + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .quad 0 /* reserved */ + .byte 0x41 /* Magic number, "ARM\x64" */ + .byte 0x52 + .byte 0x4d + .byte 0x64 + .word 0 /* reserved */ diff --git a/board/qualcomm/dragonboard410c/readme.txt b/board/qualcomm/dragonboard410c/readme.txt new file mode 100644 index 0000000..7fc7c7a --- /dev/null +++ b/board/qualcomm/dragonboard410c/readme.txt @@ -0,0 +1,71 @@ +# +# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +Build & Run instructions: + +1) Install mkbootimg and dtbTool from + git://codeaurora.org/quic/kernel/skales (15ece94f09 worked for me) +2) Setup CROSS_COMPILE to aarch64 compiler +3) make dragonboard410c_config +4) make +5) generate fake, empty ramdisk (can have 0 bytes) +$ touch rd + +6) Generate qualcomm device tree table with dtbTool [1] +$ dtbTool -o dt.img arch/arm/dts + +7) Generate Android boot image with mkbootimg [2]: +$ mkbootimg --kernel=u-boot-dtb.bin --output=u-boot.img --dt=dt.img \ + --pagesize 2048 --base 0x80000000 --ramdisk=rd --cmdline="" + +8) Enter fastboot (reboot board with vol- button pressed) + +9) Boot it: +$ fastboot boot u-boot.img +or flash as kernel: +$ fastboot flash boot u-boot.img +$ fastboot reboot + + +What is working: +- UART +- GPIO (SoC) +- SD +- eMMC +- Reset +- USB in EHCI mode (usb starts does switch device->host, usb stop does the opposite) +- PMIC GPIOS (but not in generic subsystem) +- PMIC "special" buttons (power, vol-) + +What is not working / known bugs: +- SDHCI is slow (~2.5MiB/s for SD and eMMC) + +[1] To boot any kernel image, Little Kernel requires valid device tree for the +platform it runs on. dtbTool creates device tree table that Little Kernel scans. +Later on proper device tree is passed to next boot stage. +Full device tree is not required to boot u-boot. Enough would be: +/dts-v1/; + +/ { + model = "Qualcomm Technologies, Inc. Dragonboard 410c"; + compatible = "qcom,dragonboard", "qcom,apq8016-sbc"; + qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>; + qcom,board-id = <0x10018 0x0>; + #address-cells = <0x2>; + #size-cells = <0x2>; + chosen { }; + aliases { }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x3da00000>; + }; +}; + +but for simplicity (and because size of image is not that critical) we use +existing Qualcomm device trees. + +[2] Note that ramdisk is required, even if it is unused. diff --git a/board/qualcomm/dragonboard410c/u-boot.lds b/board/qualcomm/dragonboard410c/u-boot.lds new file mode 100644 index 0000000..6e1c5a8 --- /dev/null +++ b/board/qualcomm/dragonboard410c/u-boot.lds @@ -0,0 +1,90 @@ +/* + * Override linker script for fastboot-readable images + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(_arm64_header) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(8); + .text : + { + *(.__image_copy_start) + board/qualcomm/dragonboard410c/head.o (.text*) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(8); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(8); + .data : { + *(.data*) + } + + . = ALIGN(8); + + . = .; + + . = ALIGN(8); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(8); + + .image_copy_end : + { + *(.__image_copy_end) + } + + . = ALIGN(8); + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rela.dyn : { + *(.rela*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + . = ALIGN(8); + + .bss_start : { + KEEP(*(.__bss_start)); + } + + .bss : { + *(.bss*) + . = ALIGN(8); + } + + .bss_end : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/raspberrypi/rpi/MAINTAINERS b/board/raspberrypi/rpi/MAINTAINERS index 6dcb7bd..98c3758 100644 --- a/board/raspberrypi/rpi/MAINTAINERS +++ b/board/raspberrypi/rpi/MAINTAINERS @@ -3,4 +3,4 @@ M: Stephen Warren <swarren@wwwdotorg.org> S: Maintained F: board/raspberrypi/rpi/ F: include/configs/rpi.h -F: configs/rpi_defconfig +F: configs/rpi_*defconfig diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 1d3a4e0..c45ddb1 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2012-2013,2015 Stephen Warren + * (C) Copyright 2012-2016 Stephen Warren * * SPDX-License-Identifier: GPL-2.0 */ @@ -18,6 +18,10 @@ #include <asm/arch/sdhci.h> #include <asm/global_data.h> #include <dm/platform_data/serial_pl01x.h> +#include <dm/platform_data/serial_bcm283x_mu.h> +#ifdef CONFIG_ARM64 +#include <asm/armv8/mmu.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -30,20 +34,33 @@ U_BOOT_DEVICE(bcm2835_gpios) = { .platdata = &gpio_platdata, }; +#ifdef CONFIG_PL01X_SERIAL static const struct pl01x_serial_platdata serial_platdata = { -#ifdef CONFIG_BCM2836 +#ifndef CONFIG_BCM2835 .base = 0x3f201000, #else .base = 0x20201000, #endif .type = TYPE_PL011, - .clock = 3000000, + .skip_init = true, }; U_BOOT_DEVICE(bcm2835_serials) = { .name = "serial_pl01x", .platdata = &serial_platdata, }; +#else +static const struct bcm283x_mu_serial_platdata serial_platdata = { + .base = 0x3f215040, + .clock = 250000000, + .skip_init = true, +}; + +U_BOOT_DEVICE(bcm2837_serials) = { + .name = "serial_bcm283x_mu", + .platdata = &serial_platdata, +}; +#endif struct msg_get_arm_mem { struct bcm2835_mbox_hdr hdr; @@ -99,11 +116,7 @@ struct rpi_model { static const struct rpi_model rpi_model_unknown = { "Unknown model", -#ifdef CONFIG_BCM2836 - "bcm2836-rpi-other.dtb", -#else - "bcm2835-rpi-other.dtb", -#endif + "bcm283x-rpi-other.dtb", false, }; @@ -113,6 +126,11 @@ static const struct rpi_model rpi_models_new_scheme[] = { "bcm2836-rpi-2-b.dtb", true, }, + [0x8] = { + "3 Model B", + "bcm2837-rpi-3-b.dtb", + true, + }, [0x9] = { "Zero", "bcm2835-rpi-zero.dtb", @@ -213,6 +231,28 @@ static uint32_t rev_scheme; static uint32_t rev_type; static const struct rpi_model *model; +#ifdef CONFIG_ARM64 +static struct mm_region bcm2837_mem_map[] = { + { + .base = 0x00000000UL, + .size = 0x3f000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .base = 0x3f000000UL, + .size = 0x01000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm2837_mem_map; +#endif + int dram_init(void) { ALLOC_CACHE_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1); diff --git a/board/raspberrypi/rpi_2/MAINTAINERS b/board/raspberrypi/rpi_2/MAINTAINERS deleted file mode 100644 index 85a480c..0000000 --- a/board/raspberrypi/rpi_2/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -RPI_2 BOARD -M: Stephen Warren <swarren@wwwdotorg.org> -S: Maintained -F: board/raspberrypi/rpi_2/ -F: include/configs/rpi_2.h -F: configs/rpi_2_defconfig diff --git a/board/raspberrypi/rpi_2/Makefile b/board/raspberrypi/rpi_2/Makefile deleted file mode 100644 index d82cd21..0000000 --- a/board/raspberrypi/rpi_2/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# -# (C) Copyright 2012,2015 Stephen Warren -# -# SPDX-License-Identifier: GPL-2.0 -# - -obj-y := ../rpi/rpi.o diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 823b70f..bcc9729 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -33,7 +33,7 @@ #include <asm/arch/sys_proto.h> #include <spl.h> #include <usb.h> -#include <usb/ehci-fsl.h> +#include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 5e9d3af..fa78720 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -77,6 +77,11 @@ config MACH_SUN8I_H3 select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT +config MACH_SUN50I + bool "sun50i (Allwinner A64)" + select ARM64 + select SUNXI_GEN_SUN6I + config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7 @@ -213,6 +218,7 @@ config DRAM_ODT_CORRECTION endif config SYS_CLK_FREQ + default 816000000 if MACH_SUN50I default 912000000 if MACH_SUN7I default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I @@ -223,6 +229,7 @@ config SYS_CONFIG_NAME default "sun7i" if MACH_SUN7I default "sun8i" if MACH_SUN8I default "sun9i" if MACH_SUN9I + default "sun50i" if MACH_SUN50I config SYS_BOARD default "sunxi" @@ -305,6 +312,15 @@ config MMC_SUNXI_SLOT_EXTRA slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable support for this. +config INITIAL_USB_SCAN_DELAY + int "delay initial usb scan by x ms to allow builtin devices to init" + default 0 + ---help--- + Some boards have on board usb devices which need longer than the + USB spec's 1 second to connect from board powerup. Set this config + option to a non 0 value to add an extra delay before the first usb + bus scan. + config USB0_VBUS_PIN string "Vbus enable pin for usb0 (otg)" default "" @@ -342,6 +358,12 @@ config USB2_VBUS_PIN ---help--- See USB1_VBUS_PIN help text. +config USB3_VBUS_PIN + string "Vbus enable pin for usb3 (ehci2)" + default "" + ---help--- + See USB1_VBUS_PIN help text. + config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I @@ -598,7 +620,7 @@ config GMAC_TX_DELAY Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR - default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I + default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I default 0x2fe00000 if MACH_SUN9I endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 739b6fd..2cb8a75 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -7,6 +7,7 @@ F: configs/A10-OLinuXino-Lime_defconfig F: configs/ba10_tv_box_defconfig F: configs/Chuwi_V7_CW0825_defconfig F: configs/Cubieboard_defconfig +F: configs/dserve_dsrv9703c_defconfig F: configs/Hyundai_A7HD_defconfig F: configs/inet1_defconfig F: configs/inet97fv2_defconfig @@ -25,6 +26,7 @@ F: configs/A13-OLinuXinoM_defconfig F: configs/Auxtek-T003_defconfig F: configs/Auxtek-T004_defconfig F: configs/CHIP_defconfig +F: configs/difrnce_dit4350_defconfig F: configs/Empire_electronix_d709_defconfig F: configs/inet98v_rev2_defconfig F: configs/mk802_a10s_defconfig @@ -33,6 +35,7 @@ F: configs/r7-tv-dongle_defconfig F: configs/UTOO_P66_defconfig F: configs/Wobo_i5_defconfig F: include/configs/sun6i.h +F: configs/colorfly_e708_q1_defconfig F: configs/CSQ_CS908_defconfig F: configs/Mele_A1000G_quad_defconfig F: configs/Mele_M9_defconfig @@ -51,13 +54,18 @@ F: configs/Wits_Pro_A20_DKT_defconfig F: include/configs/sun8i.h F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig +F: configs/orangepi_2_defconfig +F: configs/orangepi_one_defconfig F: configs/orangepi_pc_defconfig F: configs/orangepi_plus_defconfig +F: configs/polaroid_mid2809pxe04_defconfig F: configs/q8_a23_tablet_800x480_defconfig F: configs/q8_a33_tablet_800x480_defconfig F: configs/q8_a33_tablet_1024x600_defconfig F: include/configs/sun9i.h F: configs/Merrii_A80_Optimus_defconfig +F: include/configs/sun50i.h +F: configs/pine64_plus_defconfig A20-OLIMEX-SOM-EVB BOARD M: Marcus Cooper <codekipper@gmail.com> @@ -97,6 +105,11 @@ F: include/configs/sun7i.h F: configs/Cubieboard2_defconfig F: configs/Cubietruck_defconfig +CUBIETRUCK-PLUS BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Cubietruck_plus_defconfig + GEMEI-G9 TABLET M: Priit Laes <plaes@plaes.org> S: Maintained @@ -112,6 +125,16 @@ M: Chen-Yu Tsai <wens@csie.org> S: Maintained F: configs/Hummingbird_A31_defconfig +ICnova-A20-SWAC BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: configs/icnova-a20-swac_defconfig + +ITEAD IBOX BOARD +M: Marcus Cooper <codekipper@gmail.com> +S: Maintained +F: configs/Itead_Ibox_A20_defconfig + INET 3F BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained @@ -177,6 +200,12 @@ M: Siarhei Siamashka <siarhei.siamashka@gmail.com> S: Maintained F: configs/MSI_Primo81_defconfig +SINLINX SINA31s BOARD +M: Chen-Yu Tsai <wens@csie.org> +S: Maintained +F: configs/Sinlinx_SinA31s_defconfig +W: http://linux-sunxi.org/Sinlinx_SinA31s + SINLINX SINA33 BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained @@ -197,3 +226,8 @@ YONES TOPTECH BD1078 BOARD M: Paul Kocialkowski <contact@paulk.fr> S: Maintained F: configs/Yones_Toptech_BD1078_defconfig + +YONES TOPTECH BS1078 V2 BOARD +M: Peter Korsgaard <peter@korsgaard.com> +S: Maintained +F: configs/Yones_Toptech_BS1078_V2_defconfig diff --git a/board/sunxi/ahci.c b/board/sunxi/ahci.c index 6d51b9b..522e54a 100644 --- a/board/sunxi/ahci.c +++ b/board/sunxi/ahci.c @@ -72,14 +72,6 @@ static int sunxi_ahci_phy_init(u32 base) void scsi_init(void) { - printf("SUNXI SCSI INIT\n"); -#ifdef CONFIG_SATAPWR - gpio_request(CONFIG_SATAPWR, "satapwr"); - gpio_direction_output(CONFIG_SATAPWR, 1); - /* Give attached sata device time to power-up to avoid link timeouts */ - mdelay(500); -#endif - if (sunxi_ahci_phy_init(SUNXI_SATA_BASE) < 0) return; diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 80eae9c..3cf3614 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -21,6 +21,9 @@ #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/usb_phy.h> +#ifndef CONFIG_ARM64 +#include <asm/armv7.h> +#endif #include <asm/gpio.h> #include <asm/io.h> #include <nand.h> @@ -73,23 +76,52 @@ DECLARE_GLOBAL_DATA_PTR; /* add board specific code here */ int board_init(void) { - int id_pfr1, ret; + __maybe_unused int id_pfr1, ret; gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); +#ifndef CONFIG_ARM64 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); debug("id_pfr1: 0x%08x\n", id_pfr1); /* Generic Timer Extension available? */ - if ((id_pfr1 >> 16) & 0xf) { + if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { + uint32_t freq; + debug("Setting CNTFRQ\n"); - /* CNTFRQ == 24 MHz */ - asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + + /* + * CNTFRQ is a secure register, so we will crash if we try to + * write this from the non-secure world (read is OK, though). + * In case some bootcode has already set the correct value, + * we avoid the risk of writing to it. + */ + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); + if (freq != CONFIG_TIMER_CLK_FREQ) { + debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", + freq, CONFIG_TIMER_CLK_FREQ); +#ifdef CONFIG_NON_SECURE + printf("arch timer frequency is wrong, but cannot adjust it\n"); +#else + asm volatile("mcr p15, 0, %0, c14, c0, 0" + : : "r"(CONFIG_TIMER_CLK_FREQ)); +#endif + } } +#endif /* !CONFIG_ARM64 */ ret = axp_gpio_init(); if (ret) return ret; +#ifdef CONFIG_SATAPWR + gpio_request(CONFIG_SATAPWR, "satapwr"); + gpio_direction_output(CONFIG_SATAPWR, 1); +#endif +#ifdef CONFIG_MACPWR + gpio_request(CONFIG_MACPWR, "macpwr"); + gpio_direction_output(CONFIG_MACPWR, 1); +#endif + /* Uses dm gpio code so do this here and not in i2c_init_board() */ return soft_i2c_board_init(); } @@ -101,6 +133,15 @@ int dram_init(void) return 0; } +#ifdef CONFIG_MACH_SUN50I +void dram_init_banksize(void) +{ + /* We need to reserve the first 16MB of RAM for ATF */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024); + gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024); +} +#endif + #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) static void nand_pinmux_setup(void) { @@ -255,7 +296,7 @@ static void mmc_pinmux_setup(int sdc) sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); sunxi_gpio_set_drv(SUNXI_GPC(24), 2); } -#elif defined(CONFIG_MACH_SUN8I) +#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) /* SDC2: PC5-PC6, PC8-PC16 */ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); @@ -477,6 +518,12 @@ void sunxi_board_init(void) power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); #endif + +#ifdef CONFIG_AXP818_POWER + power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); + power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); + power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); +#endif #endif printf("DRAM:"); ramsize = sunxi_dram_init(); @@ -532,7 +579,7 @@ void get_board_serial(struct tag_serialnr *serialnr) */ static void parse_spl_header(const uint32_t spl_addr) { - struct boot_file_head *spl = (void *)spl_addr; + struct boot_file_head *spl = (void *)(ulong)spl_addr; if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { uint8_t spl_header_version = spl->spl_signature[3]; if (spl_header_version == SPL_HEADER_VERSION) { @@ -598,11 +645,14 @@ int misc_init_r(void) } #endif -#ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { + int __maybe_unused r; + #ifdef CONFIG_VIDEO_DT_SIMPLEFB - return sunxi_simplefb_setup(blob); + r = sunxi_simplefb_setup(blob); + if (r) + return r; #endif + return 0; } -#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 4e222d8..69eb8ff 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -6,7 +6,7 @@ #include <asm/arch/clock.h> #include <asm/arch/gpio.h> -int sunxi_gmac_initialize(bd_t *bis) +void eth_init_board(void) { int pin; struct sunxi_ccm_reg *const ccm = @@ -79,16 +79,4 @@ int sunxi_gmac_initialize(bd_t *bis) for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC); #endif - -#ifdef CONFIG_DM_ETH - return 0; -#else -# ifdef CONFIG_RGMII - return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); -# elif defined CONFIG_GMII - return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); -# else - return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); -# endif -#endif } diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h index 83b1093..51b262b 100644 --- a/board/terasic/sockit/qts/iocsr_config.h +++ b/board/terasic/sockit/qts/iocsr_config.h @@ -181,17 +181,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0x40680208, - 0x41034051, - 0x12481A00, - 0x802080D0, - 0x34051406, - 0x01A02490, - 0x080D0000, - 0x51406802, - 0x02490340, + 0xE0680B2C, + 0x20834038, + 0x11441A00, + 0x80B2C0D0, + 0x34038E06, + 0x01A00208, + 0x2C0D0000, + 0x38E0680B, + 0x00208340, 0xD000001A, - 0x0680A280, + 0x0680B2C0, 0x10040000, 0x00200000, 0x10040000, @@ -255,17 +255,17 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x00001000, 0xA0000034, 0x0D000001, - 0x40680208, - 0x49034051, - 0x12481A02, - 0x80A280D0, - 0x34030C06, + 0xE0680B2C, + 0x20834038, + 0x11441A00, + 0x80B2C0D0, + 0x34038E06, 0x01A00040, - 0x280D0002, - 0x5140680A, - 0x02490340, - 0xD012481A, - 0x0680A280, + 0x2C0D0002, + 0x38E0680B, + 0x00208340, + 0xD001041A, + 0x0680B2C0, 0x10040000, 0x00200000, 0x10040000, @@ -330,18 +330,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x04864000, - 0x59647A01, - 0xD32CA3DE, - 0xF551451E, - 0x034CD348, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, - 0x05140680, - 0xD669A47A, - 0x1ED32CA3, - 0x48F55E79, - 0x00034C92, + 0x05960680, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -404,18 +404,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x14864000, - 0x59647A05, - 0x9228A3DE, - 0xF65E791E, - 0x034CD348, - 0x821A0186, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, + 0x821A01C7, 0x0000D000, 0x00000680, - 0xD669A47A, - 0x1E9228A3, - 0x48F65E79, - 0x00034CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -478,18 +478,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F3690D, 0x1A041414, 0x00D00000, - 0x0C864000, - 0x79E47A03, - 0xB2AAA3D1, - 0xF551451E, - 0x035CD348, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, 0x00000680, - 0xD159647A, - 0x1ED32CA3, - 0x48F55145, - 0x00035CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, @@ -552,18 +552,18 @@ const unsigned long iocsr_scan_chain3_table[] = { 0x14F1690D, 0x1A041414, 0x00D00000, - 0x04864000, - 0x69A47A01, - 0x9228A3D6, - 0xF65E791E, - 0x034C9248, + 0x18864000, + 0x49247A06, + 0xABCF23D7, + 0xF7DE791E, + 0x0356E388, 0x821A0000, 0x0000D000, 0x00000680, - 0xDE59647A, - 0x1ED32CA3, - 0x48F55E79, - 0x00034CD3, + 0xD749247A, + 0x1EABCF23, + 0x88F7DE79, + 0x000356E3, 0x00080200, 0x00001000, 0x00080200, diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h index 0ecccbf..820b9ff 100644 --- a/board/terasic/sockit/qts/pll_config.h +++ b/board/terasic/sockit/qts/pll_config.h @@ -10,13 +10,13 @@ #define CONFIG_HPS_DBCTRL_STAYOSC1 1 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 @@ -61,7 +61,7 @@ #define CONFIG_HPS_CLK_OSC2_HZ 25000000 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 #define CONFIG_HPS_CLK_EMAC0_HZ 1953125 @@ -69,7 +69,7 @@ #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_CAN0_HZ 12500000 #define CONFIG_HPS_CLK_CAN1_HZ 12500000 @@ -78,8 +78,8 @@ #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h index 81c7d8e..769aa77 100644 --- a/board/terasic/sockit/qts/sdram_config.h +++ b/board/terasic/sockit/qts/sdram_config.h @@ -32,11 +32,11 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 @@ -46,7 +46,7 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 @@ -127,8 +127,8 @@ /* Sequencer defines configuration */ #define AFI_RATE_RATIO 1 -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 #define ENABLE_SUPER_QUICK_CALIBRATION 0 #define IO_DELAY_PER_DCHAIN_TAP 25 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 @@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32 @@ -171,16 +171,16 @@ const u32 ac_rom_init[] = { 0x20700000, 0x20780000, - 0x10080431, - 0x10080530, - 0x10090044, - 0x100a0008, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, 0x100b0000, 0x10380400, - 0x10080449, - 0x100804c8, - 0x100a0024, - 0x10090010, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, 0x100b0000, 0x30780000, 0x38780000, diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile index 9d5b39e..ef5a519 100644 --- a/board/theadorable/Makefile +++ b/board/theadorable/Makefile @@ -5,3 +5,4 @@ # obj-y := theadorable.o +obj-y += fpga.o diff --git a/board/theadorable/fpga.c b/board/theadorable/fpga.c new file mode 100644 index 0000000..6f068c3 --- /dev/null +++ b/board/theadorable/fpga.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <altera.h> +#include <errno.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch-mvebu/spi.h> +#include "theadorable.h" + +/* + * FPGA programming support + */ +static int fpga_pre_fn(int cookie) +{ + int gpio_config = COOKIE2CONFIG(cookie); + int gpio_done = COOKIE2DONE(cookie); + int ret; + + debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n", + __func__, __LINE__, cookie, gpio_config, gpio_done); + + /* Configure config pin */ + /* Set to output */ + ret = gpio_request(gpio_config, "CONFIG"); + if (ret < 0) + return ret; + gpio_direction_output(gpio_config, 1); + + /* Configure done pin */ + /* Set to input */ + ret = gpio_request(gpio_done, "DONE"); + if (ret < 0) + return ret; + + gpio_direction_input(gpio_done); + + return 0; +} + +static int fpga_config_fn(int assert, int flush, int cookie) +{ + int gpio_config = COOKIE2CONFIG(cookie); + + debug("%s (%d): cookie=%08x gpio_config=%d\n", + __func__, __LINE__, cookie, gpio_config); + + if (assert) + gpio_set_value(gpio_config, 1); + else + gpio_set_value(gpio_config, 0); + + return 0; +} + +static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie) +{ + int spi_bus = COOKIE2SPI_BUS(cookie); + int spi_dev = COOKIE2SPI_DEV(cookie); + struct kwspi_registers *reg; + u32 control_reg; + u32 config_reg; + void *dst; + + /* + * Write data to FPGA attached to SPI bus via SPI direct write. + * This results in the fastest and easiest way to program the + * bitstream into the FPGA. + */ + debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n", + __func__, __LINE__, cookie, spi_bus, spi_dev); + + if (spi_bus == 0) { + reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600); + dst = (void *)SPI_BUS0_DEV1_BASE; + } else { + reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680); + dst = (void *)SPI_BUS1_DEV2_BASE; + } + + /* Configure SPI controller for direct access mode */ + control_reg = readl(®->ctrl); + config_reg = readl(®->cfg); + writel(0x00000214, ®->cfg); /* 27MHz clock */ + writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */ + writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */ + + /* Copy data to the SPI direct mapped window */ + memcpy(dst, buf, len); + + /* Restore original register values */ + writel(control_reg, ®->ctrl); + writel(config_reg, ®->cfg); + + return 0; +} + +/* Returns the state of CONF_DONE Pin */ +static int fpga_done_fn(int cookie) +{ + int gpio_done = COOKIE2DONE(cookie); + unsigned long ts; + + debug("%s (%d): cookie=%08x gpio_done=%d\n", + __func__, __LINE__, cookie, gpio_done); + + ts = get_timer(0); + do { + if (gpio_get_value(gpio_done)) + return 0; + } while (get_timer(ts) < 1000); + + /* timeout so return error */ + return -ENODEV; +} + +static altera_board_specific_func stratixv_fns = { + .pre = fpga_pre_fn, + .config = fpga_config_fn, + .write = fpga_write_fn, + .done = fpga_done_fn, +}; + +static Altera_desc altera_fpga[] = { + { + /* Family */ + Altera_StratixV, + /* Interface type */ + passive_serial, + /* No limitation as additional data will be ignored */ + -1, + /* Device function table */ + (void *)&stratixv_fns, + /* Base interface address specified in driver */ + NULL, + /* Cookie implementation */ + /* + * In this 32bit word the following information is coded: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin + */ + FPGA_COOKIE(0, 1, 26, 7) + }, + { + /* Family */ + Altera_StratixV, + /* Interface type */ + passive_serial, + /* No limitation as additional data will be ignored */ + -1, + /* Device function table */ + (void *)&stratixv_fns, + /* Base interface address specified in driver */ + NULL, + /* Cookie implementation */ + /* + * In this 32bit word the following information is coded: + * Bit 31 ... Bit 0 + * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin + */ + FPGA_COOKIE(1, 2, 29, 9) + }, +}; + +/* Add device descriptor to FPGA device table */ +void board_fpga_add(void) +{ + int i; + + fpga_init(); + for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) + fpga_add(fpga_altera, &altera_fpga[i]); +} diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 0e23265..c1db289 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -5,18 +5,28 @@ */ #include <common.h> +#include <i2c.h> +#include <pci.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <linux/crc8.h> +#include <linux/mbus.h> #ifdef CONFIG_NET #include <netdev.h> #endif +#include "theadorable.h" #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" DECLARE_GLOBAL_DATA_PTR; +#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800) +#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \ + (MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8) + #define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780 #define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0 #define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0)) @@ -25,6 +35,15 @@ DECLARE_GLOBAL_DATA_PTR; #define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c #define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000 +#define GPIO_USB0_PWR_ON 18 +#define GPIO_USB1_PWR_ON 19 + +#define PEX_SWITCH_NOT_FOUNT_LIMIT 3 + +#define STM_I2C_BUS 1 +#define STM_I2C_ADDR 0x27 +#define REBOOT_DELAY 1000 /* reboot-delay in ms */ + /* DDR3 static configuration */ static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = { {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */ @@ -133,15 +152,48 @@ int board_early_init_f(void) int board_init(void) { + int ret; + /* adress of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + /* + * Map SPI devices via MBUS so that they can be accessed via + * the SPI direct access mode + */ + mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1); + mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2); + + /* + * Set RX Channel Control 0 Register: + * Tests have shown, that setting the LPF_COEF from 0 (1/8) + * to 3 (1/1) results in a more stable USB connection. + */ + setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc); + setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc); + setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc); + + /* Toggle USB power */ + ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON"); + if (ret < 0) + return ret; + gpio_direction_output(GPIO_USB0_PWR_ON, 0); + ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON"); + if (ret < 0) + return ret; + gpio_direction_output(GPIO_USB1_PWR_ON, 0); + mdelay(1); + gpio_set_value(GPIO_USB0_PWR_ON, 1); + gpio_set_value(GPIO_USB1_PWR_ON, 1); + return 0; } int checkboard(void) { - puts("Board: theadorable\n"); + board_fpga_add(); return 0; } @@ -169,3 +221,63 @@ int board_video_init(void) return mvebu_lcd_register_init(&lcd_info); } + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + pci_dev_t bdf; + ulong bootcount; + + /* + * Check if the PEX switch is detected (somtimes its not available + * on the PCIe bus). In this case, try to recover by issuing a + * soft-reset or even a power-cycle, depending on the bootcounter + * value. + */ + bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0); + if (bdf == -1) { + u8 i2c_buf[8]; + int ret; + + /* PEX switch not found! */ + bootcount = bootcount_load(); + printf("Failed to find PLX PEX-switch (bootcount=%ld)\n", + bootcount); + if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) { + printf("Issuing power-switch via uC!\n"); + + printf("Issuing power-switch via uC!\n"); + i2c_set_bus_num(STM_I2C_BUS); + i2c_buf[0] = STM_I2C_ADDR << 1; + i2c_buf[1] = 0xc5; /* cmd */ + i2c_buf[2] = 0x01; /* enable */ + /* Delay before reboot */ + i2c_buf[3] = REBOOT_DELAY & 0x00ff; + i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8; + /* Delay before shutdown */ + i2c_buf[5] = 0x00; + i2c_buf[6] = 0x00; + i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7); + + ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7); + if (ret) { + printf("I2C write error (ret=%d)\n", ret); + printf("Issuing soft-reset...\n"); + /* default handling: SOFT reset */ + do_reset(NULL, 0, 0, NULL); + } + + /* Wait for power-cycle to occur... */ + printf("Waiting for power-cycle via uC...\n"); + while (1) + ; + } else { + printf("Issuing soft-reset...\n"); + /* default handling: SOFT reset */ + do_reset(NULL, 0, 0, NULL); + } + } + + return 0; +} +#endif diff --git a/board/theadorable/theadorable.h b/board/theadorable/theadorable.h new file mode 100644 index 0000000..89fe117 --- /dev/null +++ b/board/theadorable/theadorable.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Base addresses for the SPI direct access mode */ +#define SPI_BUS0_DEV1_BASE 0xe0000000 +#define SPI_BUS0_DEV1_SIZE (1 << 20) +#define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE) + +void board_fpga_add(void); diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 67191af..a5f02e6 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -324,7 +324,6 @@ int board_init(void) int board_late_init(void) { - init_sata(0); setup_board_eeprom_env(); /* @@ -537,12 +536,39 @@ static struct cpsw_platform_data cpsw_data = { .version = CPSW_CTRL_VERSION_2, }; +static u64 mac_to_u64(u8 mac[6]) +{ + int i; + u64 addr = 0; + + for (i = 0; i < 6; i++) { + addr <<= 8; + addr |= mac[i]; + } + + return addr; +} + +static void u64_to_mac(u64 addr, u8 mac[6]) +{ + mac[5] = addr; + mac[4] = addr >> 8; + mac[3] = addr >> 16; + mac[2] = addr >> 24; + mac[1] = addr >> 32; + mac[0] = addr >> 40; +} + int board_eth_init(bd_t *bis) { int ret; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; + int i; + u64 mac1, mac2; + u8 mac_addr1[6], mac_addr2[6]; + int num_macs; /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); @@ -583,6 +609,32 @@ int board_eth_init(bd_t *bis) if (ret < 0) printf("Error %d registering CPSW switch\n", ret); + /* + * Export any Ethernet MAC addresses from EEPROM. + * On AM57xx the 2 MAC addresses define the address range + */ + board_ti_get_eth_mac_addr(0, mac_addr1); + board_ti_get_eth_mac_addr(1, mac_addr2); + + if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { + mac1 = mac_to_u64(mac_addr1); + mac2 = mac_to_u64(mac_addr2); + + /* must contain an address range */ + num_macs = mac2 - mac1 + 1; + /* <= 50 to protect against user programming error */ + if (num_macs > 0 && num_macs <= 50) { + for (i = 0; i < num_macs; i++) { + u64_to_mac(mac1 + i, mac_addr); + if (is_valid_ethaddr(mac_addr)) { + eth_setenv_enetaddr_by_index("eth", + i + 2, + mac_addr); + } + } + } + } + return ret; } #endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 4e45abf..9bd71d8 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -27,13 +27,17 @@ #include <dwc3-uboot.h> #include <dwc3-omap-uboot.h> #include <ti-usb-phy-uboot.h> +#include <miiphy.h> #include "mux_data.h" #include "../common/board_detect.h" #define board_is_dra74x_evm() board_ti_is("5777xCPU") +#define board_is_dra72x_evm() board_ti_is("DRA72x-T") #define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ (strncmp("H", board_ti_get_rev(), 1) <= 0) +#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \ + (strncmp("C", board_ti_get_rev(), 1) <= 0) #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ board_ti_get_emif2_size() @@ -127,6 +131,31 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { .emif_rd_wr_exec_thresh = 0x00000305 }; +const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { + .sdram_config_init = 0x61862BB2, + .sdram_config = 0x61862BB2, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514D, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD1137824, + .sdram_tim2 = 0x30B37FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400E, + .emif_ddr_phy_ctlr_1 = 0x0E24400E, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { .sdram_config_init = 0x61851ab2, .sdram_config = 0x61851ab2, @@ -203,7 +232,11 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) } break; case DRA722_ES1_0: - *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + case DRA722_ES2_0: + if (ram_size < CONFIG_MAX_MEM_MAPPED) + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; + else + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; break; default: *regs = &emif1_ddr3_532_mhz_1cs; @@ -234,6 +267,18 @@ const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { .is_ma_present = 0x1 }; +/* + * DRA722 EVM EMIF1 2GB CONFIGURATION + * EMIF1 4 devices of 512Mb x 8 Micron + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80700100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) { u64 ram_size; @@ -250,8 +295,13 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) *dmm_lisa_regs = &lisa_map_dra7_1536MB; break; case DRA722_ES1_0: + case DRA722_ES2_0: default: - *dmm_lisa_regs = &lisa_map_2G_x_2; + if (ram_size < CONFIG_MAX_MEM_MAPPED) + *dmm_lisa_regs = &lisa_map_2G_x_2; + else + *dmm_lisa_regs = &lisa_map_2G_x_4; + break; } } @@ -324,8 +374,10 @@ void do_board_detect(void) if (board_is_dra74x_evm()) { bname = "DRA74x EVM"; - /* If EEPROM is not populated */ + } else if (board_is_dra72x_evm()) { + bname = "DRA72x EVM"; } else { + /* If EEPROM is not populated */ if (is_dra72x()) bname = "DRA72x EVM"; else @@ -347,16 +399,29 @@ void set_muxconf_regs(void) #ifdef CONFIG_IODELAY_RECALIBRATION void recalibrate_iodelay(void) { - struct pad_conf_entry const *pads; + struct pad_conf_entry const *pads, *delta_pads = NULL; struct iodelay_cfg_entry const *iodelay; - int npads, niodelays; + int npads, niodelays, delta_npads = 0; + int ret; switch (omap_revision()) { case DRA722_ES1_0: - pads = dra72x_core_padconf_array; - npads = ARRAY_SIZE(dra72x_core_padconf_array); - iodelay = dra72_iodelay_cfg_array; - niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array); + case DRA722_ES2_0: + pads = dra72x_core_padconf_array_common; + npads = ARRAY_SIZE(dra72x_core_padconf_array_common); + if (board_is_dra72x_revc_or_later()) { + delta_pads = dra72x_rgmii_padconf_array_revc; + delta_npads = + ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); + iodelay = dra72_iodelay_cfg_array_revc; + niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); + } else { + delta_pads = dra72x_rgmii_padconf_array_revb; + delta_npads = + ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); + iodelay = dra72_iodelay_cfg_array_revb; + niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); + } break; case DRA752_ES1_0: case DRA752_ES1_1: @@ -376,7 +441,24 @@ void recalibrate_iodelay(void) RGMII1_ID_MODE_N_MASK); break; } - __recalibrate_iodelay(pads, npads, iodelay, niodelays); + /* Setup I/O isolation */ + ret = __recalibrate_iodelay_start(); + if (ret) + goto err; + + /* Do the muxing here */ + do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); + + /* Now do the weird minor deltas that should be safe */ + if (delta_npads) + do_set_mux32((*ctrl)->control_padconf_core_base, + delta_pads, delta_npads); + + /* Setup IOdelay configuration */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); +err: + /* Closeup.. remove isolation */ + __recalibrate_iodelay_end(ret); } #endif @@ -598,6 +680,11 @@ int board_eth_init(bd_t *bis) if (*omap_si_rev == DRA722_ES1_0) cpsw_data.active_slave = 1; + if (board_is_dra72x_revc_or_later()) { + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; + } + ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); @@ -614,7 +701,7 @@ static inline void vtt_regulator_enable(void) return; /* Do not enable VTT for DRA722 */ - if (omap_revision() == DRA722_ES1_0) + if (is_dra72x()) return; /* diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 6db11a2..34a05dd 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -12,7 +12,7 @@ #include <asm/arch/mux_dra7xx.h> -const struct pad_conf_entry dra72x_core_padconf_array[] = { +const struct pad_conf_entry dra72x_core_padconf_array_common[] = { {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */ {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */ {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */ @@ -104,37 +104,11 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */ {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */ {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */ - {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ - {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ - {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ - {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ - {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ - {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ - {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ - {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ - {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ - {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ - {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ - {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */ - {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */ - {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */ - {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */ - {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */ - {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */ - {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */ - {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */ - {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */ - {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */ - {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */ - {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */ {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ {GPIO6_14, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_14.i2c3_sda */ {GPIO6_15, (M9 | PIN_INPUT_PULLUP)}, /* gpio6_15.i2c3_scl */ {GPIO6_16, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */ - {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */ {MCASP1_AXR0, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr0.i2c5_sda */ {MCASP1_AXR1, (M10 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.i2c5_scl */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ @@ -160,7 +134,6 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ {MMC1_SDWP, (M14 | PIN_INPUT_SLEW)}, /* mmc1_sdwp.gpio6_28 */ - {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ {SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.spi1_sclk */ {SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.spi1_d1 */ {SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.spi1_d0 */ @@ -188,6 +161,65 @@ const struct pad_conf_entry dra72x_core_padconf_array[] = { {WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */ }; +const struct pad_conf_entry dra72x_rgmii_padconf_array_revb[] = { + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d0.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d1.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d2.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d3.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d4.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d5.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d6.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d7.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d8.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d9.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d10.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d11.rgmii1_rxd0 */ + {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */ + {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */ +}; + +const struct pad_conf_entry dra72x_rgmii_padconf_array_revc[] = { + {VIN2A_FLD0, (M14 | PIN_INPUT)}, /* vin2a_fld0.gpio3_30 */ + {RGMII0_TXC, (M0 | PIN_OUTPUT)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_OUTPUT)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_OUTPUT)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_OUTPUT)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_OUTPUT)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_OUTPUT)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {VIN2A_D12, (M3 | PIN_OUTPUT)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_OUTPUT)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_OUTPUT)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_OUTPUT)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_OUTPUT)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_OUTPUT)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLDOWN)}, /* vin2a_d23.rgmii1_rxd0 */ + {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */ +}; + const struct pad_conf_entry early_padconf[] = { #if (CONFIG_CONS_INDEX == 1) {UART1_RXD, (PIN_INPUT_SLEW | M0)}, /* UART1_RXD */ @@ -201,7 +233,7 @@ const struct pad_conf_entry early_padconf[] = { }; #ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = { +const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revb[] = { {0x6F0, 359, 0}, /* RGMMI0_RXC_IN */ {0x6FC, 129, 1896}, /* RGMMI0_RXCTL_IN */ {0x708, 80, 1391}, /* RGMMI0_RXD0_IN */ @@ -236,6 +268,18 @@ const struct iodelay_cfg_entry dra72_iodelay_cfg_array[] = { {0x188, 0, 0}, /* CFG_GPMC_A18_OUT */ {0x374, 121, 0}, /* CFG_GPMC_CS2_OUT */ }; + +const struct iodelay_cfg_entry dra72_iodelay_cfg_array_revc[] = { + {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */ + {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */ + {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */ + {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */ + {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */ + {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */ + {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */ + {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */ +}; + #endif const struct pad_conf_entry dra74x_core_padconf_array[] = { diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index ca668a7..e16669d 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -7,8 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "board.h" #include <common.h> +#include "board.h" #include <spl.h> #include <exports.h> #include <fdt_support.h> diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index ccb528e..dc5645b 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -13,21 +13,10 @@ #define XILINX_BOARD_NAME microblaze-generic -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - /* Microblaze is microblaze_0 */ #define XILINX_USE_MSR_INSTR 1 #define XILINX_FSL_NUMBER 3 -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 6 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 2f17e97..4c20450 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -98,6 +98,19 @@ int checkboard(void) } #endif +int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ +#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \ + defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) + if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR, + CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, + ethaddr, 6)) + printf("I2C EEPROM MAC address read failed\n"); +#endif + + return 0; +} + int dram_init(void) { int node; diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c index 2c0feca..83daf7b 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c @@ -310,11 +310,11 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -339,39 +339,39 @@ unsigned long ps7_clock_init_data_3_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -667,9 +667,9 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -677,7 +677,7 @@ unsigned long ps7_ddr_init_data_3_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -2020,6 +2020,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -2194,6 +2223,267 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -3063,6 +3353,35 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -3139,6 +3458,64 @@ unsigned long ps7_mio_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -3277,11 +3654,11 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -3329,29 +3706,6 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -3390,24 +3744,50 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -3420,6 +3800,14 @@ unsigned long ps7_peripherals_init_data_3_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -3660,29 +4048,6 @@ unsigned long ps7_post_config_3_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -3759,6 +4124,8 @@ unsigned long ps7_post_config_3_0[] = { /* .. .. FINISH: AFI2 REGISTERS */ /* .. .. START: AFI3 REGISTERS */ /* .. .. FINISH: AFI3 REGISTERS */ + /* .. .. START: AFI2 SECURE REGISTER */ + /* .. .. FINISH: AFI2 SECURE REGISTER */ /* .. FINISH: AFI REGISTERS */ /* .. START: LOCK IT BACK */ /* .. LOCK_KEY = 0X767B */ @@ -4110,11 +4477,11 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -4139,39 +4506,39 @@ unsigned long ps7_clock_init_data_2_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -4491,9 +4858,9 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -4501,7 +4868,7 @@ unsigned long ps7_ddr_init_data_2_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -5981,6 +6348,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -6155,6 +6551,267 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -7024,6 +7681,35 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -7100,6 +7786,64 @@ unsigned long ps7_mio_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -7238,11 +7982,11 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -7296,29 +8040,6 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -7357,24 +8078,50 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -7387,6 +8134,14 @@ unsigned long ps7_peripherals_init_data_2_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -7621,29 +8376,6 @@ unsigned long ps7_post_config_2_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ @@ -8071,11 +8803,11 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. SRCSEL = 0x0 */ /* .. ==> 0XF8000154[5:4] = 0x00000000U */ /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. DIVISOR = 0x14 */ - /* .. ==> 0XF8000154[13:8] = 0x00000014U */ - /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ + /* .. DIVISOR = 0xa */ + /* .. ==> 0XF8000154[13:8] = 0x0000000AU */ + /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ /* .. */ - EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00001402U), + EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U), /* .. .. START: TRACE CLOCK */ /* .. .. FINISH: TRACE CLOCK */ /* .. .. CLKACT = 0x1 */ @@ -8100,39 +8832,39 @@ unsigned long ps7_clock_init_data_1_0[] = { /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U), - /* .. .. SRCSEL = 0x3 */ - /* .. .. ==> 0XF8000180[5:4] = 0x00000003U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000030U */ - /* .. .. DIVISOR0 = 0x6 */ - /* .. .. ==> 0XF8000180[13:8] = 0x00000006U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U */ + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x7 */ + /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100630U), - /* .. .. SRCSEL = 0x2 */ - /* .. .. ==> 0XF8000190[5:4] = 0x00000002U */ - /* .. .. ==> MASK : 0x00000030U VAL : 0x00000020U */ - /* .. .. DIVISOR0 = 0x35 */ - /* .. .. ==> 0XF8000190[13:8] = 0x00000035U */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00003500U */ - /* .. .. DIVISOR1 = 0x2 */ - /* .. .. ==> 0XF8000190[25:20] = 0x00000002U */ - /* .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00203520U), + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U), + /* .. .. SRCSEL = 0x0 */ + /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */ + /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ + /* .. .. DIVISOR0 = 0x5 */ + /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */ + /* .. .. DIVISOR1 = 0x1 */ + /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */ + /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ + /* .. .. */ + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U), /* .. .. SRCSEL = 0x0 */ /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */ /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */ - /* .. .. DIVISOR0 = 0xa */ - /* .. .. ==> 0XF80001A0[13:8] = 0x0000000AU */ - /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */ + /* .. .. DIVISOR0 = 0x14 */ + /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */ + /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */ /* .. .. DIVISOR1 = 0x1 */ /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */ /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */ /* .. .. */ - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00100A00U), + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U), /* .. .. CLK_621_TRUE = 0x1 */ /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -8452,9 +9184,9 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. reg_ddrc_burst_rdwr = 0x4 */ /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */ /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */ - /* .. .. reg_ddrc_pre_cke_x1024 = 0x101 */ - /* .. .. ==> 0XF8006034[13:4] = 0x00000101U */ - /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001010U */ + /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */ + /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */ + /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */ /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */ /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */ /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */ @@ -8462,7 +9194,7 @@ unsigned long ps7_ddr_init_data_1_0[] = { /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */ /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */ /* .. .. */ - EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011014U), + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U), /* .. .. reg_ddrc_force_low_pri_n = 0x0 */ /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */ /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */ @@ -9875,6 +10607,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. FINISH: DDRIOB SETTINGS */ /* .. START: MIO PROGRAMMING */ /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000700[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000700[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000700[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000700[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000700[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000700[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000700[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000700[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000700[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000704[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10049,6 +10810,267 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800071C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800071C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800071C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800071C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800071C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800071C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800071C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF800071C[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800071C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000720[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 1 */ + /* .. ==> 0XF8000720[1:1] = 0x00000001U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000720[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000720[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000720[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 1 */ + /* .. ==> 0XF8000720[8:8] = 0x00000001U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000720[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF8000720[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000720[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000724[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000724[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000724[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000724[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000724[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000724[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000724[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000724[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000724[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000728[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000728[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000728[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000728[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000728[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000728[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000728[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000728[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000728[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800072C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800072C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800072C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800072C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800072C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800072C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800072C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800072C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800072C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000730[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000730[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000730[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000730[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000730[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000730[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000730[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000730[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000730[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000734[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000734[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000734[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000734[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000734[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000734[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000734[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000734[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000734[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF8000738[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF8000738[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF8000738[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF8000738[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF8000738[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF8000738[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF8000738[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF8000738[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF8000738[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF800073C[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF800073C[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF800073C[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF800073C[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF800073C[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF800073C[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 3 */ + /* .. ==> 0XF800073C[11:9] = 0x00000003U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF800073C[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF800073C[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF8000740[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 1 */ @@ -10918,6 +11940,35 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ /* .. */ EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007B8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007B8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007B8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007B8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007B8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007B8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007B8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 1 */ + /* .. ==> 0XF80007B8[12:12] = 0x00000001U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007B8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U), /* .. TRI_ENABLE = 1 */ /* .. ==> 0XF80007BC[0:0] = 0x00000001U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */ @@ -10994,6 +12045,64 @@ unsigned long ps7_mio_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U), /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007C8[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007C8[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007C8[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007C8[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007C8[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007C8[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007C8[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007C8[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007C8[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ + /* .. ==> 0XF80007CC[0:0] = 0x00000000U */ + /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ + /* .. L0_SEL = 0 */ + /* .. ==> 0XF80007CC[1:1] = 0x00000000U */ + /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */ + /* .. L1_SEL = 0 */ + /* .. ==> 0XF80007CC[2:2] = 0x00000000U */ + /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */ + /* .. L2_SEL = 0 */ + /* .. ==> 0XF80007CC[4:3] = 0x00000000U */ + /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */ + /* .. L3_SEL = 0 */ + /* .. ==> 0XF80007CC[7:5] = 0x00000000U */ + /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */ + /* .. Speed = 0 */ + /* .. ==> 0XF80007CC[8:8] = 0x00000000U */ + /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ + /* .. IO_Type = 1 */ + /* .. ==> 0XF80007CC[11:9] = 0x00000001U */ + /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */ + /* .. PULLUP = 0 */ + /* .. ==> 0XF80007CC[12:12] = 0x00000000U */ + /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */ + /* .. DisableRcvr = 0 */ + /* .. ==> 0XF80007CC[13:13] = 0x00000000U */ + /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */ + /* .. */ + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U), + /* .. TRI_ENABLE = 0 */ /* .. ==> 0XF80007D0[0:0] = 0x00000000U */ /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */ /* .. L0_SEL = 0 */ @@ -11132,11 +12241,11 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */ /* .. */ EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U), - /* .. CD = 0x3e */ - /* .. ==> 0XE0001018[15:0] = 0x0000003EU */ - /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU */ + /* .. CD = 0x7c */ + /* .. ==> 0XE0001018[15:0] = 0x0000007CU */ + /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */ /* .. */ - EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000003EU), + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU), /* .. STPBRK = 0x0 */ /* .. ==> 0XE0001000[8:8] = 0x00000000U */ /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */ @@ -11190,29 +12299,6 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. */ EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U), /* .. FINISH: UART REGISTERS */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: QSPI REGISTERS */ /* .. Holdb_dr = 1 */ /* .. ==> 0XE000D000[19:19] = 0x00000001U */ @@ -11251,24 +12337,50 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: DIR MODE BANK 0 */ /* .. .. .. .. FINISH: DIR MODE BANK 0 */ /* .. .. .. .. START: DIR MODE BANK 1 */ + /* .. .. .. .. DIRECTION_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: DIR MODE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */ /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */ + /* .. .. .. .. OP_ENABLE_1 = 0x4000 */ + /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U), /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */ /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */ /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x0 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */ @@ -11281,6 +12393,14 @@ unsigned long ps7_peripherals_init_data_1_0[] = { /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */ /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */ + /* .. .. .. .. MASK_1_LSW = 0xbfff */ + /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */ + /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */ + /* .. .. .. .. DATA_1_LSW = 0x4000 */ + /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */ + /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */ + /* .. .. .. .. */ + EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U), /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */ /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */ /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */ @@ -11515,29 +12635,6 @@ unsigned long ps7_post_config_1_0[] = { /* .. */ EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU), /* .. FINISH: ENABLING LEVEL SHIFTER */ - /* .. START: TPIU WIDTH IN CASE OF EMIO */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0XC5ACCE55 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. .. START: TRACE CURRENT PORT SIZE */ - /* .. .. a = 2 */ - /* .. .. ==> 0XF8803004[31:0] = 0x00000002U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000002U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU, 0x00000002U), - /* .. .. FINISH: TRACE CURRENT PORT SIZE */ - /* .. .. START: TRACE LOCK ACCESS REGISTER */ - /* .. .. a = 0X0 */ - /* .. .. ==> 0XF8803FB0[31:0] = 0x00000000U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU, 0x00000000U), - /* .. .. FINISH: TRACE LOCK ACCESS REGISTER */ - /* .. FINISH: TPIU WIDTH IN CASE OF EMIO */ /* .. START: FPGA RESETS TO 0 */ /* .. reserved_3 = 0 */ /* .. ==> 0XF8000240[31:25] = 0x00000000U */ diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h index 62b8a58..22d9fd9 100644 --- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h +++ b/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h @@ -62,7 +62,7 @@ extern unsigned long *ps7_peripherals_init_data; #define USB0_FREQ 60000000 #define USB1_FREQ 60000000 #define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 +#define UART_FREQ 100000000 #define SPI_FREQ 10000000 #define I2C_FREQ 108333336 #define WDT_FREQ 108333336 @@ -71,9 +71,10 @@ extern unsigned long *ps7_peripherals_init_data; #define PCAP_FREQ 200000000 #define TPIU_FREQ 200000000 #define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 175000000 -#define FPGA2_FREQ 12264151 -#define FPGA3_FREQ 100000000 +#define FPGA1_FREQ 142857132 +#define FPGA2_FREQ 200000000 +#define FPGA3_FREQ 50000000 + /* For delay calculation using global registers*/ #define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index 20ca652..69edbf2 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,7 +1,6 @@ -XILINX_ZYNQMP_EP BOARD +XILINX_ZYNQMP BOARDS M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: board/xilinx/zynqmp/ -F: include/configs/xilinx_zynqmp.h -F: include/configs/xilinx_zynqmp_ep.h -F: configs/xilinx_zynqmp_ep_defconfig +F: include/configs/xilinx_zynqmp* +F: configs/xilinx_zynqmp* diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 44d347e..087578c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -7,6 +7,7 @@ #include <common.h> #include <netdev.h> +#include <sata.h> #include <ahci.h> #include <scsi.h> #include <asm/arch/clk.h> @@ -50,12 +51,133 @@ int board_early_init_r(void) return 0; } +#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int parent_offset = fdt_parent_offset(fdt, nodeoffset); + int address_cells = fdt_address_cells(fdt, parent_offset); + int size_cells = fdt_size_cells(fdt, parent_offset); + char *p = buf; + phys_addr_t val; + phys_size_t vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +/* Up to 64-bit address + 64-bit size */ +static u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + +int dram_init(void) +{ + int node, len; + const void *blob = gd->fdt_blob; + const u32 *cell; + + memset(&tmp, 0, sizeof(tmp)); + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; + } + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); + return -1; + } + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + + return 0; +} +#else int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } +#endif void reset_cpu(ulong addr) { @@ -64,6 +186,9 @@ void reset_cpu(ulong addr) #ifdef CONFIG_SCSI_AHCI_PLAT void scsi_init(void) { +#if defined(CONFIG_SATA_CEVA) + init_sata(0); +#endif ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); scsi_scan(1); } diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig new file mode 100644 index 0000000..c663504 --- /dev/null +++ b/board/zipitz2/Kconfig @@ -0,0 +1,9 @@ +if TARGET_ZIPITZ2 + +config SYS_BOARD + default "zipitz2" + +config SYS_CONFIG_NAME + default "zipitz2" + +endif diff --git a/board/zipitz2/MAINTAINERS b/board/zipitz2/MAINTAINERS new file mode 100644 index 0000000..e027cd3 --- /dev/null +++ b/board/zipitz2/MAINTAINERS @@ -0,0 +1,6 @@ +ZIPITZ2 BOARD +M: Vasily Khoruzhick <anarsoul@gmail.com> +S: Maintained +F: board/zipitz2/ +F: include/configs/zipitz2.h +F: configs/zipitz2_defconfig diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile new file mode 100644 index 0000000..855f6bc --- /dev/null +++ b/board/zipitz2/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (C) 2009 +# Marek Vasut <marek.vasut@gmail.com> +# +# Heavily based on pxa255_idp platform +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := zipitz2.o diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c new file mode 100644 index 0000000..d3ca939 --- /dev/null +++ b/board/zipitz2/zipitz2.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2009 + * Marek Vasut <marek.vasut@gmail.com> + * + * Heavily based on pxa255_idp platform + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <serial.h> +#include <asm/arch/hardware.h> +#include <asm/arch/pxa.h> +#include <asm/arch/regs-mmc.h> +#include <spi.h> +#include <asm/io.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_SPI +void lcd_start(void); +#else +inline void lcd_start(void) {}; +#endif + +/* + * Miscelaneous platform dependent initialisations + */ +int board_init(void) +{ + /* arch number of Z2 */ + gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Enable LCD */ + lcd_start(); + + return 0; +} + +int dram_init(void) +{ + pxa2xx_dram_init(); + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +#ifdef CONFIG_CMD_USB +int board_usb_init(int index, enum usb_init_type init) +{ + /* enable port 2 */ + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} + +void usb_board_stop(void) +{ +} +#endif + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + +#ifdef CONFIG_CMD_SPI + +struct { + unsigned char reg; + unsigned short data; + unsigned char mdelay; +} lcd_data[] = { + { 0x07, 0x0000, 0 }, + { 0x13, 0x0000, 10 }, + { 0x11, 0x3004, 0 }, + { 0x14, 0x200F, 0 }, + { 0x10, 0x1a20, 0 }, + { 0x13, 0x0040, 50 }, + { 0x13, 0x0060, 0 }, + { 0x13, 0x0070, 200 }, + { 0x01, 0x0127, 0 }, + { 0x02, 0x0700, 0 }, + { 0x03, 0x1030, 0 }, + { 0x08, 0x0208, 0 }, + { 0x0B, 0x0620, 0 }, + { 0x0C, 0x0110, 0 }, + { 0x30, 0x0120, 0 }, + { 0x31, 0x0127, 0 }, + { 0x32, 0x0000, 0 }, + { 0x33, 0x0503, 0 }, + { 0x34, 0x0727, 0 }, + { 0x35, 0x0124, 0 }, + { 0x36, 0x0706, 0 }, + { 0x37, 0x0701, 0 }, + { 0x38, 0x0F00, 0 }, + { 0x39, 0x0F00, 0 }, + { 0x40, 0x0000, 0 }, + { 0x41, 0x0000, 0 }, + { 0x42, 0x013f, 0 }, + { 0x43, 0x0000, 0 }, + { 0x44, 0x013f, 0 }, + { 0x45, 0x0000, 0 }, + { 0x46, 0xef00, 0 }, + { 0x47, 0x013f, 0 }, + { 0x48, 0x0000, 0 }, + { 0x07, 0x0015, 30 }, + { 0x07, 0x0017, 0 }, + { 0x20, 0x0000, 0 }, + { 0x21, 0x0000, 0 }, + { 0x22, 0x0000, 0 }, +}; + +void zipitz2_spi_sda(int set) +{ + /* GPIO 13 */ + if (set) + writel((1 << 13), GPSR0); + else + writel((1 << 13), GPCR0); +} + +void zipitz2_spi_scl(int set) +{ + /* GPIO 22 */ + if (set) + writel((1 << 22), GPCR0); + else + writel((1 << 22), GPSR0); +} + +unsigned char zipitz2_spi_read(void) +{ + /* GPIO 40 */ + return !!(readl(GPLR1) & (1 << 8)); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* Always valid */ + return 1; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* GPIO 88 low */ + writel((1 << 24), GPCR2); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* GPIO 88 high */ + writel((1 << 24), GPSR2); +} + +void lcd_start(void) +{ + int i; + unsigned char reg[3] = { 0x74, 0x00, 0 }; + unsigned char data[3] = { 0x76, 0, 0 }; + unsigned char dummy[3] = { 0, 0, 0 }; + + /* PWM2 AF */ + writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); + /* Enable clock to all PWM */ + writel(readl(CKEN) | 0x3, CKEN); + /* Configure PWM2 */ + writel(0x4f, PWM_CTRL2); + writel(0x2ff, PWM_PWDUTY2); + writel(792, PWM_PERVAL2); + + /* Toggle the reset pin to reset the LCD */ + writel((1 << 19), GPSR0); + udelay(100000); + writel((1 << 19), GPCR0); + udelay(20000); + writel((1 << 19), GPSR0); + udelay(20000); + + /* Program the LCD init sequence */ + for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) { + reg[0] = 0x74; + reg[1] = 0x0; + reg[2] = lcd_data[i].reg; + spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + data[0] = 0x76; + data[1] = lcd_data[i].data >> 8; + data[2] = lcd_data[i].data & 0xff; + spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END); + + if (lcd_data[i].mdelay) + udelay(lcd_data[i].mdelay * 1000); + } + + writel((1 << 11), GPSR0); +} +#endif |