5 files changed, 76 insertions, 29 deletions
diff --git a/board/altera/socfpga/MAINTAINERS b/board/altera/socfpga/MAINTAINERS
index 626c0f7..0482581 100644
--- a/board/altera/socfpga/MAINTAINERS
+++ b/board/altera/socfpga/MAINTAINERS
@@ -5,3 +5,8 @@ S:	Maintained
 F:	board/altera/socfpga/
 F:	include/configs/socfpga_cyclone5.h
 F:	configs/socfpga_cyclone5_defconfig
+
+SOCRATES BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	configs/socfpga_socrates_defconfig
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index ce625e5..459d82f 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -12,7 +12,9 @@
 #include <usb/s3c_udc.h>
 #include <usb_mass_storage.h>
 
+#include <micrel.h>
 #include <netdev.h>
+#include <phy.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,6 +46,42 @@ int board_init(void)
 	return 0;
 }
 
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+	int ret;
+	/*
+	 * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+	 * to work reliably on most flavors of cyclone5 boards.
+	 */
+	ret = ksz9021_phy_extended_write(phydev,
+					 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+					 0x0);
+	if (ret)
+		return ret;
+
+	ret = ksz9021_phy_extended_write(phydev,
+					 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+					 0x0);
+	if (ret)
+		return ret;
+
+	ret = ksz9021_phy_extended_write(phydev,
+					 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+					 0xf0f0);
+	if (ret)
+		return ret;
+
+	if (phydev->drv->config)
+		return phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_USB_GADGET
 struct s3c_plat_otg_data socfpga_otg_data = {
 	.regs_otg	= CONFIG_USB_DWC2_REG_ADDR,
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 2c331ee..5aa11b1 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -11,6 +11,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -109,6 +110,19 @@ found:
 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+	/* does not provide HW signals for power management */
+	clrbits_8(cpld_base + 0x17, 0x40);
+	/* Disable MCKE isolation */
+	gpio_set_value(2, 0);
+	udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
 	phys_size_t dram_size;
@@ -124,5 +138,10 @@ phys_size_t initdram(int board_type)
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+	fsl_dp_resume();
+#endif
+
 	return dram_size;
 }
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index e394b12..4e8735b 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -11,7 +11,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
-#include <asm/mpc85xx_gpio.h>
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,8 +64,8 @@ void board_init_f(ulong bootflag)
 
 #ifdef CONFIG_DEEP_SLEEP
 	/* disable the console if boot from deep sleep */
-	if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+	if (is_warm_boot())
+		fsl_dp_disable_console();
 #endif
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("" : : : "memory");
@@ -132,16 +132,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	nand_boot();
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
-	/* does not provide HW signals for power management */
-	clrbits_8(cpld_base + 0x17, 0x40);
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 4734f9d..9cd5e15 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -17,8 +17,7 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
-#include <asm/mpc85xx_gpio.h>
-
+#include "../common/sleep.h"
 #include "t104xrdb.h"
 #include "cpld.h"
 
@@ -44,6 +43,16 @@ int checkboard(void)
 	return 0;
 }
 
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+	if (is_warm_boot())
+		fsl_dp_disable_console();
+#endif
+
+	return 0;
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
@@ -113,14 +122,3 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-	/* does not provide HW signals for power management */
-	CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
-	/* Disable MCKE isolation */
-	gpio_set_value(2, 0);
-	udelay(1);
-}
-#endif