diff options
Diffstat (limited to 'board')
62 files changed, 1356 insertions, 186 deletions
diff --git a/board/Marvell/db-88f6820-gp/README b/board/Marvell/db-88f6820-gp/README new file mode 100644 index 0000000..9bea5b3 --- /dev/null +++ b/board/Marvell/db-88f6820-gp/README @@ -0,0 +1,18 @@ +Update from original Marvell U-Boot to mainline U-Boot: +------------------------------------------------------- + +The resulting image including the SPL binary with the +full DDR setup is "u-boot-spl.kwb". + +To update the SPI NOR flash, please use the following +command: + +=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ +sf update 2000000 0 60000 + +Note that the original Marvell U-Boot seems to have +problems with the "sf update" command. This does not +work reliable. So here this command should be used: + +=> sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ +sf erase 0 60000;sf write 2000000 0 60000 diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index 51ac495..e661fa1 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -11,6 +11,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" + DECLARE_GLOBAL_DATA_PTR; #define BIT(nr) (1UL << (nr)) @@ -54,6 +56,35 @@ static struct marvell_io_exp io_exp[] = { { 0x21, 3, 0xC0 } /* Output Data, register#1 */ }; +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map board_topology_map = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1866L, /* speed_bin */ + BUS_WIDTH_8, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_LOW} }, /* temperature */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + int board_early_init_f(void) { /* Configure MPP */ diff --git a/board/Marvell/db-88f6820-gp/kwbimage.cfg b/board/Marvell/db-88f6820-gp/kwbimage.cfg index e812454..cc05792 100644 --- a/board/Marvell/db-88f6820-gp/kwbimage.cfg +++ b/board/Marvell/db-88f6820-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c index 940a1c2..20eb191 100644 --- a/board/broadcom/bcm28155_ap/bcm28155_ap.c +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c @@ -12,12 +12,20 @@ #include <asm/kona-common/clk.h> #include <asm/arch/sysmap.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <g_dnl.h> + #define SECWATCHDOG_SDOGCR_OFFSET 0x00000000 #define SECWATCHDOG_SDOGCR_EN_SHIFT 27 #define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26 #define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20 #define SECWATCHDOG_SDOGCR_LD_SHIFT 0 +#ifndef CONFIG_USB_SERIALNO +#define CONFIG_USB_SERIALNO "1234567890" +#endif + DECLARE_GLOBAL_DATA_PTR; /* @@ -85,3 +93,35 @@ int board_mmc_init(bd_t *bis) return ret; } #endif + +#ifdef CONFIG_USB_GADGET +static struct s3c_plat_otg_data bcm_otg_data = { + .regs_otg = HSOTG_BASE_ADDR +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("%s: performing s3c_udc_probe\n", __func__); + return s3c_udc_probe(&bcm_otg_data); +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) +{ + debug("%s\n", __func__); + if (!getenv("serial#")) + g_dnl_set_serialnumber(CONFIG_USB_SERIALNO); + return 0; +} + +int g_dnl_get_board_bcd_device_number(int gcnum) +{ + debug("%s\n", __func__); + return 1; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + debug("%s\n", __func__); + return 0; +} +#endif diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index fad0551..6d3b18a 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -82,7 +82,7 @@ static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval) #ifdef CONFIG_SYS_MMC_ENV_PART uint mmc_get_env_part(struct mmc *mmc) { - u32 bootmode = gd->arch.omap_boot_params.omap_bootmode; + u32 bootmode = gd->arch.omap_boot_mode; uint bootpart = CONFIG_SYS_MMC_ENV_PART; /* diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 8148e46..56e4f63 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + +#if !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the * SRAM is at 0xfff00000, it covered the 0xfffff000. @@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#else + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot + * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR, + * and virtual address is CONFIG_SYS_MONITOR_BASE + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000, + CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#endif + #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 5cb7570..29aa778 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -90,7 +90,7 @@ static void show_eeprom(void) /* EEPROM tag ID, either CCID or NXID */ #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - e.version); + be32_to_cpu(e.version)); #else printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif @@ -340,7 +340,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (cmd == 'i') { #ifdef CONFIG_SYS_I2C_EEPROM_NXID memcpy(e.id, "NXID", sizeof(e.id)); - e.version = NXID_VERSION; + e.version = cpu_to_be32(NXID_VERSION); #else memcpy(e.id, "CCID", sizeof(e.id)); #endif @@ -485,7 +485,7 @@ int mac_read_from_eeprom(void) #ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], - e.version); + be32_to_cpu(e.version)); #else printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]); #endif @@ -496,7 +496,7 @@ int mac_read_from_eeprom(void) * that at boot time, U-Boot will still say "NXID v0". */ if (e.version == 0) { - e.version = NXID_VERSION; + e.version = cpu_to_be32(NXID_VERSION); update_crc(); } #endif diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 745847c..73b0553 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -28,3 +28,10 @@ F: configs/P5040DS_NAND_defconfig F: configs/P5040DS_SDCARD_defconfig F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig + +CORENET_DS_SECURE_BOOT BOARD +M: Aneesh Bansal <aneesh.bansal@freescale.com> +S: Maintained +F: configs/P3041DS_NAND_SECURE_BOOT_defconfig +F: configs/P5020DS_NAND_SECURE_BOOT_defconfig +F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 92f613a..ce5cb52 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -209,6 +209,9 @@ int board_early_init_f(void) out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 043d938..8fef8e9 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -368,6 +368,9 @@ int board_early_init_f(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif + /* Configure Little endian for SAI, ASRC and SPDIF */ + out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); + /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A7 core cluster) diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2085a/README index b7023e1..bc1d0bb 100644 --- a/board/freescale/ls2085a/README +++ b/board/freescale/ls2085a/README @@ -14,3 +14,14 @@ Memory map from core's view Other addresses are either reserved, or not used directly by u-boot. This list should be updated when more addresses are used. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index dd0acf2..73c4410 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -80,7 +80,7 @@ unsigned long get_dram_size_to_hide(void) dram_to_hide += mc_get_dram_block_size(); #endif - return dram_to_hide; + return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); } int board_eth_init(bd_t *bis) @@ -127,15 +127,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README index fb3938e..11b2e79 100644 --- a/board/freescale/ls2085aqds/README +++ b/board/freescale/ls2085aqds/README @@ -127,3 +127,22 @@ b) NOR boot c) NAND boot d) SD boot e) QSPI boot + +Environment Variables +--------------------- +- mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined + the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. + +- mcmemsize: MC DRAM block size. If this variable is not defined + the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2085aqds/eth.c index 5ba4770..1f8a31f 100644 --- a/board/freescale/ls2085aqds/eth.c +++ b/board/freescale/ls2085aqds/eth.c @@ -53,7 +53,7 @@ static int riser_phy_addr[] = { #define EMI1_SLOT5 4 #define EMI1_SLOT6 5 #define EMI2 6 -#define SFP_TX 1 +#define SFP_TX 0 static const char * const mdio_names[] = { "LS2085A_QDS_MDIO0", @@ -210,6 +210,7 @@ static void initialize_dpmac_to_slot(void) switch (serdes2_prtcl) { case 0x07: case 0x08: + case 0x49: printf("qds: WRIOP: Supported SerDes Protocol 0x%02x\n", serdes2_prtcl); lane_to_slot_fsm2[0] = EMI1_SLOT4; @@ -247,6 +248,7 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id) switch (serdes2_prtcl) { case 0x07: case 0x08: + case 0x49: lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + (dpmac_id - 9)); slot = lane_to_slot_fsm2[lane]; diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index 6a22122..08906a6 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -17,12 +17,23 @@ #include <environment.h> #include <i2c.h> #include <asm/arch-fsl-lsch3/soc.h> +#include <hwconfig.h> #include "../common/qixis.h" #include "ls2085aqds_qixis.h" +#define PIN_MUX_SEL_SDHC 0x00 +#define PIN_MUX_SEL_DSPI 0x0a + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) + DECLARE_GLOBAL_DATA_PTR; +enum { + MUX_TYPE_SDHC, + MUX_TYPE_DSPI, +}; + unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -49,11 +60,15 @@ int checkboard(void) "100 separate SSCG"}; int clock; + cpu_name(buf); + printf("Board: %s-QDS, ", buf); + sw = QIXIS_READ(arch); - printf("Board: %s, ", CONFIG_IDENT_STRING); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -149,10 +164,47 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int config_board_mux(int ctrl_type) +{ + u8 reg5; + + reg5 = QIXIS_READ(brdcfg[5]); + + switch (ctrl_type) { + case MUX_TYPE_SDHC: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_DSPI: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[5], reg5); + + return 0; +} + int board_init(void) { + char *env_hwconfig; + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; + init_final_memctl_regs(); + val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); + + env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("dspi", env_hwconfig) && + DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) + config_board_mux(MUX_TYPE_DSPI); + else + config_board_mux(MUX_TYPE_SDHC); + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif @@ -211,7 +263,7 @@ unsigned long get_dram_size_to_hide(void) dram_to_hide += mc_get_dram_block_size(); #endif - return dram_to_hide; + return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); } #ifdef CONFIG_FSL_MC_ENET @@ -240,15 +292,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2085ardb/Makefile index 0bfe21c..de383cc 100644 --- a/board/freescale/ls2085ardb/Makefile +++ b/board/freescale/ls2085ardb/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += ls2085ardb.o +obj-y += ls2085ardb.o eth_ls2085rdb.o obj-y += ddr.o diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2085ardb/README index cfd5185..2f18243 100644 --- a/board/freescale/ls2085ardb/README +++ b/board/freescale/ls2085ardb/README @@ -107,3 +107,14 @@ Booting Options --------------- a) NOR boot b) NAND boot + +Booting Linux flavors which do not support 48-bit VA (< Linux 3.18) +------------------------------------------------------------------- +One needs to use appropriate bootargs to boot Linux flavors which do +not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown +below: + +=> setenv bootargs 'console=ttyS1,115200 root=/dev/ram + earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m + hugepages=16 mem=2048M' + diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2085ardb/eth_ls2085rdb.c new file mode 100644 index 0000000..0a1163a --- /dev/null +++ b/board/freescale/ls2085ardb/eth_ls2085rdb.c @@ -0,0 +1,148 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <malloc.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <exports.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <fsl-mc/ldpaa_wriop.h> + +DECLARE_GLOBAL_DATA_PTR; + +int load_firmware_cortina(struct phy_device *phy_dev) +{ + if (phy_dev->drv->config) + return phy_dev->drv->config(phy_dev); + + return 0; +} + +void load_phy_firmware(void) +{ + int i; + u8 phy_addr; + struct phy_device *phy_dev; + struct mii_dev *dev; + phy_interface_t interface; + + /*Initialize and upload firmware for all the PHYs*/ + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) { + interface = wriop_get_enet_if(i); + if (interface == PHY_INTERFACE_MODE_XGMII) { + dev = wriop_get_mdio(i); + phy_addr = wriop_get_phy_address(i); + phy_dev = phy_find_by_mask(dev, 1 << phy_addr, + interface); + if (!phy_dev) { + printf("No phydev for phyaddr %d\n", phy_addr); + continue; + } + + /*Flash firmware for All CS4340 PHYS */ + if (phy_dev->phy_id == PHY_UID_CS4340) + load_firmware_cortina(phy_dev); + } + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FSL_MC_ENET) + int i, interface; + struct memac_mdio_info mdio_info; + struct mii_dev *dev; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1; + struct memac_mdio_controller *reg; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /* Register the EMI 1 */ + fm_memac_mdio_init(bis, &mdio_info); + + reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = reg; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /* Register the EMI 2 */ + fm_memac_mdio_init(bis, &mdio_info); + + switch (srds_s1) { + case 0x2A: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + + break; + default: + printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n", + srds_s1); + break; + } + + for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) { + interface = wriop_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) { + switch (wriop_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(i, dev); + break; + default: + break; + } + } + + /* Load CORTINA CS4340 PHY firmware */ + load_phy_firmware(); + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + return pci_eth_init(bis); +} diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index d05f2bc..5e7997c 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -10,6 +10,7 @@ #include <fsl_ifc.h> #include <fsl_ddr.h> #include <asm/io.h> +#include <hwconfig.h> #include <fdt_support.h> #include <libfdt.h> #include <fsl_debug_server.h> @@ -21,8 +22,17 @@ #include "../common/qixis.h" #include "ls2085ardb_qixis.h" +#define PIN_MUX_SEL_SDHC 0x00 +#define PIN_MUX_SEL_DSPI 0x0a + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) DECLARE_GLOBAL_DATA_PTR; +enum { + MUX_TYPE_SDHC, + MUX_TYPE_DSPI, +}; + unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -44,11 +54,14 @@ unsigned long long get_qixis_addr(void) int checkboard(void) { u8 sw; + char buf[15]; + + cpu_name(buf); + printf("Board: %s-RDB, ", buf); sw = QIXIS_READ(arch); - printf("Board: %s, ", CONFIG_IDENT_STRING); printf("Board Arch: V%d, ", sw >> 4); - printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -109,10 +122,47 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int config_board_mux(int ctrl_type) +{ + u8 reg5; + + reg5 = QIXIS_READ(brdcfg[5]); + + switch (ctrl_type) { + case MUX_TYPE_SDHC: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); + break; + case MUX_TYPE_DSPI: + reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[5], reg5); + + return 0; +} + int board_init(void) { + char *env_hwconfig; + u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; + u32 val; + init_final_memctl_regs(); + val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); + + env_hwconfig = getenv("hwconfig"); + + if (hwconfig_f("dspi", env_hwconfig) && + DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) + config_board_mux(MUX_TYPE_DSPI); + else + config_board_mux(MUX_TYPE_SDHC); + #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif @@ -129,6 +179,14 @@ int board_early_init_f(void) return 0; } +int misc_init_r(void) +{ + if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + + return 0; +} + void detail_board_ddr_info(void) { puts("\nDDR "); @@ -173,20 +231,7 @@ unsigned long get_dram_size_to_hide(void) dram_to_hide += mc_get_dram_block_size(); #endif - return dram_to_hide; -} - -int board_eth_init(bd_t *bis) -{ - int error = 0; - -#ifdef CONFIG_FSL_MC_ENET - error = cpu_eth_init(bis); -#endif - - error = pci_eth_init(bis); - - return error; + return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); } #ifdef CONFIG_FSL_MC_ENET @@ -215,15 +260,18 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { - phys_addr_t base; - phys_size_t size; + u64 base[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; ft_cpu_setup(blob, bd); - /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ - base = getenv_bootm_low(); - size = getenv_bootm_size(); - fdt_fixup_memory(blob, (u64)base, (u64)size); + /* fixup DT for the two GPP DDR banks */ + base[0] = gd->bd->bi_dram[0].start; + size[0] = gd->bd->bi_dram[0].size; + base[1] = gd->bd->bi_dram[1].start; + size[1] = gd->bd->bi_dram[1].size; + + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET fdt_fixup_board_enet(blob); @@ -247,3 +295,22 @@ void qixis_dump_switch(void) printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); } } + +/* + * Board rev C and earlier has duplicated I2C addresses for 2nd controller. + * Both slots has 0x54, resulting 2nd slot unusable. + */ +void update_spd_address(unsigned int ctrl_num, + unsigned int slot, + unsigned int *addr) +{ + u8 sw; + + sw = QIXIS_READ(arch); + if ((sw & 0xf) < 0x3) { + if (ctrl_num == 1 && slot == 0) + *addr = SPD_EEPROM_ADDRESS4; + else if (ctrl_num == 1 && slot == 1) + *addr = SPD_EEPROM_ADDRESS3; + } +} diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 3f47cfb..61b7a91 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -428,8 +428,13 @@ int ft_board_setup(void *blob, bd_t *bd) { phys_addr_t base; phys_size_t size; +#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; + int usb_err, usb1_off, usb2_off; +#endif +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) + int err; +#endif ft_cpu_setup(blob, bd); @@ -473,6 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif +#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC) /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); @@ -488,11 +494,12 @@ int ft_board_setup(void *blob, bd_t *bd) soc_usb_compat); return usb2_off; } - err = fdt_del_node(blob, usb2_off); - if (err < 0) { + usb_err = fdt_del_node(blob, usb2_off); + if (usb_err < 0) { printf("WARNING: could not remove %s\n", soc_usb_compat); - return err; + return usb_err; } +#endif return 0; } diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg index 7b9e9b0..98efca2 100644 --- a/board/freescale/t102xqds/t1024_pbi.cfg +++ b/board/freescale/t102xqds/t1024_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index 922450e..7d3794a 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -70,6 +70,7 @@ Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit +Package: 23x23 19x19 T1024RDB board Overview @@ -192,7 +193,7 @@ Software configurations and board settings on T1024RDB: set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot on T1023RDB: - set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot + set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot Switching between default bank0 and alternate bank4 on NOR flash To change boot source to vbank4: @@ -200,7 +201,7 @@ Software configurations and board settings via software: run command 'cpld reset altbank' in u-boot. via DIP-switch: set SW3[5:7] = '100' on T1023RDB: - via software: run command 'gpio vbank4' in u-boot. + via software: run command 'switch bank4' in u-boot. via DIP-switch: set SW3[5:7] = '100' To change boot source to vbank0: @@ -208,7 +209,7 @@ Software configurations and board settings via software: run command 'cpld reset' in u-boot. via DIP-Switch: set SW3[5:7] = '000' on T1023RDB: - via software: run command 'gpio vbank0' in u-boot. + via software: run command 'switch bank0' in u-boot. via DIP-switch: set SW3[5:7] = '000' 2. NAND Boot: @@ -219,7 +220,7 @@ Software configurations and board settings => tftp 1000000 u-boot-with-spl-pbl.bin => nand erase 0 $filesize => nand write 1000000 0 $filesize - set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot 3. SPI Boot: a. build PBL image for SPI boot @@ -241,11 +242,14 @@ Software configurations and board settings $ make b. program u-boot-with-spl-pbl.bin to SD/MMC card => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x800 + => mmc write 1000000 8 0x7f0 => tftp 1000000 fsl_fman_ucode_t1024_xx.bin => mmc write 1000000 0x820 80 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot + SW3[3] = '1' for SD card(or 'switch sd' by software) + SW3[3] = '0' for eMMC (or 'switch emmc' by software) + 2-stage NAND/SPI/SD boot loader ------------------------------- @@ -292,7 +296,7 @@ Start End Definition Size 0x160000 0x17FFFF FMAN Ucode 128KB -SD Card memory Map on T1024RDB +SD Card memory Map on T102xRDB ---------------------------------------------------- Block #blocks Definition Size 0x008 2048 u-boot img 1MB @@ -313,5 +317,5 @@ Start End Definition Size 0xa00000 0x3FFFFFF rootfs 54MB -For more details, please refer to T1024RDB Reference Manual +For more details, please refer to T1024RDB/T1023RDB User Guide and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index 1a3a996..9c581ff 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -30,6 +30,30 @@ unsigned long get_board_ddr_clk(void) return CONFIG_DDR_CLK_FREQ; } +#if defined(CONFIG_SPL_MMC_BOOT) +#define GPIO1_SD_SEL 0x00020000 +int board_mmc_getcd(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + /* GPIO1_14, 0: eMMC, 1: SD */ + val &= GPIO1_SD_SEL; + + return val ? -1 : 1; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + val &= GPIO1_SD_SEL; + + return val ? -1 : 0; +} +#endif + void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg index fa781d6..1d11a2e 100644 --- a/board/freescale/t102xrdb/t1023_rcw.cfg +++ b/board/freescale/t102xrdb/t1023_rcw.cfg @@ -4,5 +4,5 @@ aa55aa55 010e0100 #Core/DDR: 1400Mhz/1600MT/s with single source clock 0810000e 00000000 00000000 00000000 3b800003 00000012 e8104000 21000000 -00000000 00000000 00000000 00020800 +00000000 00000000 00000000 00022800 00000130 04020200 00000000 00000006 diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg index 7b9e9b0..98efca2 100644 --- a/board/freescale/t102xrdb/t1024_pbi.cfg +++ b/board/freescale/t102xrdb/t1024_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index f971976..fddd240 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -20,6 +20,9 @@ #include "t102xrdb.h" #ifdef CONFIG_T1024RDB #include "cpld.h" +#elif defined(CONFIG_T1023RDB) +#include <i2c.h> +#include <mmc.h> #endif #include "../common/sleep.h" @@ -27,13 +30,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_T1023RDB enum { - GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */ + GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */ GPIO1_EMMC_SEL, - GPIO1_VBANK0, - GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */ - GPIO1_VBANK_MASK = 0x00008a00, - GPIO1_DIR_OUTPUT = 0x00028a00, - GPIO1_GET_VAL, + GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */ + GPIO3_BRD_VER_MASK = 0x0c000000, + GPIO3_OFFSET = 0x2000, + I2C_GET_BANK, + I2C_SET_BANK0, + I2C_SET_BANK4, }; #endif @@ -48,9 +52,11 @@ int checkboard(void) srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; printf("Board: %sRDB, ", cpu->name); -#ifdef CONFIG_T1024RDB +#if defined(CONFIG_T1024RDB) printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); +#elif defined(CONFIG_T1023RDB) + printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B'); #endif printf("boot from "); @@ -73,8 +79,7 @@ int checkboard(void) #ifdef CONFIG_NAND puts("NAND\n"); #else - printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) & - GPIO1_VBANK4) >> 15 ? 4 : 0); + printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK)); #endif #endif @@ -196,64 +201,126 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_board_enet(blob); #endif +#ifdef CONFIG_T1023RDB + if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0) + fdt_enable_nor(blob); +#endif + return 0; } - #ifdef CONFIG_T1023RDB -static u32 t1023rdb_gpio_ctrl(u32 ctrl_type) +/* Enable NOR flash for RevC */ +static void fdt_enable_nor(void *blob) { - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 gpioval; + int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash"); + + if (nodeoff >= 0) + fdt_status_okay(blob, nodeoff); + else + printf("WARNING unable to set status for NOR\n"); +} - setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT); - gpioval = in_be32(&pgpio->gpdat); +int board_mmc_getcd(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + /* GPIO1_14, 0: eMMC, 1: SD/MMC */ + val &= GPIO1_SD_SEL; + + return val ? -1 : 1; +} + +int board_mmc_getwp(struct mmc *mmc) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + u32 val = in_be32(&pgpio->gpdat); + + val &= GPIO1_SD_SEL; + + return val ? -1 : 0; +} + +static u32 t1023rdb_ctrl(u32 ctrl_type) +{ + ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 val, orig_bus = i2c_get_bus_num(); + u8 tmp; switch (ctrl_type) { case GPIO1_SD_SEL: - gpioval |= GPIO1_SD_SEL; + val = in_be32(&pgpio->gpdat); + val |= GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; case GPIO1_EMMC_SEL: - gpioval &= ~GPIO1_SD_SEL; + val = in_be32(&pgpio->gpdat); + val &= ~GPIO1_SD_SEL; + out_be32(&pgpio->gpdat, val); + setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; - case GPIO1_VBANK0: - gpioval &= ~GPIO1_VBANK_MASK; + case GPIO3_GET_VERSION: + pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + + GPIO3_OFFSET); + val = in_be32(&pgpio->gpdat); + val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; + if (val == 0x3) /* GPIO3_4/5 not used on RevB */ + val = 0; + return val; + case I2C_GET_BANK: + i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1); + tmp &= 0x7; + tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2); + i2c_set_bus_num(orig_bus); + return tmp; + case I2C_SET_BANK0: + i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + tmp = 0x0; + i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); + tmp = 0xf8; + i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); + /* asserting HRESET_REQ */ + out_be32(&gur->rstcr, 0x2); break; - case GPIO1_VBANK4: - gpioval &= ~GPIO1_VBANK_MASK; - gpioval |= GPIO1_VBANK4; + case I2C_SET_BANK4: + i2c_set_bus_num(I2C_PCA6408_BUS_NUM); + tmp = 0x1; + i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1); + tmp = 0xf8; + i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1); + out_be32(&gur->rstcr, 0x2); break; - case GPIO1_GET_VAL: - return gpioval; default: break; } - out_be32(&pgpio->gpdat, gpioval); - return 0; } -static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc, +static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return CMD_RET_USAGE; - if (!strcmp(argv[1], "vbank0")) - t1023rdb_gpio_ctrl(GPIO1_VBANK0); - else if (!strcmp(argv[1], "vbank4")) - t1023rdb_gpio_ctrl(GPIO1_VBANK4); + if (!strcmp(argv[1], "bank0")) + t1023rdb_ctrl(I2C_SET_BANK0); + else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank")) + t1023rdb_ctrl(I2C_SET_BANK4); else if (!strcmp(argv[1], "sd")) - t1023rdb_gpio_ctrl(GPIO1_SD_SEL); - else if (!strcmp(argv[1], "EMMC")) - t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL); + t1023rdb_ctrl(GPIO1_SD_SEL); + else if (!strcmp(argv[1], "emmc")) + t1023rdb_ctrl(GPIO1_EMMC_SEL); else return CMD_RET_USAGE; return 0; } U_BOOT_CMD( - gpio, 2, 0, gpio_cmd, - "for vbank0/vbank4/SD/eMMC switch control in runtime", - "command (e.g. gpio vbank4)" + switch, 2, 0, switch_cmd, + "for bank0/bank4/sd/emmc switch control in runtime", + "command (e.g. switch bank4)" ); #endif diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h index 3f5d85a..ae5c60f 100644 --- a/board/freescale/t102xrdb/t102xrdb.h +++ b/board/freescale/t102xrdb/t102xrdb.h @@ -10,6 +10,7 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, bd_t *bd); #ifdef CONFIG_T1023RDB -static u32 t1023rdb_gpio_ctrl(u32 ctrl_type); +static u32 t1023rdb_ctrl(u32 ctrl_type); +static void fdt_enable_nor(void *blob); #endif #endif diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg index 10b1a6d..121b005 100644 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -6,7 +6,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cf0 00000000 diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 13d9be9..7597800 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h F: configs/T1040RDB_defconfig F: configs/T1040RDB_NAND_defconfig F: configs/T1040RDB_SPIFLASH_defconfig +F: configs/T1040D4RDB_defconfig +F: configs/T1040D4RDB_NAND_defconfig +F: configs/T1040D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_defconfig +F: configs/T1042D4RDB_defconfig +F: configs/T1042D4RDB_NAND_defconfig +F: configs/T1042D4RDB_SPIFLASH_defconfig F: configs/T1042RDB_PI_defconfig F: configs/T1042RDB_PI_NAND_defconfig F: configs/T1042RDB_PI_SPIFLASH_defconfig @@ -15,10 +21,14 @@ T1040RDB_SDCARD BOARD #M: - S: Maintained F: configs/T1040RDB_SDCARD_defconfig +F: configs/T1040D4RDB_SDCARD_defconfig +F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD M: Aneesh Bansal <aneesh.bansal@freescale.com> S: Maintained F: configs/T1040RDB_SECURE_BOOT_defconfig +F: configs/T1040D4RDB_SECURE_BOOT_defconfig F: configs/T1042RDB_SECURE_BOOT_defconfig +F: configs/T1042D4RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index ac95b5e..b9d2212 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. (a personality of T1040 SoC). The board is similar to T1040RDB but is designed specially with low power features targeted for Printing Image Market. +The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory and some enhancements + +The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC. +The board is re-designed T1040RDB board with following changes : + - Support of DDR4 memory + - Support for 0x86 serdes protocol which can support following interfaces + - 2 RGMII's on DTSEC4, DTSEC5 + - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3 + Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB ------------------------------------------------------------------------- Board Si Protocol Targeted Market @@ -19,6 +30,8 @@ Board Si Protocol Targeted Market T1040RDB T1040 0x66 Networking T1040RDB T1042 0x86 Networking T1042RDB_PI T1042 0x06 Printing & Imaging +T1040D4RDB T1040 0x66 Networking +T1042D4RDB T1042 0x86 Networking T1040 SoC Overview @@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features: T1040 SoC Personalities ------------------------- - T1022 Personality: T1022 is a reduced personality of T1040 with less core/clusters. @@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB Please note QE Firmware is only valid for T1040RDB -Switch Settings: (ON is 0, OFF is 1) -=============== +Switch Settings for T104xRDB boards: (ON is 0, OFF is 1) +========================================================== +NOR boot SW setting: +SW1: 00010011 +SW2: 10111011 +SW3: 11100001 + NAND boot SW setting: SW1: 10001000 SW2: 00111011 @@ -284,3 +301,67 @@ SD boot SW setting: SW1: 00100000 SW2: 00111011 SW3: 11100001 + +Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1) +============================================================= +NOR boot SW setting: +SW1: 00010011 +SW2: 10111001 +SW3: 11100001 + +NAND boot SW setting: +SW1: 10001000 +SW2: 00111001 +SW3: 11110001 + +SPI boot SW setting: +SW1: 00100010 +SW2: 10111001 +SW3: 11100001 + +SD boot SW setting: +SW1: 00100000 +SW2: 00111001 +SW3: 11100001 + +PBL-based image generation +========================== +Changes only the required register bit in in PBI commands. + +Provides reference code which might needs some +modification as per requirement. +example: +By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file +which needs to be changed for SPI and SD. + +For SD-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 6c027000 01000000 + +2. SD does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 + +For SPI-boot +============== +1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files) + +example: + RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg + +Change +66000002 40000002 ec027000 01000000 +to +66000002 40000002 5c027000 01000000 + +2. SPI does not support flush so remove flush from pbl, make changes in + tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000 + with 0x091380c0 diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c index df0e348..0ce4e47 100644 --- a/board/freescale/t104xrdb/cpld.c +++ b/board/freescale/t104xrdb/cpld.c @@ -69,7 +69,11 @@ static void cpld_dump_regs(void) printf("int_status = 0x%02x\n", CPLD_READ(int_status)); printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status)); printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); +#if defined(CONFIG_T104XD4RDB) + printf("int_mask = 0x%02x\n", CPLD_READ(int_mask)); +#else printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); +#endif printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h index 0da9a01..2fb4105 100644 --- a/board/freescale/t104xrdb/cpld.h +++ b/board/freescale/t104xrdb/cpld.h @@ -21,7 +21,11 @@ struct cpld_data { u8 int_status; /* 0x12 - Interrupt status Register */ u8 flash_ctl_status; /* 0x13 - Flash control and status register */ u8 fan_ctl_status; /* 0x14 - Fan control and status register */ +#if defined(CONFIG_T104XD4RDB) + u8 int_mask; /* 0x15 - Interrupt mask Register */ +#else u8 led_ctl_status; /* 0x15 - LED control and status register */ +#endif u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ u8 boot_override; /* 0x18 - Boot override register */ @@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value); #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) #define CPLD_WRITE(reg, value)\ cpld_write(offsetof(struct cpld_data, reg), value) +#define MISC_CTL_SG_SEL 0x80 +#define MISC_CTL_AURORA_SEL 0x02 diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index e1148e5..cf79d2d 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -75,7 +75,11 @@ found: * Factors to consider for half-strength driver enable: * - number of DIMMs installed */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->half_strength_driver_enable = 1; +#else popts->half_strength_driver_enable = 0; +#endif /* * Write leveling override */ @@ -91,8 +95,14 @@ found: popts->zq_en = 1; /* DHC_EN =1, ODT = 75 Ohm */ +#ifdef CONFIG_SYS_FSL_DDR4 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) | + DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ +#else popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +#endif } #if defined(CONFIG_DEEP_SLEEP) diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index ab1c32d..b9c02f7 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ +#ifdef CONFIG_SYS_FSL_DDR4 + {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, +#elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, @@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = { {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, +#else +#error DDR type not defined +#endif {} }; +#endif + static const struct board_specific_parameters *udimms[] = { udimm0, }; -#endif diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 7581a4cd..71d0457 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis) int idx = i - FM1_DTSEC1; switch (fm_info_get_enet_if(i)) { -#ifdef CONFIG_T1040RDB +#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) case PHY_INTERFACE_MODE_SGMII: - /* T1040RDB only supports SGMII on DTSEC3 */ + /* T1040RDB & T1040D4RDB only supports SGMII on + * DTSEC3 + */ fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_SGMII1_PHY_ADDR); break; @@ -60,6 +62,20 @@ int board_eth_init(bd_t *bis) CONFIG_SYS_SGMII1_PHY_ADDR); break; #endif +#ifdef CONFIG_T1042D4RDB + case PHY_INTERFACE_MODE_SGMII: + /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2 + * & DTSEC3 + */ + if (FM1_DTSEC1 == i) + phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; + if (FM1_DTSEC2 == i) + phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; + if (FM1_DTSEC3 == i) + phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; + fm_info_set_phy_address(i, phy_addr); + break; +#endif case PHY_INTERFACE_MODE_RGMII: if (FM1_DTSEC4 == i) phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg new file mode 100644 index 0000000..c1034b3 --- /dev/null +++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342580f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg new file mode 100644 index 0000000..9e0ee27 --- /dev/null +++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x86 +0c18000e 0e000000 00000000 00000000 +86000002 40000002 ec027000 01000000 +00000000 00000000 00000000 00030810 +00000000 0342500f 00000000 00000000 diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index b83b9b7..51945b4 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -16,7 +16,7 @@ #Configure CPC1 as 256KB SRAM 09010100 00000000 09010104 fffc0007 -09010f00 08000000 +09010f00 081e000d 09010000 80000000 #Configure LAW for CPC1 09000cd0 00000000 diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 9cd5e15..d982dfc 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -28,17 +28,18 @@ int checkboard(void) struct cpu_type *cpu = gd->arch.cpu; u8 sw; +#ifdef CONFIG_T104XD4RDB + printf("Board: %sD4RDB\n", cpu->name); +#else printf("Board: %sRDB\n", cpu->name); +#endif printf("Board rev: 0x%02x CPLD ver: 0x%02x, ", CPLD_READ(hw_ver), CPLD_READ(sw_ver)); sw = CPLD_READ(flash_ctl_status); sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); - if (sw <= 7) - printf("vBank: %d\n", sw); - else - printf("Unsupported Bank=%x\n", sw); + printf("vBank: %d\n", sw); return 0; } @@ -91,6 +92,34 @@ int board_early_init_r(void) int misc_init_r(void) { + ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; + + printf("SERDES Reference : 0x%X\n", srds_s1); + + /* select SGMII*/ + if (srds_s1 == 0x86) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL); + + /* select SGMII and Aurora*/ + if (srds_s1 == 0x8E) + CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) | + MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL); + +#if defined(CONFIG_T1040D4RDB) + /* Mask all CPLD interrupt sources, except QSGMII interrupts */ + if (CPLD_READ(sw_ver) < 0x03) { + debug("CPLD SW version 0x%02x doesn't support int_mask\n", + CPLD_READ(sw_ver)); + } else { + CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL & + ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2)); + } +#endif + return 0; } diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c index d5f3812..d563d0d 100644 --- a/board/freescale/t4rdb/cpld.c +++ b/board/freescale/t4rdb/cpld.c @@ -47,14 +47,8 @@ void cpld_set_altbank(void) switch (curbank) { case CPLD_SELECT_BANK0: - altbank = CPLD_SELECT_BANK4; - CPLD_WRITE(vbank, altbank); - override = CPLD_READ(software_on); - CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); - CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET); - break; case CPLD_SELECT_BANK4: - altbank = CPLD_SELECT_BANK0; + altbank = CPLD_SELECT_BANK4; CPLD_WRITE(vbank, altbank); override = CPLD_READ(software_on); CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN); diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index 2fbb90c..119ba4c 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -11,8 +11,8 @@ #include <asm/arch/soc.h> #include <linux/mbus.h> -#include "../drivers/ddr/mvebu/ddr3_hw_training.h" -#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h" +#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" +#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index 9c5fbaa..9c838ba 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -234,8 +234,8 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), - PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), - PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT), @@ -257,7 +257,7 @@ static const struct pmux_pingrp_config nyan_big_pingrps[] = { PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT), PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT), - PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT), + PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT), PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT), diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig new file mode 100644 index 0000000..7bc4874 --- /dev/null +++ b/board/nvidia/p2571/Kconfig @@ -0,0 +1,12 @@ +if TARGET_P2571 + +config SYS_BOARD + default "p2571" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2571" + +endif diff --git a/board/nvidia/p2571/MAINTAINERS b/board/nvidia/p2571/MAINTAINERS new file mode 100644 index 0000000..c165135 --- /dev/null +++ b/board/nvidia/p2571/MAINTAINERS @@ -0,0 +1,6 @@ +P2571 BOARD +M: Tom Warren <twarren@nvidia.com> +S: Maintained +F: board/nvidia/p2571/ +F: include/configs/p2571.h +F: configs/p2571_defconfig diff --git a/board/nvidia/p2571/Makefile b/board/nvidia/p2571/Makefile new file mode 100644 index 0000000..223062e --- /dev/null +++ b/board/nvidia/p2571/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2013-2015 +# NVIDIA Corporation <www.nvidia.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += max77620_init.o +obj-y += p2571.o diff --git a/board/nvidia/p2571/max77620_init.c b/board/nvidia/p2571/max77620_init.c new file mode 100644 index 0000000..ed8d4dc --- /dev/null +++ b/board/nvidia/p2571/max77620_init.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/tegra_i2c.h> +#include "max77620_init.h" + +/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */ + +void tegra_i2c_ll_write_addr(uint addr, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(addr, ®->cmd_addr0); + writel(config, ®->cnfg); +} + +void tegra_i2c_ll_write_data(uint data, uint config) +{ + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE; + + writel(data, ®->cmd_data1); + writel(config, ®->cnfg); +} + +void pmic_enable_cpu_vdd(void) +{ + uint reg; + debug("%s entry\n", __func__); + + /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ + debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__); + /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */ + reg = 0x0900 | MAX77620_GPIO5_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */ + debug("%s: Setting GPIO1 to enable HDMI\n", __func__); + reg = 0x0900 | MAX77620_GPIO1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ + reg = 0x1C00 | MAX77620_AME_GPIO; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */ + debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n", + __func__); + /* bit1=0, SD1 remote sense disabled */ + reg = 0x0400 | MAX77620_CNFG2SD_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + /* SD1 output = 1.125V */ + reg = 0x2A00 | MAX77620_SD1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xF200 | MAX77620_CNFG1_L2_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); + + debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__); + /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + reg = 0xCA00 | MAX77620_CNFG1_L1_REG; + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2); + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES); + udelay(10 * 1000); +} diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h new file mode 100644 index 0000000..9d5cce7 --- /dev/null +++ b/board/nvidia/p2571/max77620_init.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MAX77620_INIT_H_ +#define _MAX77620_INIT_H_ + +/* MAX77620-PMIC-specific early init regs */ + +#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */ + +#define MAX77620_SD0_REG 0x16 +#define MAX77620_SD1_REG 0x17 +#define MAX77620_SD2_REG 0x18 +#define MAX77620_SD3_REG 0x19 +#define MAX77620_CNFG2SD_REG 0x22 + +#define MAX77620_CNFG1_L0_REG 0x23 +#define MAX77620_CNFG2_L0_REG 0x24 +#define MAX77620_CNFG1_L1_REG 0x25 +#define MAX77620_CNFG2_L1_REG 0x26 +#define MAX77620_CNFG1_L2_REG 0x27 +#define MAX77620_CNFG2_L2_REG 0x28 +#define MAX77620_CNFG1_L3_REG 0x29 +#define MAX77620_CNFG2_L3_REG 0x2A +#define MAX77620_CNFG1_L4_REG 0x2B +#define MAX77620_CNFG2_L4_REG 0x2C +#define MAX77620_CNFG1_L5_REG 0x2D +#define MAX77620_CNFG2_L5_REG 0x2E +#define MAX77620_CNFG1_L6_REG 0x2F +#define MAX77620_CNFG2_L6_REG 0x30 +#define MAX77620_CNFG1_L7_REG 0x31 +#define MAX77620_CNFG2_L7_REG 0x32 +#define MAX77620_CNFG1_L8_REG 0x33 +#define MAX77620_CNFG2_L8_REG 0x34 +#define MAX77620_CNFG3_LDO_REG 0x35 + +#define MAX77620_GPIO0_REG 0x36 +#define MAX77620_GPIO1_REG 0x37 +#define MAX77620_GPIO2_REG 0x38 +#define MAX77620_GPIO3_REG 0x39 +#define MAX77620_GPIO4_REG 0x3A +#define MAX77620_GPIO5_REG 0x3B +#define MAX77620_GPIO6_REG 0x3C +#define MAX77620_GPIO7_REG 0x3D +#define MAX77620_GPIO_PUE_GPIO 0x3E +#define MAX77620_GPIO_PDE_GPIO 0x3F + +#define MAX77620_AME_GPIO 0x40 +#define MAX77620_REG_ONOFF_CFG1 0x41 +#define MAX77620_REG_ONOFF_CFG2 0x42 + +#define MAX77620_CID0_REG 0x58 +#define MAX77620_CID1_REG 0x59 +#define MAX77620_CID2_REG 0x5A +#define MAX77620_CID3_REG 0x5B +#define MAX77620_CID4_REG 0x5C +#define MAX77620_CID5_REG 0x5D + +#define I2C_SEND_2_BYTES 0x0A02 + +void pmic_enable_cpu_vdd(void); + +#endif /* _MAX77620_INIT_H_ */ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c new file mode 100644 index 0000000..fc710c1 --- /dev/null +++ b/board/nvidia/p2571/p2571.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2013-2015 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include "pinmux-config-p2571.h" + +/* + * Routine: pinmux_init + * Description: Do individual peripheral pinmux configs + */ +void pinmux_init(void) +{ + pinmux_clear_tristate_input_clamping(); + + gpio_config_table(p2571_gpio_inits, + ARRAY_SIZE(p2571_gpio_inits)); + + pinmux_config_pingrp_table(p2571_pingrps, + ARRAY_SIZE(p2571_pingrps)); + + pinmux_config_drvgrp_table(p2571_drvgrps, + ARRAY_SIZE(p2571_drvgrps)); +} diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h new file mode 100644 index 0000000..ac414f0 --- /dev/null +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PINMUX_CONFIG_P2571_H_ +#define _PINMUX_CONFIG_P2571_H_ + +#define GPIO_INIT(_gpio, _init) \ + { \ + .gpio = GPIO_P##_gpio, \ + .init = TEGRA_GPIO_INIT_##_init, \ + } + +static const struct tegra_gpio_config p2571_gpio_inits[] = { + /* gpio, init_val */ + GPIO_INIT(A0, IN), + GPIO_INIT(A5, IN), + GPIO_INIT(D4, IN), + GPIO_INIT(E4, OUT0), + GPIO_INIT(G0, IN), + GPIO_INIT(H0, OUT0), + GPIO_INIT(H2, IN), + GPIO_INIT(H3, OUT0), + GPIO_INIT(H4, OUT0), + GPIO_INIT(H5, IN), + GPIO_INIT(I0, OUT0), + GPIO_INIT(I1, IN), + GPIO_INIT(V1, OUT0), + GPIO_INIT(V6, OUT1), + GPIO_INIT(X4, IN), + GPIO_INIT(X6, IN), + GPIO_INIT(X7, IN), + GPIO_INIT(Y1, IN), + GPIO_INIT(Z0, IN), + GPIO_INIT(Z4, OUT0), + GPIO_INIT(BB2, OUT0), + GPIO_INIT(CC1, IN), + GPIO_INIT(CC3, IN), +}; + +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ + { \ + .pingrp = PMUX_PINGRP_##_pingrp, \ + .func = PMUX_FUNC_##_mux, \ + .pull = PMUX_PULL_##_pull, \ + .tristate = PMUX_TRI_##_tri, \ + .io = PMUX_PIN_##_io, \ + .od = PMUX_PIN_OD_##_od, \ + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \ + .lock = PMUX_PIN_LOCK_DEFAULT, \ + } + +static const struct pmux_pingrp_config p2571_pingrps[] = { + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */ + PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL), + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH), + PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL), + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT), + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT), + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT), +}; + +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ + { \ + .drvgrp = PMUX_DRVGRP_##_drvgrp, \ + .slwf = _slwf, \ + .slwr = _slwr, \ + .drvup = _drvup, \ + .drvdn = _drvdn, \ + .lpmd = PMUX_LPMD_##_lpmd, \ + .schmt = PMUX_SCHMT_##_schmt, \ + .hsm = PMUX_HSM_##_hsm, \ + } + +static const struct pmux_drvgrp_config p2571_drvgrps[] = { +}; + +#endif /* PINMUX_CONFIG_P2571_H */ diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 93347ef..5fb01ce 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -6,7 +6,7 @@ # obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o -obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o +obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c index d81f548..6c869ed 100644 --- a/board/siemens/common/factoryset.c +++ b/board/siemens/common/factoryset.c @@ -144,7 +144,7 @@ int factoryset_read_eeprom(int i2c_addr) unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; unsigned char *cp, *cp1; -#if defined(CONFIG_DFU_FUNCTION) +#if defined(CONFIG_USB_FUNCTION_DFU) factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM; factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM; #endif @@ -202,7 +202,7 @@ int factoryset_read_eeprom(int i2c_addr) cp1 += 3; } -#if defined(CONFIG_DFU_FUNCTION) +#if defined(CONFIG_USB_FUNCTION_DFU) /* read vid and pid for dfu mode */ if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", (uchar *)"vid", buf, diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2dd5d93..f418186 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -285,3 +285,22 @@ int board_init(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char serialno[25]; + uint32_t u_id_low, u_id_mid, u_id_high; + + if (!getenv("serial#")) { + u_id_low = readl(&STM32_U_ID->u_id_low); + u_id_mid = readl(&STM32_U_ID->u_id_mid); + u_id_high = readl(&STM32_U_ID->u_id_high); + sprintf(serialno, "%08x%08x%08x", + u_id_high, u_id_mid, u_id_low); + setenv("serial#", serialno); + } + + return 0; +} +#endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 2a1cd3c..441c880 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -294,6 +294,13 @@ config USB0_VBUS_DET Set the Vbus detect pin for usb0 (otg). This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +config USB0_ID_DET + string "ID detect pin for usb0 (otg)" + default "" + ---help--- + Set the ID detect pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + config USB1_VBUS_PIN string "Vbus enable pin for usb1 (ehci0)" default "PH6" if MACH_SUN4I || MACH_SUN7I diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ed60e74..afed6a3 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -31,7 +31,6 @@ #include <asm/arch/usb_phy.h> #include <asm/gpio.h> #include <asm/io.h> -#include <linux/usb/musb.h> #include <net.h> #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) @@ -294,21 +293,19 @@ int board_mmc_init(bd_t *bis) return -1; #endif -#if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 +#if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 /* - * Both mmc0 and mmc2 are bootable, figure out where we're booting - * from. Try mmc0 first, just like the brom does. + * On systems with an emmc (mmc2), figure out if we are booting from + * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. + * are searched there first. Note we only do this for u-boot proper, + * not for the SPL, see spl_boot_device(). */ - if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && - mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { - buf[12] = 0; - if (strcmp(&buf[4], "eGON.BT0") == 0) - return 0; + if (!sunxi_mmc_has_egon_boot_signature(mmc0) && + sunxi_mmc_has_egon_boot_signature(mmc1)) { + /* Booting from emmc / mmc2, swap */ + mmc0->block_dev.dev = 1; + mmc1->block_dev.dev = 0; } - - /* no bootable card in mmc0, so we must be booting from mmc2, swap */ - mmc0->block_dev.dev = 1; - mmc1->block_dev.dev = 0; #endif return 0; @@ -451,28 +448,6 @@ void sunxi_board_init(void) } #endif -#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) -extern const struct musb_platform_ops sunxi_musb_ops; - -static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, - .num_eps = 6, - .ram_bits = 11, -}; - -static struct musb_hdrc_platform_data musb_plat = { -#if defined(CONFIG_MUSB_HOST) - .mode = MUSB_HOST, -#else - .mode = MUSB_PERIPHERAL, -#endif - .config = &musb_config, - .power = 250, - .platform_ops = &sunxi_musb_ops, -}; -#endif - #ifdef CONFIG_USB_GADGET int g_dnl_board_usb_cable_connected(void) { @@ -535,9 +510,8 @@ int misc_init_r(void) if (ret) return ret; #endif -#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) - musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); -#endif + sunxi_musb_board_init(); + return 0; } #endif diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 149bb51..7d4409b 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -1,6 +1,5 @@ #include <common.h> #include <asm/arch/dram.h> -#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index 596a206..e3fa243 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -2,7 +2,6 @@ #include <common.h> #include <asm/arch/dram.h> -#include <linux/kconfig.h> static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/board/ti/ks2_evm/README b/board/ti/ks2_evm/README index 9ee90a4..6586fab 100644 --- a/board/ti/ks2_evm/README +++ b/board/ti/ks2_evm/README @@ -47,7 +47,6 @@ Board configuration files: include/configs/k2hk_evm.h include/configs/k2e_evm.h include/configs/k2l_evm.h -include/configs/k2l_evm.h As u-boot is migrating to Kconfig there is also board defconfig files configs/k2e_evm_defconfig @@ -71,7 +70,7 @@ Don't forget to add ARCH=arm and CROSS_COMPILE. To build u-boot.bin >make k2hk_evm_defconfig - >make u-boot-spi.gph + >make u-boot.bin To build u-boot-spi.gph >make k2hk_evm_defconfig diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 8892a28..0cefb34 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -48,7 +48,7 @@ int dram_init(void) int board_init(void) { - gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index 20522fb..fd5d6fe 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -25,7 +25,7 @@ ifeq ($(init-objs),) ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),) init-objs := ps7_init_gpl.o $(if $(CONFIG_SPL_BUILD),\ -$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custome_hw_platform/)) +$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/)) endif endif diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig deleted file mode 100644 index b07932e..0000000 --- a/board/xilinx/zynqmp/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_XILINX_ZYNQMP - -config SYS_BOARD - default "zynqmp" - -config SYS_VENDOR - default "xilinx" - -config SYS_SOC - default "zynqmp" - -config SYS_CONFIG_NAME - default "xilinx_zynqmp" - -endif diff --git a/board/xilinx/zynqmp/MAINTAINERS b/board/xilinx/zynqmp/MAINTAINERS index da33340..20ca652 100644 --- a/board/xilinx/zynqmp/MAINTAINERS +++ b/board/xilinx/zynqmp/MAINTAINERS @@ -1,6 +1,7 @@ -XILINX_ZYNQMP BOARD +XILINX_ZYNQMP_EP BOARD M: Michal Simek <michal.simek@xilinx.com> S: Maintained F: board/xilinx/zynqmp/ F: include/configs/xilinx_zynqmp.h -F: configs/xilinx_zynqmp_defconfig +F: include/configs/xilinx_zynqmp_ep.h +F: configs/xilinx_zynqmp_ep_defconfig diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f5ff64d..0c9a814 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -7,6 +7,8 @@ #include <common.h> #include <netdev.h> +#include <ahci.h> +#include <scsi.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> @@ -15,6 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { + printf("EL Level:\tEL%d\n", current_el()); + return 0; } @@ -51,6 +55,39 @@ void reset_cpu(ulong addr) { } +#ifdef CONFIG_SCSI_AHCI_PLAT +void scsi_init(void) +{ + ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); + scsi_scan(1); +} +#endif + +int board_eth_init(bd_t *bis) +{ + u32 ret = 0; + +#if defined(CONFIG_ZYNQ_GEM) +# if defined(CONFIG_ZYNQ_GEM0) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, + CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM1) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, + CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM2) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, + CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); +# endif +# if defined(CONFIG_ZYNQ_GEM3) + ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, + CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); +# endif +#endif + return ret; +} + #ifdef CONFIG_CMD_MMC int board_mmc_init(bd_t *bd) { |