diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/p1_p2_rdb/Kconfig | 12 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/MAINTAINERS | 37 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/Makefile | 30 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/README | 145 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/ddr.c | 221 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/law.c | 17 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/p1_p2_rdb.c | 303 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/pci.c | 27 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/spl.c | 141 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/spl_minimal.c | 84 | ||||
| -rw-r--r-- | board/freescale/p1_p2_rdb/tlb.c | 91 |
11 files changed, 0 insertions, 1108 deletions
diff --git a/board/freescale/p1_p2_rdb/Kconfig b/board/freescale/p1_p2_rdb/Kconfig deleted file mode 100644 index d7ad35d..0000000 --- a/board/freescale/p1_p2_rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P1_P2_RDB - -config SYS_BOARD - default "p1_p2_rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P1_P2_RDB" - -endif diff --git a/board/freescale/p1_p2_rdb/MAINTAINERS b/board/freescale/p1_p2_rdb/MAINTAINERS deleted file mode 100644 index aabf587..0000000 --- a/board/freescale/p1_p2_rdb/MAINTAINERS +++ /dev/null @@ -1,37 +0,0 @@ -P1_P2_RDB BOARD -#M: - -S: Maintained -F: board/freescale/p1_p2_rdb/ -F: include/configs/P1_P2_RDB.h -F: configs/P1011RDB_defconfig -F: configs/P1011RDB_36BIT_defconfig -F: configs/P1011RDB_36BIT_SDCARD_defconfig -F: configs/P1011RDB_36BIT_SPIFLASH_defconfig -F: configs/P1011RDB_NAND_defconfig -F: configs/P1011RDB_SDCARD_defconfig -F: configs/P1011RDB_SPIFLASH_defconfig -F: configs/P1020RDB_defconfig -F: configs/P1020RDB_36BIT_defconfig -F: configs/P1020RDB_36BIT_SDCARD_defconfig -F: configs/P1020RDB_36BIT_SPIFLASH_defconfig -F: configs/P1020RDB_NAND_defconfig -F: configs/P1020RDB_SDCARD_defconfig -F: configs/P1020RDB_SPIFLASH_defconfig -F: configs/P2010RDB_defconfig -F: configs/P2010RDB_36BIT_defconfig -F: configs/P2010RDB_36BIT_SDCARD_defconfig -F: configs/P2010RDB_36BIT_SPIFLASH_defconfig -F: configs/P2010RDB_NAND_defconfig -F: configs/P2010RDB_SDCARD_defconfig -F: configs/P2010RDB_SPIFLASH_defconfig -F: configs/P2020RDB_36BIT_defconfig -F: configs/P2020RDB_36BIT_SDCARD_defconfig -F: configs/P2020RDB_36BIT_SPIFLASH_defconfig -F: configs/P2020RDB_NAND_defconfig -F: configs/P2020RDB_SDCARD_defconfig -F: configs/P2020RDB_SPIFLASH_defconfig - -P2020RDB BOARD -M: Poonam Aggrwal <poonam.aggrwal@freescale.com> -S: Maintained -F: configs/P2020RDB_defconfig diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/p1_p2_rdb/Makefile deleted file mode 100644 index a97bf45..0000000 --- a/board/freescale/p1_p2_rdb/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2009 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-y += p1_p2_rdb.o -obj-$(CONFIG_PCI) += pci.o -endif -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - -endif diff --git a/board/freescale/p1_p2_rdb/README b/board/freescale/p1_p2_rdb/README deleted file mode 100644 index cd66e58..0000000 --- a/board/freescale/p1_p2_rdb/README +++ /dev/null @@ -1,145 +0,0 @@ -Overview --------- -P2020RDB is a Low End Dual core platform supporting the P2020 processor -of QorIQ series. P2020 is an e500 based dual core SOC. - -Building U-boot ------------ -To build the u-boot for P2020RDB: - make P2020RDB_config - make - -NOR Flash Banks ------------ -RDB board for P2020 has two flash banks. They are both present on boot. - -Booting by default is always from the boot bank at 0xef00_0000. - -Memory Map ----------- -0xef00_0000 - 0xef7f_ffff Alternate bank 8MB -0xe800_0000 - 0xefff_ffff Boot bank 8MB - -0xef74_0000 - 0xef7f_ffff Alternate u-boot address 768KB -0xeff4_0000 - 0xefff_ffff Boot u-boot address 768KB - -Switch settings to boot from the NOR flash banks ------------------------------------------------- -SW4[8]=0 default NOR Flash bank -SW4[8]=1 Alternate NOR Flash bank - -Flashing Images ---------------- -To place a new u-boot image in the alternate flash bank and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot.bin - erase ef740000 ef7fffff - cp.b 1000000 ef740000 c0000 - -Now to boot from the alternate bank change the SW4[8] from 0 to 1. - -To program the image in the boot flash bank: - tftp 1000000 u-boot.bin - protect off all - erase eff40000 ffffffff - cp.b 1000000 eff40000 c0000 - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb p2020rdb.dts > p2020rdb.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/p2020rdb.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage.p2020rdb - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 p2020rdb.dtb - bootm 1000000 2000000 c00000 - -Implementing AMP(Asymmetric MultiProcessing) ---------------------------------------------- -1. Build kernel image for core0: - - a. $ make 85xx/p1_p2_rdb_defconfig - - b. $ make menuconfig - - un-select "Processor support"-> - "Symetric multi-processing support" - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 - -2. Build kernel image for core1: - - a. $ make 85xx/p1_p2_rdb_defconfig - - b. $ make menuconfig - - Un-select "Processor support"-> - "Symetric multi-processing support" - - Select "Advanced setup" -> - "Prompt for advanced kernel configuration options" - - Select - "Set physical address where the kernel is loaded" - and set it to 0x20000000, assuming core1 will - start from 512MB. - - Select "Set custom page offset address" - - Select "Set custom kernel base address" - - Select "Set maximum low memory" - - "Exit" and save the selection. - - c. $ make uImage - - d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 - -3. Create dtb for core0: - - $ dtc -I dts -O dtb -f -b 0 - arch/powerpc/boot/dts/p2020rdb_camp_core0.dts > - /tftpboot/p2020rdb_camp_core0.dtb - -4. Create dtb for core1: - - $ dtc -I dts -O dtb -f -b 1 - arch/powerpc/boot/dts/p2020rdb_camp_core1.dts > - /tftpboot/p2020rdb_camp_core1.dtb - -5. Bring up two cores separately: - - a. Power on the board, under u-boot prompt: - => setenv <serverip> - => setenv <ipaddr> - => setenv bootargs root=/dev/ram rw console=ttyS0,115200 - b. Bring up core1's kernel first: - => setenv bootm_low 0x20000000 - => setenv bootm_size 0x10000000 - => tftp 21000000 uImage.core1 - => tftp 22000000 ramdiskfile - => tftp 20c00000 p2020rdb_camp_core1.dtb - => interrupts off - => bootm start 21000000 22000000 20c00000 - => bootm loados - => bootm ramdisk - => bootm fdt - => fdt boardsetup - => fdt chosen $initrd_start $initrd_end - => bootm prep - => cpu 1 release $bootm_low - $fdtaddr - - c. Bring up core0's kernel(on the same u-boot console): - => setenv bootm_low 0 - => setenv bootm_size 0x20000000 - => tftp 1000000 uImage.core0 - => tftp 2000000 ramdiskfile - => tftp c00000 p2020rdb_camp_core0.dtb - => bootm 1000000 2000000 c00000 - -Please note only core0 will run u-boot, core1 starts kernel directly -after "cpu release" command is issued. diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c deleted file mode 100644 index 98ee5f1..0000000 --- a/board/freescale/p1_p2_rdb/ddr.c +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright 2009, 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> -#include <asm/immap_85xx.h> -#include <asm/processor.h> -#include <fsl_ddr_sdram.h> -#include <asm/io.h> -#include <asm/fsl_law.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000000 -#define CONFIG_SYS_DDR_TIMING_5 0x00000000 - -#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322 -#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca -#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_400 0x00480432 -#define CONFIG_SYS_DDR_MODE_2_400 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100 - -#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432 -#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce -#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_533 0x00040642 -#define CONFIG_SYS_DDR_MODE_2_533 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100 - -#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802 -#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543 -#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_667 0x00040852 -#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1 -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00040852 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 - -fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram (void) -{ - fsl_ddr_cfg_regs_t ddr_cfg_regs; - size_t ddr_size; - struct cpu_type *cpu; - ulong ddr_freq, ddr_freq_mhz; - - cpu = gd->arch.cpu; - - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - -#if defined(CONFIG_SYS_RAMBOOT) - return ddr_size; -#endif - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %ld T/s data rate\n", ddr_freq); - - if(ddr_freq_mhz <= 400) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 533) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 667) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs)); - else if(ddr_freq_mhz <= 800) - memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs)); - else - panic("Unsupported DDR data rate %ld T/s\n", ddr_freq); - - /* P1020 and it's derivatives support max 32bit DDR width */ - if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) { - ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; - ddr_cfg_regs.cs[0].bnds = 0x0000001F; - } - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); - return ddr_size; -} diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c deleted file mode 100644 index b60a27f..0000000 --- a/board/freescale/p1_p2_rdb/law.c +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c deleted file mode 100644 index 61ed466..0000000 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/mmu.h> -#include <asm/cache.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <miiphy.h> -#include <libfdt.h> -#include <fdt_support.h> -#include <fsl_mdio.h> -#include <tsec.h> -#include <vsc7385.h> -#include <netdev.h> -#include <rtc.h> -#include <i2c.h> -#include <hwconfig.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define VSC7385_RST_SET 0x00080000 -#define SLIC_RST_SET 0x00040000 -#define SGMII_PHY_RST_SET 0x00020000 -#define PCIE_RST_SET 0x00010000 -#define RGMII_PHY_RST_SET 0x02000000 - -#define USB_RST_CLR 0x04000000 -#define USB2_PORT_OUT_EN 0x01000000 - -#define GPIO_DIR 0x060f0000 - -#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \ - SGMII_PHY_RST_SET | PCIE_RST_SET | \ - RGMII_PHY_RST_SET - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 -#define BOARDREV_C 0x00100000 -#define BOARDREV_D 0x00000000 - -#define SYSCLK_66 66666666 -#define SYSCLK_100 100000000 - -unsigned long get_board_sys_clk(ulong dummy) -{ - volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio; - - val_gpdat = in_be32(&pgpio->gpdat); - sysclk_gpio = val_gpdat & SYSCLK_MASK; - - if(sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - - return 0; -} - -#ifdef CONFIG_MMC -int board_early_init_f (void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | - MPC85xx_PMUXCR_SDHC_WP)); - return 0; -} -#endif - -int checkboard (void) -{ - u32 val_gpdat, board_rev_gpio; - volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - char board_rev = 0; - struct cpu_type *cpu; - - val_gpdat = in_be32(&pgpio->gpdat); - board_rev_gpio = val_gpdat & BOARDREV_MASK; - if (board_rev_gpio == BOARDREV_C) - board_rev = 'C'; - else if (board_rev_gpio == BOARDREV_D) - board_rev = 'D'; - else - panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); - - cpu = gd->arch.cpu; - printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); - - setbits_be32(&pgpio->gpdir, GPIO_DIR); - -/* - * Bringing the following peripherals out of reset via GPIOs - * 0 = reset and 1 = out of reset - * GPIO12 - Reset to Ethernet Switch - * GPIO13 - Reset to SLIC/SLAC devices - * GPIO14 - Reset to SGMII_PHY_N - * GPIO15 - Reset to PCIe slots - * GPIO6 - Reset to RGMII PHY - * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset - */ - clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR; - - setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN); - setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON); -#endif - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - unsigned int orig_bus = i2c_get_bus_num(); - u8 i2c_data; - - i2c_set_bus_num(1); - if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, - 1, &i2c_data, sizeof(i2c_data)) == 0) { - if (i2c_data & 0x2) - puts("NOR Flash Bank : Secondary\n"); - else - puts("NOR Flash Bank : Primary\n"); - - if (i2c_data & 0x1) { - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); - puts("SD/MMC : 8-bit Mode\n"); - puts("eSPI : Disabled\n"); - } else { - puts("SD/MMC : 4-bit Mode\n"); - puts("eSPI : Enabled\n"); - } - } else { - puts("Failed reading I2C Chip 0x18 on bus 1\n"); - } - i2c_set_bus_num(orig_bus); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_16M, 1); - rtc_reset(); - return 0; -} - - -#ifdef CONFIG_TSEC_ENET -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - char *tmp; - unsigned int vscfw_addr; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } -#ifdef CONFIG_VSC7385_ENET -/* If a VSC7385 microcode image is present, then upload it. */ - if ((tmp = getenv ("vscfw_addr")) != NULL) { - vscfw_addr = simple_strtoul (tmp, NULL, 16); - printf("uploading VSC7385 microcode from %x\n", vscfw_addr); - if (vsc7385_upload_firmware((void *) vscfw_addr, - CONFIG_VSC7385_IMAGE_SIZE)) - puts("Failure uploading VSC7385 microcode.\n"); - } else - puts("No address specified for VSC7385 microcode.\n"); -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - - return pci_eth_init(bis); -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -extern void ft_pci_board_setup(void *blob); - -int ft_board_setup(void *blob, bd_t *bd) -{ - const char *soc_usb_compat = "fsl-usb2-dr"; - int err, usb1_off, usb2_off; - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = getenv_bootm_low(); - size = getenv_bootm_size(); - -#if defined(CONFIG_PCI) - ft_pci_board_setup(blob); -#endif /* #if defined(CONFIG_PCI) */ - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#if defined(CONFIG_HAS_FSL_DR_USB) - fdt_fixup_dr_usb(blob, bd); -#endif - -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) - /* Delete eLBC node as it is muxed with USB2 controller */ - if (hwconfig("usb2")) { - const char *soc_elbc_compat = "fsl,p1020-elbc"; - int off = fdt_node_offset_by_compatible(blob, -1, - soc_elbc_compat); - if (off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_elbc_compat); - return off; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s\n", - soc_elbc_compat); - return err; - } - return 0; - } -#endif - /* Delete USB2 node as it is muxed with eLBC */ - usb1_off = fdt_node_offset_by_compatible(blob, -1, - soc_usb_compat); - if (usb1_off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_usb_compat); - return usb1_off; - } - usb2_off = fdt_node_offset_by_compatible(blob, usb1_off, - soc_usb_compat); - if (usb2_off < 0) { - printf("WARNING: could not find compatible node %s\n", - soc_usb_compat); - return usb2_off; - } - err = fdt_del_node(blob, usb2_off); - if (err < 0) { - printf("WARNING: could not remove %s\n", soc_usb_compat); - return err; - } - - return 0; -} - -#endif diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c deleted file mode 100644 index 745ebb1..0000000 --- a/board/freescale/p1_p2_rdb/pci.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <pci.h> -#include <asm/immap_85xx.h> -#include <asm/fsl_serdes.h> -#include <asm/io.h> -#include <asm/fsl_pci.h> -#include <libfdt.h> -#include <fdt_support.h> - -DECLARE_GLOBAL_DATA_PTR; - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void ft_pci_board_setup(void *blob) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/p1_p2_rdb/spl.c b/board/freescale/p1_p2_rdb/spl.c deleted file mode 100644 index f30c5fe..0000000 --- a/board/freescale/p1_p2_rdb/spl.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ns16550.h> -#include <malloc.h> -#include <mmc.h> -#include <nand.h> -#include <i2c.h> -#include <fsl_esdhc.h> -#include <spi_flash.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 - -#define SYSCLK_66 66666666 -#define SYSCLK_100 100000000 - -unsigned long get_board_sys_clk(ulong dummy) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio; - - val_gpdat = in_be32(&pgpio->gpdat); - sysclk_gpio = val_gpdat & SYSCLK_MASK; - - if (sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - - return 0; -} - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - console_init_f(); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - -#ifdef CONFIG_SPL_SPI_BOOT - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - gd->bus_clk = bus_clk; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - bd_t *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; - - probecpu(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(CONFIG_ENV_ADDR); - gd->env_valid = 1; - - gd->ram_size = initdram(0); -#ifdef CONFIG_SPL_NAND_BOOT - puts("Tertiary program loader running in sram..."); -#else - puts("Second program loader running in sram...\n"); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/p1_p2_rdb/spl_minimal.c b/board/freescale/p1_p2_rdb/spl_minimal.c deleted file mode 100644 index 96a4d1c..0000000 --- a/board/freescale/p1_p2_rdb/spl_minimal.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ns16550.h> -#include <asm/io.h> -#include <nand.h> -#include <linux/compiler.h> -#include <asm/fsl_law.h> -#include <fsl_ddr_sdram.h> -#include <asm/global_data.h> - -DECLARE_GLOBAL_DATA_PTR; -#define SYSCLK_MASK 0x00200000 -#define BOARDREV_MASK 0x10100000 - -#define SYSCLK_66 66666666 -#define SYSCLK_100 100000000 - -unsigned long get_board_sys_clk(ulong dummy) -{ - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - u32 val_gpdat, sysclk_gpio; - - val_gpdat = in_be32(&pgpio->gpdat); - sysclk_gpio = val_gpdat & SYSCLK_MASK; - - if (sysclk_gpio == 0) - return SYSCLK_66; - else - return SYSCLK_100; - - return 0; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c deleted file mode 100644 index 73f5729..0000000 --- a/board/freescale/p1_p2_rdb/tlb.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_16M, 1), - -#if defined(CONFIG_PCI) - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - -#endif /* #if defined(CONFIG_PCI) */ -#endif - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), - - /* *I*G - VSC7385 Switch */ - SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_1M, 1), - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1), -#if CONFIG_SYS_L2_SIZE >= (256 << 10) - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1), -#endif -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); |