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-rw-r--r--board/amcc/canyonlands/Makefile2
-rw-r--r--board/amcc/canyonlands/bootstrap.c23
-rw-r--r--board/amcc/canyonlands/canyonlands.c27
-rw-r--r--board/amcc/canyonlands/init.S7
-rw-r--r--board/amcc/canyonlands/u-boot-nand.lds137
5 files changed, 179 insertions, 17 deletions
diff --git a/board/amcc/canyonlands/Makefile b/board/amcc/canyonlands/Makefile
index 02281ae..7a2eaa5 100644
--- a/board/amcc/canyonlands/Makefile
+++ b/board/amcc/canyonlands/Makefile
@@ -34,7 +34,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 3f5822e..37fa1c9 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -28,7 +28,7 @@
#include <asm/io.h>
/*
- * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
+ * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*/
@@ -45,14 +45,14 @@ static char *config_labels[] = {
static u8 boot_configs[][17] = {
{
- (NOR_COMPATIBLE),
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x95, 0x00, 0x00
+ 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
- (NOR_COMPATIBLE),
+ (NAND_COMPATIBLE | NOR_COMPATIBLE),
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
- 0x23, 0x50, 0x0d, 0x95, 0x00, 0x00
+ 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
@@ -61,10 +61,10 @@ static u8 boot_configs[][17] = {
};
/*
- * Bytes 6,8,9,11 change for NAND boot
+ * Bytes 5,6,8,9,11 change for NAND boot
*/
static u8 nand_boot[] = {
- 0xd0, 0xa0, 0x68, 0x58
+ 0x90, 0x01, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -146,10 +146,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
buf = &boot_configs[x][1];
if (b_nand) {
- buf[6] = nand_boot[0];
- buf[8] = nand_boot[1];
- buf[9] = nand_boot[2];
- buf[11] = nand_boot[3];
+ buf[5] = nand_boot[0];
+ buf[6] = nand_boot[1];
+ buf[8] = nand_boot[2];
+ buf[9] = nand_boot[3];
+ buf[11] = nand_boot[4];
}
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 8292d2d..3551429 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -134,6 +134,18 @@ u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
+#if defined(CONFIG_NAND_U_BOOT)
+/*
+ * NAND booting U-Boot version uses a fixed initialization, since the whole
+ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
+ * code.
+ */
+long int initdram(int board_type)
+{
+ return CFG_MBYTES_SDRAM << 20;
+}
+#endif
+
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
@@ -308,14 +320,14 @@ int board_early_init_r (void)
* EBC address which accepts bigger regions:
*
* 0xfc00.0000 -> 4.cc00.0000
- *
- * For this we have to remap the CS0 and re-relocate the envrironment,
- * since the original FLASH location which was needed upon startup is
- * now not correct anymore.
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+#else
mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+#endif
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
@@ -329,6 +341,13 @@ int board_early_init_r (void)
* 0xfc00.0000 is possible
*/
+ /*
+ * Clear potential errors resulting from auto-calibration.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
+
return 0;
}
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 5d48847..b7cac23 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -46,7 +46,12 @@ tlbtab:
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
+#ifndef CONFIG_NAND_SPL
tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+#else
+ tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+#endif
/*
* TLB entries for SDRAM are not needed on this platform.
@@ -78,7 +83,7 @@ tlbtab:
tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for OCM */
- tlbentry(CFG_OCM_BASE, SZ_4K, 0x00040000, 4, AC_R|AC_W|AC_X)
+ tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
/* TLB-entry for Local Configuration registers => peripherals */
tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds
new file mode 100644
index 0000000..12a5dcf
--- /dev/null
+++ b/board/amcc/canyonlands/u-boot-nand.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ /* Align to next NAND block */
+ . = ALIGN(0x4000);
+ common/environment.o (.ppcenv)
+ /* Keep some space here for redundant env and potential bad env blocks */
+ . = ALIGN(0x10000);
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ _end = . ;
+ PROVIDE (end = .);
+}