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-rw-r--r--board/freescale/corenet_ds/corenet_ds.c47
-rw-r--r--board/freescale/corenet_ds/ddr.c18
-rw-r--r--board/freescale/p2020ds/ddr.c4
-rw-r--r--board/ve8313/ve8313.c2
4 files changed, 45 insertions, 26 deletions
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index 3cdefb3..48d95d6 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
#include <netdev.h>
+#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
@@ -120,28 +121,6 @@ int board_early_init_r(void)
set_liodns();
setup_portals();
-#ifdef CONFIG_SRIO1
- if (is_serdes_configured(SRIO1)) {
- set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
- LAW_TRGT_IF_RIO_1);
- } else {
- printf (" SRIO1: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
-#endif
-
-#ifdef CONFIG_SRIO2
- if (is_serdes_configured(SRIO2)) {
- set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
- LAW_TRGT_IF_RIO_2);
- } else {
- printf (" SRIO2: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
-#endif
-
return 0;
}
@@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock)
int misc_init_r(void)
{
serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ __maybe_unused ccsr_gur_t *gur;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw3;
+ gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_SRIO1
+ if (is_serdes_configured(SRIO1)) {
+ set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M,
+ LAW_TRGT_IF_RIO_1);
+ } else {
+ printf (" SRIO1: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO2
+ if (is_serdes_configured(SRIO2)) {
+ set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M,
+ LAW_TRGT_IF_RIO_2);
+ } else {
+ printf (" SRIO2: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */
+#endif
+
/* Warn if the expected SERDES reference clocks don't match the
* actual reference clocks. This needs to be done after calling
* p4080_erratum_serdes8(), since that function may modify the clocks.
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 82b2b4f..18adf2f 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -66,11 +66,19 @@ typedef struct {
* seem reliable, but errors will appear when memory intensive
* program is run. */
/* XXX: Single rank at 800 MHz is OK. */
-const board_specific_parameters_t board_specific_parameters[][20] = {
+const board_specific_parameters_t board_specific_parameters[][30] = {
{
/* memory controller 0 */
/* lo| hi| num| clk| cpo|wrdata|2T */
/* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 4, 6, 7, 3, 0},
+ {334, 400, 4, 6, 9, 3, 0},
+ {401, 549, 4, 6, 11, 3, 0},
+ {550, 680, 4, 1, 10, 5, 0},
+ {681, 850, 4, 1, 12, 5, 0},
+ {851, 1050, 4, 1, 12, 5, 0},
+ {1051, 1250, 4, 1, 15, 4, 0},
+ {1251, 1350, 4, 1, 15, 4, 0},
{ 0, 333, 2, 6, 7, 3, 0},
{334, 400, 2, 6, 9, 3, 0},
{401, 549, 2, 6, 11, 3, 0},
@@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = {
/* memory controller 1 */
/* lo| hi| num| clk| cpo|wrdata|2T */
/* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 4, 6, 7, 3, 0},
+ {334, 400, 4, 6, 9, 3, 0},
+ {401, 549, 4, 6, 11, 3, 0},
+ {550, 680, 4, 1, 10, 5, 0},
+ {681, 850, 4, 1, 12, 5, 0},
+ {851, 1050, 4, 1, 12, 5, 0},
+ {1051, 1250, 4, 1, 15, 4, 0},
+ {1251, 1350, 4, 1, 15, 4, 0},
{ 0, 333, 2, 6, 7, 3, 0},
{334, 400, 2, 6, 9, 3, 0},
{401, 549, 2, 6, 11, 3, 0},
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index 30d640f..9a1b075 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = {
{550, 680, 1, 4, 0x1f, 3, 0},
{681, 850, 1, 4, 0x1f, 4, 0}
#else
- { 0, 850, 2, 4, 0x1f, 4, 0},
+ { 0, 850, 2, 6, 0x1f, 4, 0},
{ 0, 850, 1, 4, 0x1f, 4, 0}
#endif
},
@@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
/* Write leveling override */
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xa;
- popts->wrlvl_start = 0x7;
+ popts->wrlvl_start = 0x8;
/* Rtt and Rtt_WR override */
popts->rtt_override = 1;
popts->rtt_override_value = DDR3_RTT_120_OHM;
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
index 8ba1b19..2272ff0 100644
--- a/board/ve8313/ve8313.c
+++ b/board/ve8313/ve8313.c
@@ -101,7 +101,7 @@ static long fixed_sdram(void)
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile fsl_lbus_t *lbc = &im->lbus;
+ volatile fsl_lbc_t *lbc = &im->im_lbc;
u32 msize;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)