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-rw-r--r--board/AndesTech/adp-ag102/Makefile43
-rw-r--r--board/AndesTech/adp-ag102/adp-ag102.c107
-rw-r--r--board/freescale/common/p_corenet/law.c13
-rw-r--r--board/freescale/common/p_corenet/tlb.c19
-rw-r--r--board/freescale/corenet_ds/corenet_ds.c4
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c7
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c6
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c3
-rw-r--r--board/freescale/p1010rdb/ddr.c6
-rw-r--r--board/freescale/p1010rdb/p1010rdb.c6
-rw-r--r--board/freescale/p1022ds/p1022ds.c8
-rw-r--r--board/freescale/p1023rds/p1023rds.c6
-rw-r--r--board/freescale/p1_p2_rdb/p1_p2_rdb.c4
-rw-r--r--board/freescale/p1_p2_rdb_pc/ddr.c4
-rw-r--r--board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c8
-rw-r--r--board/freescale/p2020ds/p2020ds.c8
-rw-r--r--board/freescale/p2041rdb/p2041rdb.c4
-rw-r--r--board/freescale/p3060qds/p3060qds.c3
18 files changed, 202 insertions, 57 deletions
diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile
new file mode 100644
index 0000000..1cbf2d4
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := adp-ag102.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 0000000..5a25632
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <faraday/ftsdc010.h>
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+ * refer to BOOT_PARAMETER_PA_BASE within
+ * "linux/arch/nds32/include/asm/misc_spec.h"
+ */
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ ftsmc020_init(); /* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ /* should be pci_ftpci100_init() */
+ extern void pci_ftpci_init();
+
+ pci_ftpci_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ ftsdc010_mmc_init(0);
+ return 0;
+}
+#endif
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c
index 09ef561..c4566dd 100644
--- a/board/freescale/common/p_corenet/law.c
+++ b/board/freescale/common/p_corenet/law.c
@@ -48,6 +48,19 @@ struct law_entry law_table[] = {
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
+ SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+ SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
+#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 6a0026a..da21627 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIOBOOT_SLAVE)
+ /*
+ * SRIOBOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -138,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_1M, 1),
#endif
+#ifdef CONFIG_SRIOBOOT_SLAVE
+ /*
+ * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode
+ * and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c
index b1eecc4..a33c936 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -62,10 +62,6 @@ int checkboard (void)
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
-#ifdef CONFIG_PHYS_64BIT
- puts("36-bit Addressing\n");
-#endif
-
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index c9f85c8..6d0bfde 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -68,12 +68,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts("Board: MPC8536DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf ("Sys ID: 0x%02x, "
+ printf("Board: MPC8536DS Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index b20299e..33a02ba 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -45,11 +45,7 @@ int checkboard (void)
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
- puts ("Board: MPC8572DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts ("(36-bit addrmap) ");
-#endif
- printf ("Sys ID: 0x%02x, "
+ printf("Board: MPC8572DS Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 455569e..6a0a3a2 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -50,9 +50,6 @@ int checkboard(void)
else
puts ("Promjet\n");
-#ifdef CONFIG_PHYS_64BIT
- printf (" 36-bit physical address map\n");
-#endif
return 0;
}
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index e5d8423..36c8545 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DDR_RAW_TIMING
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
@@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
-#else /* CONFIG_DDR_RAW_TIMING */
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index b9e66f7..79a6ead 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -165,11 +165,7 @@ int checkboard(void)
struct cpu_type *cpu;
cpu = gd->cpu;
- printf("Board: %sRDB ", cpu->name);
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap)");
-#endif
- puts("\n");
+ printf("Board: %sRDB\n", cpu->name);
return 0;
}
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 456d9b0..aca30f3 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -56,12 +56,8 @@ int checkboard(void)
{
u8 sw;
- puts("Board: P1022DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ printf("Board: P1022DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 546819c..082976a 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -197,6 +197,12 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+ /* By default NOR is on, and NAND is disabled */
+#ifdef CONFIG_NAND_U_BOOT
+ do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
+ do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
+#endif
+
fdt_fixup_fman_ethernet(blob);
}
#endif
diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index cfbae69..437eaf0 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -110,9 +110,7 @@ int checkboard (void)
cpu = gd->cpu;
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
-#ifdef CONFIG_PHYS_64BIT
- puts ("(36-bit addrmap) \n");
-#endif
+
setbits_be32(&pgpio->gpdir, GPIO_DIR);
/*
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index f0cbde7..88ba56f 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
-#ifdef CONFIG_DDR_RAW_TIMING
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_P1021RDB) || \
defined(CONFIG_P1020UTM)
@@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0;
}
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index a60c5a2..aa39260 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -225,13 +225,7 @@ int checkboard(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 in, out, io_config, val;
- printf("Board: %s ", CONFIG_BOARDNAME);
-
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf("CPLD: V%d.%d PCBA: V%d.0\n",
+ printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
in_8(&cpld_data->cpld_rev_major) & 0x0F,
in_8(&cpld_data->cpld_rev_minor) & 0x0F,
in_8(&cpld_data->pcba_rev) & 0x0F);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index d3af6cf..e8d31a4 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -61,12 +61,8 @@ int checkboard(void)
{
u8 sw;
- puts("Board: P2020DS ");
-#ifdef CONFIG_PHYS_64BIT
- puts("(36-bit addrmap) ");
-#endif
-
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ printf("Board: P2020DS Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 1f6a34b..976c8d2 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -54,10 +54,6 @@ int checkboard(void)
sw = CPLD_READ(fbank_sel);
printf("vBank: %d\n", sw & 0x1);
-#ifdef CONFIG_PHYS_64BIT
- puts("36-bit Addressing\n");
-#endif
-
/*
* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c
index c6c74f2..c7cca2a 100644
--- a/board/freescale/p3060qds/p3060qds.c
+++ b/board/freescale/p3060qds/p3060qds.c
@@ -68,9 +68,6 @@ int checkboard(void)
else
printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH);
-#ifdef CONFIG_PHYS_64BIT
- puts("36-bit Addressing\n");
-#endif
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
u32 rcw = in_be32(&gur->rcwsr[i]);
generated by cgit v1.1 at 2024-11-14 21:49:37 +0000