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-rw-r--r--board/delta/delta.c67
-rw-r--r--board/delta/lowlevel_init.S245
-rw-r--r--board/delta/nand.c10
3 files changed, 72 insertions, 250 deletions
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 3ffcc2a..6ef7e2f 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -26,9 +26,13 @@
*/
#include <common.h>
+#include <i2c.h>
+#include <da9030.h>
+#include <asm/arch/pxa-regs.h>
/* ------------------------------------------------------------------------- */
+static void init_DA9030(void);
/*
* Miscelaneous platform dependent initialisations
@@ -54,6 +58,7 @@ int board_late_init(void)
{
setenv("stdout", "serial");
setenv("stderr", "serial");
+ init_DA9030();
return 0;
}
@@ -73,3 +78,65 @@ int dram_init (void)
return 0;
}
+
+/* initialize the DA9030 Power Controller */
+static void init_DA9030()
+{
+ uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+
+ /* setup I2C GPIO's */
+ GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
+ GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
+
+ /* rising Edge on EXTON */
+ GPIO17 = 0x8800;
+ udelay(5);
+ GPIO17 = 0xc800;
+ udelay(100000); /* wait for DA9030 */
+
+ /* reset the watchdog and go active (0xec) */
+ val = (SYS_CONTROL_A_HWRES_ENABLE |
+ (0x6<<4) |
+ SYS_CONTROL_A_WDOG_ACTION |
+ SYS_CONTROL_A_WATCHDOG);
+
+ i2c_reg_write(addr, SYS_CONTROL_A, val);
+
+ i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
+ i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
+ i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
+ i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */
+ i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */
+ i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */
+ i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */
+ i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
+ i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */
+ i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */
+ i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */
+ i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */
+ i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
+ i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */
+ i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
+ i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
+ i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */
+
+ val = i2c_reg_read(addr, STATUS);
+ if(val & STATUS_CHDET)
+ printf("Charger detected, turning on LED.\n");
+ else {
+ printf("No charger detetected.\n");
+ /* undervoltage? print error and power down */
+ }
+}
+
+
+#if 0
+/* reset the DA9030 watchdog */
+void hw_watchdog_reset(void)
+{
+ uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
+ val = i2c_reg_read(addr, SYS_CONTROL_A);
+ val |= SYS_CONTROL_A_WATCHDOG;
+ i2c_reg_write(addr, SYS_CONTROL_A, val);
+}
+#endif
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
index 498cf7f..f059db5 100644
--- a/board/delta/lowlevel_init.S
+++ b/board/delta/lowlevel_init.S
@@ -1,10 +1,5 @@
/*
- * Most of this taken from Redboot hal_platform_setup.h with cleanup
- *
- * NOTE: I haven't clean this up considerably, just enough to get it
- * running. See hal_platform_setup.h for the source. See
- * board/cradle/lowlevel_init.S for another PXA250 setup that is
- * much cleaner.
+ * (C) Copyright 2006 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -31,14 +26,6 @@
DRAM_SIZE: .long CFG_DRAM_SIZE
-/* wait for coprocessor write complete */
-.macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
-.endm
-
-
.macro wait time
ldr r2, =OSCR
mov r3, #0
@@ -49,13 +36,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE
bls 0b
.endm
-/*
- * Memory setup
- */
-
.globl lowlevel_init
lowlevel_init:
- /* Set up GPIO pins first ----------------------------------------- */
+ /* Set up GPIO pins first */
mov r10, lr
/* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
@@ -73,22 +56,7 @@ lowlevel_init:
bic r1, r1, #0x80000000
str r1, [r0]
- /* ---------------------------------------------------------------- */
- /* Enable memory interface */
- /* ---------------------------------------------------------------- */
-
- /* ---------------------------------------------------------------- */
- /* Step 1: Wait for at least 200 microsedonds to allow internal */
- /* clocks to settle. Only necessary after hard reset... */
- /* FIXME: can be optimized later */
- /* ---------------------------------------------------------------- */
-; wait #300
-
mem_init:
-
-#define NEW_SDRAM_INIT 1
-#ifdef NEW_SDRAM_INIT
-
/* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
ldr r0, =ACCR
ldr r1, [r0]
@@ -99,7 +67,7 @@ mem_init:
/* 2. Programm MDCNFG, leaving DMCEN de-asserted */
ldr r0, =MDCNFG
ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
- /* ldr r1, =0x80000403 */
+ /* ldr r1, =0x80000403 */
str r1, [r0]
ldr r1, [r0] /* delay until written */
@@ -140,121 +108,6 @@ mem_init:
orr r1, r1, #MDCNFG_DMCEN
str r1, [r0]
-
-#else /* NEW_SDRAM_INIT */
-
- /* configure the MEMCLKCFG register */
- ldr r1, =MEMCLKCFG
- ldr r2, =0x00010001
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[0] to data flash SRAM mode */
- ldr r1, =CSADRCFG0
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[1] to data flash SRAM mode */
- ldr r1, =CSADRCFG1
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set MSC 0 register for SRAM memory */
- ldr r1, =MSC0
- ldr r2, =0x11191119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[2] to data flash SRAM mode */
- ldr r1, =CSADRCFG2
- ldr r2, =0x00320809
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set CSADRCFG[3] to VLIO mode */
- ldr r1, =CSADRCFG3
- ldr r2, =0x0032080B
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
- /* set MSC 1 register for VLIO memory */
- ldr r1, =MSC1
- ldr r2, =0x123C1119
- str r2, [r1] @ WRITE
- ldr r2, [r1] @ DELAY UNTIL WRITTEN
-
-#if 0
- /* This does not work in Zylonite. -SC */
- ldr r0, =0x15fffff0
- ldr r1, =0xb10b
- str r1, [r0]
- str r1, [r0, #4]
-#endif
-
- /* Configure ACCR Register */
- ldr r0, =ACCR @ ACCR
- ldr r1, =0x0180b108
- str r1, [r0]
- ldr r1, [r0]
-
- /* Configure MDCNFG Register */
- ldr r0, =MDCNFG @ MDCNFG
- ldr r1, =0x403
- str r1, [r0]
- ldr r1, [r0]
-
- /* Perform Resistive Compensation by configuring RCOMP register */
- ldr r1, =RCOMP @ RCOMP
- ldr r2, =0x000000ff
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDMRS Register for SDCS0 */
- ldr r1, =MDMRS @ MDMRS
- ldr r2, =0x60000023
- ldr r3, [r1]
- orr r2, r2, r3
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDMRS Register for SDCS1 */
- ldr r1, =MDMRS @ MDMRS
- ldr r2, =0xa0000023
- ldr r3, [r1]
- orr r2, r2, r3
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure MDREFR */
- ldr r1, =MDREFR @ MDREFR
- ldr r2, =0x00000006
- str r2, [r1]
- ldr r2, [r1]
-
- /* Configure EMPI */
- ldr r1, =EMPI @ EMPI
- ldr r2, =0x80000000
- str r2, [r1]
- ldr r2, [r1]
-
- /* Hardware DDR Read-Strobe Delay Calibration */
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
- wait #5
- ldr r1, [r0]
-
- /* Here we assume the hardware calibration alwasy be successful. -SC */
- /* Set DMCEN bit in MDCNFG Register */
- ldr r0, =MDCNFG @ MDCNFG
- ldr r1, [r0]
- orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
- str r1, [r0]
-
-#endif /* NEW_SDRAM_INIT */
-
#ifndef CFG_SKIP_DRAM_SCRUB
/* scrub/init SDRAM if enabled/present */
ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
@@ -290,96 +143,4 @@ mem_init:
mcr p14,0,r0,c10,c0,0 /* dcsr */
endlowlevel_init:
-
mov pc, lr
-
-
-/*
-@********************************************************************************
-@ DDR calibration
-@
-@ This function is used to calibrate DQS delay lines.
-@ Monahans supports three ways to do it. One is software
-@ calibration. Two is hardware calibration. Three is hybrid
-@ calibration.
-@
-@ TBD
-@ -SC
-ddr_calibration:
-
- @ Case 1: Write the correct delay value once
- @ Configure DDR_SCAL Register
- ldr r0, =DDR_SCAL @ DDR_SCAL
-q ldr r1, =0xaf2f2f2f
- str r1, [r0]
- ldr r1, [r0]
-*/
-/* @ Case 2: Software Calibration
- @ Write test pattern to memory
- ldr r5, =0x0faf0faf @ Data Pattern
- ldr r4, =0xa0000000 @ DDR ram
- str r5, [r4]
-
- mov r1, =0x0 @ delay count
- mov r6, =0x0
- mov r7, =0x0
-ddr_loop1:
- add r1, r1, =0x1
- cmp r1, =0xf
- ble end_loop
- mov r3, r1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
- str r3, [r2]
-
- ldr r2, [r4]
- cmp r2, r5
- bne ddr_loop1
- mov r6, r1
-ddr_loop2:
- add r1, r1, =0x1
- cmp r1, =0xf
- ble end_loop
- mov r3, r1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
- str r3, [r2]
-
- ldr r2, [r4]
- cmp r2, r5
- be ddr_loop2
- mov r7, r2
-
- add r3, r6, r7
- lsr r3, r3, =0x1
- mov r0, r1, lsl #30
- orr r3, r3, r0
- mov r0, r1, lsl #22
- orr r3, r3, r0
- mov r0, r1, lsl #14
- orr r3, r3, r0
- orr r3, r3, =0x80000000
- ldr r2, =DDR_SCAL
-
-end_loop:
-
- @ Case 3: Hardware Calibratoin
- ldr r0, =DDR_HCAL @ DDR_HCAL
- ldr r1, =0x803ffc07 @ the offset is correct? -SC
- str r1, [r0]
- wait #5
- ldr r1, [r0]
- mov pc, lr
-*/
diff --git a/board/delta/nand.c b/board/delta/nand.c
index c4df6e5..5d2cd65 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -293,11 +293,6 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
{
unsigned long ndsr=0, event=0;
- /* mk@tbd set appropriate timeouts */
- /* if (state == FL_ERASING) */
- /* timeo = CFG_HZ * 400; */
- /* else */
- /* timeo = CFG_HZ * 20; */
if(state == FL_WRITING) {
event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
} else if(state == FL_ERASING) {
@@ -563,13 +558,12 @@ void board_nand_init(struct nand_chip *nand)
/* wait 10 us due to cmd buffer clear reset */
- /* wait(10); */
+ /* wait(10); */
nand->hwcontrol = dfc_hwcontrol;
-/* nand->dev_ready = dfc_device_ready; */
+/* nand->dev_ready = dfc_device_ready; */
nand->eccmode = NAND_ECC_SOFT;
- nand->chip_delay = NAND_DELAY_US;
nand->options = NAND_BUSWIDTH_16;
nand->waitfunc = dfc_wait;
nand->read_byte = dfc_read_byte;
generated by cgit v1.1 at 2024-11-23 07:06:29 +0000