diff options
Diffstat (limited to 'board')
141 files changed, 7231 insertions, 2081 deletions
diff --git a/board/AndesTech/adp-ag102/Makefile b/board/AndesTech/adp-ag102/Makefile index ec67dd0..6c18719 100644 --- a/board/AndesTech/adp-ag102/Makefile +++ b/board/AndesTech/adp-ag102/Makefile @@ -9,7 +9,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := adp-ag102.o +COBJS-y := adp-ag102.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) diff --git a/board/esd/canbt/Makefile b/board/Barix/ipam390/Makefile index e5caf23..c84ee05 100644 --- a/board/esd/canbt/Makefile +++ b/board/Barix/ipam390/Makefile @@ -1,29 +1,27 @@ # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# # SPDX-License-Identifier: GPL-2.0+ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o flash.o ../common/misc.o +COBJS += ipam390.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS)) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ######################################################################### - -# defines $(obj).depend target +# This is for $(obj).depend target include $(SRCTREE)/rules.mk sinclude $(obj).depend diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390 new file mode 100644 index 0000000..2d155a3 --- /dev/null +++ b/board/Barix/ipam390/README.ipam390 @@ -0,0 +1,229 @@ +Summary +======= +The README is for the boot procedure on the ipam390 board + +In the context of U-Boot, the board is booted in three stages. The initial +bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits +in the internal ROM. The RBL initializes the internal memory and then +depending on the exact board and pin configurations will initialize another +controller (such as NAND) to continue the boot process by loading +the secondary program loader (SPL). The SPL will initialize the system +further (some clocks, SDRAM). As on this board is used the falcon boot +mode, now 2 ways are possible depending on the GPIO 7_14 input pin, +connected with the "soft reset switch" + +If this pin is logical 1 (high level): +spl code starts the kernel image without delay + +If this pin is logical 0 (low level): +spl code starts the u-boot image + +AIS is an image format defined by TI for the images that are to be loaded +to memory by the RBL. The image is divided into a series of sections and +the image's entry point is specified. Each section comes with meta data +like the target address the section is to be copied to and the size of the +section, which is used by the RBL to load the image. At the end of the +image the RBL jumps to the image entry point. The AIS format allows for +other things such as programming the clocks and SDRAM if the header is +programmed for it. We do not take advantage of this and instead use SPL as +it allows for additional flexibility (run-time detect of board revision, +loading the next image from a different media, etc). + +Compilation +=========== +run "./MAKEALL ipam390" in the u-boot source tree. +Once this build completes you will have a u-boot.ais file that needs to +be written to the nand flash. + +Flashing the images to NAND +========================== +The AIS image can be written to NAND flash using the following commands. +Assuming that the network is configured and enabled and the u-boot.ais file +is tftp'able. + +U-Boot > print upd_uboot +upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} +U-Boot > +U-Boot > run upd_uboot +Using DaVinci-EMAC device +TFTP from server 192.168.1.1; our IP address is 192.168.20.71 +Filename '/tftpboot/ipam390/u-boot.ais'. +Load address: 0xc0000000 +Loading: ################################## + 1.5 MiB/s +done +Bytes transferred = 493716 (78894 hex) + +NAND erase.part: device 0 offset 0x20000, size 0x160000 +Erasing at 0x160000 -- 100% complete. +OK + +NAND write: device 0 offset 0x20000, size 0x78894 + 493716 bytes written: OK +U-Boot > + +Recovery +======== + +In the case of a "bricked" board, you need to use the TI tools found +here[1] to create an uboot-uart-ais.bin file + +- cd to the u-boot source tree + +- compile the u-boot for the ipam390 board: +$ ./MAKEALL ipam390 + + -> Now we shall have u-boot.bin + +- Create u-boot-uart-ais.bin +$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini +ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; + +Note: The ipam390-ais-uart.cfg is found in the board directory +for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg + +- We can now run bootloader on IPAM390 via UART using the command below: + +$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin +NOTE: Do not cancel the command execution! The command takes 20+ seconds +to upload u-boot over serial and run it! +Outcome: +Waiting for the OMAP-L138... +(AIS Parse): Read magic word 0x41504954. +(AIS Parse): Waiting for BOOTME... (power on or reset target now) +(AIS Parse): BOOTME received! +(AIS Parse): Performing Start-Word Sync... +(AIS Parse): Performing Ping Opcode Sync... +(AIS Parse): Processing command 0: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 1: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 2: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 3: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 4: 0x5853590D. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Executing function... +(AIS Parse): Processing command 5: 0x58535901. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Loading section... +(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. +(AIS Parse): Processing command 6: 0x58535906. +(AIS Parse): Performing Opcode Sync... +(AIS Parse): Performing jump and close... +(AIS Parse): AIS complete. Jump to address 0xC1080000. +(AIS Parse): Waiting for DONE... +(AIS Parse): Boot completed successfully. + +Operation completed successfully. + +Falcon Bootmode (boot linux without booting U-Boot) +=================================================== + +The Falcon Mode extends this way allowing to start the Linux kernel directly +from SPL. A new command is added to U-Boot to prepare the parameters that SPL +must pass to the kernel, using ATAGS or Device Tree. + +In normal mode, these parameters are generated each time before +loading the kernel, passing to Linux the address in memory where +the parameters can be read. +With Falcon Mode, this snapshot can be saved into persistent storage and SPL is +informed to load it before running the kernel. + +To boot the kernel, these steps under a Falcon-aware U-Boot are required: + +1. Boot the board into U-Boot. +Use the "spl export" command to generate the kernel parameters area or the DT. +U-Boot runs as when it boots the kernel, but stops before passing the control +to the kernel. + +Here the command sequence for the ipam390 board: +- load the linux kernel image into ram: + +U-Boot > nand read c0100000 2 200000 400000 + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK + +- generate the bootparms image: + +U-Boot > spl export atags c0100000 +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +- copy the bootparms image into nand: + +U-Boot > mtdparts + +device nand0 <davinci_nand.0>, # parts = 6 + #: name size offset mask_flags + 0: u-boot-env 0x00020000 0x00000000 0 + 1: u-boot 0x00160000 0x00020000 0 + 2: bootparms 0x00020000 0x00180000 0 + 3: factory-info 0x00060000 0x001a0000 0 + 4: kernel 0x00400000 0x00200000 0 + 5: rootfs 0x07a00000 0x00600000 0 + +active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 + +defaults: +mtdids : nand0=davinci_nand.0 +mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) +U-Boot > nand erase.part bootparms + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK +U-Boot > nand write c0000100 180000 20000 + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +You can use also the predefined U-Boot Environment variable "setbootparms", +which will do all the above steps in one command: + +U-Boot > print setbootparms +setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 +U-Boot > run setbootparms + +NAND read: device 0 offset 0x200000, size 0x400000 + 4194304 bytes read: OK +## Booting kernel from Legacy Image at c0100000 ... + Image Name: Linux-3.5.1 + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 2504280 Bytes = 2.4 MiB + Load Address: c0008000 + Entry Point: c0008000 + Verifying Checksum ... OK + Loading Kernel Image ... OK +subcommand not supported +subcommand not supported +Argument image is now in RAM at: 0xc0000100 + +NAND erase.part: device 0 offset 0x180000, size 0x20000 +Erasing at 0x180000 -- 100% complete. +OK + +NAND write: device 0 offset 0x180000, size 0x20000 + 131072 bytes written: OK +U-Boot > + +Links +===== +[1] + http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg new file mode 100644 index 0000000..e1a99f2 --- /dev/null +++ b/board/Barix/ipam390/ipam390-ais-uart.cfg @@ -0,0 +1,202 @@ +; General settings that can be overwritten in the host code +; that calls the AISGen library. +[General] + +; Can be 8 or 16 - used in emifa +busWidth=8 + +; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW +BootMode=UART + +; 8,16,24 - used for SPI,I2C +;AddrWidth=8 + +; NO_CRC,SECTION_CRC,SINGLE_CRC +crcCheckType=NO_CRC + +; This section allows setting the PLL0 system clock with a +; specified multiplier and divider as shown. The clock source +; can also be chosen for internal or external. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| +; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| +;[PLL0CONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 + +[PLLANDCLOCKCONFIG] +PLL0CFG0 = 0x00180001 +PLL0CFG1 = 0x00000205 +PERIPHCLKCFG = 0x00000051 + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +[PLL1CONFIG] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 + +; This section lets us configure the peripheral interface +; of the current booting peripheral (I2C, SPI, or UART). +; Use with caution. The format of the PERIPHCLKCFG field +; is as follows: +; SPI: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| +; +; I2C: |------24|------16|-------8|-------0| +; | RSVD |PRESCALE| CLKL | CLKH | +; +; UART: |------24|------16|-------8|-------0| +; | RSVD | OSR | DLH | DLL | +[PERIPHCLKCFG] +PERIPHCLKCFG = 0x00000051 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface. +; See PLL1CONFIG section for the format of the PLL1CFG fields. +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLL1CFG | +; PLL1CFG1: | PLL1CFG | +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +[EMIF3DDR] +PLL1CFG0 = 0x18010001 +PLL1CFG1 = 0x00000002 +DDRPHYC1R = 0x000000C2 +SDCR = 0x0017C432 +SDTIMR = 0x26922A09 +SDTIMR2 = 0x4414C722 +SDRCR = 0x00000498 +CLK2XSRC = 0x00000000 + +; This section can be used to configure the EMIFA to use +; CS0 as an SDRAM interface. The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; SDBCR: | SDBCR | +; SDTIMR: | SDTIMR | +; SDRSRPDEXIT: | SDRSRPDEXIT | +; SDRCR: | SDRCR | +; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | +;[EMIF25SDRAM] +;SDBCR = 0x00004421 +;SDTIMR = 0x42215810 +;SDRSRPDEXIT = 0x00000009 +;SDRCR = 0x00000410 +;DIV4p5_CLK_ENABLE = 0x00000001 + +; This section can be used to configure the async chip selects +; of the EMIFA (CS2-CS5). The fields required to do this +; are given below. +; |------24|------16|-------8|-------0| +; A1CR: | A1CR | +; A2CR: | A2CR | +; A3CR: | A3CR | +; A4CR: | A4CR | +; NANDFCR: | NANDFCR | +;[EMIF25ASYNC] +;A1CR = 0x00000000 +;A2CR = 0x00000000 +;A3CR = 0x00000000 +;A4CR = 0x00000000 +;NANDFCR = 0x00000000 +[EMIF25ASYNC] +A1CR = 0x00000000 +A2CR = 0x3FFFFFFE +A3CR = 0x00000000 +A4CR = 0x00000000 +NANDFCR = 0x00000012 + +; This section should be used in place of PLL0CONFIG when +; the I2C, SPI, or UART modes are being used. This ensures that +; the system PLL and the peripheral's clocks are changed together. +; See PLL0CONFIG section for the format of the PLL0CFG fields. +; See PERIPHCLKCFG section for the format of the CLKCFG field. +; |------24|------16|-------8|-------0| +; PLL0CFG0: | PLL0CFG | +; PLL0CFG1: | PLL0CFG | +; PERIPHCLKCFG: | CLKCFG | +;[PLLANDCLOCKCONFIG] +;PLL0CFG0 = 0x00180001 +;PLL0CFG1 = 0x00000205 +;PERIPHCLKCFG = 0x00010032 + +; This section should be used to setup the power state of modules +; of the two PSCs. This section can be included multiple times to +; allow the configuration of any or all of the device modules. +; |------24|------16|-------8|-------0| +; LPSCCFG: | PSCNUM | MODULE | PD | STATE | +;[PSCCONFIG] +;LPSCCFG= + +; This section allows setting of a single PINMUX register. +; This section can be included multiple times to allow setting +; as many PINMUX registers as needed. +; |------24|------16|-------8|-------0| +; REGNUM: | regNum | +; MASK: | mask | +; VALUE: | value | +;[PINMUX] +;REGNUM = 5 +;MASK = 0x00FF0000 +;VALUE = 0x00880000 + +; No Params required - simply include this section for the fast boot +; function to be called +;[FASTBOOT] + +; This section allows setting up the PLL1. Usually this will +; take place as part of the EMIF3a DDR setup. The format of +; the input args is as follows: +; |------24|------16|-------8|-------0| +; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| +; PLL1CFG1: | RSVD | PLLDIV3| +;[PLL1CONFIG] +;PLL1CFG0 = 0x15010001 +;PLL1CFG1 = 0x00000002 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on ARM-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[ARM_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C2 +;SDCR = 0x0017C432 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x4414C722 +;SDRCR = 0x00000498 +;CLK2XSRC = 0x00000000 + +; This section can be used to configure the PLL1 and the EMIF3a registers +; for starting the DDR2 interface on DSP-boot D800K002 devices. +; |------24|------16|-------8|-------0| +; DDRPHYC1R: | DDRPHYC1R | +; SDCR: | SDCR | +; SDTIMR: | SDTIMR | +; SDTIMR2: | SDTIMR2 | +; SDRCR: | SDRCR | +; CLK2XSRC: | CLK2XSRC | +;[DSP_EMIF3DDR_PATCHFXN] +;DDRPHYC1R = 0x000000C4 +;SDCR = 0x08134632 +;SDTIMR = 0x26922A09 +;SDTIMR2 = 0x0014C722 +;SDRCR = 0x00000492 +;CLK2XSRC = 0x00000000 + +;[INPUTFILE] +;FILENAME=u-boot.bin +;LOADADDRESS=0xC1080000 +;ENTRYPOINTADDRESS=0xC1080000 diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c new file mode 100644 index 0000000..f3f276e --- /dev/null +++ b/board/Barix/ipam390/ipam390.c @@ -0,0 +1,348 @@ +/* + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * Based on: + * U-Boot:board/davinci/da8xxevm/da850evm.c + * + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <net.h> +#include <netdev.h> +#include <spi.h> +#include <spi_flash.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/io.h> +#include <asm/arch/davinci_misc.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <hwconfig.h> +#include <bootstage.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_DRIVER_TI_EMAC +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII +#define HAS_RMII 1 +#else +#define HAS_RMII 0 +#endif +#endif /* CONFIG_DRIVER_TI_EMAC */ + +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) * 10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + return 0; +} + +static const struct pinmux_config gpio_pins[] = { + /* GP7[14] selects bootmode*/ + { pinmux(16), 8, 3 }, /* GP7[14] */ +}; + +const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(uart0_pins_txrx), + PINMUX_ITEM(uart0_pins_rtscts), +#ifdef CONFIG_NAND_DAVINCI + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_nand), +#endif + PINMUX_ITEM(gpio_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ + { DAVINCI_LPSC_EMAC }, /* image download */ + { DAVINCI_LPSC_UART2 }, /* console */ + { DAVINCI_LPSC_UART0 }, /* console */ + { DAVINCI_LPSC_GPIO }, +}; + +const int lpsc_size = ARRAY_SIZE(lpsc); + +#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK +#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 +#endif + +#define REV_AM18X_EVM 0x100 + +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] Maximum cpu clock rate supported by onboard SoC + * 0000b - 300 MHz + * 0001b - 372 MHz + * 0010b - 408 MHz + * 0011b - 456 MHz + */ +u32 get_board_rev(void) +{ + char *s; + u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; + u32 rev = 0; + + s = getenv("maxcpuclk"); + if (s) + maxcpuclk = simple_strtoul(s, NULL, 10); + + if (maxcpuclk >= 456000000) + rev = 3; + else if (maxcpuclk >= 408000000) + rev = 2; + else if (maxcpuclk >= 372000000) + rev = 1; +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif + return rev; +} + +int board_early_init_f(void) +{ + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return 1; + + return 0; +} + +int board_init(void) +{ +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* setup the SUSPSRC for ARM to control emulation suspend */ + writel(readl(&davinci_syscfg_regs->suspsrc) & + ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART0), + &davinci_syscfg_regs->suspsrc); + + /* configure pinmux settings */ + if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) + return 1; + +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(HAS_RMII); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + /* enable the console UART */ + writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | + DAVINCI_UART_PWREMU_MGMT_UTRST), +#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) + &davinci_uart0_ctrl_regs->pwremu_mgmt); +#else + &davinci_uart2_ctrl_regs->pwremu_mgmt); +#endif + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +static int init_led(int gpio, char *name, int val) +{ + int ret; + + ret = gpio_request(gpio, name); + if (ret) + return -1; + ret = gpio_direction_output(gpio, val); + if (ret) + return -1; + + return gpio; +} + +#define LED_ON 0 +#define LED_OFF 1 + +#if !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int status) +{ + static int red; + static int green; + + if (red == 0) + red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); + if (red != CONFIG_IPAM390_GPIO_LED_RED) + return; + if (green == 0) + green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", + LED_OFF); + if (green != CONFIG_IPAM390_GPIO_LED_GREEN) + return; + + switch (status) { + case BOOTSTAGE_ID_RUN_OS: + /* + * set normal state + * LED Red : off + * LED green: off + */ + gpio_set_value(red, LED_OFF); + gpio_set_value(green, LED_OFF); + break; + case BOOTSTAGE_ID_MAIN_LOOP: + /* + * U-Boot operation + * LED Red : on + * LED green: on + */ + gpio_set_value(red, LED_ON); + gpio_set_value(green, LED_ON); + break; + } +} +#endif +#endif + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + int ret; + int bootmode = 0; + + /* + * GP7[14] selects bootmode: + * 1: boot linux + * 0: boot u-boot + * if error accessing gpio boot U-Boot + * + * SPL bootmode + * 0: boot linux + * 1: boot u-boot + */ + ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); + if (ret) + bootmode = 1; + if (!bootmode) { + ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); + if (ret) + bootmode = 1; + } + if (!bootmode) + ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); + if (!bootmode) + if (ret == 0) + bootmode = 1; + if (bootmode) { + /* + * Booting U-Boot + * LED Red : on + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); + } else { + /* + * Booting Linux + * LED Red : off + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); + } + return bootmode; +} +#endif diff --git a/board/Barix/ipam390/u-boot-spl-ipam390.lds b/board/Barix/ipam390/u-boot-spl-ipam390.lds new file mode 100644 index 0000000..5480d1f --- /dev/null +++ b/board/Barix/ipam390/u-boot-spl-ipam390.lds @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_FOOTPRINT } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + __start = .; + arch/arm/cpu/arm926ejs/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sram + + __image_copy_end = .; + _end = .; +} diff --git a/board/a3m071/README b/board/a3m071/README index a0fe832..112c47b 100644 --- a/board/a3m071/README +++ b/board/a3m071/README @@ -57,13 +57,13 @@ the following command: => fdt print 5. Save fdt to NOR flash: -=> erase fc060000 fc07ffff -=> cp.b 1800000 fc060000 10000 +=> erase fc180000 fc07ffff +=> cp.b 1800000 fc180000 10000 All this can be integrated into an environment command: -=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \ - fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \ - cp.b 1800000 fc060000 10000' +=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \ + fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \ + cp.b 1800000 fc180000 10000' => saveenv After this, only "run upd_fdt" needs to get called to load, patch diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/atmel/at91sam9m10g45ek/config.mk deleted file mode 100644 index 9d3c5ae..0000000 --- a/board/atmel/at91sam9m10g45ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x73f00000 diff --git a/board/atmel/at91sam9x5ek/config.mk b/board/atmel/at91sam9x5ek/config.mk deleted file mode 100644 index 6589a12..0000000 --- a/board/atmel/at91sam9x5ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x26f00000 diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 4a309ad..97caf64 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -17,6 +17,7 @@ #include <lcd.h> #include <atmel_lcdc.h> #include <atmel_mci.h> +#include <micrel.h> #include <net.h> #include <netdev.h> @@ -178,6 +179,8 @@ int board_init(void) #ifdef CONFIG_MACB if (has_emac()) at91_macb_hw_init(); + if (has_gmac()) + at91_gmac_hw_init(); #endif #ifdef CONFIG_LCD if (has_lcdc()) @@ -193,6 +196,21 @@ int dram_init(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + /* rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); + /* tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); + /* rx/tx clock delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); + + return 0; +} + int board_eth_init(bd_t *bis) { int rc = 0; @@ -200,6 +218,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_MACB if (has_emac()) rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); + if (has_gmac()) + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); #endif return rc; diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk index f720851..0c05dd0 100644 --- a/board/chromebook-x86/coreboot/config.mk +++ b/board/chromebook-x86/coreboot/config.mk @@ -1,37 +1,7 @@ # # Copyright (c) 2011 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above -# copyright notice, this list of conditions and the following disclaimer -# in the documentation and/or other materials provided with the -# distribution. -# * Neither the name of Google Inc. nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Alternatively, this software may be distributed under the terms of the -# GNU General Public License ("GPL") version 2 as published by the Free -# Software Foundation. +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause # HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts index d0738cb..c95ee8a 100644 --- a/board/chromebook-x86/dts/link.dts +++ b/board/chromebook-x86/dts/link.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +/include/ "coreboot.dtsi" / { #address-cells = <1>; diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index 1662141..82f21b0 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -1,27 +1,6 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /*----------------------------------------------------------------------------- */ /* Function: ext_bus_cntlr_init */ diff --git a/board/csb272/init.S b/board/csb272/init.S index 82c6fdb..b1283aa 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -1,26 +1,6 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ #include <config.h> #include <asm/ppc4xx.h> diff --git a/board/csb472/init.S b/board/csb472/init.S index e00b5f5..f5805b7 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -1,26 +1,6 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ #include <config.h> #include <asm/ppc4xx.h> diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index c786997..c4444c7 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -24,7 +24,7 @@ #include <asm/io.h> #include <asm/arch/davinci_misc.h> #include <asm/gpio.h> -#include <asm/arch/da8xx-fb.h> +#include "../../../drivers/video/da8xx-fb.h" DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +43,30 @@ static const struct da8xx_panel lcd_panel = { .invert_pxl_clk = 0, }; +static const struct display_panel disp_panel = { + QVGA, + 16, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 255, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + /* SPI0 pin muxer settings */ static const struct pinmux_config spi1_pins[] = { { pinmux(5), 1, 1 }, @@ -259,7 +283,7 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - da8xx_video_init(&lcd_panel, 16); + da8xx_video_init(&lcd_panel, &lcd_cfg, 16); return 0; } diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c deleted file mode 100644 index 5884975..0000000 --- a/board/esd/canbt/canbt.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * (C) Copyright 2001 - * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include "canbt.h" -#include <asm/processor.h> -#include <asm/io.h> -#include <command.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#if 0 -#define FPGA_DEBUG -#endif - -/* fpga configuration data */ -const unsigned char fpgadata[] = { -#include "fpgadata.c" -}; - -/* - * include common fpga code (for esd boards) - */ -#include "../common/fpga.c" - - -int board_early_init_f (void) -{ - unsigned long CPC0_CR0Reg; - int index, len, i; - int status; - - /* - * Setup GPIO pins - */ - CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; - CPC0_CR0Reg |= 0x0070f000; - mtdcr (CPC0_CR0, CPC0_CR0Reg); - -#ifdef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - - /* - * Boot onboard FPGA - */ - status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata)); - if (status != 0) { - /* booting FPGA failed */ -#ifndef FPGA_DEBUG - /* set up serial port with default baudrate */ - (void) get_clocks (); - gd->baudrate = CONFIG_BAUDRATE; - serial_init (); - console_init_f (); -#endif - printf ("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf ("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("FPGA: %s\n", &(fpgadata[index + 1])); - index += len + 3; - } - putc ('\n'); - /* delayed reboot */ - for (i = 20; i > 0; i--) { - printf ("Rebooting in %2d seconds \r", i); - for (index = 0; index < 1000; index++) - udelay (1000); - } - putc ('\n'); - do_reset (NULL, 0, 0, NULL); - } - - /* - * Setup port pins for normal operation - */ - out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32 ((void *)GPIO0_TCR, 0x07038100); /* setup for output */ - out_be32 ((void *)GPIO0_OR, 0x07030100); /* set output pins to high (default) */ - - /* - * IRQ 0-15 405GP internally generated; active high; level sensitive - * IRQ 16 405GP internally generated; active low; level sensitive - * IRQ 17-24 RESERVED - * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive - * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive - * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive - * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive - * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive - * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive - */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr (UIC0PR, 0xFFFFFF81); /* set int polarities */ - mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - int index; - int len; - char str[64]; - int i = getenv_f("serial#", str, sizeof (str)); - - puts ("Board: "); - - if (!i || strncmp (str, "CANBT", 5)) { - puts ("### No HW ID - assuming CANBT\n"); - return (0); - } - - puts (str); - - puts ("\nFPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i = 0; i < 4; i++) { - len = fpgadata[index]; - printf ("%s ", &(fpgadata[index + 1])); - index += len + 3; - } - - putc ('\n'); - - return 0; -} diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h deleted file mode 100644 index 75e7950..0000000 --- a/board/esd/canbt/canbt.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c deleted file mode 100644 index 34bdc05..0000000 --- a/board/esd/canbt/flash.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/ppc4xx.h> -#include <asm/processor.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0; - int i; - uint pbcr; - unsigned long base_b0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (-size_b0, &flash_info[0]); - - /* Re-do sizing to get full correct info */ - mtdcr(EBC0_CFGADDR, PB0CR); - pbcr = mfdcr(EBC0_CFGDATA); - mtdcr(EBC0_CFGADDR, PB0CR); - base_b0 = -size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(EBC0_CFGDATA, pbcr); - /* printf("PB1CR = %x\n", pbcr); */ - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -monitor_flash_len, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -} diff --git a/board/esd/canbt/fpgadata.c b/board/esd/canbt/fpgadata.c deleted file mode 100644 index af401cd..0000000 --- a/board/esd/canbt/fpgadata.c +++ /dev/null @@ -1,807 +0,0 @@ -0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0, -0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0c, -0x69, 0x6f, 0x5f, 0x63, 0x68, 0x69, 0x70, 0x2e, -0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, 0x73, -0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31, 0x30, -0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, 0x30, -0x31, 0x2f, 0x31, 0x31, 0x2f, 0x32, 0x33, 0x00, -0x64, 0x00, 0x09, 0x31, 0x33, 0x3a, 0x33, 0x34, -0x3a, 0x34, 0x33, 0x00, 0x65, 0xe2, 0x01, 0x00, -0x00, 0x18, 0xe6, 0xff, 0x30, 0xe8, 0x01, 0x01, -0x01, 0x01, 0xe7, 0xe6, 0x04, 0x01, 0x0d, 0x04, -0x07, 0x03, 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0xe6, 0x1b, 0xe5, 0x04, 0x02, 0xe5, 0x08, -0x38, 0x12, 0x33, 0x36, 0xe6, 0x0b, 0x01, 0xe5, -0xe5, 0x6a, 0x10, 0xe6, 0x02, 0x0b, 0xe5, 0xe5, -0x05, 0xe5, 0x07, 0xe5, 0x07, 0xe6, 0x06, 0xe5, -0x07, 0xe7, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, -0x07, 0xe5, 0x0b, 0x03, 0xe5, 0x0f, 0x09, 0x09, -0x09, 0x09, 0x04, 0x04, 0x01, 0x09, 0x09, 0x09, -0x01, 0x07, 0x0d, 0xe5, 0xe6, 0x0e, 0x09, 0x03, -0x05, 0x09, 0x09, 0x04, 0x06, 0x04, 0x04, 0x04, -0x04, 0x04, 0x04, 0x09, 0x0e, 0x03, 0x26, 0x57, -0x0f, 0x09, 0x09, 0x09, 0x09, 0x0b, 0x01, 0x07, -0x09, 0x09, 0x02, 0x06, 0x0e, 0xe5, 0xe6, 0x0c, -0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, -0xe5, 0x09, 0xe5, 0x07, 0xe5, 0x07, 0xe5, 0x07, -0xe5, 0x07, 0xe5, 0x0e, 0x03, 0x03, 0x09, 0x09, -0x09, 0x09, 0x09, 0x0b, 0x09, 0x09, 0x09, 0x09, -0x12, 0xe6, 0x0d, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, -0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, -0xe5, 0x07, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, -0xe5, 0xe5, 0x05, 0xe5, 0xe5, 0x05, 0xe5, 0xe5, -0x0b, 0x03, 0x0e, 0x09, 0x09, 0x09, 0x09, 0x03, -0x07, 0x09, 0x09, 0x09, 0x09, 0x0f, 0x02, 0xe5, -0x79, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09, 0x09, -0x08, 0x02, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe6, -0x3e, 0x3b, 0x02, 0x10, 0x09, 0x09, 0x09, 0x09, -0x0b, 0x09, 0x09, 0x09, 0x09, 0x10, 0xe5, 0x7d, -0x3f, 0x3a, 0xe5, 0x01, 0x3f, 0x36, 0x04, 0x02, -0x7a, 0x01, 0x01, 0x13, 0x3d, 0x28, 0x01, 0x01, -0x3f, 0x33, 0x0a, 0x3f, 0x34, 0x08, 0xe5, 0x79, -0x01, 0x01, 0x14, 0x09, 0x09, 0x09, 0x09, 0x0b, -0x09, 0x09, 0x09, 0x09, 0x09, 0xe5, 0x01, 0x0f, -0x09, 0x09, 0x09, 0x09, 0x07, 0x03, 0x09, 0x09, -0x09, 0x08, 0xe5, 0x0d, 0x03, 0x3a, 0x04, 0x3a, -0x02, 0xe5, 0x0c, 0x09, 0x03, 0x05, 0x09, 0x09, -0x03, 0x07, 0x09, 0x09, 0x07, 0x01, 0x1b, 0x01, -0xe5, 0x0a, 0x02, 0x07, 0x05, 0x03, 0x01, 0x03, -0x03, 0x01, 0x03, 0x03, 0x09, 0x06, 0xe5, 0x02, -0x04, 0x04, 0x04, 0x02, 0x06, 0xe5, 0x02, 0x02, -0x06, 0x02, 0xe5, 0x02, 0x03, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, -0xff, diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index 91b4063..cbdcfe3 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -5,7 +5,7 @@ * based on - Driver for MV64360X ethernet ports * Copyright (C) 2002 rabeeh@galileo.co.il * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ /* @@ -1025,21 +1025,6 @@ bool db64360_eth_start (struct eth_device *dev) * based on Linux code * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports * Copyright (C) 2002 rabeeh@galileo.co.il - - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * */ /******************************************************************************** diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S index 5925bc6..38acca1 100644 --- a/board/esd/pci405/writeibm.S +++ b/board/esd/pci405/writeibm.S @@ -1,28 +1,6 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /*----------------------------------------------------------------------------- */ /* Function: ext_bus_cntlr_init */ /* Description: Initializes the External Bus Controller for the external */ diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index 86e44ea..f74651c 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -21,12 +21,14 @@ #include "../common/qixis.h" #include "../common/vsc3316_3308.h" +#include "../common/idt8t49n222a_serdes_clk.h" #include "b4860qds.h" #include "b4860qds_qixis.h" #include "b4860qds_crossbar_con.h" #define CLK_MUX_SEL_MASK 0x4 #define ETH_PHY_CLK_OUT 0x4 +#define PLL_NUM 2 DECLARE_GLOBAL_DATA_PTR; @@ -35,8 +37,6 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - unsigned int i; static const char *const freq[] = {"100", "125", "156.25", "161.13", "122.88", "122.88", "122.88"}; int clock; @@ -61,19 +61,6 @@ int checkboard(void) /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could @@ -252,6 +239,106 @@ int configure_vsc3316_3308(void) return 0; } +int config_serdes1_refclks(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 serdes1_prtcl, lane; + unsigned int flag_sgmii_prtcl = 0; + int ret, i; + + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return -1; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks + */ + for (i = 0; i < PLL_NUM; i++) + clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); + /* Reconfigure IDT idt8t49n222a device for CPRI to work + * For this SerDes1's Refclk1 and refclk2 need to be set + * to 122.88MHz + */ + switch (serdes1_prtcl) { + case 0x2A: + case 0x2C: + case 0x2D: + case 0x2E: + debug("Configuring idt8t49n222a for CPRI SerDes clks:" + " for srds_prctl:%x\n", serdes1_prtcl); + ret = select_i2c_ch_pca(I2C_CH_IDT); + if (!ret) { + ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, + SERDES_REFCLK_122_88, + SERDES_REFCLK_122_88, 0); + if (ret) { + printf("IDT8T49N222A configuration failed.\n"); + return ret; + } else + printf("IDT8T49N222A configured.\n"); + } else { + return ret; + } + select_i2c_ch_pca(I2C_CH_DEFAULT); + + /* Change SerDes1's Refclk1 to 125MHz for on board + * SGMIIs to work + */ + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl + (0, serdes1_prtcl, lane); + switch (lane_prtcl) { + case SGMII_FM1_DTSEC1: + case SGMII_FM1_DTSEC2: + case SGMII_FM1_DTSEC3: + case SGMII_FM1_DTSEC4: + case SGMII_FM1_DTSEC5: + case SGMII_FM1_DTSEC6: + flag_sgmii_prtcl++; + break; + default: + break; + } + } + + if (flag_sgmii_prtcl) + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + + /* Steps For SerDes PLLs reset and reconfiguration after + * changing SerDes's refclks + */ + for (i = 0; i < PLL_NUM; i++) { + debug("For PLL%d reset and reconfiguration after" + " changing refclks\n", i+1); + clrbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_SDRST_B); + udelay(10); + clrbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); + udelay(10); + setbits_be32(&srds_regs->bank[i].rstctl, + SRDS_RSTCTL_RST); + setbits_be32(&srds_regs->bank[i].rstctl, + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B + | SRDS_RSTCTL_SDRST_B)); + } + break; + default: + printf("WARNING:IDT8T49N222A configuration not" + " supported for:%x SerDes1 Protocol.\n", + serdes1_prtcl); + return -1; + } + + return 0; +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -277,6 +364,16 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + /* SerDes1 refclks need to be set again, as default clks + * are not suitable for CPRI and onboard SGMIIs to work + * simultaneously. + * This function will set SerDes1's Refclk1 and refclk2 + * as per SerDes1 protocols + */ + if (config_serdes1_refclks()) + printf("SerDes1 Refclks couldn't set properly.\n"); + else + printf("SerDes1 Refclks have been set.\n"); /* Configure VSC3316 and VSC3308 crossbar switches */ if (configure_vsc3316_3308()) diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h index 6e64745..db0cf28 100644 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -13,10 +13,10 @@ static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, {5, 11}, {4, 5}, {2, 6}, {12, 9} }; -static const int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, +static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, +static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, {2, 14}, {12, 15}, {-1, -1}, {-1, -1} }; @@ -25,7 +25,7 @@ static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, {-1, -1}, {-1, -1} }; #ifdef CONFIG_PPC_B4420 -static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, +static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif @@ -35,10 +35,10 @@ static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, {11, 11}, {5, 10}, {6, 3}, {9, 12} }; -static const int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, +static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -static const int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, +static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, {14, 3}, {15, 12}, {-1, -1}, {-1, -1} }; @@ -47,7 +47,7 @@ static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, {-1, -1}, {-1, -1} }; #ifdef CONFIG_PPC_B4420 -static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, +static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; #endif diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c index 19ca66e..dc4ef80 100644 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -201,8 +201,6 @@ int board_eth_init(bd_t *bis) debug("Setting phy addresses for FM1_DTSEC5: %x and" "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); - /* Fixing Serdes clock by programming FPGA register */ - QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC6, diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c index a4161ad..c82fe0a 100644 --- a/board/freescale/bsc9131rdb/ddr.c +++ b/board/freescale/bsc9131rdb/ddr.c @@ -87,7 +87,7 @@ phys_size_t fixed_sdram(void) } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 4574894..a895e4e 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -125,6 +125,27 @@ void board_config_serdes_mux(void) } } +/* Configure DSP DDR controller */ +void dsp_ddr_configure(void) +{ + /* + *There are separate DDR-controllers for DSP and PowerPC side DDR. + *copy the ddr controller settings from PowerPC side DDR controller + *to the DSP DDR controller as connected DDR memories are similar. + */ + ccsr_ddr_t __iomem *pa_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t temp_ddr; + ccsr_ddr_t __iomem *dsp_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + + memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); + temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; + temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; + memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); + dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; +} + int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH @@ -153,6 +174,7 @@ int board_early_init_r(void) 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); #endif board_config_serdes_mux(); + dsp_ddr_configure(); return 0; } diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c index 05bea8a..fdea193 100644 --- a/board/freescale/bsc9132qds/ddr.c +++ b/board/freescale/bsc9132qds/ddr.c @@ -109,7 +109,7 @@ phys_size_t fixed_sdram(void) strmhz(buf, ddr_freq)); ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c index fed2edf..e10de9a 100644 --- a/board/freescale/bsc9132qds/law.c +++ b/board/freescale/bsc9132qds/law.c @@ -16,6 +16,14 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_FPGA_BASE_PHYS SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, + LAW_TRGT_IF_OCN_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, + LAW_TRGT_IF_CLASS_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, + LAW_TRGT_IF_CLASS_DSP) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c index 6d82353..02655e9 100644 --- a/board/freescale/bsc9132qds/tlb.c +++ b/board/freescale/bsc9132qds/tlb.c @@ -41,6 +41,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), + /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, + MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), + #ifndef CONFIG_SPL_BUILD SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile new file mode 100644 index 0000000..ab8eb8f --- /dev/null +++ b/board/freescale/c29xpcie/Makefile @@ -0,0 +1,30 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += cpld.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README new file mode 100644 index 0000000..430f0824 --- /dev/null +++ b/board/freescale/c29xpcie/README @@ -0,0 +1,100 @@ +Overview +========= +C29XPCIE board is a series of Freescale PCIe add-in cards to perform +as public key crypto accelerator or secure key management module. +It includes C293PCIE board, C293PCIE board and C291PCIE board. +The Freescale C29x family is a high performance crypto co-processor. +It combines a single e500v2 core with necessary SEC engines. +(maximum core frequency 1000/1200 MHz). + +The C29xPCIE board features are as follows: +Memory subsystem: + - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 64 Mbyte NOR flash single-chip memory + - 4 Gbyte NAND flash memory + - 1 Mbit AT24C1024 I2C EEPROM + - 16 Mbyte SPI memory + +Interfaces: + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port + - eTSEC2, RGMII: one 10/100/1000 port + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging + +Physical Memory Map on C29xPCIE +=============================== +Address Start Address End Memory type +0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR +0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory +0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash +0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM +0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO +0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD +0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR + +Serial Port Configuration on C29xPCIE +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + +Settings of DIP-switch +====================== + SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash + SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash +Note: 1 stands for 'off', 0 stands for 'on' + +Build and program u-boot to NOR flash +================================== +1. Build u-boot.bin image example: + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make C293PCIE + +2. Program u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff80000 +$filesize + => erase eff80000 +$filesize + => cp.b $loadaddr eff80000 $filesize + +3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. + +Alternate NOR bank +================== +There are four banks in C29XPCIE board, example to change bank booting: +1. Program u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off e9f80000 +$filesize + => erase e9f80000 +$filesize + => cp.b $loadaddr e9f80000 $filesize + +2. Switch to alternate NOR bank + => cpld_cmd reset altbank [bank] + - [bank] bank value select 1-4 + - bank 1 on the flash 0x0000000~0x0ffffff + - bank 2 on the flash 0x1000000~0x1ffffff + - bank 3 on the flash 0x2000000~0x2ffffff + - bank 4 on the flash 0x3000000~0x3ffffff + or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. + +Build and program u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make C29xPCIE_SPIFLASH_config; make + Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin. + +2. Program u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on. diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c new file mode 100644 index 0000000..48c4b30 --- /dev/null +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -0,0 +1,148 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <mmc.h> +#include <netdev.h> +#include <pci.h> +#include <asm/fsl_ifc.h> +#include <asm/fsl_pci.h> + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("Board: %sPCIe, ", cpu->name); + printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver)); + + return 0; +} + +int board_early_init_f(void) +{ + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned long flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_64M, 1); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[2]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + /* Register 1G MDIO bus */ + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_sec(void *blob, int offset) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", + CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET + + offset * 0x20000)) >= 0) { + fdt_del_node(blob, nodeoff); + offset++; + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->arch.cpu; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + if (cpu->soc_ver == SVR_C291) + fdt_del_sec(blob, 1); + else if (cpu->soc_ver == SVR_C292) + fdt_del_sec(blob, 2); +} +#endif diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c new file mode 100644 index 0000000..5cbccff --- /dev/null +++ b/board/freescale/c29xpcie/cpld.c @@ -0,0 +1,131 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu@freescale.com> + * Po Liu <Po.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" +/** + * Set the boot bank to the alternate bank + */ +void cpld_set_altbank(u8 banksel) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + u8 reg11; + + reg11 = in_8(&cpld_data->flhcsr); + + switch (banksel) { + case 1: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1); + break; + case 2: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2); + break; + case 3: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3); + break; + case 4: + out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4); + break; + default: + printf("Invalid value! [1-4]\n"); + return; + } + + udelay(100); + do_reset(NULL, 0, 0, NULL); +} + +/** + * Set the boot bank to the default bank + */ +void cpld_set_defbank(void) +{ + cpld_set_altbank(4); +} + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1)); + printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2)); + printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver)); + printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver)); + printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon)); + printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr)); + printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr)); + printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick)); + printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr)); + printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr)); + printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr)); + printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor)); + printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1)); + printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2)); + printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3)); + printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4)); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned char value; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (!strcmp(argv[2], "altbank") && argv[3]) { + value = (u8)simple_strtoul(argv[3], NULL, 16); + cpld_set_altbank(value); + } else if (!argv[2]) + cpld_set_defbank(); + else + cmd_usage(cmdtp); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board using the CPLD sequencer", + "reset - hard reset to default bank 4\n" + "cpld_cmd reset altbank [bank]- reset to alternate bank\n" + " - [bank] bank value select 1-4\n" + " - bank 1 on the flash 0x0000000~0x0ffffff\n" + " - bank 2 on the flash 0x1000000~0x1ffffff\n" + " - bank 3 on the flash 0x2000000~0x2ffffff\n" + " - bank 4 on the flash 0x3000000~0x3ffffff\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h new file mode 100644 index 0000000..20862a3 --- /dev/null +++ b/board/freescale/c29xpcie/cpld.h @@ -0,0 +1,40 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.Hu@freescale.com> + * Po Liu <Po.Liu@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ + u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ + u8 hwver; /* 0x2 - Hardware Version Register */ + u8 cpldver; /* 0x3 - Software Version Register */ + u8 res[12]; + u8 rstcon; /* 0x10 - Reset control register */ + u8 flhcsr; /* 0x11 - Flash control and status Register */ + u8 wdcsr; /* 0x12 - Watchdog control and status Register */ + u8 wdkick; /* 0x13 - Watchdog kick Register */ + u8 fancsr; /* 0x14 - Fan control and status Register */ + u8 ledcsr; /* 0x15 - LED control and status Register */ + u8 misccsr; /* 0x16 - Misc control and status Register */ + u8 bootor; /* 0x17 - Boot configure override Register */ + u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ + u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ + u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ + u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ +}; + +#define CPLD_BANKSEL_EN 0x02 +#define CPLD_BANKSEL_MASK 0x3f +#define CPLD_SELECT_BANK1 0xc0 +#define CPLD_SELECT_BANK2 0x80 +#define CPLD_SELECT_BANK3 0x40 +#define CPLD_SELECT_BANK4 0x00 diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c new file mode 100644 index 0000000..b017cfd --- /dev/null +++ b/board/freescale/c29xpcie/ddr.c @@ -0,0 +1,86 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +/* + * Micron MT41J128M16HA-15E + * */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 536870912u, + .capacity = 536870912u, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1650, + .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ + .tAA_ps = 14050, + .tWR_ps = 15000, + .tRCD_ps = 13500, + .tRRD_ps = 75000, + .tRP_ps = 13500, + .tRAS_ps = 40000, + .tRC_ps = 49500, + .tRFC_ps = 160000, + .tWTR_ps = 75000, + .tRTP_ps = 75000, + .refresh_rate_ps = 7800000, + .tFAW_ps = 30000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 2; + popts->cpo_override = 0x1f; + popts->write_data_delay = 4; + popts->half_strength_driver_enable = 1; + popts->bstopre = 0x3cf; + popts->quad_rank_present = 1; + popts->rtt_override = 1; + popts->rtt_override_value = 1; + popts->dynamic_power = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x4; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c new file mode 100644 index 0000000..cd8fc21 --- /dev/null +++ b/board/freescale/c29xpcie/law.c @@ -0,0 +1,19 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, + LAW_TRGT_IF_PLATFORM_SRAM), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c new file mode 100644 index 0000000..ddd1ef8 --- /dev/null +++ b/board/freescale/c29xpcie/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256K, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_4K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256K, 1), + +#ifdef CONFIG_SYS_RAMBOOT + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index d451f6f..f9550c4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -45,15 +45,14 @@ COBJS-$(CONFIG_MPC8555CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o -ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_P1022DS) += ics307_clk.o -endif COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o COBJS-$(CONFIG_P5040DS) += ics307_clk.o COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o +COBJS-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c new file mode 100644 index 0000000..d347162 --- /dev/null +++ b/board/freescale/common/idt8t49n222a_serdes_clk.c @@ -0,0 +1,207 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Shaveta Leekha <shaveta@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "idt8t49n222a_serdes_clk.h" + +#define DEVICE_ID_REG 0x00 + +static int check_pll_status(u8 idt_addr) +{ + u8 val = 0; + int ret; + + ret = i2c_read(idt_addr, 0x17, 1, &val, 1); + if (ret < 0) { + printf("IDT:0x%x could not read status register from device.\n", + idt_addr); + return ret; + } + + if (val & 0x04) { + debug("idt8t49n222a PLL is LOCKED: %x\n", val); + } else { + printf("idt8t49n222a PLL is not LOCKED: %x\n", val); + return -1; + } + + return 0; +} + +int set_serdes_refclk(u8 idt_addr, u8 serdes_num, + enum serdes_refclk refclk1, + enum serdes_refclk refclk2, u8 feedback) +{ + u8 dev_id = 0; + int i, ret; + + debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n", + idt_addr); + + ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); + if (ret < 0) { + debug("IDT:0x%x could not read DEV_ID from device.\n", + idt_addr); + return ret; + } + + if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) { + debug("IDT: device at address 0x%x is not idt8t49n222a.\n", + idt_addr); + } + + if (serdes_num != 1 && serdes_num != 2) { + debug("serdes_num should be 1 for SerDes1 and" + " 2 for SerDes2.\n"); + return -1; + } + + if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88) + || (refclk1 != SERDES_REFCLK_122_88 + && refclk2 == SERDES_REFCLK_122_88)) { + debug("Only one refclk at 122.88MHz is not supported." + " Please set both refclk1 & refclk2 to 122.88MHz" + " or both not to 122.88MHz.\n"); + return -1; + } + + if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88 + && refclk1 != SERDES_REFCLK_125 + && refclk1 != SERDES_REFCLK_156_25) { + debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" + " or 156.25MHz.\n"); + return -1; + } + + if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88 + && refclk2 != SERDES_REFCLK_125 + && refclk2 != SERDES_REFCLK_156_25) { + debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" + " or 156.25MHz.\n"); + return -1; + } + + if (feedback != 0 && feedback != 1) { + debug("valid values for feedback are 0(default) or 1.\n"); + return -1; + } + + /* Configuring IDT for output refclks as + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + */ + if (refclk1 == SERDES_REFCLK_122_88 && + refclk2 == SERDES_REFCLK_122_88) { + printf("Setting refclk1:122.88 and refclk2:122.88\n"); + for (i = 0; i < NUM_IDT_REGS; i++) + i2c_reg_write(idt_addr, idt_conf_122_88[i][0], + idt_conf_122_88[i][1]); + + if (feedback) { + for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++) + i2c_reg_write(idt_addr, + idt_conf_122_88_feedback[i][0], + idt_conf_122_88_feedback[i][1]); + } + } + + if (refclk1 != SERDES_REFCLK_122_88 && + refclk2 != SERDES_REFCLK_122_88) { + for (i = 0; i < NUM_IDT_REGS; i++) + i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0], + idt_conf_not_122_88[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 100MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:100 and refclk2:125\n"); + i2c_reg_write(idt_addr, 0x11, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:125 and refclk2:125\n"); + i2c_reg_write(idt_addr, 0x10, 0x10); + i2c_reg_write(idt_addr, 0x11, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 100MHz + */ + if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) { + printf("Setting refclk1:125 and refclk2:100\n"); + i2c_reg_write(idt_addr, 0x10, 0x10); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:156.25 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25[i][0], + idt_conf_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 100MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_100 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:100 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0], + idt_conf_100_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 125MHz Refclk2 = 156.25MHz + */ + if (refclk1 == SERDES_REFCLK_125 && + refclk2 == SERDES_REFCLK_156_25) { + printf("Setting refclk1:125 and refclk2:156.25\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0], + idt_conf_125_156_25[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 100MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_100) { + printf("Setting refclk1:156.25 and refclk2:100\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0], + idt_conf_156_25_100[i][1]); + } + + /* Configuring IDT for output refclks as + * Refclk1 = 156.25MHz Refclk2 = 125MHz + */ + if (refclk1 == SERDES_REFCLK_156_25 && + refclk2 == SERDES_REFCLK_125) { + printf("Setting refclk1:156.25 and refclk2:125\n"); + for (i = 0; i < NUM_IDT_REGS_156_25; i++) + i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0], + idt_conf_156_25_125[i][1]); + } + + /* waiting for maximum of 1 second if PLL doesn'r get locked + * initially. then check the status again. + */ + if (check_pll_status(idt_addr)) { + mdelay(1000); + if (check_pll_status(idt_addr)) + return -1; + } + + return 0; +} diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h new file mode 100644 index 0000000..787bdd9 --- /dev/null +++ b/board/freescale/common/idt8t49n222a_serdes_clk.h @@ -0,0 +1,107 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * Author: Shaveta Leekha <shaveta@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IDT8T49N222A_SERDES_CLK_H_ +#define __IDT8T49N222A_SERDES_CLK_H_ 1 + +#include <common.h> +#include <i2c.h> +#include "qixis.h" +#include "../b4860qds/b4860qds_qixis.h" +#include <errno.h> + +#define NUM_IDT_REGS 23 +#define NUM_IDT_REGS_FEEDBACK 12 +#define NUM_IDT_REGS_156_25 11 + +/* CLK */ +enum serdes_refclk { + SERDES_REFCLK_100, /* refclk 100Mhz */ + SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ + SERDES_REFCLK_125, /* refclk 125Mhz */ + SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ + SERDES_REFCLK_NONE = -1, +}; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + */ +static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, + {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, + {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, + {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, + {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, + {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, + {0x16, 0xA0} }; + + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz + */ +static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, + {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, + {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, + {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, + {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, + {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, + {0x16, 0xA0} }; + +/* Reconfiguration values for some of IDT registers for + * Output Refclks: + * Refclk1 = 122.88MHz Refclk2 = 122.88MHz + * and with feedback as 1 + */ +static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, + {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, + {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, + {0x14, 0x00}, {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 100MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 125MHz Refclk2 : 156.25MHz + */ +static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 100MHz + */ +static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +/* configuration values for IDT registers for Output Refclks: + * Refclk1 : 156.25MHz Refclk2 : 125MHz + */ +static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, + {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, + {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, + {0x15, 0xE8} }; + +int set_serdes_refclk(u8 idt_addr, u8 serdes_num, + enum serdes_refclk refclk1, + enum serdes_refclk refclk2, u8 feedback); + +#endif /*__IDT8T49N222A_SERDES_CLK_H_ */ diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 40ce6b0..a49e300 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -107,6 +107,26 @@ const char *byte_to_binary_mask(u8 val, u8 mask, char *buf) return buf; } +#ifdef QIXIS_RST_FORCE_MEM +void board_assert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (!(rst & QIXIS_RST_FORCE_MEM)) + QIXIS_WRITE(rst_frc[0], rst | QIXIS_RST_FORCE_MEM); +} + +void board_deassert_mem_reset(void) +{ + u8 rst; + + rst = QIXIS_READ(rst_frc[0]); + if (rst & QIXIS_RST_FORCE_MEM) + QIXIS_WRITE(rst_frc[0], rst & ~QIXIS_RST_FORCE_MEM); +} +#endif + void qixis_reset(void) { QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET); diff --git a/board/freescale/common/vsc3316_3308.c b/board/freescale/common/vsc3316_3308.c index 8a3dc33..97a25e8 100644 --- a/board/freescale/common/vsc3316_3308.c +++ b/board/freescale/common/vsc3316_3308.c @@ -31,7 +31,7 @@ int vsc_if_enable(unsigned int vsc_addr) return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1); } -int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], +int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], unsigned int num_con) { unsigned int i; diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h index 4003fcd..2a49187 100644 --- a/board/freescale/common/vsc3316_3308.h +++ b/board/freescale/common/vsc3316_3308.h @@ -12,7 +12,7 @@ #include <errno.h> int vsc_if_enable(unsigned int vsc_addr); -int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2], +int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2], unsigned int num_con); int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2], unsigned int num_con); diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index fffb0c8..60e2100 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -27,8 +27,10 @@ int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ + defined(CONFIG_P5040DS) unsigned int i; +#endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); @@ -47,19 +49,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index da284cd..517e87f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -56,14 +56,14 @@ phys_size_t fixed_sdram(void) ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); #if (CONFIG_NUM_DDR_CONTROLLERS == 2) memcpy(&ddr_cfg_regs, fixed_ddr_parm_1[i].ddr_settings, sizeof(ddr_cfg_regs)); ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0); #endif /* diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 7a84cd2..2fb4037 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -68,7 +68,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 3d2dabd..1e21a66 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -250,7 +250,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index d4e7abe..ee92695 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -248,7 +248,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr |= LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index a45a558..162636e 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -273,7 +273,7 @@ local_bus_init(void) get_sys_info(&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_hz = sysinfo.freq_systembus / 1000000 / clkdiv; if (lbc_hz < 66) { lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index aa8bada..681f052 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -139,7 +139,7 @@ phys_size_t fixed_sdram(void) } ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index 73289f3..d0e712e 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -26,7 +26,7 @@ void sdram_init(void) ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; - ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000; + ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 1000000; /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index cfc05f7..3bc4f43 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -21,6 +21,9 @@ ifdef MINIMAL COBJS-y += spl_minimal.o tlb.o law.o else +ifdef CONFIG_SPL_BUILD +COBJS-y += spl.o +endif COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c new file mode 100644 index 0000000..b9dbf81 --- /dev/null +++ b/board/freescale/p1022ds/spl.c @@ -0,0 +1,121 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <mmc.h> +#include <nand.h> +#include <i2c.h> +#include "../common/ngpixis.h" +#include <fsl_esdhc.h> +#include <spi_flash.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 sysclk_tbl[] = { + 66666000, 7499900, 83332500, 8999900, + 99999000, 11111000, 12499800, 13333200 +}; + +ulong get_effective_memsize(void) +{ + return CONFIG_SYS_L2_SIZE; +} + +void board_init_f(ulong bootflag) +{ + int px_spd; + u32 plat_ratio, sys_clk, bus_clk; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + console_init_f(); + + /* Set pmuxcr to allow both i2c1 and i2c2 */ + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); + setbits_be32(&gur->pmuxcr, + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); + +#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + + /* Read back the register to synchronize the write. */ + in_be32(&gur->pmuxcr); + + /* initialize selected port with appropriate baud rate */ + px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); + sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + bus_clk = sys_clk * plat_ratio / 2; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + bus_clk / 16 / CONFIG_BAUDRATE); +#ifdef CONFIG_SPL_MMC_BOOT + puts("\nSD boot...\n"); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts("\nSPI Flash boot...\n"); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *)CONFIG_SPL_GD_ADDR; + bd_t *bd; + + memset(gd, 0, sizeof(gd_t)); + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); + memset(bd, 0, sizeof(bd_t)); + gd->bd = bd; + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; + bd->bi_memsize = CONFIG_SYS_L2_SIZE; + + probecpu(); + get_clocks(); + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, + CONFIG_SPL_RELOC_MALLOC_SIZE); +#ifndef CONFIG_SPL_NAND_BOOT + env_init(); +#endif +#ifdef CONFIG_SPL_MMC_BOOT + mmc_initialize(bd); +#endif + /* relocate environment function pointers etc. */ +#ifdef CONFIG_SPL_NAND_BOOT + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); + + gd->env_addr = (ulong)(CONFIG_ENV_ADDR); + gd->env_valid = 1; +#else + env_relocate(); +#endif + + i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + gd->ram_size = initdram(0); +#ifdef CONFIG_SPL_NAND_BOOT + puts("Tertiary program loader running in sram..."); +#else + puts("Second program loader running in sram...\n"); +#endif + +#ifdef CONFIG_SPL_MMC_BOOT + mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); +#elif defined(CONFIG_SPL_NAND_BOOT) + nand_boot(); +#endif +} diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index d150d95..8b34396 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -12,51 +12,6 @@ #include <asm/fsl_ddr_sdram.h> -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -void sdram_init(void) -{ - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, - &ddr->sdram_cfg); - - in_be32(&ddr->sdram_cfg); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - in_be32(&ddr->sdram_cfg); - - set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); -} - const static u32 sysclk_tbl[] = { 66666000, 7499900, 83332500, 8999900, 99999000, 11111000, 12499800, 13333200 @@ -68,6 +23,10 @@ void board_init_f(ulong bootflag) u32 plat_ratio, sys_clk, bus_clk; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); +#endif /* for FPGA */ set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); @@ -83,9 +42,6 @@ void board_init_f(ulong bootflag) puts("\nNAND boot... "); - /* Initialize the DDR3 */ - sdram_init(); - /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. @@ -96,6 +52,7 @@ void board_init_f(ulong bootflag) void board_init_r(gd_t *gd, ulong dest_addr) { + puts("\nSecond program loader running in sram..."); nand_boot(); } diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c index 2eef6ad..e7ae2e2 100644 --- a/board/freescale/p1022ds/tlb.c +++ b/board/freescale/p1022ds/tlb.c @@ -71,25 +71,32 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_4K, 1), -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#if defined(CONFIG_SYS_RAMBOOT) || \ + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) /* **** - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_1G, 1), + CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1G, 1), #endif #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16K, 1), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16K, 1), #endif +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1) +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 0038077..5bee22e 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -220,7 +220,7 @@ phys_size_t fixed_sdram (void) ddr_cfg_regs.cs[0].bnds = 0x0000001F; } - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size; diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index 4437731..f4cc43f 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -3,6 +3,7 @@ Overview P1_P2_RDB_PC represents a set of boards including P1020MSBG-PC P1020RDB-PC + P1020RDB-PD P1020UTM-PC P1021RDB-PC P1024RDB diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 9355536..c0b72e0 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -80,7 +80,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 30000, }; -#elif defined(CONFIG_P1020MBG) +#elif (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) /* Micron MT41J512M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 2, @@ -111,7 +111,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tFAW_ps = 37500, }; -#elif defined(CONFIG_P1020RDB) +#elif defined(CONFIG_P1020RDB_PC) /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -247,11 +247,11 @@ phys_size_t fixed_sdram(void) get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freqDDRBus)); + strmhz(buf, sysinfo.freq_ddrbus)); ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, LAW_TRGT_IF_DDR_1) < 0) { diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 93896dc..d4561c7 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_1G, 1), -#ifdef CONFIG_P1020MBG +#if defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile new file mode 100644 index 0000000..915b9bc --- /dev/null +++ b/board/freescale/p1_twr/Makefile @@ -0,0 +1,35 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c new file mode 100644 index 0000000..67f69d7 --- /dev/null +++ b/board/freescale/p1_twr/ddr.c @@ -0,0 +1,69 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +/* Fixed sdram init -- doesn't use serial presence detect. */ +phys_size_t fixed_sdram(void) +{ + sys_info_t sysinfo; + char buf[32]; + size_t ddr_size; + fsl_ddr_cfg_regs_t ddr_cfg_regs = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, +#endif + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 + }; + + get_sys_info(&sysinfo); + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, sysinfo.freq_ddrbus)); + + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + + return ddr_size; +} diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c new file mode 100644 index 0000000..e79d8a4 --- /dev/null +++ b/board/freescale/p1_twr/law.c @@ -0,0 +1,16 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c new file mode 100644 index 0000000..ea8db6f --- /dev/null +++ b/board/freescale/p1_twr/p1_twr.c @@ -0,0 +1,281 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <hwconfig.h> +#include <pci.h> +#include <i2c.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_pci.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> +#include <asm/mp.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <ioports.h> +#include <asm/fsl_serdes.h> +#include <netdev.h> + +#define SYSCLK_64 64000000 +#define SYSCLK_66 66666666 + +unsigned long get_board_sys_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); + unsigned int cpdat_val = 0; + + /* Set-up up pin muxing based on board switch settings */ + cpdat_val = par_io[1].cpdat; + + /* Check switch setting for SYSCLK select (PB3) */ + if (cpdat_val & 0x10000000) + return SYSCLK_64; + else + return SYSCLK_66; + + return 0; +} + +#ifdef CONFIG_QE + +#define PCA_IOPORT_I2C_ADDR 0x23 +#define PCA_IOPORT_OUTPUT_CMD 0x2 +#define PCA_IOPORT_CFG_CMD 0x6 + +const qe_iop_conf_t qe_iop_conf_tab[] = { + +#ifdef CONFIG_TWR_P1025 + /* GPIO */ + {1, 0, 1, 0, 0}, + {1, 18, 1, 0, 0}, + + /* GPIO for switch options */ + {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ + {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ + {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ + {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ + + /* QE_MUX_MDC */ + {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ + + /* QE_MUX_MDIO */ + {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ + + /* UCC_1_MII */ + {0, 23, 2, 0, 2}, /* CLK12 */ + {0, 24, 2, 0, 1}, /* CLK9 */ + {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ + {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ + {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ + {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ + {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ + {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ + {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ + {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ + {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ + {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ + {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ + {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ + {0, 17, 2, 0, 2}, /* ENET1_CRS */ + {0, 16, 2, 0, 2}, /* ENET1_COL */ + + /* UCC_5_RMII */ + {1, 11, 2, 0, 1}, /* CLK13 */ + {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ + {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ + {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ + {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ + {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ + {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ + {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ + + /* TDMA - clock option is configured in OS based on board setting */ + {1, 23, 2, 0, 2}, /* TDMA_TXD */ + {1, 25, 2, 0, 2}, /* TDMA_RXD */ + {1, 26, 1, 0, 2}, /* TDMA_SYNC */ +#endif + + {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ +}; +#endif + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + + /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + + return 0; +} + +int checkboard(void) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u8 boot_status; + + printf("Board: %s\n", CONFIG_BOARDNAME); + + boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; + puts("rom_loc: "); + if (boot_status == PORBMSR_ROMLOC_NOR) + puts("nor flash"); + else if (boot_status == PORBMSR_ROMLOC_SDHC) + puts("sd"); + else + puts("unknown"); + puts("\n"); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + ccsr_gur_t *gur __attribute__((unused)) = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + printf("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + +#if defined(CONFIG_UEC_ETH) + /* QE0 and QE3 need to be exposed for UCC1 + * and UCC5 Eth mode (in PMUXCR register). + * Currently QE/LBC muxed pins assumed to be + * LBC for U-Boot and PMUXCR updated by OS if required */ + + uec_standard_init(bis); +#endif + + return pci_eth_init(bis); +} + +#if defined(CONFIG_QE) +static void fdt_board_fixup_qe_pins(void *blob) +{ + int node; + + if (!hwconfig("qe")) { + /* For QE and eLBC pins multiplexing, + * When don't use QE function, remove + * qe node from dt blob. + */ + node = fdt_path_offset(blob, "/qe"); + if (node >= 0) + fdt_del_node(blob, node); + } else { + /* For TWR Peripheral Modules - TWR-SER2 + * board only can support Signal Port MII, + * so delete one UEC node when use MII port. + */ + if (hwconfig("mii")) + node = fdt_path_offset(blob, "/qe/ucc@2400"); + else + node = fdt_path_offset(blob, "/qe/ucc@2000"); + if (node >= 0) + fdt_del_node(blob, node); + } + + return; +} +#endif + +#ifdef CONFIG_OF_BOARD_SETUP +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + FT_FSL_PCI_SETUP; + +#ifdef CONFIG_QE + do_fixup_by_compat(blob, "fsl,qe", "status", "okay", + sizeof("okay"), 0); +#endif +#if defined(CONFIG_TWR_P1025) + fdt_board_fixup_qe_pins(blob); +#endif + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c new file mode 100644 index 0000000..308335c --- /dev/null +++ b/board/freescale/p1_twr/tlb.c @@ -0,0 +1,76 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifndef CONFIG_SPL_BUILD + /* W**G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + + /* W**G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI memory 1.5G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O effective: 192K */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + +#endif + +#ifdef CONFIG_SYS_RAMBOOT + /* *I*G - eSDHC boot */ + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 08d10bc..60694a6 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -28,7 +28,6 @@ int checkboard(void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; printf("Board: %sRDB, ", cpu->name); @@ -39,20 +38,6 @@ int checkboard(void) printf("vBank: %d\n", sw & 0x1); /* - * Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index 85df066..a2167b3 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -8,7 +8,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-y += $(BOARD).o +COBJS-$(CONFIG_T4240QDS) += t4240qds.o +COBJS-$(CONFIG_T4240EMU) += t4240emu.o COBJS-y += ddr.o COBJS-$(CONFIG_T4240QDS)+= eth.o COBJS-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 058d625..26ac2a5 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -13,81 +13,10 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include "ddr.h" DECLARE_GLOBAL_DATA_PTR; -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2T; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0}, - {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h new file mode 100644 index 0000000..d0a0951 --- /dev/null +++ b/board/freescale/t4qds/ddr.h @@ -0,0 +1,108 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +#ifdef CONFIG_T4240QDS +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {} +}; + +#else /* CONFIG_T4240EMU */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, + {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, + {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, + {} +}; +#endif /* CONFIG_T4240EMU */ + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index c771e17..b5f488b 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -172,7 +172,10 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval) void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + int interface = fm_info_get_enet_if(port); + + if (interface == PHY_INTERFACE_MODE_SGMII || + interface == PHY_INTERFACE_MODE_QSGMII) { switch (port) { case FM1_DTSEC1: if (qsgmiiphy_fix[port]) @@ -272,6 +275,7 @@ void fdt_fixup_board_enet(void *fdt) for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: switch (mdio_mux[i]) { case EMI1_SLOT1: fdt_status_okay_by_alias(fdt, "emi1_slot1"); @@ -393,7 +397,7 @@ static void initialize_qsgmiiphy_fix(void) int board_eth_init(bd_t *bis) { #if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot; + int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -470,9 +474,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC9, - slot_qsgmii_phyaddr[1][3]); - fm_info_set_phy_address(FM1_DTSEC10, slot_qsgmii_phyaddr[1][2]); + fm_info_set_phy_address(FM1_DTSEC10, + slot_qsgmii_phyaddr[1][3]); } break; case 40: @@ -482,9 +486,9 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { fm_info_set_phy_address(FM1_DTSEC10, - slot_qsgmii_phyaddr[1][3]); - fm_info_set_phy_address(FM1_DTSEC9, slot_qsgmii_phyaddr[1][2]); + fm_info_set_phy_address(FM1_DTSEC9, + slot_qsgmii_phyaddr[1][3]); } fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); @@ -498,15 +502,31 @@ int board_eth_init(bd_t *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { + interface = fm_info_get_enet_if(i); + switch (interface) { case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_QSGMII) { + if (idx <= 3) + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_A); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + QSGMII_FM1_B); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects QSGMII in slot %u\n", + idx + 1, slot); + } else { + lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); + if (lane < 0) + break; + slot = lane_to_slot_fsm1[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { @@ -600,8 +620,8 @@ int board_eth_init(bd_t *bis) fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); - fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); - fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); + fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); + fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); break; case 40: case 46: @@ -641,15 +661,31 @@ int board_eth_init(bd_t *bis) for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { idx = i - FM2_DTSEC1; - switch (fm_info_get_enet_if(i)) { + interface = fm_info_get_enet_if(i); + switch (interface) { case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_2, + case PHY_INTERFACE_MODE_QSGMII: + if (interface == PHY_INTERFACE_MODE_QSGMII) { + if (idx <= 3) + lane = serdes_get_first_lane(FSL_SRDS_2, + QSGMII_FM2_A); + else + lane = serdes_get_first_lane(FSL_SRDS_2, + QSGMII_FM2_B); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects QSGMII in slot %u\n", + idx + 1, slot); + } else { + lane = serdes_get_first_lane(FSL_SRDS_2, SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); + if (lane < 0) + break; + slot = lane_to_slot_fsm2[lane]; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + } if (QIXIS_READ(present2) & (1 << (slot - 1))) fm_disable_port(i); switch (slot) { diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c index 63549df..367783b 100644 --- a/board/freescale/t4qds/law.c +++ b/board/freescale/t4qds/law.c @@ -19,7 +19,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), #endif +#ifdef QIXIS_BASE_PHYS SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c new file mode 100644 index 0000000..7a61036 --- /dev/null +++ b/board/freescale/t4qds/t4240emu.c @@ -0,0 +1,80 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sEMU\n", cpu->name); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); +} diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4240qds.c index aa6a217..0c1a4fb 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -26,16 +26,16 @@ DECLARE_GLOBAL_DATA_PTR; -static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, +static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, {8, 8}, {9, 9}, {14, 14}, {15, 15} }; -static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, +static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, {10, 10}, {11, 11}, {12, 12}, {13, 13} }; -static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, +static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, {10, 11}, {11, 10}, {12, 2}, {13, 3} }; -static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, +static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, {8, 9}, {9, 8}, {14, 1}, {15, 0} }; int checkboard(void) @@ -43,12 +43,11 @@ int checkboard(void) char buf[64]; u8 sw; struct cpu_type *cpu = gd->arch.cpu; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; printf("Board: %sQDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch)); + QIXIS_READ(id), QIXIS_READ(arch)); sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -63,24 +62,11 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); /* the timestamp string contains "\n" at the end */ printf(" on %s", qixis_read_time(buf)); - /* Display the RCW, so that no one gets confused as to what RCW - * we're actually using for this boot. - */ - puts("Reset Configuration Word (RCW):"); - for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_be32(&gur->rcwsr[i]); - - if ((i % 4) == 0) - printf("\n %08x:", i * 4); - printf(" %08x", rcw); - } - puts("\n"); - /* * Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could @@ -92,7 +78,7 @@ int checkboard(void) puts("SERDES Reference Clocks: "); sw = QIXIS_READ(brdcfg[2]); for (i = 0; i < MAX_SERDES; i++) { - static const char *freq[] = { + static const char * const freq[] = { "100", "125", "156.25", "161.1328125"}; unsigned int clock = (sw >> (6 - 2 * i)) & 3; @@ -367,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void) srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - if (srds_prtcl_s1) { + switch (srds_prtcl_s1) { + case 38: + /* swap first lane and third lane on slot1 */ + vsc3316_fsm1_tx[0][1] = 14; + vsc3316_fsm1_tx[6][1] = 0; + vsc3316_fsm1_rx[1][1] = 2; + vsc3316_fsm1_rx[6][1] = 13; + case 40: + case 46: + case 48: + /* swap first lane and third lane on slot2 */ + vsc3316_fsm1_tx[2][1] = 8; + vsc3316_fsm1_tx[4][1] = 6; + vsc3316_fsm1_rx[2][1] = 10; + vsc3316_fsm1_rx[5][1] = 5; + default: ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); if (ret) return ret; ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); if (ret) return ret; + break; } srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - if (srds_prtcl_s2) { + switch (srds_prtcl_s2) { + case 38: + /* swap first lane and third lane on slot3 */ + vsc3316_fsm2_tx[2][1] = 11; + vsc3316_fsm2_tx[5][1] = 4; + vsc3316_fsm2_rx[2][1] = 9; + vsc3316_fsm2_rx[4][1] = 7; + case 40: + case 46: + case 48: + case 50: + case 52: + case 54: + /* swap first lane and third lane on slot4 */ + vsc3316_fsm2_tx[6][1] = 3; + vsc3316_fsm2_tx[1][1] = 12; + vsc3316_fsm2_rx[0][1] = 1; + vsc3316_fsm2_rx[6][1] = 15; + default: ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); if (ret) return ret; ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); if (ret) return ret; + break; } return 0; @@ -430,7 +451,7 @@ int config_backside_crossbar_mux(void) break; default: printf("WARNING: unsupported for SerDes3 Protocol %d\n", - srds_prtcl_s3); + srds_prtcl_s3); return -1; } @@ -470,7 +491,7 @@ int config_backside_crossbar_mux(void) break; default: printf("WARNING: unsupported for SerDes4 Protocol %d\n", - srds_prtcl_s4); + srds_prtcl_s4); return -1; } @@ -495,8 +516,8 @@ int board_early_init_r(void) disable_tlb(flash_esel); set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); set_liodns(); #ifdef CONFIG_SYS_DPAA_QBMAN @@ -634,9 +655,8 @@ int misc_init_r(void) u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { - printf("Warning: SERDES%u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), + printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", + i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } @@ -795,42 +815,44 @@ void qixis_dump_switch(void) } sw[0] = dutcfg[0]; - sw[1] = (dutcfg[1] << 0x07) | \ - ((dutcfg[12] & 0xC0) >> 1) | \ - ((dutcfg[11] & 0xE0) >> 3) | \ - ((dutcfg[6] & 0x80) >> 6) | \ + sw[1] = (dutcfg[1] << 0x07) | + ((dutcfg[12] & 0xC0) >> 1) | + ((dutcfg[11] & 0xE0) >> 3) | + ((dutcfg[6] & 0x80) >> 6) | ((dutcfg[1] & 0x80) >> 7); - sw[2] = ((brdcfg[1] & 0x0f) << 4) | \ - ((brdcfg[1] & 0x30) >> 2) | \ - ((brdcfg[1] & 0x40) >> 5) | \ + sw[2] = ((brdcfg[1] & 0x0f) << 4) | + ((brdcfg[1] & 0x30) >> 2) | + ((brdcfg[1] & 0x40) >> 5) | ((brdcfg[1] & 0x80) >> 7); sw[3] = brdcfg[2]; - sw[4] = ((dutcfg[2] & 0x01) << 7) | \ - ((dutcfg[2] & 0x06) << 4) | \ - ((~QIXIS_READ(present)) & 0x10) | \ - ((brdcfg[3] & 0x80) >> 4) | \ - ((brdcfg[3] & 0x01) << 2) | \ - ((brdcfg[6] == 0x62) ? 3 : \ - ((brdcfg[6] == 0x5a) ? 2 : \ + sw[4] = ((dutcfg[2] & 0x01) << 7) | + ((dutcfg[2] & 0x06) << 4) | + ((~QIXIS_READ(present)) & 0x10) | + ((brdcfg[3] & 0x80) >> 4) | + ((brdcfg[3] & 0x01) << 2) | + ((brdcfg[6] == 0x62) ? 3 : + ((brdcfg[6] == 0x5a) ? 2 : ((brdcfg[6] == 0x5e) ? 1 : 0))); - sw[5] = ((brdcfg[0] & 0x0f) << 4) | \ - ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \ + sw[5] = ((brdcfg[0] & 0x0f) << 4) | + ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | ((brdcfg[0] & 0x40) >> 5); sw[6] = (brdcfg[11] & 0x20) | ((brdcfg[5] & 0x02) << 3); - sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \ + sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | ((brdcfg[5] & 0x10) << 2); - sw[8] = ((brdcfg[12] & 0x08) << 4) | \ + sw[8] = ((brdcfg[12] & 0x08) << 4) | ((brdcfg[12] & 0x03) << 5); puts("DIP switch (reverse-engineering)\n"); for (i = 0; i < 9; i++) { printf("SW%d = 0b%s (0x%02x)\n", - i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); + i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); } } -static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +static int do_vdd_adjust(cmd_tbl_t *cmdtp, + int flag, int argc, + char * const argv[]) { ulong override; diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c index b27356a..b701e75 100644 --- a/board/freescale/t4qds/tlb.c +++ b/board/freescale/t4qds/tlb.c @@ -120,9 +120,11 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_64K, 1), #endif +#ifdef QIXIS_BASE_PHYS SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 17, BOOKE_PAGESZ_4K, 1), +#endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index f0df2e3..426dc05 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -18,6 +18,12 @@ #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + DECLARE_GLOBAL_DATA_PTR; int get_fpga_state(unsigned dev) @@ -90,23 +96,17 @@ int board_early_init_r(void) gd405ep_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - struct ihs_fpga *fpga = - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI - u16 *reflection_target = &fpga->reflection_low; -#else - u16 *reflection_target = &fpga->reflection_high; -#endif /* * wait for fpga out of reset */ ctr = 0; while (1) { - out_le16(&fpga->reflection_low, - REFLECTION_TESTPATTERN); + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - if (in_le16(reflection_target) == - REFLECTION_TESTPATTERN_INV) + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) break; udelay(100000); diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index 48d8786..35dfbbc 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -55,6 +55,8 @@ enum { RAM_DDR2_64 = 2, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -79,10 +81,9 @@ static unsigned int get_mc2_present(void) static void print_fpga_info(unsigned dev) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_rs232; @@ -96,6 +97,10 @@ static void print_fpga_info(unsigned dev) printf("FPGA%d: ", dev); + FPGA_GET_REG(dev, versions, &versions); + FPGA_GET_REG(dev, fpga_version, &fpga_version); + FPGA_GET_REG(dev, fpga_features, &fpga_features); + hardware_version = versions & 0x000f; if (fpga_state @@ -247,8 +252,9 @@ int checkboard(void) int last_stage_init(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); + u16 versions; + + FPGA_GET_REG(0, versions, &versions); print_fpga_info(0); if (get_mc2_present()) diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index eee9ba0..03d796c 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -37,6 +37,8 @@ enum { HWVER_122 = 3, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -101,15 +103,18 @@ int checkboard(void) static void print_fpga_info(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; @@ -163,7 +168,6 @@ static void print_fpga_info(void) */ int last_stage_init(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; print_fpga_info(); @@ -175,7 +179,7 @@ int last_stage_init(void) configure_gbit_phy(k); /* take fpga serdes blocks out of reset */ - out_le16(&fpga->quad_serdes_reset, 0); + FPGA_SET_REG(0, quad_serdes_reset, 0); return 0; } diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index c728bc7..7a98e41 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -7,6 +7,7 @@ #include <common.h> #include <command.h> +#include <errno.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-gpio.h> @@ -15,11 +16,22 @@ #include <gdsys_fpga.h> #include "../common/osd.h" +#include "../common/mclink.h" + +#include <i2c.h> +#include <pca953x.h> +#include <pca9698.h> + +#include <miiphy.h> + +DECLARE_GLOBAL_DATA_PTR; #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define MAX_MUX_CHANNELS 2 + enum { UNITTYPE_MAIN_SERVER = 0, UNITTYPE_MAIN_USER = 1, @@ -31,11 +43,22 @@ enum { HWVER_100 = 0, HWVER_104 = 1, HWVER_110 = 2, + HWVER_120 = 3, + HWVER_200 = 4, + HWVER_210 = 5, + HWVER_220 = 6, + HWVER_230 = 7, +}; + +enum { + FPGA_HWVER_200 = 0, + FPGA_HWVER_210 = 1, }; enum { COMPRESSION_NONE = 0, - COMPRESSION_TYPE1_DELTA, + COMPRESSION_TYPE1_DELTA = 1, + COMPRESSION_TYPE1_TYPE2_DELTA = 3, }; enum { @@ -51,8 +74,75 @@ enum { enum { RAM_DDR2_32 = 0, + RAM_DDR3_32 = 1, }; +enum { + CARRIER_SPEED_1G = 0, + CARRIER_SPEED_2_5G = 1, +}; + +enum { + MCFPGA_DONE = 1 << 0, + MCFPGA_INIT_N = 1 << 1, + MCFPGA_PROGRAM_N = 1 << 2, + MCFPGA_UPDATE_ENABLE_N = 1 << 3, + MCFPGA_RESET_N = 1 << 4, +}; + +enum { + GPIO_MDC = 1 << 14, + GPIO_MDIO = 1 << 15, +}; + +unsigned int mclink_fpgacount; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + +static int setup_88e1518(const char *bus, unsigned char addr); + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + int res; + + switch (fpga) { + case 0: + out_le16(reg, data); + break; + default: + res = mclink_send(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_send reg %02lx data %04x returned %d\n", + regoff, data, res); + return res; + } + break; + } + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + int res; + + switch (fpga) { + case 0: + *data = in_le16(reg); + break; + default: + if (fpga > mclink_fpgacount) + return -EINVAL; + res = mclink_receive(fpga - 1, regoff, data); + if (res < 0) { + printf("mclink_receive reg %02lx returned %d\n", + regoff, res); + return res; + } + } + + return 0; +} + /* * Check Board Identity: */ @@ -74,12 +164,11 @@ int checkboard(void) return 0; } -static void print_fpga_info(void) +static void print_fpga_info(unsigned int fpga, bool rgmii2_present) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; unsigned unit_type; unsigned hardware_version; unsigned feature_compression; @@ -87,19 +176,29 @@ static void print_fpga_info(void) unsigned feature_audio; unsigned feature_sysclock; unsigned feature_ramconfig; + unsigned feature_carrier_speed; unsigned feature_carriers; unsigned feature_video_channels; + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; - hardware_version = versions & 0x000f; feature_compression = (fpga_features & 0xe000) >> 13; feature_osd = fpga_features & (1<<11); feature_audio = (fpga_features & 0x0600) >> 9; feature_sysclock = (fpga_features & 0x0180) >> 7; feature_ramconfig = (fpga_features & 0x0060) >> 5; + feature_carrier_speed = fpga_features & (1<<4); feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; + if (legacy) + printf("legacy "); + switch (unit_type) { case UNITTYPE_MAIN_USER: printf("Mainchannel"); @@ -114,27 +213,78 @@ static void print_fpga_info(void) break; } - switch (hardware_version) { - case HWVER_100: - printf(" HW-Ver 1.00\n"); - break; - - case HWVER_104: - printf(" HW-Ver 1.04\n"); - break; - - case HWVER_110: - printf(" HW-Ver 1.10\n"); - break; + if (unit_type == UNITTYPE_MAIN_USER) { + if (legacy) + hardware_version = + (in_le16((void *)LATCH2_BASE)>>8) & 0x0f; + else + hardware_version = + (!!pca9698_get_value(0x20, 24) << 0) + | (!!pca9698_get_value(0x20, 25) << 1) + | (!!pca9698_get_value(0x20, 26) << 2) + | (!!pca9698_get_value(0x20, 27) << 3); + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00,"); + break; + + case HWVER_104: + printf(" HW-Ver 1.04,"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10,"); + break; + + case HWVER_120: + printf(" HW-Ver 1.20-1.21,"); + break; + + case HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + case HWVER_220: + printf(" HW-Ver 2.20,"); + break; + + case HWVER_230: + printf(" HW-Ver 2.30,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } + if (rgmii2_present) + printf(" RGMII2,"); + } - default: - printf(" HW-Ver %d(not supported)\n", - hardware_version); - break; + if (unit_type == UNITTYPE_VIDEO_USER) { + hardware_version = versions & 0x000f; + switch (hardware_version) { + case FPGA_HWVER_200: + printf(" HW-Ver 2.00,"); + break; + + case FPGA_HWVER_210: + printf(" HW-Ver 2.10,"); + break; + + default: + printf(" HW-Ver %d(not supported),", + hardware_version); + break; + } } - printf(" FPGA V %d.%02d, features:", - fpga_version / 100, fpga_version % 100); + printf(" FPGA V %d.%02d\n features:", + fpga_version / 100, fpga_version % 100); switch (feature_compression) { @@ -146,6 +296,10 @@ static void print_fpga_info(void) printf(" type1-deltacompression"); break; + case COMPRESSION_TYPE1_TYPE2_DELTA: + printf(" type1-deltacompression, type2-inlinecompression"); + break; + default: printf(" compression %d(not supported)", feature_compression); break; @@ -192,53 +346,145 @@ static void print_fpga_info(void) printf(", RAM 32 bit DDR2"); break; + case RAM_DDR3_32: + printf(", RAM 32 bit DDR3"); + break; + default: printf(", RAM %d(not supported)", feature_ramconfig); break; } - printf(", %d carrier(s)", feature_carriers); + printf(", %d carrier(s) %s", feature_carriers, + feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); printf(", %d video channel(s)\n", feature_video_channels); } int last_stage_init(void) { - print_fpga_info(); + int slaves; + unsigned int k; + unsigned int mux_ch; + unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 }; + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + u16 fpga_features; + int feature_carrier_speed = fpga_features & (1<<4); + bool ch0_rgmii2_present = false; + + FPGA_GET_REG(0, fpga_features, &fpga_features); + + if (!legacy) + ch0_rgmii2_present = !pca9698_get_value(0x20, 30); + + print_fpga_info(0, ch0_rgmii2_present); + osd_probe(0); + + /* wait for FPGA done */ + for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { + unsigned int ctr = 0; + + if (i2c_probe(mclink_controllers[k])) + continue; + + while (!(pca953x_get_val(mclink_controllers[k]) + & MCFPGA_DONE)) { + udelay(100000); + if (ctr++ > 5) { + printf("no done for mclink_controller %d\n", k); + break; + } + } + } + + if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { + miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, + bb_miiphy_write); + for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { + if ((mux_ch == 1) && !ch0_rgmii2_present) + continue; + + setup_88e1518(bb_miiphy_buses[0].name, mux_ch); + } + } + + /* wait for slave-PLLs to be up and running */ + udelay(500000); + + mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; + slaves = mclink_probe(); + mclink_fpgacount = 0; + + if (slaves <= 0) + return 0; + + mclink_fpgacount = slaves; + + for (k = 1; k <= slaves; ++k) { + FPGA_GET_REG(k, fpga_features, &fpga_features); + feature_carrier_speed = fpga_features & (1<<4); + + print_fpga_info(k, false); + osd_probe(k); + if (feature_carrier_speed == CARRIER_SPEED_1G) { + miiphy_register(bb_miiphy_buses[k].name, + bb_miiphy_read, bb_miiphy_write); + setup_88e1518(bb_miiphy_buses[k].name, 0); + } + } - return osd_probe(0); + return 0; } /* * provide access to fpga gpios (for I2C bitbang) + * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(int pin) +void fpga_gpio_set(unsigned int bus, int pin) { - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin); + FPGA_SET_REG(bus, gpio.set, pin); } -void fpga_gpio_clear(int pin) +void fpga_gpio_clear(unsigned int bus, int pin) { - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin); + FPGA_SET_REG(bus, gpio.clear, pin); } -int fpga_gpio_get(int pin) +int fpga_gpio_get(unsigned int bus, int pin) { - return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; + u16 val; + + FPGA_GET_REG(bus, gpio.read, &val); + + return val & pin; } void gd405ep_init(void) { + unsigned int k; + + if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */ + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM; + } else { + pca9698_direction_output(0x20, 4, 1); + } } void gd405ep_set_fpga_reset(unsigned state) { - if (state) { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) { + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } } else { - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + pca9698_set_value(0x20, 4, state ? 0 : 1); } } @@ -253,5 +499,333 @@ void gd405ep_setup_hw(void) int gd405ep_get_fpga_done(unsigned fpga) { - return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) + return in_le16((void *)LATCH2_BASE) + & CONFIG_SYS_FPGA_DONE(fpga); + else + return pca9698_get_value(0x20, 20); +} + +/* + * FPGA MII bitbang implementation + */ + +struct fpga_mii { + unsigned fpga; + int mdio; +} fpga_mii[] = { + { 0, 1}, + { 1, 1}, + { 2, 1}, + { 3, 1}, +}; + +static int mii_dummy_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int mii_mdio_active(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (fpga_mii->mdio) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + return 0; +} + +static int mii_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + + return 0; +} + +static int mii_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); + + fpga_mii->mdio = v; + + return 0; +} + +static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + u16 gpio; + struct fpga_mii *fpga_mii = bus->priv; + + FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio); + + *v = ((gpio & GPIO_MDIO) != 0); + + return 0; +} + +static int mii_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct fpga_mii *fpga_mii = bus->priv; + + if (v) + FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); + else + FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC); + + return 0; +} + +static int mii_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "board0", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[0], + }, + { + .name = "board1", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[1], + }, + { + .name = "board2", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[2], + }, + { + .name = "board3", + .init = mii_dummy_init, + .mdio_active = mii_mdio_active, + .mdio_tristate = mii_mdio_tristate, + .set_mdio = mii_set_mdio, + .get_mdio = mii_get_mdio, + .set_mdc = mii_set_mdc, + .delay = mii_delay, + .priv = &fpga_mii[3], + }, +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); + +enum { + MIICMD_SET, + MIICMD_MODIFY, + MIICMD_VERIFY_VALUE, + MIICMD_WAIT_FOR_VALUE, +}; + +struct mii_setupcmd { + u8 token; + u8 reg; + u16 data; + u16 mask; + u32 timeout; +}; + +/* + * verify we are talking to a 88e1518 + */ +struct mii_setupcmd verify_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_VERIFY_VALUE, 2, 0x0141, 0xffff }, + { MIICMD_VERIFY_VALUE, 3, 0x0dd0, 0xfff0 }, +}; + +/* + * workaround for erratum mentioned in 88E1518 release notes + */ +struct mii_setupcmd fixup_88e1518[] = { + { MIICMD_SET, 22, 0x00ff }, + { MIICMD_SET, 17, 0x214b }, + { MIICMD_SET, 16, 0x2144 }, + { MIICMD_SET, 17, 0x0c28 }, + { MIICMD_SET, 16, 0x2146 }, + { MIICMD_SET, 17, 0xb233 }, + { MIICMD_SET, 16, 0x214d }, + { MIICMD_SET, 17, 0xcc0c }, + { MIICMD_SET, 16, 0x2159 }, + { MIICMD_SET, 22, 0x00fb }, + { MIICMD_SET, 7, 0xc00d }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * default initialization: + * - set RGMII receive timing to "receive clock transition when data stable" + * - set RGMII transmit timing to "transmit clock internally delayed" + * - set RGMII output impedance target to 78,8 Ohm + * - run output impedance calibration + * - set autonegotiation advertise to 1000FD only + */ +struct mii_setupcmd default_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 21, 0x0030, 0x0030 }, + { MIICMD_MODIFY, 25, 0x0000, 0x0003 }, + { MIICMD_MODIFY, 24, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 24, 0x4000, 0x4000, 2000 }, + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 4, 0x0000, 0x01e0 }, + { MIICMD_MODIFY, 9, 0x0200, 0x0300 }, +}; + +/* + * turn off CLK125 for PHY daughterboard + */ +struct mii_setupcmd ch1fix_88e1518[] = { + { MIICMD_SET, 22, 0x0002 }, + { MIICMD_MODIFY, 16, 0x0006, 0x0006 }, + { MIICMD_SET, 22, 0x0000 }, +}; + +/* + * perform copper software reset + */ +struct mii_setupcmd swreset_88e1518[] = { + { MIICMD_SET, 22, 0x0000 }, + { MIICMD_MODIFY, 0, 0x8000, 0x8000 }, + { MIICMD_WAIT_FOR_VALUE, 0, 0x0000, 0x8000, 2000 }, +}; + +static int process_setupcmd(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd) +{ + int res; + u8 reg = setupcmd->reg; + u16 data = setupcmd->data; + u16 mask = setupcmd->mask; + u32 timeout = setupcmd->timeout; + u16 orig_data; + unsigned long start; + + debug("mii %s:%u reg %2u ", bus, addr, reg); + + switch (setupcmd->token) { + case MIICMD_MODIFY: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + debug("is %04x. (value %04x mask %04x) ", orig_data, data, + mask); + data = (orig_data & ~mask) | (data & mask); + case MIICMD_SET: + debug("=> %04x\n", data); + res = miiphy_write(bus, addr, reg, data); + break; + case MIICMD_VERIFY_VALUE: + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + break; + if ((orig_data & mask) != (data & mask)) + res = -1; + debug("(value %04x mask %04x) == %04x? %s\n", data, mask, + orig_data, res ? "FAIL" : "PASS"); + break; + case MIICMD_WAIT_FOR_VALUE: + res = -1; + start = get_timer(0); + while ((res != 0) && (get_timer(start) < timeout)) { + res = miiphy_read(bus, addr, reg, &orig_data); + if (res) + continue; + if ((orig_data & mask) != (data & mask)) + res = -1; + } + debug("(value %04x mask %04x) == %04x? %s after %lu ms\n", data, + mask, orig_data, res ? "FAIL" : "PASS", + get_timer(start)); + break; + default: + res = -1; + break; + } + + return res; +} + +static int process_setup(const char *bus, unsigned char addr, + struct mii_setupcmd *setupcmd, unsigned int count) +{ + int res = 0; + unsigned int k; + + for (k = 0; k < count; ++k) { + res = process_setupcmd(bus, addr, &setupcmd[k]); + if (res) { + printf("mii cmd %u on bus %s addr %u failed, aborting setup", + setupcmd[k].token, bus, addr); + break; + } + } + + return res; +} + +static int setup_88e1518(const char *bus, unsigned char addr) +{ + int res; + + res = process_setup(bus, addr, + verify_88e1518, ARRAY_SIZE(verify_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + fixup_88e1518, ARRAY_SIZE(fixup_88e1518)); + if (res) + return res; + + res = process_setup(bus, addr, + default_88e1518, ARRAY_SIZE(default_88e1518)); + if (res) + return res; + + if (addr) { + res = process_setup(bus, addr, + ch1fix_88e1518, ARRAY_SIZE(ch1fix_88e1518)); + if (res) + return res; + } + + res = process_setup(bus, addr, + swreset_88e1518, ARRAY_SIZE(swreset_88e1518)); + if (res) + return res; + + return 0; } diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c index bca7803..ff0edb2 100644 --- a/board/gdsys/405ep/neo.c +++ b/board/gdsys/405ep/neo.c @@ -28,6 +28,8 @@ enum { HWVER_300 = 3, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + int misc_init_r(void) { /* startup fans */ @@ -54,10 +56,9 @@ int checkboard(void) static void print_fpga_info(void) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; int fpga_state = get_fpga_state(0); unsigned unit_type; unsigned hardware_version; @@ -74,6 +75,10 @@ static void print_fpga_info(void) return; } + FPGA_GET_REG(0, versions, &versions); + FPGA_GET_REG(0, fpga_version, &fpga_version); + FPGA_GET_REG(0, fpga_features, &fpga_features); + unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c index 32e24c0..c1a583f 100644 --- a/board/gdsys/405ex/405ex.c +++ b/board/gdsys/405ex/405ex.c @@ -11,6 +11,12 @@ #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI +#define REFLECTION_TESTREG reflection_low +#else +#define REFLECTION_TESTREG reflection_high +#endif + DECLARE_GLOBAL_DATA_PTR; int get_fpga_state(unsigned dev) @@ -220,23 +226,17 @@ int board_early_init_r(void) gd405ex_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - struct ihs_fpga *fpga = - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI - u16 *reflection_target = &fpga->reflection_low; -#else - u16 *reflection_target = &fpga->reflection_high; -#endif /* * wait for fpga out of reset */ ctr = 0; while (1) { - out_le16(&fpga->reflection_low, - REFLECTION_TESTPATTERN); + u16 val; + + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); - if (in_le16(reflection_target) == - REFLECTION_TESTPATTERN_INV) + FPGA_GET_REG(k, REFLECTION_TESTREG, &val); + if (val == REFLECTION_TESTPATTERN_INV) break; udelay(100000); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index fa8961a..2f8e306 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -51,6 +51,8 @@ enum { HWVER_110 = 1, }; +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR; + static inline void blank_string(int size) { int i; @@ -84,10 +86,9 @@ int misc_init_r(void) static void print_fpga_info(unsigned dev) { - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); - u16 versions = in_le16(&fpga->versions); - u16 fpga_version = in_le16(&fpga->fpga_version); - u16 fpga_features = in_le16(&fpga->fpga_features); + u16 versions; + u16 fpga_version; + u16 fpga_features; int fpga_state = get_fpga_state(dev); unsigned unit_type; @@ -95,6 +96,10 @@ static void print_fpga_info(unsigned dev) unsigned feature_channels; unsigned feature_expansion; + FPGA_GET_REG(dev, versions, &versions); + FPGA_GET_REG(dev, fpga_version, &fpga_version); + FPGA_GET_REG(dev, fpga_features, &fpga_features); + printf("FPGA%d: ", dev); if (fpga_state & FPGA_STATE_PLATFORM) printf("(legacy) "); @@ -226,8 +231,6 @@ int last_stage_init(void) { unsigned int k; unsigned int fpga; - struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); - struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1); int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; @@ -265,17 +268,16 @@ int last_stage_init(void) /* take fpga serdes blocks out of reset */ puts(str_serdes); udelay(500000); - out_le16(&fpga0->quad_serdes_reset, 0); - out_le16(&fpga1->quad_serdes_reset, 0); + FPGA_SET_REG(0, quad_serdes_reset, 0); + FPGA_SET_REG(1, quad_serdes_reset, 0); blank_string(strlen(str_serdes)); /* take channels out of reset */ puts(str_channels); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; for (k = 0; k < 32; ++k) - out_le16(ch0_config_int + 4 * k, 0); + FPGA_SET_REG(fpga, ch[k].config_int, 0); } blank_string(strlen(str_channels)); @@ -283,16 +285,16 @@ int last_stage_init(void) puts(str_locks); udelay(500000); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; for (k = 0; k < 32; ++k) { - u16 status = in_le16(ch0_status_int + 4*k); + u16 status; + FPGA_GET_REG(k, ch[k].status_int, &status); if (!(status & (1 << 4))) { failed = 1; printf("fpga %d channel %d: no serdes lock\n", fpga, k); } /* reset events */ - out_le16(ch0_status_int + 4*k, status); + FPGA_SET_REG(fpga, ch[k].status_int, 0); } } blank_string(strlen(str_locks)); @@ -300,14 +302,14 @@ int last_stage_init(void) /* verify hicb_status */ puts(str_hicb); for (fpga = 0; fpga < 2; ++fpga) { - u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; for (k = 0; k < 32; ++k) { - u16 status = in_le16(ch0_hicb_status_int + 4*k); + u16 status; + FPGA_GET_REG(k, hicb_ch[k].status_int, &status); if (status) printf("fpga %d hicb %d: hicb status %04x\n", fpga, k, status); /* reset events */ - out_le16(ch0_hicb_status_int + 4*k, status); + FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0); } } blank_string(strlen(str_hicb)); diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 43e6a4c..216ad96 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -13,9 +13,11 @@ endif LIB = $(obj)lib$(VENDOR).o +COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o + COBJS-$(CONFIG_IO) += miiphybb.o COBJS-$(CONFIG_IO64) += miiphybb.o -COBJS-$(CONFIG_IOCON) += osd.o +COBJS-$(CONFIG_IOCON) += osd.o mclink.o COBJS-$(CONFIG_DLVISION_10G) += osd.o COBJS-$(CONFIG_CONTROLCENTERD) += dp501.o diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 9aa4e3f..52f3ea1 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -2,23 +2,7 @@ * (C) Copyright 2012 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */ diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c new file mode 100644 index 0000000..e10c105 --- /dev/null +++ b/board/gdsys/common/fpga.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2013 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <gdsys_fpga.h> + +#include <asm/io.h> + +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data) +{ + out_le16(reg, data); + + return 0; +} + +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) +{ + *data = in_le16(reg); + + return 0; +} diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c new file mode 100644 index 0000000..9f230c9 --- /dev/null +++ b/board/gdsys/common/mclink.c @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <errno.h> + +#include <gdsys_fpga.h> + +enum { + MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7, + MCINT_TX_ERROR_EV = 1 << 9, + MCINT_TX_BUFFER_FREE = 1 << 10, + MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11, + MCINT_RX_ERROR_EV = 1 << 13, + MCINT_RX_CONTENT_AVAILABLE = 1 << 14, + MCINT_RX_PACKET_RECEIVED_EV = 1 << 15, +}; + +int mclink_probe(void) +{ + unsigned int k; + int slaves = 0; + + for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) { + int timeout = 0; + unsigned int ctr = 0; + u16 mc_status; + + FPGA_GET_REG(k, mc_status, &mc_status); + + if (!(mc_status & (1 << 15))) + break; + + FPGA_SET_REG(k, mc_control, 0x8000); + + FPGA_GET_REG(k, mc_status, &mc_status); + while (!(mc_status & (1 << 14))) { + udelay(100); + if (ctr++ > 500) { + timeout = 1; + break; + } + FPGA_GET_REG(k, mc_status, &mc_status); + } + if (timeout) + break; + + printf("waited %d us for mclink %d to come up\n", ctr * 100, k); + + slaves++; + } + + return slaves; +} + +int mclink_send(u8 slave, u16 addr, u16 data) +{ + unsigned int ctr = 0; + u16 int_status; + u16 rx_cmd_status; + u16 rx_cmd; + + /* reset interrupt status */ + FPGA_GET_REG(0, mc_int, &int_status); + FPGA_SET_REG(0, mc_int, int_status); + + /* send */ + FPGA_SET_REG(0, mc_tx_address, addr); + FPGA_SET_REG(0, mc_tx_data, data); + FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); + FPGA_SET_REG(0, mc_control, 0x8001); + + /* wait for reply */ + FPGA_GET_REG(0, mc_int, &int_status); + while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) { + udelay(100); + if (ctr++ > 3) + return -ETIMEDOUT; + FPGA_GET_REG(0, mc_int, &int_status); + } + + FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); + rx_cmd = (rx_cmd_status >> 12) & 0x03; + if (rx_cmd != 0) + printf("mclink_send: received cmd %d, expected %d\n", rx_cmd, + 0); + + return 0; +} + +int mclink_receive(u8 slave, u16 addr, u16 *data) +{ + u16 rx_cmd_status; + u16 rx_cmd; + u16 int_status; + unsigned int ctr = 0; + + /* send read request */ + FPGA_SET_REG(0, mc_tx_address, addr); + FPGA_SET_REG(0, mc_tx_cmd, + ((slave & 0x03) << 14) | (1 << 12) | (1 << 0)); + FPGA_SET_REG(0, mc_control, 0x8001); + + + /* wait for reply */ + FPGA_GET_REG(0, mc_int, &int_status); + while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) { + udelay(100); + if (ctr++ > 3) + return -ETIMEDOUT; + FPGA_GET_REG(0, mc_int, &int_status); + } + + /* check reply */ + FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status); + if ((rx_cmd_status >> 14) != slave) { + printf("mclink_receive: reply from slave %d, expected %d\n", + rx_cmd_status >> 14, slave); + return -EINVAL; + } + + rx_cmd = (rx_cmd_status >> 12) & 0x03; + if (rx_cmd != 1) { + printf("mclink_send: received cmd %d, expected %d\n", + rx_cmd, 1); + return -EIO; + } + + FPGA_GET_REG(0, mc_rx_data, data); + + return 0; +} diff --git a/board/gdsys/common/mclink.h b/board/gdsys/common/mclink.h new file mode 100644 index 0000000..febd46a --- /dev/null +++ b/board/gdsys/common/mclink.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2012 + * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MCLINK_H_ +#define _MCLINK_H_ + +int mclink_probe(void); +int mclink_send(u8 slave, u16 addr, u16 data); +int mclink_receive(u8 slave, u16 addr, u16 *data); + +#endif diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 45cea5e..c49cd9a 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -7,7 +7,7 @@ #include <common.h> #include <i2c.h> -#include <asm/io.h> +#include <malloc.h> #include <gdsys_fpga.h> @@ -26,10 +26,6 @@ #define PIXCLK_640_480_60 25180000 -#define BASE_WIDTH 32 -#define BASE_HEIGHT 16 -#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT) - enum { CH7301_CM = 0x1c, /* Clock Mode Register */ CH7301_IC = 0x1d, /* Input Clock Register */ @@ -51,37 +47,55 @@ enum { CH7301_DSP = 0x56, /* DVI Sync polarity Register */ }; +unsigned int base_width; +unsigned int base_height; +size_t bufsize; +u16 *buf; + +unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1; + +#ifdef CONFIG_SYS_CH7301 +int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C; +#endif + #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_i2c *i2c = &fpga->i2c; + u16 val; - while (in_le16(&fpga->extended_interrupt) & (1 << 12)) - ; - out_le16(&i2c->write_mailbox_ext, reg | (data << 8)); - out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1)); + do { + FPGA_GET_REG(screen, extended_interrupt, &val); + } while (val & (1 << 12)); + + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8)); + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1)); } static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_i2c *i2c = &fpga->i2c; unsigned int ctr = 0; + u16 val; + + do { + FPGA_GET_REG(screen, extended_interrupt, &val); + } while (val & (1 << 12)); - while (in_le16(&fpga->extended_interrupt) & (1 << 12)) - ; - out_le16(&fpga->extended_interrupt, 1 << 14); - out_le16(&i2c->write_mailbox_ext, reg); - out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1)); - while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) { + FPGA_SET_REG(screen, extended_interrupt, 1 << 14); + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg); + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1)); + + FPGA_GET_REG(screen, extended_interrupt, &val); + while (!(val & (1 << 14))) { udelay(100000); if (ctr++ > 5) { printf("iic receive timeout\n"); break; } + FPGA_GET_REG(screen, extended_interrupt, &val); } - return in_le16(&i2c->read_mailbox_ext) >> 8; + + FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val); + return val >> 8; } #endif @@ -113,7 +127,6 @@ static void mpc92469ac_calc_parameters(unsigned int fout, static void mpc92469ac_set(unsigned screen, unsigned int fout) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); unsigned int n; unsigned int m; unsigned int bitval = 0; @@ -134,7 +147,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout) break; } - out_le16(&fpga->mpc3w_control, (bitval << 9) | m); + FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); } #endif @@ -249,14 +262,12 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) static int osd_write_videomem(unsigned screen, unsigned offset, u16 *data, size_t charcount) { - struct ihs_fpga *fpga = - (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen); unsigned int k; for (k = 0; k < charcount; ++k) { - if (offset + k >= BUFSIZE) + if (offset + k >= bufsize) return -1; - out_le16(&fpga->videomem + offset + k, data[k]); + FPGA_SET_REG(screen, videomem[offset + k], data[k]); } return charcount; @@ -266,14 +277,13 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { + for (screen = 0; screen <= max_osd_screen; ++screen) { unsigned x; unsigned y; unsigned charcount; unsigned len; u8 color; unsigned int k; - u16 buf[BUFSIZE]; char *text; int res; @@ -287,12 +297,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) color = simple_strtoul(argv[3], NULL, 16); text = argv[4]; charcount = strlen(text); - len = (charcount > BUFSIZE) ? BUFSIZE : charcount; + len = (charcount > bufsize) ? bufsize : charcount; for (k = 0; k < len; ++k) buf[k] = (text[k] << 8) | color; - res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len); + res = osd_write_videomem(screen, y * base_width + x, buf, len); if (res < 0) return res; } @@ -302,24 +312,32 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int osd_probe(unsigned screen) { - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); - struct ihs_osd *osd = &fpga->osd; - u16 version = in_le16(&osd->version); - u16 features = in_le16(&osd->features); - unsigned width; - unsigned height; + u16 version; + u16 features; u8 value; +#ifdef CONFIG_SYS_CH7301 + int old_bus = i2c_get_bus_num(); +#endif - width = ((features & 0x3f00) >> 8) + 1; - height = (features & 0x001f) + 1; + FPGA_GET_REG(0, osd.version, &version); + FPGA_GET_REG(0, osd.features, &features); + + base_width = ((features & 0x3f00) >> 8) + 1; + base_height = (features & 0x001f) + 1; + bufsize = base_width * base_height; + buf = malloc(sizeof(u16) * bufsize); + if (!buf) + return -1; printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n", - screen, version/100, version%100, width, height); + screen, version/100, version%100, base_width, base_height); #ifdef CONFIG_SYS_CH7301 + i2c_set_bus_num(ch7301_i2c[screen]); value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID); if (value != 0x17) { printf(" Probing CH7301 failed, DID %02x\n", value); + i2c_set_bus_num(old_bus); return -1; } i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08); @@ -327,6 +345,7 @@ int osd_probe(unsigned screen) i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60); i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09); i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0); + i2c_set_bus_num(old_bus); #endif #ifdef CONFIG_SYS_MPC92469AC @@ -356,12 +375,15 @@ int osd_probe(unsigned screen) fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37); #endif - out_le16(&fpga->videocontrol, 0x0002); - out_le16(&osd->control, 0x0049); + FPGA_SET_REG(screen, videocontrol, 0x0002); + FPGA_SET_REG(screen, osd.control, 0x0049); + + FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1)); + FPGA_SET_REG(screen, osd.x_pos, 0x007f); + FPGA_SET_REG(screen, osd.y_pos, 0x005f); - out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1)); - out_le16(&osd->x_pos, 0x007f); - out_le16(&osd->y_pos, 0x005f); + if (screen > max_osd_screen) + max_osd_screen = screen; return 0; } @@ -370,11 +392,11 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned screen; - for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) { + for (screen = 0; screen <= max_osd_screen; ++screen) { unsigned x; unsigned y; unsigned k; - u16 buffer[BASE_WIDTH]; + u16 buffer[base_width]; char *rp; u16 *wp = buffer; unsigned count = (argc > 4) ? @@ -399,13 +421,13 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rp += 4; wp++; - if (wp - buffer > BASE_WIDTH) + if (wp - buffer > base_width) break; } for (k = 0; k < count; ++k) { unsigned offset = - y * BASE_WIDTH + x + k * (wp - buffer); + y * base_width + x + k * (wp - buffer); osd_write_videomem(screen, offset, buffer, wp - buffer); } diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index c0f0c0d..9e91f68 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -1,5 +1,5 @@ /* - * Board functions for IGEP COM AQUILA/CYGNUS based boards + * Board functions for IGEP COM AQUILA based boards * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * @@ -27,11 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -/* MII mode defines */ -#define RMII_MODE_ENABLE 0x4D - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_SPL_BUILD @@ -66,60 +61,39 @@ static struct emif_regs ddr3_emif_reg_data = { .zq_config = K4B2G1646EBIH9_ZQ_CFG, .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY, }; -#endif -/* - * Early system init of muxing and clocks. - */ -void s_init(void) -{ - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 303, OSC-1, 1, -1, -1, -1, -1}; - /* Enable RTC32K clock */ - rtc32k_enable(); +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} +void set_uart_mux_conf(void) +{ enable_uart0_pin_mux(); +} - uart_soft_reset(); - gd = &gdata; - - preloader_console_init(); - - /* Configure board pin mux */ +void set_mux_conf_regs(void) +{ enable_board_pin_mux(); +} +void sdram_init(void) +{ config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); @@ -181,7 +155,8 @@ int board_eth_init(bd_t *bis) eth_setenv_enetaddr("ethaddr", mac_addr); } - writel(RMII_MODE_ENABLE, &cdev->miisel); + writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN), + &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) diff --git a/board/isee/igep0033/board.h b/board/isee/igep0033/board.h index a6f17e3..a11d7ab 100644 --- a/board/isee/igep0033/board.h +++ b/board/isee/igep0033/board.h @@ -1,5 +1,5 @@ /* - * IGEP COM AQUILA/CYGNUS boards information header + * IGEP COM AQUILA boards information header * * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ * diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 77a9bc6..7a7500b 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -138,6 +138,18 @@ int board_mmc_init(bd_t *bis) } #endif +void set_fdt(void) +{ + switch (gd->bd->bi_arch_number) { + case MACH_TYPE_IGEP0020: + setenv("dtbfile", "omap3-igep0020.dtb"); + break; + case MACH_TYPE_IGEP0030: + setenv("dtbfile", "omap3-igep0030.dtb"); + break; + } +} + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -150,6 +162,8 @@ int misc_init_r(void) dieid_num_r(); + set_fdt(); + return 0; } diff --git a/board/jse/init.S b/board/jse/init.S index bccc7e0..7b918b5 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -1,28 +1,6 @@ -/*------------------------------------------------------------------------+ */ -/* */ -/* This source code is dual-licensed. You may use it under the terms */ -/* of the GNU General Public License version 2, or under the license */ -/* below. */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------- */ - +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /*------------------------------------------------------------------------- */ /* Function: ext_bus_cntlr_init */ /* Description: Initializes the External Bus Controller for the external */ diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index f9bb6ab..6ab263a 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -1,25 +1,6 @@ -/*-----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of -| the GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1995 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+-----------------------------------------------------------------------------*/ +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /* * Adapted for PIP405 03.07.01 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 39a1d68..bf886c0 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -1,26 +1,6 @@ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /*----------------------------------------------------------------------------- * Function: ext_bus_cntlr_init * Description: Initializes the External Bus Controller for the external diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index b77517f..9ed2799 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -1,26 +1,6 @@ -/*------------------------------------------------------------------------------+ - * This source code is dual-licensed. You may use it under the terms of - * the GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *-------------------------------------------------------------------------------*/ - +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ /*----------------------------------------------------------------------------- * Function: ext_bus_cntlr_init * Description: Initializes the External Bus Controller for the external diff --git a/board/overo/overo.c b/board/overo/overo.c index a6e2e93..aace42a 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -142,16 +142,22 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_165(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; default: timings->mcfg = MICRON_V_MCFG_165(128 << 20); diff --git a/board/overo/overo.h b/board/overo/overo.h index 88e197d..64604de 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -21,6 +21,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_0 0x0 #define REVISION_1 0x1 #define REVISION_2 0x2 +#define REVISION_3 0x3 /* * IEN - Input Enable diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 6291d03..e40b0bd 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -30,11 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - /* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA #define RMII_RGMII2_MODE_ENABLE 0x49 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -44,6 +40,15 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* DDR RAM defines */ #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + static const struct ddr_data ddr3_data = { .datardsratio0 = MT41J256M8HX15E_RD_DQS, .datawdsratio0 = MT41J256M8HX15E_WR_DQS, @@ -76,57 +81,27 @@ static struct emif_regs ddr3_emif_reg_data = { .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* - * WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - -#ifdef CONFIG_SPL_BUILD - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - enable_uart0_pin_mux(); - uart_soft_reset(); - - gd = &gdata; - - preloader_console_init(); +} +void set_mux_conf_regs(void) +{ /* Initalize the board header */ enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); enable_board_pin_mux(); +} +void sdram_init(void) +{ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. @@ -135,7 +110,7 @@ int board_init(void) { i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/samsung/common/multi_i2c.c b/board/samsung/common/multi_i2c.c index 4fce987..084858d 100644 --- a/board/samsung/common/multi_i2c.c +++ b/board/samsung/common/multi_i2c.c @@ -11,13 +11,12 @@ /* Handle multiple I2C buses instances */ int get_multi_scl_pin(void) { - unsigned int bus = I2C_GET_BUS(); + unsigned int bus = i2c_get_bus_num(); switch (bus) { - case I2C_0: /* I2C_0 definition - compatibility layer */ - case I2C_5: + case I2C_0: return CONFIG_SOFT_I2C_I2C5_SCL; - case I2C_9: + case I2C_1: return CONFIG_SOFT_I2C_I2C9_SCL; default: printf("I2C_%d not supported!\n", bus); @@ -28,13 +27,12 @@ int get_multi_scl_pin(void) int get_multi_sda_pin(void) { - unsigned int bus = I2C_GET_BUS(); + unsigned int bus = i2c_get_bus_num(); switch (bus) { - case I2C_0: /* I2C_0 definition - compatibility layer */ - case I2C_5: + case I2C_0: return CONFIG_SOFT_I2C_I2C5_SDA; - case I2C_9: + case I2C_1: return CONFIG_SOFT_I2C_I2C9_SDA; default: printf("I2C_%d not supported!\n", bus); diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index 80ffe30..1e94c7f 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ ARCH_CPU_DTS +/include/ "exynos5250.dtsi" / { model = "SAMSUNG SMDK5250 board based on EXYNOS5250"; diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts index dca3386..7832e4e 100644 --- a/board/samsung/dts/exynos5250-snow.dts +++ b/board/samsung/dts/exynos5250-snow.dts @@ -10,7 +10,7 @@ */ /dts-v1/; -/include/ ARCH_CPU_DTS +/include/ "exynos5250.dtsi" / { model = "Google Snow"; diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index c05801d..5b3d6ef 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -32,7 +32,11 @@ int power_init_board(void) { int ret; - ret = pmic_init(I2C_5); + /* + * For PMIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + */ + ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index c8698f3..7f61d17 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -61,10 +61,10 @@ void i2c_init_board(void) struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); - /* I2C_5 -> PMIC */ + /* I2C_5 -> PMIC -> Adapter 0 */ s5p_gpio_direction_output(&gpio1->b, 7, 1); s5p_gpio_direction_output(&gpio1->b, 6, 1); - /* I2C_9 -> FG */ + /* I2C_9 -> FG -> Adapter 1 */ s5p_gpio_direction_output(&gpio2->y4, 0, 1); s5p_gpio_direction_output(&gpio2->y4, 1, 1); } @@ -282,10 +282,17 @@ int power_init_board(void) struct power_battery *pb; struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; - ret = pmic_init(I2C_5); + /* + * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + * + * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected + * to logical I2C adapter 1 + */ + ret = pmic_init(I2C_0); ret |= pmic_init_max8997(); - ret |= power_fg_init(I2C_9); - ret |= power_muic_init(I2C_5); + ret |= power_fg_init(I2C_1); + ret |= power_muic_init(I2C_0); ret |= power_bat_init(0); if (ret) return ret; diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 2e1dba6..54d0e1e 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -45,6 +45,10 @@ int power_init_board(void) { int ret; + /* + * For PMIC the I2C bus is named as I2C5, but it is connected + * to logical I2C adapter 0 + */ ret = pmic_init(I2C_5); if (ret) return ret; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index dee8710..8378518 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -65,8 +65,8 @@ local_bus_init(void) get_sys_info(&sysinfo); - lbc_mhz = sysinfo.freqLocalBus / 1000000; - clkdiv = sysinfo.freqSystemBus / sysinfo.freqLocalBus; + lbc_mhz = sysinfo.freq_localbus / 1000000; + clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus; debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); diff --git a/board/sc3/init.S b/board/sc3/init.S index 6352368..9921f8f 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -1,31 +1,6 @@ -/*------------------------------------------------------------------------------+ - * - * This souce code has been made available to you by EuroDesign - * (www.eurodsn.de). It's based on the original IBM source code, so - * this follows: - * - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - *------------------------------------------------------------------------------- */ - +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ #include <config.h> #include <asm/ppc4xx.h> diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h index 77498b6..5596d27 100644 --- a/board/scb9328/intel.h +++ b/board/scb9328/intel.h @@ -2,28 +2,7 @@ * Copyright (C) 2002 ETC s.r.o. * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause * * Written by Marcel Telka <marcel@telka.sk>, 2002. * diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c new file mode 100644 index 0000000..6279c32 --- /dev/null +++ b/board/siemens/common/board.c @@ -0,0 +1,171 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/board/ti/am335x/board.c + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + spl_siemens_board_init(); + board_init_ddr(); + + return; +} +#endif /* #ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif /* defined(CONFIG_HW_WATCHDOG) */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_FACTORYSET + factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); +#endif + gpmc_init(); + +#ifdef CONFIG_VIDEO + board_video_init(); +#endif + + return 0; +} +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); + + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +#if defined(BOARD_DFU_BUTTON_GPIO) +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + int gpio; + + gpio = BOARD_DFU_BUTTON_GPIO; + gpio_request(gpio, "DFU"); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + if (!button) { + /* LED0 - RED=1: GPIO2_0 2*32 = 64 */ + gpio_request(BOARD_DFU_BUTTON_LED, ""); + gpio_direction_output(BOARD_DFU_BUTTON_LED, 1); + gpio_set_value(BOARD_DFU_BUTTON_LED, 1); + } + + return button; +} + +U_BOOT_CMD( + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" +); +#endif + +static int +do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("\n\n\n Go into infinite loop\n\n\n"); + while (1) + ; + return 0; +}; + +U_BOOT_CMD( + testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt, + "Sends U-Boot into infinite loop", + "" +); + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + printf("Enable d-cache\n"); + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c new file mode 100644 index 0000000..eda9141 --- /dev/null +++ b/board/siemens/common/factoryset.c @@ -0,0 +1,284 @@ +/* + * + * Read FactorySet information from EEPROM into global structure. + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#if !defined(CONFIG_SPL_BUILD) + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/unaligned.h> +#include <net.h> +#include <usbdescriptors.h> +#include "factoryset.h" + +#define EEPR_PG_SZ 0x80 +#define EEPROM_FATORYSET_OFFSET 0x400 +#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ + +/* Global variable that contains necessary information from FactorySet */ +struct factorysetcontainer factory_dat; + +#define fact_get_char(i) *((char *)&eeprom_buf[i]) + +static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2) +{ + if (s1 == NULL) + return -1; + + while (*s1 == fact_get_char(i2++)) + if (*s1++ == '=') + return i2; + + if (*s1 == '\0' && fact_get_char(i2-1) == '=') + return i2; + + return -1; +} + +static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name, + uchar *buf, int len) +{ + int i, nxt = 0; + + for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) { + int val, n; + + for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= size) + return -1; + } + + val = fact_match(eeprom_buf, (uchar *)name, i); + if (val < 0) + continue; + + /* found; copy out */ + for (n = 0; n < len; ++n, ++buf) { + *buf = fact_get_char(val++); + if (*buf == '\0') + return n; + } + + if (n) + *--buf = '\0'; + + printf("env_buf [%d bytes] too small for value of \"%s\"\n", + len, name); + + return n; + } + return -1; +} + +static +int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, + uchar *name, uchar *buf, int len) +{ + int ret = -1; + int i, nxt = 0; + int c; + unsigned char end = 0xff; + + for (i = 0; fact_get_char(i) != end; i = nxt) { + nxt = i + 1; + if (fact_get_char(i) == '>') { + int pos; + int endpos; + int z; + + c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, + strlen((char *)record)); + if (c == 0) { + /* record found */ + pos = i + strlen((char *)record) + 2; + nxt = pos; + /* search for "<" */ + c = -1; + for (z = pos; fact_get_char(z) != end; z++) { + if ((fact_get_char(z) == '<') || + (fact_get_char(z) == '>')) { + endpos = z; + nxt = endpos; + c = 0; + break; + } + } + } + if (c == 0) { + /* end found -> call get_factory_val */ + eeprom_buf[endpos] = end; + ret = get_factory_val(&eeprom_buf[pos], + size - pos, name, buf, len); + /* fix buffer */ + eeprom_buf[endpos] = '<'; + debug("%s: %s.%s = %s\n", + __func__, record, name, buf); + return ret; + } + } + } + return ret; +} + +int factoryset_read_eeprom(int i2c_addr) +{ + int i, pages = 0, size = 0; + unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; + unsigned char *cp, *cp1; + +#if defined(CONFIG_DFU_FUNCTION) + factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM; + factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM; +#endif + if (i2c_probe(i2c_addr)) + goto err; + + if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + goto err; + + if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { + printf("FactorySet is not right in eeprom.\n"); + return 1; + } + + /* get FactorySet size */ + size = (hdr[2] << 8) + hdr[3] + sizeof(hdr); + if (size > 0x3bfa) + size = 0x3bfa; + + pages = size / EEPR_PG_SZ; + + /* + * read the eeprom using i2c + * I can not read entire eeprom in once, so separate into several + * times. Furthermore, fetch eeprom take longer time, so we fetch + * data after every time we got a record from eeprom + */ + debug("Read eeprom page :\n"); + for (i = 0; i < pages; i++) + if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + goto err; + + if (size % EEPR_PG_SZ) + if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, + eeprom_buf + (pages * EEPR_PG_SZ), + (size % EEPR_PG_SZ))) + goto err; + + /* we do below just for eeprom align */ + for (i = 0; i < size; i++) + if (eeprom_buf[i] == '\n') + eeprom_buf[i] = 0; + + /* skip header */ + size -= sizeof(hdr); + cp = (uchar *)eeprom_buf + sizeof(hdr); + + /* get mac address */ + get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16); + cp1 += 3; + } + +#if defined(CONFIG_DFU_FUNCTION) + /* read vid and pid for dfu mode */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"vid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_vendor_id = simple_strtoul((char *)buf, + NULL, 16); + } + + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"pid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_product_id = simple_strtoul((char *)buf, + NULL, 16); + } + printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, + factory_dat.usb_product_id); +#endif + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", buf, + MAX_STRING_LENGTH)) { + if (strncmp((const char *)buf, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + } + debug("PXM50: %d\n", factory_dat.pxm50); +#if defined(CONFIG_VIDEO) + if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", + (uchar *)"name", factory_dat.disp_name, + MAX_STRING_LENGTH)) { + debug("display name: %s\n", factory_dat.disp_name); + } + +#endif + return 0; + +err: + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int factoryset_mac_setenv(void) +{ + uint8_t mac_addr[6]; + + debug("FactorySet: Set mac address\n"); + if (is_valid_ether_addr(factory_dat.mac)) { + memcpy(mac_addr, factory_dat.mac, 6); + } else { + uint32_t mac_hi, mac_lo; + + debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n"); + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (!is_valid_ether_addr(mac_addr)) { + printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n"); + return -1; + } + } + + eth_setenv_enetaddr("ethaddr", mac_addr); + return 0; +} + +int factoryset_setenv(void) +{ + int ret = 0; + + if (factoryset_mac_setenv() < 0) + ret = -1; + + return ret; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev) +{ + put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor); + put_unaligned(factory_dat.usb_product_id, &dev->idProduct); + return 0; +} +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h new file mode 100644 index 0000000..445f384 --- /dev/null +++ b/board/siemens/common/factoryset.h @@ -0,0 +1,27 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FACTORYSET_H +#define __FACTORYSET_H + +#define MAX_STRING_LENGTH 32 + +struct factorysetcontainer { + uchar mac[6]; + int usb_vendor_id; + int usb_product_id; + int pxm50; +#if defined(CONFIG_VIDEO) + unsigned char disp_name[MAX_STRING_LENGTH]; +#endif +}; + +int factoryset_read_eeprom(int i2c_addr); +int factoryset_setenv(void); +extern struct factorysetcontainer factory_dat; + +#endif /* __FACTORYSET_H */ diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/dxr2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c new file mode 100644 index 0000000..af9d84f --- /dev/null +++ b/board/siemens/dxr2/board.c @@ -0,0 +1,241 @@ +/* + * Board functions for TI AM335X based dxr2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include "board.h" +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; + +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B, + 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2, + 0x00000618, +}; + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\n\nDDR3 Timing parameters:\n"); + printf("Diff Eeprom Default\n"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); +} + +static void print_chip_data(void) +{ + printf("\n"); + printf("Device: '%s'\n", settings.chip.sdevname); + printf("HW version: '%s'\n", settings.chip.shwver); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Error: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Error: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) { + printf("Valid chip data in eeprom\n"); + print_chip_data(); + } else { + printf("Error: No chip data in eeprom\n"); + } + + print_ddr3_timings(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs dxr2_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data dxr2_ddr3_data = { + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control dxr2_ddr3_cmd_ctrl_data = { + .cmd0dldiff = 0, + .cmd1dldiff = 0, + .cmd2dldiff = 0, +}; + /* pass values from eeprom */ + dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data, + &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_setenv(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#include "../common/board.c" diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h new file mode 100644 index 0000000..2be78fb --- /dev/null +++ b/board/siemens/dxr2/board.h @@ -0,0 +1,69 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ + settings.ddr3.x, ddr3_default.x +#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 19 Jun 2013 10:57:48 +0200 */ +/* From file: draco/ddr3-data-micron.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e33 */ + unsigned short int ddr3_sratio; /* 0x0100 */ + unsigned short int iclkout; /* 0x0001 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x008A */ + unsigned short int dt0fwsratio0; /* 0x010B */ + unsigned short int dt0wrsratio0; /* 0x00C4 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */ + unsigned int sdram_config; /* 0x61C04AB2 */ + unsigned int ref_ctrl; /* 0x00000618 */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct dxr2_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c new file mode 100644 index 0000000..bc80b79 --- /dev/null +++ b/board/siemens/dxr2/mux.c @@ -0,0 +1,112 @@ +/* + * pinmux setup for siemens dxr2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/pxm2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c new file mode 100644 index 0000000..2c1841f --- /dev/null +++ b/board/siemens/pxm2/board.c @@ -0,0 +1,429 @@ +/* + * Board functions for TI AM335X based pxm2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include "../../../drivers/video/da8xx-fb.h" +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <watchdog.h> +#include "board.h" +#include "../common/factoryset.h" +#include "pmic.h" +#include <nand.h> +#include <bmp_layout.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs pxm2_ddr3_emif_reg_data = { + .sdram_config = 0x41805332, + .sdram_tim1 = 0x666b3c9, + .sdram_tim2 = 0x243631ca, + .sdram_tim3 = 0x33f, + .emif_ddr_phy_ctlr_1 = 0x100005, + .zq_config = 0, + .ref_ctrl = 0x81a, +}; + +struct ddr_data pxm2_ddr3_data = { + .datardsratio0 = 0x81204812, + .datawdsratio0 = 0, + .datafwsratio0 = 0x8020080, + .datawrsratio0 = 0x4010040, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control pxm2_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0, + .cmd0iclkout = 0, + .cmd1csratio = 0x80, + .cmd1dldiff = 0, + .cmd1iclkout = 0, + .cmd2csratio = 0x80, + .cmd2dldiff = 0, + .cmd2iclkout = 0, +}; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data, + &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if (module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} + +#define OSC (V_OSCK/1000000) + +const struct dpll_params dpll_mpu_pxm2 = { + 720, OSC-1, 1, -1, -1, -1, -1}; + +void spl_siemens_board_init(void) +{ + uchar buf[4]; + /* + * pxm2 PMIC code. All boards currently want an MPU voltage + * of 1.2625V and CORE voltage of 1.1375V to operate at + * 720MHz. + */ + if (i2c_probe(PMIC_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + /* Frequency switching for OPP 120 */ + if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || + voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { + printf("voltage update failed\n"); + } +} +#endif /* if def CONFIG_SPL_BUILD */ + +int read_eeprom(void) +{ + /* nothing ToDo here for this board */ + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + int n = 0; +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#ifdef CONFIG_FACTORYSET + int rv; + if (!is_valid_ether_addr(factory_dat.mac)) + printf("Error: no valid mac address\n"); + else + eth_setenv_enetaddr("ethaddr", factory_dat.mac); +#endif /* #ifdef CONFIG_FACTORYSET */ + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel(RGMII_MODE_ENABLE , &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* AUO G156XW01 V1 */ + [0] = { + .name = "AUO_G156XW01_V1", + .width = 1376, + .height = 768, + .hfp = 14, + .hbp = 64, + .hsw = 56, + .vfp = 1, + .vbp = 28, + .vsw = 3, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* AUO B101EVN06 V0 */ + [1] = { + .name = "AUO_B101EVN06_V0", + .width = 1280, + .height = 800, + .hfp = 52, + .hbp = 84, + .hsw = 36, + .vfp = 3, + .vbp = 14, + .vsw = 6, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* + * Settings from factoryset + * stored in EEPROM + */ + [2] = { + .name = "factoryset", + .width = 0, + .height = 0, + .hfp = 0, + .hbp = 0, + .hsw = 0, + .vfp = 0, + .vbp = 0, + .vsw = 0, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, +}; + +static const struct display_panel disp_panel = { + WVGA, + 32, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 32, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_backlight(void) +{ + set_gpio(BOARD_LCD_POWER, 1); + set_gpio(BOARD_BACK_LIGHT, 1); + set_gpio(BOARD_TOUCH_POWER, 1); + return 0; +} + +static int enable_pwm(void) +{ + struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; + struct pwmss_ecap_regs *ecap; + int ticks = PWM_TICKS; + int duty = PWM_DUTY; + + ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; + /* enable clock */ + setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); + /* TimeStam Counter register */ + writel(0xdb9, &ecap->tsctr); + /* config period */ + writel(ticks - 1, &ecap->cap3); + writel(ticks - 1, &ecap->cap1); + setbits_le16(&ecap->ecctl2, + (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); + /* config duty */ + writel(duty, &ecap->cap2); + writel(duty, &ecap->cap4); + /* start */ + setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); + return 0; +} + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->epwmss0clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + + return 0; +} + +static int board_video_init(void) +{ + /* set 300 MHz */ + conf_disp_pll(25, 2); + if (factory_dat.pxm50) + da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); + else + da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); + + enable_pwm(); + enable_backlight(); + + return 0; +} +#endif +#include "../common/board.c" diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h new file mode 100644 index 0000000..0362612 --- /dev/null +++ b/board/siemens/pxm2/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c new file mode 100644 index 0000000..c64b0d2 --- /dev/null +++ b/board/siemens/pxm2/mux.c @@ -0,0 +1,186 @@ +/* + * pinmux setup for siemens pxm2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ + {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +#ifndef CONFIG_NO_ETH +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; +#endif + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux lcdc_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ + {-1}, +}; + +static struct module_pin_mux ecap0_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ + {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ + {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ + {-1}, +}; +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifndef CONFIG_NO_ETH + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +#endif +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc0_pin_mux); +#endif + configure_module_pin_mux(lcdc_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(ecap0_pin_mux); +} diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h new file mode 100644 index 0000000..c6347e5 --- /dev/null +++ b/board/siemens/pxm2/pmic.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef PMIC_H +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile new file mode 100644 index 0000000..a09b467 --- /dev/null +++ b/board/siemens/rut/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c new file mode 100644 index 0000000..f2b0476 --- /dev/null +++ b/board/siemens/rut/board.c @@ -0,0 +1,432 @@ +/* + * Board functions for TI AM335X based rut board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <spi.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <video.h> +#include <watchdog.h> +#include "board.h" +#include "../common/factoryset.h" +#include "../../../drivers/video/da8xx-fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs rut_ddr3_emif_reg_data = { + .sdram_config = 0x61C04AB2, + .sdram_tim1 = 0x0888A39B, + .sdram_tim2 = 0x26337FDA, + .sdram_tim3 = 0x501F830F, + .emif_ddr_phy_ctlr_1 = 0x6, + .zq_config = 0x50074BE4, + .ref_ctrl = 0x93B, +}; + +struct ddr_data rut_ddr3_data = { + .datardsratio0 = 0x3b, + .datawdsratio0 = 0x85, + .datafwsratio0 = 0x100, + .datawrsratio0 = 0xc1, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control rut_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x40, + .cmd0dldiff = 0, + .cmd0iclkout = 1, + .cmd1csratio = 0x40, + .cmd1dldiff = 0, + .cmd1iclkout = 1, + .cmd2csratio = 0x40, + .cmd2dldiff = 0, + .cmd2iclkout = 1, +}; + + config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, + &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + +#ifndef CONFIG_SPL_BUILD + factoryset_setenv(); +#endif + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_HW_WATCHDOG) +static bool hw_watchdog_init_done; +static int hw_watchdog_trigger_level; + +void hw_watchdog_reset(void) +{ + if (!hw_watchdog_init_done) + return; + + hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; + gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); +} + +void hw_watchdog_init(void) +{ + gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); + gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); + + hw_watchdog_reset(); + + hw_watchdog_init_done = 1; +} +#endif /* defined(CONFIG_HW_WATCHDOG) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ + [0] = { + .name = "KWH043MC17-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */ + [1] = { + .name = "KWH043ST20-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */ + [2] = { + .name = "MI0430VT-1", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, +}; + +static const struct display_panel disp_panels[] = { + [0] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [1] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [2] = { + WVGA, + 24, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, +}; + +static const struct lcd_ctrl_config lcd_cfgs[] = { + [0] = { + &disp_panels[0], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [1] = { + &disp_panels[1], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [2] = { + &disp_panels[2], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 24, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + + + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; +#endif + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->spi1clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */ + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ + writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ + writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12), + &cmwkup->clkmoddplldisp); /* 0x98 */ +#endif + return 0; +} + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_lcd(void) +{ + unsigned char buf[1]; + + set_gpio(BOARD_LCD_RESET, 1); + + /* spi lcd init */ + kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3); + + /* backlight on */ + buf[0] = 0xf; + i2c_write(0x24, 0x7, 1, buf, 1); + buf[0] = 0x3f; + i2c_write(0x24, 0x8, 1, buf, 1); + return 0; +} + +int arch_early_init_r(void) +{ + enable_lcd(); + return 0; +} + +static int board_video_init(void) +{ + int i; + int anzdisp = ARRAY_SIZE(lcd_panels); + int display = 1; + + for (i = 0; i < anzdisp; i++) { + if (strncmp((const char *)factory_dat.disp_name, + lcd_panels[i].name, + strlen((const char *)factory_dat.disp_name)) == 0) { + printf("DISPLAY: %s\n", factory_dat.disp_name); + break; + } + } + if (i == anzdisp) { + i = 1; + printf("%s: %s not found, using default %s\n", __func__, + factory_dat.disp_name, lcd_panels[i].name); + } + conf_disp_pll(25, 2); + da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display], + lcd_cfgs[display].bpp); + + return 0; +} + + +#endif /* ifdef CONFIG_VIDEO */ +#include "../common/board.c" diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h new file mode 100644 index 0000000..0362612 --- /dev/null +++ b/board/siemens/rut/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c new file mode 100644 index 0000000..1eced01 --- /dev/null +++ b/board/siemens/rut/mux.c @@ -0,0 +1,347 @@ +/* + * pinmux setup for siemens rut board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux ddr_pin_mux[] = { + {OFFSET(ddr_resetn), (MODE(0))}, + {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ck), (MODE(0))}, + {OFFSET(ddr_nck), (MODE(0))}, + {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_odt), (MODE(0))}, + {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(1))}, + {OFFSET(gpmc_ad9), (MODE(1))}, + {OFFSET(gpmc_ad10), (MODE(1))}, + {OFFSET(gpmc_ad11), (MODE(1))}, + {OFFSET(gpmc_ad12), (MODE(1))}, + {OFFSET(gpmc_ad13), (MODE(1))}, + {OFFSET(gpmc_ad14), (MODE(1))}, + {OFFSET(gpmc_ad15), (MODE(1))}, + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0))}, + {OFFSET(lcd_hsync), (MODE(0))}, + {OFFSET(lcd_pclk), (MODE(0))}, + {OFFSET(lcd_ac_bias_en), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, + {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_fsr), (MODE(7))}, + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux ainx_pin_mux[] = { + {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux rtc_pin_mux[] = { + {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux pmic_pin_mux[] = { + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux osc_pin_mux[] = { + {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(gpmc_a2), (MODE(6))}, + {OFFSET(gpmc_a3), (MODE(6))}, + {-1}, +}; + +static struct module_pin_mux emu_pin_mux[] = { + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux vref_pin_mux[] = { + {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux misc_pin_mux[] = { + {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(ddr_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mii_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ainx_pin_mux); + configure_module_pin_mux(rtc_pin_mux); + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(pmic_pin_mux); + configure_module_pin_mux(osc_pin_mux); + configure_module_pin_mux(pwm_pin_mux); + configure_module_pin_mux(emu_pin_mux); + configure_module_pin_mux(vref_pin_mux); + configure_module_pin_mux(misc_pin_mux); +} diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 97fd0e4..2caefbb 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -143,7 +143,7 @@ void local_bus_init (void) get_sys_info (&sysinfo); clkdiv = lbc->lcrr & LCRR_CLKDIV; - lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; + lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ if (lbc_mhz >= 66) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 67b5246..2a30ab8 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -13,7 +13,33 @@ documented in TI's reference designs: - AM335x EVM SK - Beaglebone White - Beaglebone Black -' + +Customization +============= + +Given that all of the above boards are reference platforms (and the +Beaglebone platforms are OSHA), it is likely that this platform code and +configuration will be used as the basis of a custom platform. It is +worth noting that aside from things such as NAND or MMC only being +required if a custom platform makes use of these blocks, the following +are required, depending on design: + +- GPIO is only required if DDR3 power is controlled in a way similar to + EVM SK +- SPI is only required for SPI flash, or exposing the SPI bus. + +The following blocks are required: +- I2C, to talk with the PMIC and ensure that we do not run afoul of + errata 1.0.24. + +When removing options as part of customization, +CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your +needs and to remove no longer relevant options as in some cases we +define additional text blocks (such as for NAND or DFU strings). Also +note that all of the SPL options are grouped together, rather than with +the IP blocks, so both areas will need their choices updated to reflect +the custom design. + NAND ==== diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 728afc2..cc04426 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -30,12 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -/* MII mode defines */ -#define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0x3A - /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 @@ -242,59 +236,35 @@ int spl_start_uboot(void) } #endif -#endif +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + 266, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_evm_sk = { + 303, OSC-1, 1, -1, -1, -1, -1}; +const struct dpll_params dpll_ddr_bone_black = { + 400, OSC-1, 1, -1, -1, -1, -1}; -/* - * early system init of muxing and clocks. - */ -void s_init(void) +const struct dpll_params *get_dpll_ddr_params(void) { - __maybe_unused struct am335x_baseboard_id header; - - /* - * The ROM will only have set up sufficient pinmux to allow for the - * first 4KiB NOR to be read, we must finish doing what we know of - * the NOR mux in this space in order to continue. - */ -#ifdef CONFIG_NOR_BOOT - asm("stmfd sp!, {r2 - r4}"); - asm("movw r4, #0x8A4"); - asm("movw r3, #0x44E1"); - asm("orr r4, r4, r3, lsl #16"); - asm("mov r2, #9"); - asm("mov r3, #8"); - asm("gpmc_mux: str r2, [r4], #4"); - asm("subs r3, r3, #1"); - asm("bne gpmc_mux"); - asm("ldmfd sp!, {r2 - r4}"); -#endif - -#ifdef CONFIG_SPL_BUILD - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; + struct am335x_baseboard_id header; -#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); - /* Enable RTC32K clock */ - rtc32k_enable(); + if (board_is_evm_sk(&header)) + return &dpll_ddr_evm_sk; + else if (board_is_bone_lt(&header)) + return &dpll_ddr_bone_black; + else if (board_is_evm_15_or_later(&header)) + return &dpll_ddr_evm_sk; + else + return &dpll_ddr; +} +void set_uart_mux_conf(void) +{ #ifdef CONFIG_SERIAL1 enable_uart0_pin_mux(); #endif /* CONFIG_SERIAL1 */ @@ -313,27 +283,25 @@ void s_init(void) #ifdef CONFIG_SERIAL6 enable_uart5_pin_mux(); #endif /* CONFIG_SERIAL6 */ +} - uart_soft_reset(); +void set_mux_conf_regs(void) +{ + __maybe_unused struct am335x_baseboard_id header; + + if (read_eeprom(&header) < 0) + puts("Could not get board ID.\n"); -#if defined(CONFIG_NOR_BOOT) - /* We want our console now. */ - gd->baudrate = CONFIG_BAUDRATE; - serial_init(); - gd->have_console = 1; -#else - gd = &gdata; + enable_board_pin_mux(&header); +} - preloader_console_init(); -#endif +void sdram_init(void) +{ + __maybe_unused struct am335x_baseboard_id header; - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); - enable_board_pin_mux(&header); if (board_is_evm_sk(&header)) { /* * EVM SK 1.2A and later use gpio0_7 to enable DDR3. @@ -357,8 +325,8 @@ void s_init(void) else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. @@ -371,7 +339,7 @@ int board_init(void) STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; #endif - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); @@ -488,7 +456,7 @@ int board_eth_init(bd_t *bis) cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { - writel(RGMII_MODE_ENABLE, &cdev->miisel); + writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 5b7ed63..b2bfda5 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -239,6 +239,25 @@ static struct module_pin_mux bone_norcape_pin_mux[] = { }; #endif +#if defined(CONFIG_NOR_BOOT) +static struct module_pin_mux norboot_pin_mux[] = { + {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, + {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, + {-1}, +}; + +void enable_norboot_pin_mux(void) +{ + configure_module_pin_mux(norboot_pin_mux); +} +#endif void enable_uart0_pin_mux(void) { diff --git a/board/ti/am43xx/Makefile b/board/ti/am43xx/Makefile new file mode 100644 index 0000000..4a1bb7c --- /dev/null +++ b/board/ti/am43xx/Makefile @@ -0,0 +1,38 @@ +# +# Makefile +# +# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c new file mode 100644 index 0000000..51b2576 --- /dev/null +++ b/board/ti/am43xx/board.c @@ -0,0 +1,57 @@ +/* + * board.c + * + * Board functions for TI AM43XX based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD + +const struct dpll_params dpll_ddr = { + -1, -1, -1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + return 0; +} +#endif diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h new file mode 100644 index 0000000..8ca098b --- /dev/null +++ b/board/ti/am43xx/board.h @@ -0,0 +1,17 @@ +/* + * board.h + * + * TI AM437x boards information header + * Derived from AM335x board. + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c new file mode 100644 index 0000000..700e9a7 --- /dev/null +++ b/board/ti/am43xx/mux.c @@ -0,0 +1,27 @@ +/* + * mux.c + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mux.h> +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0))}, /* UART0_TXD */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ +} diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index 2c00648..4706330 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -14,10 +14,22 @@ #include "mux_data.h" +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/ehci.h> +#include <asm/ehci-omap.h> + +#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) +#define DIE_ID_REG_OFFSET 0x200 + +#endif + DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { - "Board: OMAP5430 EVM\n" + "Board: OMAP5432 uEVM\n" }; /** @@ -109,3 +121,85 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC, + .port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC, +}; + +static void enable_host_clocks(void) +{ + int hs_clk_ctrl_val = (OPTFCLKEN_HSIC60M_P3_CLK | + OPTFCLKEN_HSIC480M_P3_CLK | + OPTFCLKEN_HSIC60M_P2_CLK | + OPTFCLKEN_HSIC480M_P2_CLK | + OPTFCLKEN_UTMI_P3_CLK | OPTFCLKEN_UTMI_P2_CLK); + + /* Enable port 2 and 3 clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); + + /* Enable port 2 and 3 usb host ports tll clocks*/ + setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, + (OPTFCLKEN_USB_CH1_CLK_ENABLE | OPTFCLKEN_USB_CH2_CLK_ENABLE)); +} + +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int ret; + int auxclk; + int reg; + uint8_t device_mac[6]; + + enable_host_clocks(); + + if (!getenv("usbethaddr")) { + reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET; + + /* + * create a fake MAC address from the processor ID code. + * first byte is 0x02 to signify locally administered. + */ + device_mac[0] = 0x02; + device_mac[1] = readl(reg + 0x10) & 0xff; + device_mac[2] = readl(reg + 0xC) & 0xff; + device_mac[3] = readl(reg + 0x8) & 0xff; + device_mac[4] = readl(reg) & 0xff; + device_mac[5] = (readl(reg) >> 8) & 0xff; + + eth_setenv_enetaddr("usbethaddr", device_mac); + } + + auxclk = readl((*prcm)->scrm_auxclk1); + /* Request auxilary clock */ + auxclk |= AUXCLK_ENABLE_MASK; + writel(auxclk, (*prcm)->scrm_auxclk1); + + ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); + if (ret < 0) { + puts("Failed to initialize ehci\n"); + return ret; + } + + return 0; +} + +int ehci_hcd_stop(void) +{ + int ret; + + ret = omap_ehci_hcd_stop(); + return ret; +} + +void usb_hub_reset_devices(int port) +{ + /* The LAN9730 needs to be reset after the port power has been set. */ + if (port == 3) { + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0); + udelay(10); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1); + } +} +#endif diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index 612c13e..31ce363 100644 --- a/board/ti/omap5_uevm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h @@ -42,7 +42,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ - + {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */ + {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { @@ -50,6 +51,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ {SYS_32K, (IEN | M0)}, /* SYS_32K */ + {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */ }; diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 25daaa9..79270a9 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -28,7 +28,6 @@ int board_init(void) { gpmc_init(); - gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; @@ -66,7 +65,8 @@ void set_muxconf_regs_essential(void) sizeof(wkup_padconf_array_essential) / sizeof(struct pad_conf_entry)); - if (omap_revision() >= OMAP4460_ES1_0) + if ((omap_revision() >= OMAP4460_ES1_0) && + (omap_revision() < OMAP4470_ES1_0)) do_set_mux((*ctrl)->control_padconf_wkup_base, wkup_padconf_array_essential_4460, sizeof(wkup_padconf_array_essential_4460) / diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index c469645..e406326 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -27,30 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SPL_BUILD -static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; -#endif - static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; /* UART Defines */ #ifdef CONFIG_SPL_BUILD -static void uart_enable(void) -{ - /* UART softreset */ - uart_soft_reset(); -} - -static void wdt_disable(void) -{ - writel(0xAAAA, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; - writel(0x5555, &wdtimer->wdtwspr); - while (readl(&wdtimer->wdtwwps) != 0x0) - ; -} - static const struct cmd_control evm_ddr2_cctrl_data = { .cmd0csratio = 0x80, .cmd0dldiff = 0x04, @@ -100,68 +80,39 @@ static const struct ddr_data evm_ddr2_data = { .datauserank0delay = 1, .datadldiff0 = 0x4, }; -#endif -/* - * early system init of muxing and clocks. - */ -void s_init(void) +void set_uart_mux_conf(void) { -#ifdef CONFIG_SPL_BUILD - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ -#ifdef CONFIG_SPL_BUILD - save_omap_boot_params(); -#endif - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - wdt_disable(); - - /* Enable timer */ - timer_init(); - - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(); - - /* Enable RTC32K clock */ - rtc32k_enable(); - /* Set UART pins */ enable_uart0_pin_mux(); +} +void set_mux_conf_regs(void) +{ /* Set MMC pins */ enable_mmc1_pin_mux(); /* Set Ethernet pins */ enable_enet_pin_mux(); +} - /* Enable UART */ - uart_enable(); - - gd = &gdata; - - preloader_console_init(); - +void sdram_init(void) +{ config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); -#endif } +#endif /* * Basic board specific setup. Pinmux has been handled already. */ int board_init(void) { - gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile new file mode 100644 index 0000000..17ce72a --- /dev/null +++ b/board/ti/ti816x/Makefile @@ -0,0 +1,37 @@ +# +# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> +# Antoine Tenart, <atenart@adeneo-embedded.com> +# +# Based on TI-PSP-04.00.02.14 : +# +# Copyright (C) 2009, Texas Instruments, Incorporated +# +# SPDX-License-Identifier: GPL-2.0 +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := evm.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c new file mode 100644 index 0000000..74d35e9 --- /dev/null +++ b/board/ti/ti816x/evm.c @@ -0,0 +1,229 @@ +/* + * evm.c + * + * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> + * Antoine Tenart, <atenart@adeneo-embedded.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/cache.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +static struct module_pin_mux mmc_pin_mux[] = { + { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, + { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, + { -1 }, +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x80640300, + .dmm_lisa_map_3 = 0xC0640320, +}; + +/* + * DDR2 related definitions + */ +#ifdef CONFIG_TI816X_EVM_DDR2 +static struct ddr_data ddr2_data = { + .datardsratio0 = ((0x40<<10) | (0x40<<0)), + .datawdsratio0 = ((0x4A<<10) | (0x4A<<0)), + .datawiratio0 = ((0x0<<10) | (0x0<<0)), + .datagiratio0 = ((0x0<<10) | (0x0<<0)), + .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), + .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct cmd_control ddr2_ctrl = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0x04, /* reset value is 0x4 */ + .cmd0iclkout = 0x00, + + .cmd1csratio = 0x80, + .cmd1dldiff = 0x04, /* reset value is 0x4 */ + .cmd1iclkout = 0x00, + + .cmd2csratio = 0x80, + .cmd2dldiff = 0x04, /* reset value is 0x4 */ + .cmd2iclkout = 0x00, + +}; + +static struct emif_regs ddr2_emif0_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; + +static struct emif_regs ddr2_emif1_regs = { + .sdram_config = 0x43801A3A, + .ref_ctrl = 0x10000C30, + .sdram_tim1 = 0x0AAB15E2, + .sdram_tim2 = 0x423631D2, + .sdram_tim3 = 0x0080032F, + .emif_ddr_phy_ctlr_1 = 0x0, /* depend on cpu rev, set later */ +}; +#endif + +/* + * DDR3 related definitions + */ + +#if defined(CONFIG_TI816X_DDR_PLL_400) +#define RD_DQS 0x03B +#define WR_DQS 0x0A6 +#define RD_DQS_GATE 0x12A +#define EMIF_SDCFG 0x62A41032 +#define EMIF_SDREF 0x10000C30 +#define EMIF_TIM1 0x0CCCE524 +#define EMIF_TIM2 0x30308023 +#define EMIF_TIM3 0x009F82CF +#define EMIF_PHYCFG 0x0000010B +#elif defined(CONFIG_TI816X_DDR_PLL_531) +#define RD_DQS 0x039 +#define WR_DQS 0x0B4 +#define RD_DQS_GATE 0x13D +#define EMIF_SDCFG 0x62A51832 +#define EMIF_SDREF 0x1000102E +#define EMIF_TIM1 0x0EF136AC +#define EMIF_TIM2 0x30408063 +#define EMIF_TIM3 0x009F83AF +#define EMIF_PHYCFG 0x0000010C +#elif defined(CONFIG_TI816X_DDR_PLL_675) +#define RD_DQS 0x039 +#define WR_DQS 0x091 +#define RD_DQS_GATE 0x196 +#define EMIF_SDCFG 0x62A63032 +#define EMIF_SDREF 0x10001491 +#define EMIF_TIM1 0x13358875 +#define EMIF_TIM2 0x5051806C +#define EMIF_TIM3 0x009F84AF +#define EMIF_PHYCFG 0x0000010F +#elif defined(CONFIG_TI816X_DDR_PLL_796) +#define RD_DQS 0x035 +#define WR_DQS 0x093 +#define RD_DQS_GATE 0x1B3 +#define EMIF_SDCFG 0x62A73832 +#define EMIF_SDREF 0x10001841 +#define EMIF_TIM1 0x1779C9FE +#define EMIF_TIM2 0x50608074 +#define EMIF_TIM3 0x009F857F +#define EMIF_PHYCFG 0x00000110 +#endif + +static struct ddr_data ddr3_data = { + .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), + .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), + .datawiratio0 = ((0x20<<10) | 0x20<<0), + .datagiratio0 = ((0x20<<10) | 0x20<<0), + .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), + .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), + .datauserank0delay = 0x1, + .datadldiff0 = 0x0, /* depend on cpu rev, set later */ +}; + +static const struct cmd_control ddr3_ctrl = { + .cmd0csratio = 0x100, + .cmd0dldiff = 0x004, /* reset value is 0x4 */ + .cmd0iclkout = 0x001, + + .cmd1csratio = 0x100, + .cmd1dldiff = 0x004, /* reset value is 0x4 */ + .cmd1iclkout = 0x001, + + .cmd2csratio = 0x100, + .cmd2dldiff = 0x004, /* reset value is 0x4 */ + .cmd2iclkout = 0x001, +}; + +static const struct emif_regs ddr3_emif0_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +static const struct emif_regs ddr3_emif1_regs = { + .sdram_config = EMIF_SDCFG, + .ref_ctrl = EMIF_SDREF, + .sdram_tim1 = EMIF_TIM1, + .sdram_tim2 = EMIF_TIM2, + .sdram_tim3 = EMIF_TIM3, + .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, +}; + +void set_uart_mux_conf(void) {} + +void set_mux_conf_regs(void) +{ + configure_module_pin_mux(mmc_pin_mux); +} + +void sdram_init(void) +{ + config_dmm(&evm_lisa_map_regs); + +#ifdef CONFIG_TI816X_EVM_DDR2 + ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) { + ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(0, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs, 0); + } + + if (CONFIG_TI816X_USE_EMIF1) { + ddr2_emif1_regs.emif_ddr_phy_ctlr_1 = + (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); + config_ddr(1, 0, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs, 1); + } +#endif + +#ifdef CONFIG_TI816X_EVM_DDR3 + ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); + + if (CONFIG_TI816X_USE_EMIF0) + config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); + + if (CONFIG_TI816X_USE_EMIF1) + config_ddr(1, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs, 1); +#endif +} +#endif /* CONFIG_SPL_BUILD */ diff --git a/board/w7o/init.S b/board/w7o/init.S index b3aadca..490411e 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -1,26 +1,6 @@ -/****************************************************************************** - * This source code is dual-licensed. You may use it under the terms of the - * GNU General Public License version 2, or under the license below. - * - * This source code has been made available to you by IBM on an AS-IS - * basis. Anyone receiving this source is licensed under IBM - * copyrights to use it in any way he or she deems fit, including - * copying it, modifying it, compiling it, and redistributing it either - * with or without modifications. No license under IBM patents or - * patent applications is to be implied by the copyright license. - * - * Any user of this software should understand that IBM cannot provide - * technical support for this software and will not be responsible for - * any consequences resulting from the use of this software. - * - * Any person who transfers this source code or any derivative work - * must include the IBM copyright notice, this paragraph, and the - * preceding two paragraphs in the transferred software. - * - * COPYRIGHT I B M CORPORATION 1995 - * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M - * - *****************************************************************************/ +/* + * SPDX-License-Identifier: GPL-2.0 ibm-pibs + */ #include <config.h> #include <asm/ppc4xx.h> diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 0daa189..c128fcb 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -210,7 +210,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int datarate; get_sys_info(&sysinfo); - datarate = sysinfo.freqDDRBus / 1000 / 1000; + datarate = sysinfo.freq_ddrbus / 1000 / 1000; for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { if ((bopts[i].datarate_mhz_low <= datarate) && diff --git a/board/xilinx/microblaze-generic/dts/microblaze.dts b/board/xilinx/dts/microblaze-generic.dts index 2033309..2033309 100644 --- a/board/xilinx/microblaze-generic/dts/microblaze.dts +++ b/board/xilinx/dts/microblaze-generic.dts diff --git a/board/xilinx/dts/microblaze.dts b/board/xilinx/dts/microblaze.dts deleted file mode 100644 index bf984b0..0000000 --- a/board/xilinx/dts/microblaze.dts +++ /dev/null @@ -1 +0,0 @@ -/include/ BOARD_DTS diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 4bb140e..f7f1c59 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) @@ -42,6 +43,9 @@ int board_init(void) case XILINX_ZYNQ_7045: fpga = fpga045; break; + case XILINX_ZYNQ_7100: + fpga = fpga100; + break; } #endif @@ -61,6 +65,23 @@ int board_eth_init(bd_t *bis) { u32 ret = 0; +#ifdef CONFIG_XILINX_AXIEMAC + ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, + XILINX_AXIDMA_BASEADDR); +#endif +#ifdef CONFIG_XILINX_EMACLITE + u32 txpp = 0; + u32 rxpp = 0; +# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG + txpp = 1; +# endif +# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG + rxpp = 1; +# endif + ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, + txpp, rxpp); +#endif + #if defined(CONFIG_ZYNQ_GEM) # if defined(CONFIG_ZYNQ_GEM0) ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, @@ -96,5 +117,7 @@ int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + zynq_ddrc_init(); + return 0; } |