diff options
Diffstat (limited to 'board')
46 files changed, 1742 insertions, 225 deletions
diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 0e06c29..e524f35 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 101a80a..0aa5345 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 0000000..b43c3d3 --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 0000000..0daf5b5 --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,82 @@ +# +# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 0000000..2080658 --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d6497aa..0caf34f 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -46,7 +46,7 @@ int board_early_init_f(void) DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, /* SPI Flash */ MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index f5c1c3c..3a52ab2 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 43852f6..fb57faa 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -45,7 +45,7 @@ int board_early_init_f(void) MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index d48f05a..c59a326 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -48,7 +48,7 @@ int board_early_init_f(void) OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 1fd7677..adaa6a1 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -44,7 +44,7 @@ int board_early_init_f(void) RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 688d308..16efe64 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index fc88520..4f1f899 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -47,7 +47,7 @@ int board_early_init_f(void) DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index edb0886..8773e6f 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -295,6 +295,9 @@ int board_init(void) at91_macb_hw_init(); #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) + at91_uhp_hw_init(); +#endif #ifdef CONFIG_LCD at91sam9x5ek_lcd_hw_init(); #endif diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 57776fb..83eea04 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -49,9 +49,8 @@ * you can do this only with a working network connection. Therefore, a random * ethernet address is generated if none is set and a DHCP request is sent. * After a successful DHCP response is received, the network settings are - * configured and the ncip parameter is set to the serverip. Eg. for a working - * resuce mode, you should set 'next-server' to the host where the netconsole - * client is started. + * configured and the ncip is unset. Therefore, all netconsole packets are + * broadcasted. * Additionally, the bootsource is set to 'rescue'. */ @@ -76,7 +75,7 @@ int board_early_init_f(void) * Multi-Purpose Pins Functionality configuration * These strappings are taken from the original vendor uboot port. */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index bac9ce5..3b1c8ec 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -45,7 +45,7 @@ int board_early_init_f(void) POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 6c2e95b..edbb941 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -32,6 +32,7 @@ #include <netdev.h> #include <net.h> #include <i2c.h> +#include <usb.h> #include <twl4030.h> #include <linux/compiler.h> @@ -41,6 +42,8 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +#include <asm/ehci-omap.h> +#include <asm/gpio.h> #include "eeprom.h" @@ -260,6 +263,36 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/ + /* USB EHCI */ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/ + + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/ + MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/ + MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/ + + /* SB_T35_USB_HUB_RESET_GPIO */ + MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/ + /* I2C1 */ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ @@ -461,3 +494,47 @@ void __weak get_board_serial(struct tag_serialnr *serialnr) serialnr->low = 0; serialnr->high = 0; }; + +#ifdef CONFIG_USB_EHCI_OMAP +struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +#define SB_T35_USB_HUB_RESET_GPIO 167 +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + u8 val; + int offset; + + if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) { + printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset", + SB_T35_USB_HUB_RESET_GPIO); + return -1; + } + + gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0); + udelay(10); + gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); + udelay(1000); + + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1; + twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset); + /* Set GPIO6 and GPIO7 of TPS65930 as output */ + val |= 0xC0; + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset); + offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1; + /* Take both PHYs out of reset */ + twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset); + udelay(1); + + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index aaff2e8..56fe495 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; } diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 11260fe..4187901 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -44,7 +44,7 @@ int board_early_init_f(void) DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 2aa000f..b7f474e 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -274,7 +274,7 @@ int board_late_init(void) mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); - gpio_direction_output(37, 1); + gpio_direction_output(IMX_GPIO_NR(2, 5), 1); } val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 2c8cb7a..60cd4f0 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -343,14 +343,13 @@ static void setup_iomux_i2c(void) static int power_init(void) { unsigned int val; - int ret = -1; + int ret; struct pmic *p; - int retval; if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { - retval = pmic_dialog_init(I2C_PMIC); - if (retval) - return retval; + ret = pmic_dialog_init(I2C_PMIC); + if (ret) + return ret; p = pmic_get("DIALOG_PMIC"); if (!p) @@ -359,20 +358,39 @@ static int power_init(void) /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + if (ret) { + printf("Writing to BUCKCORE_REG failed: %d\n", ret); + return ret; + } - ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + pmic_reg_read(p, DA9053_SUPPLY_REG, &val); val |= DA9052_SUPPLY_VBCOREGO; - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } /* Set Vcc peripheral to 1.30V */ - ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); - ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + if (ret) { + printf("Writing to BUCKPRO_REG failed: %d\n", ret); + return ret; + } + + ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + if (ret) { + printf("Writing to SUPPLY_REG failed: %d\n", ret); + return ret; + } + + return ret; } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - retval = pmic_init(I2C_PMIC); - if (retval) - return retval; + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; p = pmic_get("FSL_PMIC"); if (!p) @@ -382,28 +400,50 @@ static int power_init(void) pmic_reg_read(p, REG_SW_0, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; ret = pmic_reg_write(p, REG_SW_0, val); + if (ret) { + printf("Writing to REG_SW_0 failed: %d\n", ret); + return ret; + } /* Set VCC as 1.30V on SW2 */ pmic_reg_read(p, REG_SW_1, &val); val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; - ret |= pmic_reg_write(p, REG_SW_1, val); + ret = pmic_reg_write(p, REG_SW_1, val); + if (ret) { + printf("Writing to REG_SW_1 failed: %d\n", ret); + return ret; + } /* Set global reset timer to 4s */ pmic_reg_read(p, REG_POWER_CTL2, &val); val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; - ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + ret = pmic_reg_write(p, REG_POWER_CTL2, val); + if (ret) { + printf("Writing to REG_POWER_CTL2 failed: %d\n", ret); + return ret; + } /* Set VUSBSEL and VUSBEN for USB PHY supply*/ pmic_reg_read(p, REG_MODE_0, &val); val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); - ret |= pmic_reg_write(p, REG_MODE_0, val); + ret = pmic_reg_write(p, REG_MODE_0, val); + if (ret) { + printf("Writing to REG_MODE_0 failed: %d\n", ret); + return ret; + } /* Set SWBST to 5V in auto mode */ val = SWBST_AUTO; - ret |= pmic_reg_write(p, SWBST_CTRL, val); + ret = pmic_reg_write(p, SWBST_CTRL, val); + if (ret) { + printf("Writing to SWBST_CTRL failed: %d\n", ret); + return ret; + } + + return ret; } - return ret; + return -1; } static void clock_1GHz(void) @@ -462,12 +502,18 @@ int board_init(void) mxc_set_sata_internal_clock(); setup_iomux_i2c(); + + lcd_enable(); + + return 0; +} + +int board_late_init(void) +{ if (!power_init()) clock_1GHz(); print_cpuinfo(); - lcd_enable(); - return 0; } diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 0240fb5..65c4a1a 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -86,6 +86,20 @@ static void setup_iomux_enet(void) gpio_set_value(IMX_GPIO_NR(1, 25), 1); } +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6Q_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + iomux_v3_cfg_t const usdhc3_pads[] = { MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -100,28 +114,82 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[1] = { +struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR}, {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, }; +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) + int board_mmc_getcd(struct mmc *mmc) { - gpio_direction_input(IMX_GPIO_NR(2, 0)); - return !gpio_get_value(IMX_GPIO_NR(2, 0)); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return !gpio_get_value(USDHC2_CD_GPIO); + case USDHC3_BASE_ADDR: + return !gpio_get_value(USDHC3_CD_GPIO); + default: + return 1; /* eMMC/uSDHC4 is always present */ + } } int board_mmc_init(bd_t *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + int i; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + return 0; } #endif diff --git a/board/h2200/h2200.c b/board/h2200/h2200.c index 3076306..720b06e 100644 --- a/board/h2200/h2200.c +++ b/board/h2200/h2200.c @@ -22,9 +22,16 @@ #include <asm/arch/pxa.h> #include <asm/arch/pxa-regs.h> #include <asm/io.h> +#include <usb.h> DECLARE_GLOBAL_DATA_PTR; +int board_eth_init(bd_t *bis) +{ + usb_eth_initialize(bis); + return 0; +} + int board_init(void) { /* We have RAM, disable cache */ @@ -36,6 +43,10 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; + /* Let host see that device is disconnected */ + udc_disconnect(); + mdelay(500); + return 0; } diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 8cfb4e6..c54c95d 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -41,7 +41,7 @@ int board_early_init_f(void) ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index a8257a3..a0f2aa3 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -72,27 +72,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 107cb7f..a41e752 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -59,27 +59,26 @@ void omap_rev_string(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else if (get_cpu_family() == CPU_OMAP34XX) { - *mcfg = NUMONYX_V_MCFG_165(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } else { - *mcfg = NUMONYX_V_MCFG_200(256 << 20); - *ctrla = NUMONYX_V_ACTIMA_200; - *ctrlb = NUMONYX_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } #endif } diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index 96410d7..7a4e7b3 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -47,7 +47,7 @@ int board_early_init_f(void) TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a90f112..6f407b7 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -121,7 +121,7 @@ int i2c_make_abort(void) { #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; /* diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 0c4dddc..eda9199 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MASK_RBI_DEFECT_16 0x01 /* Multi-Purpose Pins Functionality configuration */ -u32 kwmpp_config[] = { +static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, @@ -193,15 +193,6 @@ void set_bootcount_addr(void) int misc_init_r(void) { - char *str; - int mach_type; - - str = getenv("mach_type"); - if (str != NULL) { - mach_type = simple_strtoul(str, NULL, 10); - printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); - gd->bd->bi_arch_number = mach_type; - } #if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); @@ -258,11 +249,6 @@ int board_early_init_f(void) int board_init(void) { - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; - /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 6df2ad7..5aa0de2 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index b2f5193..e5e9942 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg index bcce907..5de8df7 100644 --- a/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ???,Reserve -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg index 3e1237b..d0a09f6 100644 --- a/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ?,Reserved -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/overo/overo.c b/board/overo/overo.c index c6d50a0..fdf46a2 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -147,34 +147,33 @@ int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = MICRON_V_MCFG_165(256 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - *mcfg = HYNIX_V_MCFG_165(256 << 20); - *ctrla = HYNIX_V_ACTIMA_165; - *ctrlb = HYNIX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_165(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_165; + timings->ctrlb = HYNIX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; default: - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 5f0f396..cf4ca51 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -45,7 +45,7 @@ int board_early_init_f(void) /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile new file mode 100644 index 0000000..196c992 --- /dev/null +++ b/board/renesas/sh7752evb/Makefile @@ -0,0 +1,36 @@ +# +# Copyright (C) 2012 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := sh7752evb.o spi-boot.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(call cmd_link_o_target, $(COBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S new file mode 100644 index 0000000..73c8ac4 --- /dev/null +++ b/board/renesas/sh7752evb/lowlevel_init.S @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> + +.macro or32, addr, data + mov.l \addr, r1 + mov.l \data, r0 + mov.l @r1, r2 + or r2, r0 + mov.l r0, @r1 +.endm + +.macro wait_DBCMD + mov.l DBWAIT_A, r0 + mov.l @r0, r1 +.endm + + .global lowlevel_init + .section .spiboot1.text + .align 2 + +lowlevel_init: + /*------- GPIO -------*/ + write16 PDCR_A, PDCR_D ! SPI0 + write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1) + write16 PJCR_A, PJCR_D ! SCIF4 + write16 PTCR_A, PTCR_D ! STATUS + write16 PSEL1_A, PSEL1_D ! SPI0 + write16 PSEL2_A, PSEL2_D ! SPI0 + write16 PSEL5_A, PSEL5_D ! STATUS + + bra exit_gpio + nop + + .align 2 + +/*------- GPIO -------*/ +PDCR_A: .long 0xffec0006 +PGCR_A: .long 0xffec000c +PJCR_A: .long 0xffec0012 +PTCR_A: .long 0xffec0026 +PSEL1_A: .long 0xffec0072 +PSEL2_A: .long 0xffec0074 +PSEL5_A: .long 0xffec007a + +PDCR_D: .long 0x0000 +PGCR_D: .long 0x0004 +PJCR_D: .long 0x0000 +PTCR_D: .long 0x0000 +PSEL1_D: .long 0x0000 +PSEL2_D: .long 0x3000 +PSEL5_D: .long 0x0ffc + + .align 2 + +exit_gpio: + mov #0, r14 + mova 2f, r0 + mov.l PC_MASK, r1 + tst r0, r1 + bf 2f + + bra exit_pmb + nop + + .align 2 + +/* If CPU runs on SDRAM (PC=0x5???????) or not. */ +PC_MASK: .long 0x20000000 + +2: + mov #1, r14 + + mov.l EXPEVT_A, r0 + mov.l @r0, r0 + mov.l EXPEVT_POWER_ON_RESET, r1 + cmp/eq r0, r1 + bt 1f + + /* + * If EXPEVT value is manual reset or tlb multipul-hit, + * initialization of DDR3IF is not necessary. + */ + bra exit_ddr + nop + +1: + /*------- Reset -------*/ + write32 MRSTCR0_A, MRSTCR0_D + write32 MRSTCR1_A, MRSTCR1_D + + /* For Core Reset */ + mov.l DBACEN_A, r0 + mov.l @r0, r0 + cmp/eq #0, r0 + bt 3f + + /* + * If DBACEN == 1(DBSC was already enabled), we have to avoid the + * initialization of DDR3-SDRAM. + */ + bra exit_ddr + nop + +3: + /*------- DDR3IF -------*/ + /* oscillation stabilization time */ + wait_timer WAIT_OSC_TIME + + /* step 3 */ + write32 DBCMD_A, DBCMD_RSTL_VAL + wait_timer WAIT_30US + + /* step 4 */ + write32 DBCMD_A, DBCMD_PDEN_VAL + + /* step 5 */ + write32 DBKIND_A, DBKIND_D + + /* step 6 */ + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBTR4_A, DBTR4_D + write32 DBTR5_A, DBTR5_D + write32 DBTR6_A, DBTR6_D + write32 DBTR7_A, DBTR7_D + write32 DBTR8_A, DBTR8_D + write32 DBTR9_A, DBTR9_D + write32 DBTR10_A, DBTR10_D + write32 DBTR11_A, DBTR11_D + write32 DBTR12_A, DBTR12_D + write32 DBTR13_A, DBTR13_D + write32 DBTR14_A, DBTR14_D + write32 DBTR15_A, DBTR15_D + write32 DBTR16_A, DBTR16_D + write32 DBTR17_A, DBTR17_D + write32 DBTR18_A, DBTR18_D + write32 DBTR19_A, DBTR19_D + write32 DBRNK0_A, DBRNK0_D + + /* step 7 */ + write32 DBPDCNT3_A, DBPDCNT3_D + + /* step 8 */ + write32 DBPDCNT1_A, DBPDCNT1_D + write32 DBPDCNT2_A, DBPDCNT2_D + write32 DBPDLCK_A, DBPDLCK_D + write32 DBPDRGA_A, DBPDRGA_D + write32 DBPDRGD_A, DBPDRGD_D + + /* step 9 */ + wait_timer WAIT_30US + + /* step 10 */ + write32 DBPDCNT0_A, DBPDCNT0_D + + /* step 11 */ + wait_timer WAIT_30US + wait_timer WAIT_30US + + /* step 12 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + wait_DBCMD + + /* step 13 */ + write32 DBCMD_A, DBCMD_RSTH_VAL + wait_DBCMD + + /* step 14 */ + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + write32 DBCMD_A, DBCMD_WAIT_VAL + + /* step 15 */ + write32 DBCMD_A, DBCMD_PDXT_VAL + + /* step 16 */ + write32 DBCMD_A, DBCMD_MRS2_VAL + + /* step 17 */ + write32 DBCMD_A, DBCMD_MRS3_VAL + + /* step 18 */ + write32 DBCMD_A, DBCMD_MRS1_VAL + + /* step 19 */ + write32 DBCMD_A, DBCMD_MRS0_VAL + + /* step 20 */ + write32 DBCMD_A, DBCMD_ZQCL_VAL + + write32 DBCMD_A, DBCMD_REF_VAL + write32 DBCMD_A, DBCMD_REF_VAL + wait_DBCMD + + /* step 21 */ + write32 DBADJ0_A, DBADJ0_D + write32 DBADJ1_A, DBADJ1_D + write32 DBADJ2_A, DBADJ2_D + + /* step 22 */ + write32 DBRFCNF0_A, DBRFCNF0_D + write32 DBRFCNF1_A, DBRFCNF1_D + write32 DBRFCNF2_A, DBRFCNF2_D + + /* step 23 */ + write32 DBCALCNF_A, DBCALCNF_D + + /* step 24 */ + write32 DBRFEN_A, DBRFEN_D + write32 DBCMD_A, DBCMD_SRXT_VAL + + /* step 25 */ + write32 DBACEN_A, DBACEN_D + + /* step 26 */ + wait_DBCMD + + bra exit_ddr + nop + + .align 2 + +EXPEVT_A: .long 0xff000024 +EXPEVT_POWER_ON_RESET: .long 0x00000000 + +/*------- Reset -------*/ +MRSTCR0_A: .long 0xffd50030 +MRSTCR0_D: .long 0xfe1ffe7f +MRSTCR1_A: .long 0xffd50034 +MRSTCR1_D: .long 0xfff3ffff + +/*------- DDR3IF -------*/ +DBCMD_A: .long 0xfe800018 +DBKIND_A: .long 0xfe800020 +DBCONF_A: .long 0xfe800024 +DBTR0_A: .long 0xfe800040 +DBTR1_A: .long 0xfe800044 +DBTR2_A: .long 0xfe800048 +DBTR3_A: .long 0xfe800050 +DBTR4_A: .long 0xfe800054 +DBTR5_A: .long 0xfe800058 +DBTR6_A: .long 0xfe80005c +DBTR7_A: .long 0xfe800060 +DBTR8_A: .long 0xfe800064 +DBTR9_A: .long 0xfe800068 +DBTR10_A: .long 0xfe80006c +DBTR11_A: .long 0xfe800070 +DBTR12_A: .long 0xfe800074 +DBTR13_A: .long 0xfe800078 +DBTR14_A: .long 0xfe80007c +DBTR15_A: .long 0xfe800080 +DBTR16_A: .long 0xfe800084 +DBTR17_A: .long 0xfe800088 +DBTR18_A: .long 0xfe80008c +DBTR19_A: .long 0xfe800090 +DBRNK0_A: .long 0xfe800100 +DBPDCNT0_A: .long 0xfe800200 +DBPDCNT1_A: .long 0xfe800204 +DBPDCNT2_A: .long 0xfe800208 +DBPDCNT3_A: .long 0xfe80020c +DBPDLCK_A: .long 0xfe800280 +DBPDRGA_A: .long 0xfe800290 +DBPDRGD_A: .long 0xfe8002a0 +DBADJ0_A: .long 0xfe8000c0 +DBADJ1_A: .long 0xfe8000c4 +DBADJ2_A: .long 0xfe8000c8 +DBRFCNF0_A: .long 0xfe8000e0 +DBRFCNF1_A: .long 0xfe8000e4 +DBRFCNF2_A: .long 0xfe8000e8 +DBCALCNF_A: .long 0xfe8000f4 +DBRFEN_A: .long 0xfe800014 +DBACEN_A: .long 0xfe800010 +DBWAIT_A: .long 0xfe80001c + +WAIT_OSC_TIME: .long 6000 +WAIT_30US: .long 13333 + +DBCMD_RSTL_VAL: .long 0x20000000 +DBCMD_PDEN_VAL: .long 0x1000d73c +DBCMD_WAIT_VAL: .long 0x0000d73c +DBCMD_RSTH_VAL: .long 0x2100d73c +DBCMD_PDXT_VAL: .long 0x110000c8 +DBCMD_MRS0_VAL: .long 0x28000930 +DBCMD_MRS1_VAL: .long 0x29000004 +DBCMD_MRS2_VAL: .long 0x2a000008 +DBCMD_MRS3_VAL: .long 0x2b000000 +DBCMD_ZQCL_VAL: .long 0x03000200 +DBCMD_REF_VAL: .long 0x0c000000 +DBCMD_SRXT_VAL: .long 0x19000000 +DBKIND_D: .long 0x00000007 +DBCONF_D: .long 0x0f030a01 +DBTR0_D: .long 0x00000007 +DBTR1_D: .long 0x00000006 +DBTR2_D: .long 0x00000000 +DBTR3_D: .long 0x00000007 +DBTR4_D: .long 0x00070007 +DBTR5_D: .long 0x0000001b +DBTR6_D: .long 0x00000014 +DBTR7_D: .long 0x00000005 +DBTR8_D: .long 0x00000015 +DBTR9_D: .long 0x00000006 +DBTR10_D: .long 0x00000008 +DBTR11_D: .long 0x00000007 +DBTR12_D: .long 0x0000000e +DBTR13_D: .long 0x00000056 +DBTR14_D: .long 0x00000006 +DBTR15_D: .long 0x00000004 +DBTR16_D: .long 0x00150002 +DBTR17_D: .long 0x000c0017 +DBTR18_D: .long 0x00000200 +DBTR19_D: .long 0x00000040 +DBRNK0_D: .long 0x00000001 +DBPDCNT0_D: .long 0x00000001 +DBPDCNT1_D: .long 0x00000001 +DBPDCNT2_D: .long 0x00000000 +DBPDCNT3_D: .long 0x00004010 +DBPDLCK_D: .long 0x0000a55a +DBPDRGA_D: .long 0x00000028 +DBPDRGD_D: .long 0x00017100 + +DBADJ0_D: .long 0x00000000 +DBADJ1_D: .long 0x00000000 +DBADJ2_D: .long 0x18061806 +DBRFCNF0_D: .long 0x000001ff +DBRFCNF1_D: .long 0x08001000 +DBRFCNF2_D: .long 0x00000000 +DBCALCNF_D: .long 0x0000ffff +DBRFEN_D: .long 0x00000001 +DBACEN_D: .long 0x00000001 + + .align 2 +exit_ddr: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + */ + write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D + write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + + write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D + write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif /* if defined(CONFIG_SH_32BIT) */ + +exit_pmb: + /* CPU is running on ILRAM? */ + mov r14, r0 + tst #1, r0 + bt 1f + + mov.l _stack_ilram, r15 + mov.l _spiboot_main, r0 +100: bsrf r0 + nop + + .align 2 +_spiboot_main: .long (spiboot_main - (100b + 4)) +_stack_ilram: .long 0xe5204000 + +1: + write32 CCR_A, CCR_D + + rts + nop + + .align 2 + +#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) +PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) +PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) +PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) +PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) +PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) +PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) +PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) +PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) +PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) +PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) +PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) +PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) +PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) + +PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_NOT_USE_D: .long 0x00000000 + +PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) + +PASCR_A: .long 0xff000070 +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + +CCR_A: .long CCR +CCR_D: .long CCR_CACHE_INIT diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c new file mode 100644 index 0000000..e996593 --- /dev/null +++ b/board/renesas/sh7752evb/sh7752evb.c @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/mmc.h> +#include <spi_flash.h> + +int checkboard(void) +{ + puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); + + return 0; +} + +static void init_gpio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + struct sermux_regs *sermux = SERMUX_BASE; + + /* GPIO */ + writew(0x0000, &gpio->pacr); /* GETHER */ + writew(0x0001, &gpio->pbcr); /* INTC */ + writew(0x0000, &gpio->pccr); /* PWMU, INTC */ + writew(0xeaff, &gpio->pecr); /* GPIO */ + writew(0x0000, &gpio->pfcr); /* WDT */ + writew(0x0000, &gpio->phcr); /* SPI1 */ + writew(0x0000, &gpio->picr); /* SDHI */ + writew(0x0003, &gpio->pkcr); /* SerMux */ + writew(0x0000, &gpio->plcr); /* SerMux */ + writew(0x0000, &gpio->pmcr); /* RIIC */ + writew(0x0000, &gpio->pncr); /* USB, SGPIO */ + writew(0x0000, &gpio->pocr); /* SGPIO */ + writew(0xd555, &gpio->pqcr); /* GPIO */ + writew(0x0000, &gpio->prcr); /* RIIC */ + writew(0x0000, &gpio->pscr); /* RIIC */ + writeb(0x00, &gpio->pudr); + writew(0x5555, &gpio->pucr); /* Debug LED */ + writew(0x0000, &gpio->pvcr); /* RSPI */ + writew(0x0000, &gpio->pwcr); /* EVC */ + writew(0x0000, &gpio->pxcr); /* LBSC */ + writew(0x0000, &gpio->pycr); /* LBSC */ + writew(0x0000, &gpio->pzcr); /* eMMC */ + writew(0xfe00, &gpio->psel0); + writew(0xff00, &gpio->psel3); + writew(0x771f, &gpio->psel4); + writew(0x00ff, &gpio->psel6); + writew(0xfc00, &gpio->psel7); + + writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ +} + +static void init_usb_phy(void) +{ + struct usb_common_regs *common0 = USB0_COMMON_BASE; + struct usb_common_regs *common1 = USB1_COMMON_BASE; + struct usb0_phy_regs *phy = USB0_PHY_BASE; + struct usb1_port_regs *port = USB1_PORT_BASE; + struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; + + writew(0x0100, &phy->reset); /* set reset */ + /* port0 = USB0, port1 = USB1 */ + writew(0x0002, &phy->portsel); + writel(0x0001, &port->port1sel); /* port1 = Host */ + writew(0x0111, &phy->reset); /* clear reset */ + + writew(0x4000, &common0->suspmode); + writew(0x4000, &common1->suspmode); + +#if defined(__LITTLE_ENDIAN) + writel(0x00000000, &align->ehcidatac); + writel(0x00000000, &align->ohcidatac); +#endif +} + +static void init_gether_mdio(void) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); + writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ +} + +static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) +{ + struct ether_mac_regs *ether; + unsigned char mac[6]; + unsigned long val; + + eth_parse_enetaddr(mac_string, mac); + + if (!channel) + ether = GETHER0_MAC_BASE; + else + ether = GETHER1_MAC_BASE; + + val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; + writel(val, ðer->mahr); + val = (mac[4] << 8) | mac[5]; + writel(val, ðer->malr); +} + +/***************************************************************** + * This PMB must be set on this timing. The lowlevel_init is run on + * Area 0(phys 0x00000000), so we have to map it. + * + * The new PMB table is following: + * ent virt phys v sz c wt + * 0 0xa0000000 0x40000000 1 128M 0 1 + * 1 0xa8000000 0x48000000 1 128M 0 1 + * 2 0xb0000000 0x50000000 1 128M 0 1 + * 3 0xb8000000 0x58000000 1 128M 0 1 + * 4 0x80000000 0x40000000 1 128M 1 1 + * 5 0x88000000 0x48000000 1 128M 1 1 + * 6 0x90000000 0x50000000 1 128M 1 1 + * 7 0x98000000 0x58000000 1 128M 1 1 + */ +static void set_pmb_on_board_init(void) +{ + struct mmu_regs *mmu = MMU_BASE; + + /* clear ITLB */ + writel(0x00000004, &mmu->mmucr); + + /* delete PMB for SPIBOOT */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + /* ppn ub v s1 s0 c wt */ + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); + writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); + writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); + writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); + writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); + writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); + writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); + writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); + writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); +} + +int board_init(void) +{ + init_gpio(); + set_pmb_on_board_init(); + + init_usb_phy(); + init_gether_mdio(); + + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + struct gpio_regs *gpio = GPIO_BASE; + + writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); + writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ + udelay(1); + writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ + udelay(200); + + return mmcif_mmc_init(); +} + +static int get_sh_eth_mac_raw(unsigned char *buf, int size) +{ + struct spi_flash *spi; + int ret; + + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (spi == NULL) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); + if (ret) { + printf("%s: spi_flash read failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + return 0; +} + +static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) +{ + memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], + SH7752EVB_ETHERNET_MAC_SIZE); + mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ + + return 0; +} + +static void init_ethernet_mac(void) +{ + char mac_string[64]; + char env_string[64]; + int i; + unsigned char *buf; + + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return; + } + get_sh_eth_mac_raw(buf, 256); + + /* Gigabit Ethernet */ + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + if (i == 0) + setenv("ethaddr", mac_string); + else { + sprintf(env_string, "eth%daddr", i); + setenv(env_string, mac_string); + } + set_mac_to_sh_giga_eth_register(i, mac_string); + } + + free(buf); +} + +int board_late_init(void) +{ + init_ethernet_mac(); + + return 0; +} + +int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i, ret; + char mac_string[256]; + struct spi_flash *spi; + unsigned char *buf; + + if (argc != 3) { + buf = malloc(256); + if (!buf) { + printf("%s: malloc failed.\n", __func__); + return 1; + } + + get_sh_eth_mac_raw(buf, 256); + + /* print current MAC address */ + for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { + get_sh_eth_mac(i, mac_string, buf); + printf("GETHERC ch%d = %s\n", i, mac_string); + } + free(buf); + return 0; + } + + /* new setting */ + memset(mac_string, 0xff, sizeof(mac_string)); + sprintf(mac_string, "%s\t%s", + argv[1], argv[2]); + + /* write MAC data to SPI rom */ + spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); + if (!spi) { + printf("%s: spi_flash probe failed.\n", __func__); + return 1; + } + + ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, + SH7752EVB_SPI_SECTOR_SIZE); + if (ret) { + printf("%s: spi_flash erase failed.\n", __func__); + return 1; + } + + ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, + sizeof(mac_string), mac_string); + if (ret) { + printf("%s: spi_flash write failed.\n", __func__); + spi_flash_free(spi); + return 1; + } + spi_flash_free(spi); + + puts("The writing of the MAC address to SPI ROM was completed.\n"); + + return 0; +} + +U_BOOT_CMD( + write_mac, 3, 1, do_write_mac, + "write MAC address for GETHERC", + "[GETHERC ch0] [GETHERC ch1]\n" +); diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c new file mode 100644 index 0000000..91565d4 --- /dev/null +++ b/board/renesas/sh7752evb/spi-boot.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License. See the file "COPYING.LIB" in the main + * directory of this archive for more details. + */ + +#include <common.h> + +#define CONFIG_RAM_BOOT_PHYS CONFIG_SYS_TEXT_BASE +#define CONFIG_SPI_ADDR 0x00000000 +#define CONFIG_SPI_LENGTH CONFIG_SYS_MONITOR_LEN +#define CONFIG_RAM_BOOT CONFIG_SYS_TEXT_BASE + +#define SPIWDMADR 0xFE001018 +#define SPIWDMCNTR 0xFE001020 +#define SPIDMCOR 0xFE001028 +#define SPIDMINTSR 0xFE001188 +#define SPIDMINTMR 0xFE001190 + +#define SPIDMINTSR_DMEND 0x00000004 + +#define TBR 0xFE002000 +#define RBR 0xFE002000 + +#define CR1 0xFE002008 +#define CR2 0xFE002010 +#define CR3 0xFE002018 +#define CR4 0xFE002020 + +/* CR1 */ +#define SPI_TBE 0x80 +#define SPI_TBF 0x40 +#define SPI_RBE 0x20 +#define SPI_RBF 0x10 +#define SPI_PFONRD 0x08 +#define SPI_SSDB 0x04 +#define SPI_SSD 0x02 +#define SPI_SSA 0x01 + +/* CR2 */ +#define SPI_RSTF 0x80 +#define SPI_LOOPBK 0x40 +#define SPI_CPOL 0x20 +#define SPI_CPHA 0x10 +#define SPI_L1M0 0x08 + +/* CR4 */ +#define SPI_TBEI 0x80 +#define SPI_TBFI 0x40 +#define SPI_RBEI 0x20 +#define SPI_RBFI 0x10 +#define SPI_SpiS0 0x02 +#define SPI_SSS 0x01 + +#define spi_write(val, addr) (*(volatile unsigned long *)(addr)) = val +#define spi_read(addr) (*(volatile unsigned long *)(addr)) + +/* M25P80 */ +#define M25_READ 0x03 + +#define __uses_spiboot2 __attribute__((section(".spiboot2.text"))) +static void __uses_spiboot2 spi_reset(void) +{ + int timeout = 0x00100000; + + /* Make sure the last transaction is finalized */ + spi_write(0x00, CR3); + spi_write(0x02, CR1); + while (!(spi_read(CR4) & SPI_SpiS0)) { + if (timeout-- < 0) + break; + } + spi_write(0x00, CR1); + + spi_write(spi_read(CR2) | SPI_RSTF, CR2); /* fifo reset */ + spi_write(spi_read(CR2) & ~SPI_RSTF, CR2); + + spi_write(0, SPIDMCOR); +} + +static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr, + unsigned long len) +{ + spi_write(M25_READ, TBR); + spi_write((addr >> 16) & 0xFF, TBR); + spi_write((addr >> 8) & 0xFF, TBR); + spi_write(addr & 0xFF, TBR); + + spi_write(SPIDMINTSR_DMEND, SPIDMINTSR); + spi_write((unsigned long)buf, SPIWDMADR); + spi_write(len & 0xFFFFFFE0, SPIWDMCNTR); + spi_write(1, SPIDMCOR); + + spi_write(0xff, CR3); + spi_write(spi_read(CR1) | SPI_SSDB, CR1); + spi_write(spi_read(CR1) | SPI_SSA, CR1); + + while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND)) + ; + + /* Nagate SP0-SS0 */ + spi_write(0, CR1); +} + +void __uses_spiboot2 spiboot_main(void) +{ + void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE; + + spi_reset(); + spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR, + CONFIG_SPI_LENGTH); + + _start(); +} diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds new file mode 100644 index 0000000..28449b6 --- /dev/null +++ b/board/renesas/sh7752evb/u-boot.lds @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2007 + * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * + * Copyright (C) 2012 + * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux") +OUTPUT_ARCH(sh) +ENTRY(_start) + +SECTIONS +{ + /* + * entry and reloct_dst will be provided via ldflags + */ + . = .; + + PROVIDE (_ftext = .); + PROVIDE (_fcode = .); + PROVIDE (_start = .); + + .text : + { + KEEP(arch/sh/cpu/sh4/start.o (.text)) + *(.spiboot1.text) + *(.spiboot2.text) + . = ALIGN(8192); + common/env_embedded.o (.ppcenv) + . = ALIGN(8192); + common/env_embedded.o (.ppcenvr) + . = ALIGN(8192); + *(.text) + . = ALIGN(4); + } =0xFF + PROVIDE (_ecode = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + . = ALIGN(4); + } + PROVIDE (_etext = .); + + + PROVIDE (_fdata = .); + .data : + { + *(.data) + . = ALIGN(4); + } + PROVIDE (_edata = .); + + PROVIDE (_fgot = .); + .got : + { + *(.got) + . = ALIGN(4); + } + PROVIDE (_egot = .); + + .u_boot_list : { + #include <u-boot.lst> + } + + PROVIDE (reloc_dst_end = .); + /* _reloc_dst_end = .; */ + + PROVIDE (bss_start = .); + PROVIDE (__bss_start = .); + .bss (NOLOAD) : + { + *(.bss) + . = ALIGN(4); + } + PROVIDE (bss_end = .); + + PROVIDE (__bss_end__ = .); +} diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 1471559..c9eea9b 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -98,9 +98,12 @@ int board_init(void) return 0; } +#ifndef CONFIG_SPL_BUILD int misc_init_r(void) { char *eth_addr; + struct tam3517_module_info info; + int ret; dieid_num_r(); @@ -108,12 +111,13 @@ int misc_init_r(void) if (eth_addr) return 0; -#ifndef CONFIG_SPL_BUILD - TAM3517_READ_MAC_FROM_EEPROM; -#endif + TAM3517_READ_EEPROM(&info, ret); + if (!ret) + TAM3517_READ_MAC_FROM_EEPROM(&info); return 0; } +#endif /* * Routine: set_muxconf_regs diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index 9622a81..c516c75 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -73,10 +73,10 @@ static struct { static struct panel_config lcd_cfg[] = { { - .timing_h = PANEL_TIMING_H(4, 8, 41), - .timing_v = PANEL_TIMING_V(2, 4, 10), - .pol_freq = 0x00000000, /* Pol Freq */ - .divisor = 0x0001000d, /* 33Mhz Pixel Clock */ + .timing_h = PANEL_TIMING_H(40, 5, 2), + .timing_v = PANEL_TIMING_V(8, 8, 2), + .pol_freq = 0x00003000, /* Pol Freq */ + .divisor = 0x00010033, /* 9 Mhz Pixel Clock */ .panel_type = 0x01, /* TFT */ .data_lines = 0x03, /* 24 Bit RGB */ .load_mode = 0x02, /* Frame Mode */ @@ -258,21 +258,26 @@ int board_init(void) return 0; } +#ifndef CONFIG_SPL_BUILD int misc_init_r(void) { char *eth_addr; + struct tam3517_module_info info; + int ret; + TAM3517_READ_EEPROM(&info, ret); dieid_num_r(); - eth_addr = getenv("ethaddr"); - if (eth_addr) + if (ret) return 0; + eth_addr = getenv("ethaddr"); + if (!eth_addr) + TAM3517_READ_MAC_FROM_EEPROM(&info); -#ifndef CONFIG_SPL_BUILD - TAM3517_READ_MAC_FROM_EEPROM; -#endif + TAM3517_PRINT_SOM_INFO(&info); return 0; } +#endif /* * Routine: set_muxconf_regs diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f0eca54..ed4229e 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -44,7 +44,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; /* MII mode defines */ #define MII_MODE_ENABLE 0x0 -#define RGMII_MODE_ENABLE 0xA +#define RGMII_MODE_ENABLE 0x3A /* GPIO that controls power to DDR on EVM-SK */ #define GPIO_DDR_VTT_EN 7 @@ -318,6 +318,8 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + gpmc_init(); + return 0; } diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 8437ef5..0283708 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,6 +171,25 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, }; +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + void enable_uart0_pin_mux(void) { configure_module_pin_mux(uart0_pin_mux); @@ -257,6 +276,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) /* In profile #2 i2c1 and spi0 conflict. */ if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); + /* Profiles 2 & 3 don't have NAND */ + if (profile & ~(PROFILE_2 | PROFILE_3)) + configure_module_pin_mux(nand_pin_mux); else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux); diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index f20ebed..b829a79 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -144,8 +144,7 @@ static int get_board_revision(void) * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -156,29 +155,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, */ identify_nand_chip(&pop_mfr, &pop_id); - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; switch (get_board_revision()) { case REVISION_C4: if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { /* Beagleboard Rev C5, 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; } case REVISION_XM_A: @@ -186,24 +185,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, case REVISION_XM_C: if (pop_mfr == 0) { /* 256MB DDR */ - *mcfg = MICRON_V_MCFG_200(256 << 20); - *ctrla = MICRON_V_ACTIMA_200; - *ctrlb = MICRON_V_ACTIMB_200; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } else { /* 512MB DDR */ - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = NUMONYX_V_MCFG_165(512 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } break; default: /* Assume 128MB and Micron/165MHz timings to be safe */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; } } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 61fc7b5..8a3aa0c 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -128,8 +128,7 @@ int board_init(void) * provides the timing values back to the function that configures * the memory. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { int pop_mfr, pop_id; @@ -142,17 +141,17 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { /* 256MB DDR */ - *mcfg = HYNIX_V_MCFG_200(256 << 20); - *ctrla = HYNIX_V_ACTIMA_200; - *ctrlb = HYNIX_V_ACTIMB_200; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; } else { /* 128MB DDR */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; } - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - *mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mr = MICRON_V_MR_165; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 35f5e15..85685ee 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -188,16 +188,15 @@ int spl_start_uboot(void) * provides the timing values back to the function that configures * the memory. We have either one or two banks of 128MB DDR. */ -void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, - u32 *mr) +void get_board_mem_timings(struct board_sdrc_timings *timings) { /* General SDRC config */ - *mcfg = MICRON_V_MCFG_165(128 << 20); - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; /* AC timings */ - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; - *mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; } |