diff options
Diffstat (limited to 'board')
29 files changed, 556 insertions, 249 deletions
diff --git a/board/gdsys/neo/Makefile b/board/AndesTech/adp-ag102/Makefile index dc5b5b8..1cbf2d4 100644 --- a/board/gdsys/neo/Makefile +++ b/board/AndesTech/adp-ag102/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. +# Copyright (C) 2011 Andes Technology Corporation +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> # # See file CREDITS for list of people who contributed to this # project. @@ -25,15 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o -SOBJS = +COBJS := adp-ag102.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/AndesTech/adp-ag102/adp-ag102.c b/board/AndesTech/adp-ag102/adp-ag102.c new file mode 100644 index 0000000..5a25632 --- /dev/null +++ b/board/AndesTech/adp-ag102/adp-ag102.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <faraday/ftsdc010.h> +#ifdef CONFIG_FTSMC020 +#include <faraday/ftsmc020.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ + +int board_init(void) +{ + /* + * refer to BOOT_PARAMETER_PA_BASE within + * "linux/arch/nds32/include/asm/misc_spec.h" + */ + gd->bd->bi_arch_number = MACH_TYPE_ADPAG102; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + +#if !defined(CONFIG_SYS_NO_FLASH) + ftsmc020_init(); /* initialize Flash */ +#endif /* CONFIG_SYS_NO_FLASH */ + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + + gd->ram_size = actual_size; + + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftgmac100_initialize(bd); +} + +#if !defined(CONFIG_SYS_NO_FLASH) +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else { + return 0; + } +} +#endif /* CONFIG_SYS_NO_FLASH */ + +#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) +void pci_init_board(void) +{ + /* should be pci_ftpci100_init() */ + extern void pci_ftpci_init(); + + pci_ftpci_init(); +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + ftsdc010_mmc_init(0); + return 0; +} +#endif diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 09ef561..c4566dd 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,6 +48,19 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), +#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), +#endif +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 6a0026a..da21627 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIOBOOT_SLAVE) + /* + * SRIOBOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, + CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -138,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE + /* + * SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode + * and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index b1eecc4..a33c936 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -62,10 +62,6 @@ int checkboard (void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); -#ifdef CONFIG_PHYS_64BIT - puts("36-bit Addressing\n"); -#endif - /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index c9f85c8..6d0bfde 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -68,12 +68,7 @@ int checkboard (void) u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; - puts("Board: MPC8536DS "); -#ifdef CONFIG_PHYS_64BIT - puts("(36-bit addrmap) "); -#endif - - printf ("Sys ID: 0x%02x, " + printf("Board: MPC8536DS Sys ID: 0x%02x, " "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index b20299e..33a02ba 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -45,11 +45,7 @@ int checkboard (void) u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; - puts ("Board: MPC8572DS "); -#ifdef CONFIG_PHYS_64BIT - puts ("(36-bit addrmap) "); -#endif - printf ("Sys ID: 0x%02x, " + printf("Board: MPC8572DS Sys ID: 0x%02x, " "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 455569e..6a0a3a2 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -50,9 +50,6 @@ int checkboard(void) else puts ("Promjet\n"); -#ifdef CONFIG_PHYS_64BIT - printf (" 36-bit physical address map\n"); -#endif return 0; } diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index e5d8423..36c8545 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CONFIG_DDR_RAW_TIMING +#ifndef CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DRAM_SIZE 1024 fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { @@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } -#else /* CONFIG_DDR_RAW_TIMING */ +#else /* CONFIG_SYS_DDR_RAW_TIMING */ /* * Samsung K4B2G0846C-HCF8 * The following timing are for "downshift" @@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts, } } -#endif /* CONFIG_DDR_RAW_TIMING */ +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index b9e66f7..79a6ead 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -165,11 +165,7 @@ int checkboard(void) struct cpu_type *cpu; cpu = gd->cpu; - printf("Board: %sRDB ", cpu->name); -#ifdef CONFIG_PHYS_64BIT - puts("(36-bit addrmap)"); -#endif - puts("\n"); + printf("Board: %sRDB\n", cpu->name); return 0; } diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 456d9b0..aca30f3 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -56,12 +56,8 @@ int checkboard(void) { u8 sw; - puts("Board: P1022DS "); -#ifdef CONFIG_PHYS_64BIT - puts("(36-bit addrmap) "); -#endif - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + printf("Board: P1022DS Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 546819c..082976a 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -197,6 +197,12 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); + /* By default NOR is on, and NAND is disabled */ +#ifdef CONFIG_NAND_U_BOOT + do_fixup_by_path_string(blob, "nor_flash", "status", "disabled"); + do_fixup_by_path_string(blob, "nand_flash", "status", "okay"); +#endif + fdt_fixup_fman_ethernet(blob); } #endif diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index cfbae69..437eaf0 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -110,9 +110,7 @@ int checkboard (void) cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); -#ifdef CONFIG_PHYS_64BIT - puts ("(36-bit addrmap) \n"); -#endif + setbits_be32(&pgpio->gpdir, GPIO_DIR); /* diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index f0cbde7..88ba56f 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <asm/fsl_law.h> -#ifdef CONFIG_DDR_RAW_TIMING +#ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_P1020RDB_PROTO) || \ defined(CONFIG_P1021RDB) || \ defined(CONFIG_P1020UTM) @@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, return 0; } -#endif /* CONFIG_DDR_RAW_TIMING */ +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a60c5a2..aa39260 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -225,13 +225,7 @@ int checkboard(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, io_config, val; - printf("Board: %s ", CONFIG_BOARDNAME); - -#ifdef CONFIG_PHYS_64BIT - puts("(36-bit addrmap) "); -#endif - - printf("CPLD: V%d.%d PCBA: V%d.0\n", + printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME, in_8(&cpld_data->cpld_rev_major) & 0x0F, in_8(&cpld_data->cpld_rev_minor) & 0x0F, in_8(&cpld_data->pcba_rev) & 0x0F); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index d3af6cf..e8d31a4 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -61,12 +61,8 @@ int checkboard(void) { u8 sw; - puts("Board: P2020DS "); -#ifdef CONFIG_PHYS_64BIT - puts("(36-bit addrmap) "); -#endif - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + printf("Board: P2020DS Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 1f6a34b..976c8d2 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -54,10 +54,6 @@ int checkboard(void) sw = CPLD_READ(fbank_sel); printf("vBank: %d\n", sw & 0x1); -#ifdef CONFIG_PHYS_64BIT - puts("36-bit Addressing\n"); -#endif - /* * Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c index c6c74f2..c7cca2a 100644 --- a/board/freescale/p3060qds/p3060qds.c +++ b/board/freescale/p3060qds/p3060qds.c @@ -68,9 +68,6 @@ int checkboard(void) else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); -#ifdef CONFIG_PHYS_64BIT - puts("36-bit Addressing\n"); -#endif puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 8b80533..bc9b7d0 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -28,12 +28,9 @@ #include <asm/ppc4xx-gpio.h> #include <asm/global_data.h> +#include "405ep.h" #include <gdsys_fpga.h> -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) @@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev) int board_early_init_f(void) { unsigned k; - unsigned ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->fpga_state[k] = 0; @@ -73,26 +69,29 @@ int board_early_init_f(void) * -> ca. 15 us */ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ + return 0; +} - /* - * setup io-latches for reset - */ - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; /* - * wait for fpga-done + * reset FPGA */ + gd405ep_init(); + + gd405ep_set_fpga_reset(1); + + gd405ep_setup_hw(); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; - while (!(in_le16((void *)LATCH2_BASE) - & CONFIG_SYS_FPGA_DONE(k))) { + while (!gd405ep_get_fpga_done(k)) { udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -101,15 +100,13 @@ int board_early_init_f(void) } } - /* - * setup io-latches for boot (stop reset) - */ udelay(10); - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + + gd405ep_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); + struct ihs_fpga *fpga = + (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); #ifdef CONFIG_SYS_FPGA_NO_RFL_HI u16 *reflection_target = &fpga->reflection_low; #else diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h new file mode 100644 index 0000000..5647dbc --- /dev/null +++ b/board/gdsys/405ep/405ep.h @@ -0,0 +1,10 @@ +#ifndef __405EP_H_ +#define __405EP_H_ + +/* functions to be provided by board implementation */ +void gd405ep_init(void); +void gd405ep_set_fpga_reset(unsigned state); +void gd405ep_setup_hw(void); +int gd405ep_get_fpga_done(unsigned fpga); + +#endif /* __405EP_H_ */ diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile index feb5cec..38e5ea4 100644 --- a/board/gdsys/405ep/Makefile +++ b/board/gdsys/405ep/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS-$(CONFIG_NEO) += neo.o COBJS-$(CONFIG_IO) += io.o COBJS-$(CONFIG_IOCON) += iocon.o COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index f55afbd..644493b 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -26,16 +26,20 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include <dtt.h> +#include "405ep.h" #include <gdsys_fpga.h> #include "../common/osd.h" +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH2_MC2_PRESENT_N 0x0080 - #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) +#define LATCH2_MC2_PRESENT_N 0x0080 + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -46,6 +50,8 @@ enum { enum { HWVER_101 = 0, HWVER_110 = 1, + HWVER_120 = 2, + HWVER_130 = 3, }; enum { @@ -65,6 +71,14 @@ enum { RAM_DDR2_64 = 2, }; +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + + return 0; +} + static unsigned int get_hwver(void) { u16 latch3 = in_le16((void *)LATCH3_BASE); @@ -81,7 +95,7 @@ static unsigned int get_mc2_present(void) static void print_fpga_info(unsigned dev) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); @@ -146,7 +160,15 @@ static void print_fpga_info(unsigned dev) break; case HWVER_110: - printf(" HW-Ver 1.10\n"); + printf(" HW-Ver 1.10-1.12\n"); + break; + + case HWVER_120: + printf(" HW-Ver 1.20\n"); + break; + + case HWVER_130: + printf(" HW-Ver 1.30\n"); break; default: @@ -223,32 +245,31 @@ static void print_fpga_info(unsigned dev) */ int checkboard(void) { - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); + char *s = getenv("serial#"); - printf("Board: "); + puts("Board: "); - printf("DLVision 10G"); + puts("DLVision 10G"); - if (i > 0) { + if (s != NULL) { puts(", serial# "); - puts(buf); + puts(s); } puts("\n"); - print_fpga_info(0); - if (get_mc2_present()) - print_fpga_info(1); - return 0; } int last_stage_init(void) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); + print_fpga_info(0); + if (get_mc2_present()) + print_fpga_info(1); + if (((versions >> 4) & 0x000f) != UNITTYPE_MAIN_USER) return 0; @@ -261,3 +282,32 @@ int last_stage_init(void) return 0; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index db1ea7f..070dcbb 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -27,10 +27,16 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include <dtt.h> #include <miiphy.h> +#include "405ep.h" #include <gdsys_fpga.h> +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + #define PHYREG_CONTROL 0 #define PHYREG_PAGE_ADDRESS 22 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 @@ -47,6 +53,14 @@ enum { HWVER_122 = 3, }; +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + + return 0; +} + int configure_gbit_phy(unsigned char addr) { unsigned short value; @@ -87,9 +101,23 @@ err_out: */ int checkboard(void) { - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + char *s = getenv("serial#"); + + puts("Board: CATCenter Io"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(void) +{ + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); @@ -103,15 +131,7 @@ int checkboard(void) feature_channels = fpga_features & 0x007f; feature_expansion = fpga_features & (1<<15); - printf("Board: "); - - printf("CATCenter Io"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); + puts("FPGA: "); switch (unit_type) { case UNITTYPE_CCD_SWITCH: @@ -152,8 +172,6 @@ int checkboard(void) printf(" %d channel(s)", feature_channels); printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); - - return 0; } /* @@ -161,9 +179,11 @@ int checkboard(void) */ int last_stage_init(void) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); unsigned int k; + print_fpga_info(); + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, bb_miiphy_read, bb_miiphy_write); @@ -175,3 +195,32 @@ int last_stage_init(void) return 0; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index ce53340..0fc7db2 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -27,10 +27,15 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include "405ep.h" #include <gdsys_fpga.h> #include "../common/osd.h" +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + enum { UNITTYPE_MAIN_SERVER = 0, UNITTYPE_MAIN_USER = 1, @@ -69,9 +74,25 @@ enum { */ int checkboard(void) { - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + char *s = getenv("serial#"); + + puts("Board: "); + + puts("IoCon"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(void) +{ + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); @@ -95,16 +116,6 @@ int checkboard(void) feature_carriers = (fpga_features & 0x000c) >> 2; feature_video_channels = fpga_features & 0x0003; - printf("Board: "); - - printf("IoCon"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); - switch (unit_type) { case UNITTYPE_MAIN_USER: printf("Mainchannel"); @@ -205,12 +216,12 @@ int checkboard(void) printf(", %d carrier(s)", feature_carriers); printf(", %d video channel(s)\n", feature_video_channels); - - return 0; } int last_stage_init(void) { + print_fpga_info(); + return osd_probe(0); } @@ -231,3 +242,32 @@ int fpga_gpio_get(int pin) { return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c new file mode 100644 index 0000000..d336e55 --- /dev/null +++ b/board/gdsys/405ep/neo.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2011 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/ppc4xx-gpio.h> +#include <dtt.h> + +#include "405ep.h" +#include <gdsys_fpga.h> + +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + +enum { + UNITTYPE_CCX16 = 1, + UNITTYPE_CCIP216 = 2, +}; + +enum { + HWVER_300 = 3, +}; + +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: CATCenter Neo"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(void) +{ + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); + int fpga_state = get_fpga_state(0); + unsigned unit_type; + unsigned hardware_version; + unsigned feature_channels; + + puts("FPGA: "); + if (fpga_state & FPGA_STATE_DONE_FAILED) { + printf(" done timed out\n"); + return; + } + + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { + printf(" refelectione test failed\n"); + return; + } + + unit_type = (versions & 0xf000) >> 12; + hardware_version = versions & 0x000f; + feature_channels = fpga_features & 0x007f; + + switch (unit_type) { + case UNITTYPE_CCX16: + printf("CCX-Switch"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (hardware_version) { + case HWVER_300: + printf(" HW-Ver 3.00-3.12\n"); + break; + + default: + printf(" HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d, features:", + fpga_version / 100, fpga_version % 100); + + printf(" %d channel(s)\n", feature_channels); +} + +int last_stage_init(void) +{ + print_fpga_info(); + + return 0; +} + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + /* + * Neo hardware has no FPGA-DONE GPIO + */ + return 1; +} diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c index 0d25214..5766c0f 100644 --- a/board/gdsys/405ex/405ex.c +++ b/board/gdsys/405ex/405ex.c @@ -219,7 +219,8 @@ int board_early_init_r(void) gd405ex_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); + struct ihs_fpga *fpga = + (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); #ifdef CONFIG_SYS_FPGA_NO_RFL_HI u16 *reflection_target = &fpga->reflection_low; #else diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 177141d..41fdef7 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -100,7 +100,7 @@ int misc_init_r(void) static void print_fpga_info(unsigned dev) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); + struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); @@ -242,8 +242,8 @@ int last_stage_init(void) { unsigned int k; unsigned int fpga; - ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); - ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); + struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); + struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1); int failed = 0; char str_phys[] = "Setup PHYs -"; char str_serdes[] = "Start SERDES blocks"; diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 5065f9d..a192c98 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -70,8 +70,8 @@ enum { #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178) static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); - ihs_i2c_t *i2c = &fpga->i2c; + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); + struct ihs_i2c *i2c = &fpga->i2c; while (in_le16(&fpga->extended_interrupt) & (1 << 12)) ; @@ -81,8 +81,8 @@ static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data) static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); - ihs_i2c_t *i2c = &fpga->i2c; + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); + struct ihs_i2c *i2c = &fpga->i2c; unsigned int ctr = 0; while (in_le16(&fpga->extended_interrupt) & (1 << 12)) @@ -129,7 +129,7 @@ static void mpc92469ac_calc_parameters(unsigned int fout, static void mpc92469ac_set(unsigned screen, unsigned int fout) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); unsigned int n; unsigned int m; unsigned int bitval = 0; @@ -265,8 +265,8 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout) static int osd_write_videomem(unsigned screen, unsigned offset, u16 *data, size_t charcount) { - ihs_fpga_t *fpga = - (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); + struct ihs_fpga *fpga = + (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen); unsigned int k; for (k = 0; k < charcount; ++k) { @@ -318,8 +318,8 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int osd_probe(unsigned screen) { - ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen); - ihs_osd_t *osd = &fpga->osd; + struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen); + struct ihs_osd *osd = &fpga->osd; u16 version = in_le16(&osd->version); u16 features = in_le16(&osd->features); unsigned width; diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c deleted file mode 100644 index d21d599..0000000 --- a/board/gdsys/neo/neo.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> - -#define HWTYPE_CCX16 1 -#define HWREV_300 3 - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2); - u8 unit_type; - u8 hardware_cpu_ports; - u8 hardware_con_ports; - u8 hardware_version; - - printf("Board: CATCenter Neo"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); - - unit_type = (val & 0xf000) >> 12; - hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8; - hardware_con_ports = ((val & 0x00f0) >> 4) * 2; - hardware_version = val & 0x000f; - - switch (unit_type) { - case HWTYPE_CCX16: - printf("CCX16-FPGA (80 UARTs)"); - break; - - default: - printf("UnitType %d, unsupported", unit_type); - break; - } - - printf(", %d cpu ports, %d console ports,", - hardware_cpu_ports, hardware_con_ports); - - switch (hardware_version) { - case HWREV_300: - printf(" HW-Ver 3.00\n"); - break; - - default: - printf(" HW-Ver %d, unsupported\n", - hardware_version); - break; - } - - return 0; -} |