diff options
Diffstat (limited to 'board')
116 files changed, 2540 insertions, 963 deletions
diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index d1ac0c5..30304b0 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -248,7 +248,7 @@ void mv6436x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -351,7 +351,7 @@ void mv6436x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index 58b63a3..cd9d5a4 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -248,7 +248,7 @@ void mv6446x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -350,7 +350,7 @@ void mv6446x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG diff --git a/board/avnet/fx12mm/fx12mm.c b/board/avnet/fx12mm/fx12mm.c index 4858645..e671a7b 100644 --- a/board/avnet/fx12mm/fx12mm.c +++ b/board/avnet/fx12mm/fx12mm.c @@ -34,7 +34,7 @@ int checkboard(void) { char tmp[64]; char *s, *e; - int i = getenv_r("serial", tmp, sizeof(tmp)); + int i = getenv_f("serial", tmp, sizeof(tmp)); if (i < 0) { printf("Avnet Virtex4 FX12 with no serial #"); diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 891070b..51bdf02 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -378,6 +378,17 @@ static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) } +void video_stop(void) +{ + DisablePPI(); + DisableDMA(); + DisableTIMER0(); + DisableTIMER1(); +#ifdef CONFIG_MK_BF527_EZKIT_REV_2_1 + lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT); +#endif +} + void video_putc(const char c) { } diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c index 939bd35..75b8adc 100644 --- a/board/bf533-stamp/video.c +++ b/board/bf533-stamp/video.c @@ -150,6 +150,12 @@ static void video_init(char *NTSCFrame) bfin_write_PPI_CONTROL(0x0083); } +void video_stop(void) +{ + bfin_write_PPI_CONTROL(0); + bfin_write_DMA0_CONFIG(0); +} + int drv_video_init(void) { struct stdio_dev videodev; diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index af3d58b..cde877a 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -224,6 +224,12 @@ int video_init(void *dst) return 0; } +void video_stop(void) +{ + DisablePPI(); + DisableDMA(); +} + static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) { if (dcache_status()) diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index d43f5a1..c501697 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -225,6 +225,12 @@ int video_init(void *dst) return 0; } +void video_stop(void) +{ + DisablePPI(); + DisableDMA(); +} + static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) { if (dcache_status()) diff --git a/board/colibri_pxa270/Makefile b/board/colibri_pxa270/Makefile index 44d73cc..ae570e1 100644 --- a/board/colibri_pxa270/Makefile +++ b/board/colibri_pxa270/Makefile @@ -21,25 +21,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := colibri_pxa270.o +COBJS := colibri_pxa270.o SOBJS := lowlevel_init.o -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index d3822f0..84ec38e 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 1656e8a..33f2089 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -245,7 +245,7 @@ int testdram (void) uint *pend = (uint *) L1_MEMSIZE; uint *p; - if (getenv_r("booted",NULL,0) <= 0) + if (getenv_f("booted",NULL,0) <= 0) { printf ("testdram.."); /*AA*/ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 6bc70ef..8e26996 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -183,7 +183,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c index 63aaf2c..8e00785 100644 --- a/board/esd/adciop/adciop.c +++ b/board/esd/adciop/adciop.c @@ -62,7 +62,7 @@ int board_early_init_f (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index b58c1eb..564ee00 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -404,7 +404,7 @@ int misc_init_r(void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 21b2432..8879faf 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -151,7 +151,7 @@ int checkboard (void) int index; int len; char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); const unsigned char *fpga; puts ("Board: "); diff --git a/board/esd/ar405/config.mk b/board/esd/ar405/config.mk index 3e8baf6..da7c107 100644 --- a/board/esd/ar405/config.mk +++ b/board/esd/ar405/config.mk @@ -20,11 +20,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# esd AR405 boards -# - -#TEXT_BASE = 0xFFFE0000 -#TEXT_BASE = 0xFFFD0000 -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFFA0000 diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 03c4098..ea28090 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -173,7 +173,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index bfec548..0d2d7f1 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -157,7 +157,7 @@ int checkboard (void) int index; int len; char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/esd/canbt/config.mk b/board/esd/canbt/config.mk index 80076cd..ae855dc 100644 --- a/board/esd/canbt/config.mk +++ b/board/esd/canbt/config.mk @@ -20,10 +20,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# esd ADCIOP boards -# - -TEXT_BASE = 0xFFFE0000 -#TEXT_BASE = 0xFFFD0000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 20346e1..dcd49d4 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -96,7 +96,7 @@ int checkboard (void) puts ("Board: "); - if (getenv_r("serial#", str, sizeof(str)) == -1) { + if (getenv_f("serial#", str, sizeof(str)) == -1) { puts ("### No HW ID - assuming CMS700"); } else { puts(str); diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 00456a7..ecfcf59 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -94,7 +94,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 51d3355..51e10fd 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -416,7 +416,7 @@ int checkboard(void) int len; #endif char str[64]; - int i = getenv_r("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); unsigned short ver; puts("Board: "); diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index dedf734..781ad23 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -248,7 +248,7 @@ void mv6436x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -352,7 +352,7 @@ void mv6436x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index dcea50e..10a40be 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -153,7 +153,7 @@ int checkboard (void) int index; int len; char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c index 127374b..e7f754c 100644 --- a/board/esd/dasa_sim/dasa_sim.c +++ b/board/esd/dasa_sim/dasa_sim.c @@ -168,7 +168,7 @@ int checkboard (void) int index; int len; char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); int fpga; unsigned short val; diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index 228a570..5878092 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -86,7 +86,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; unsigned char id1, id2, rev; diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index aa7ee92..e0faa77 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -163,7 +163,7 @@ int checkboard (void) int index; int len; char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index ba3c97c..ad255f9 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -350,7 +350,7 @@ int checkboard(void) puts("Board: DU440"); - if (getenv_r("serial#", serno, sizeof(serno)) > 0) { + if (getenv_f("serial#", serno, sizeof(serno)) > 0) { puts(", serial# "); puts(serno); } diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index ca7868c..c5e9514 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -650,7 +650,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); @@ -660,7 +660,7 @@ int checkboard (void) puts(str); } - if (getenv_r("bd_type", str, sizeof(str)) != -1) { + if (getenv_f("bd_type", str, sizeof(str)) != -1) { printf(" (%s", str); } else { puts(" (Missing bd_type!"); @@ -780,7 +780,7 @@ void video_get_info_str (int line_number, char *info) { char str[64]; char str2[64]; - int i = getenv_r("serial#", str2, sizeof(str)); + int i = getenv_f("serial#", str2, sizeof(str)); if (line_number == 1) { sprintf(str, " Board: "); @@ -791,7 +791,7 @@ void video_get_info_str (int line_number, char *info) strcat(str, str2); } - if (getenv_r("bd_type", str2, sizeof(str2)) != -1) { + if (getenv_f("bd_type", str2, sizeof(str2)) != -1) { strcat(str, " ("); strcat(str, str2); } else { diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 2a2c434..d17c415 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -196,7 +196,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); @@ -206,7 +206,7 @@ int checkboard (void) puts(str); } - if (getenv_r("bd_type", str, sizeof(str)) != -1) { + if (getenv_f("bd_type", str, sizeof(str)) != -1) { printf(" (%s", str); } else { puts(" (Missing bd_type!"); diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index a1b66cb..694bd74 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -184,7 +184,7 @@ int checkboard(void) puts("Board: EtherCAN/2 Gateway"); break; } - if (getenv_r("serial#", str, sizeof(str)) > 0) { + if (getenv_f("serial#", str, sizeof(str)) > 0) { puts(", serial# "); puts(str); } diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index ab909e5..24c92e3 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -68,7 +68,7 @@ int board_early_init_f (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 07d9c62..410d8b4 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -258,7 +258,7 @@ int checkboard(void) char str[32]; puts("Board: esd ARM9 HMI Panel - OTC570"); - if (getenv_r("serial#", str, sizeof(str)) > 0) { + if (getenv_f("serial#", str, sizeof(str)) > 0) { puts(", serial# "); puts(str); } @@ -308,7 +308,7 @@ int misc_init_r(void) printf("USART0: "); - if (getenv_r("usart0", str, sizeof(str)) == -1) { + if (getenv_f("usart0", str, sizeof(str)) == -1) { printf("No entry - assuming 1-wire\n"); /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */ at91_set_pio_output(AT91_PIO_PORTA, 29, 0); diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index b0d7663..dd97c7a 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -298,7 +298,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 3a8a4cf..b68ffaf 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -240,7 +240,7 @@ int misc_init_r(void) int checkboard(void) { char str[64]; - int i = getenv_r("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts("Board: "); diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index e7415e4..03143fe 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -123,7 +123,7 @@ int checkboard (void) { ulong val; char str[64]; - int i = getenv_r("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk index 91e65ec..6e9f735 100644 --- a/board/esd/pmc440/config.mk +++ b/board/esd/pmc440/config.mk @@ -23,7 +23,7 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE -TEXT_BASE = 0xFFFA0000 +TEXT_BASE = 0xFFF90000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 6ed493e..da25212 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -271,7 +271,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); @@ -281,7 +281,7 @@ int checkboard (void) puts(str); } - if (getenv_r("bd_type", str, sizeof(str)) != -1) { + if (getenv_f("bd_type", str, sizeof(str)) != -1) { printf(" (%s)", str); } else { puts(" (Missing bd_type!)"); diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index de35036..f665a3e 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -121,7 +121,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); int flashcnt; int delay; u8 *led_reg = (u8 *)(CAN_BA + 0x1000); diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 704cd02..5a65133 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -173,7 +173,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S index 7f0686c..1a11eee 100644 --- a/board/espt/lowlevel_init.S +++ b/board/espt/lowlevel_init.S @@ -206,26 +206,31 @@ PKDR_A: .long 0xFFEF0034 /* GPIO Set data */ PADR_D: .long 0x00000000 -PACR_D: .long 0x00001400 +PACR_D: .word 0x1400 +.align 2 PBDR_D: .long 0x00000000 -PBCR_D: .long 0x0000555A +PBCR_D: .word 0x555A +.align 2 PCDR_D: .long 0x00000000 -PCCR_D: .long 0x00005555 +PCCR_D: .word 0x5555 +.align 2 PDDR_D: .long 0x00000000 -PDCR_D: .long 0x00000155 -PECR_D: .long 0x00000000 -PFCR_D: .long 0x00000000 -PGCR_D: .long 0x00000000 -PHCR_D: .long 0x00000000 -PICR_D: .long 0x00000800 +PDCR_D: .word 0x0155 +PECR_D: .word 0x0000 +PFCR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PICR_D: .word 0x0800 PJDR_D: .long 0x00000006 -PJCR_D: .long 0x00005A57 +PJCR_D: .word 0x5A57 +.align 2 PKDR_D: .long 0x00000000 -PKCR_D: .long 0x0000FFF9 -PLCR_D: .long 0x0000C330 -PMCR_D: .long 0x0000FFFF -PNCR_D: .long 0x00000242 -POCR_D: .long 0x00000000 +PKCR_D: .word 0xFFF9 +.align 2 +PLCR_D: .word 0xC330 +PMCR_D: .word 0xFFFF +PNCR_D: .word 0x0242 +POCR_D: .word 0x0000 /* Pin Select */ PSEL0_A: .long 0xFFEF0070 @@ -233,11 +238,12 @@ PSEL1_A: .long 0xFFEF0072 PSEL2_A: .long 0xFFEF0074 PSEL3_A: .long 0xFFEF0076 PSEL4_A: .long 0xFFEF0078 -PSEL0_D: .long 0x0001 -PSEL1_D: .long 0x2400 -PSEL2_D: .long 0x0000 -PSEL3_D: .long 0x2421 -PSEL4_D: .long 0x0000 +PSEL0_D: .word 0x0001 +PSEL1_D: .word 0x2400 +PSEL2_D: .word 0x0000 +PSEL3_D: .word 0x2421 +PSEL4_D: .word 0x0000 +.align 2 MMSEL_A: .long 0xFE600020 BCR_A: .long 0xFF801000 diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index ca8bab5..a96e655 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -89,7 +89,7 @@ static const char ether_port_phy_addr[3]={4,5,6}; /* MII PHY access routines are common for all i/f, use gal_ent0 */ #define GT6426x_MII_DEVNAME "gal_enet0" -int gt6426x_miiphy_read(char *devname, unsigned char phy, +int gt6426x_miiphy_read(const char *devname, unsigned char phy, unsigned char reg, unsigned short *val); static inline unsigned short @@ -345,7 +345,7 @@ gt6426x_eth_disable(void *v) MII utilities - write: write to an MII register via SMI ***************************************************************************/ int -gt6426x_miiphy_write(char *devname, unsigned char phy, +gt6426x_miiphy_write(const char *devname, unsigned char phy, unsigned char reg, unsigned short data) { unsigned int temp= (reg<<21) | (phy<<16) | data; @@ -360,7 +360,7 @@ gt6426x_miiphy_write(char *devname, unsigned char phy, MII utilities - read: read from an MII register via SMI ***************************************************************************/ int -gt6426x_miiphy_read(char *devname, unsigned char phy, +gt6426x_miiphy_read(const char *devname, unsigned char phy, unsigned char reg, unsigned short *val) { unsigned int temp= (reg<<21) | (phy<<16) | 1<<26; @@ -708,7 +708,7 @@ gt6426x_eth_initialize(bd_t *bis) return; } - temp = getenv_r (s, buf, sizeof(buf)); + temp = getenv_f(s, buf, sizeof(buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 2d48d7e..f93045f 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o +COBJS-$(CONFIG_P4080DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile new file mode 100644 index 0000000..8aa7255 --- /dev/null +++ b/board/freescale/corenet_ds/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_DDR_SPD) += ddr.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk new file mode 100644 index 0000000..72db24e --- /dev/null +++ b/board/freescale/corenet_ds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2007-2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# P4080DS board +# +ifndef TEXT_BASE +TEXT_BASE = 0xeff80000 +endif + +RESET_VECTOR_ADDRESS = 0xeffffffc diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c new file mode 100644 index 0000000..48d95d6 --- /dev/null +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -0,0 +1,262 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +extern void pci_of_setup(void *blob, bd_t *bd); + +#include "../common/ngpixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +void cpu_mp_lmb_reserve(struct lmb *lmb); + +int checkboard (void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + + printf("Board: %sDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); + + sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); + sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + + /* Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = in_8(&PIXIS_SW(3)); + printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); + printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); + printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); + + return 0; +} + +int board_early_init_f(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* + * P4080 DS board only uses the DDR1_MCK0/3 and DDR2_MCK0/3 + * disable the DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce + * the noise introduced by these unterminated and unused clock pairs. + */ + setbits_be32(&gur->ddrclkdr, 0x001B001B); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ + + set_liodns(); + setup_portals(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch(clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "???"; + } +} + +#define NUM_SRDS_BANKS 3 + +int misc_init_r(void) +{ + serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + __maybe_unused ccsr_gur_t *gur; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw3; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_SRIO1 + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_1); + } else { + printf (" SRIO1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ +#endif + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_2); + } else { + printf (" SRIO2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ +#endif + + /* Warn if the expected SERDES reference clocks don't match the + * actual reference clocks. This needs to be done after calling + * p4080_erratum_serdes8(), since that function may modify the clocks. + */ + sw3 = in_8(&PIXIS_SW(3)); + actual[0] = (sw3 & 0x40) ? + SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; + actual[1] = (sw3 & 0x20) ? + SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; + actual[2] = (sw3 & 0x10) ? + SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....\n"); + + dram_size = fsl_ddr_sdram(); + + setup_ddr_tlbs(dram_size / 0x100000); + + puts(" DDR: "); + return dram_size; +} + +#ifdef CONFIG_MP +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif + +void ft_srio_setup(void *blob) +{ +#ifdef CONFIG_SRIO1 + if (!is_serdes_configured(SRIO1)) { + fdt_del_node_and_alias(blob, "rio0"); + } +#else + fdt_del_node_and_alias(blob, "rio0"); +#endif +#ifdef CONFIG_SRIO2 + if (!is_serdes_configured(SRIO2)) { + fdt_del_node_and_alias(blob, "rio1"); + } +#else + fdt_del_node_and_alias(blob, "rio1"); +#endif +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + ft_srio_setup(blob); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c new file mode 100644 index 0000000..18adf2f --- /dev/null +++ b/board/freescale/corenet_ds/ddr.c @@ -0,0 +1,192 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +{ + int ret; + + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); + if (ret) { + debug("DDR: failed to read SPD from address %u\n", i2c_address); + memset(spd, 0, sizeof(ddr3_spd_eeprom_t)); + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + else if (ctrl_num == 1 && i == 0) + i2c_address = SPD_EEPROM_ADDRESS2; + + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ + + +/* XXX: these values need to be checked for all interleaving modes. */ +/* XXX: No reliable dual-rank 800 MHz setting has been found. It may + * seem reliable, but errors will appear when memory intensive + * program is run. */ +/* XXX: Single rank at 800 MHz is OK. */ +const board_specific_parameters_t board_specific_parameters[][30] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 10, 5, 0}, + {681, 850, 2, 1, 12, 5, 0}, + {851, 1050, 2, 1, 12, 5, 0}, + {1051, 1250, 2, 1, 15, 4, 0}, + {1251, 1350, 2, 1, 15, 4, 0}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 10, 5, 0}, + {681, 850, 1, 1, 12, 5, 0} + }, + + { + /* memory controller 1 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 11, 6, 0}, + {681, 850, 2, 1, 13, 6, 0}, + {851, 1050, 2, 1, 13, 6, 0}, + {1051, 1250, 2, 1, 15, 4, 0}, + {1251, 1350, 2, 1, 15, 4, 0}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 11, 6, 0}, + {681, 850, 1, 1, 13, 6, 0} + } +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; + + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm->n_ranks == pbsp->n_ranks) { + popts->cpo_override = 0xff; /* force auto CPO calibration */ + popts->write_data_delay = 2; + popts->clk_adjust = 5; /* Force value to be 5/8 clock cycle */ + popts->twoT_en = pbsp->force_2T; + } + pbsp++; + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x7; + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_120_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ + + /* Enable ZQ calibration */ + popts->zq_en = 1; +} diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c new file mode 100644 index 0000000..43b4b97 --- /dev/null +++ b/board/freescale/corenet_ds/law.c @@ -0,0 +1,40 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c new file mode 100644 index 0000000..2994e36 --- /dev/null +++ b/board/freescale/corenet_ds/pci.c @@ -0,0 +1,127 @@ +/* + * Copyright 2007-2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif + +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif + +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +void pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[3]; + u32 devdisr; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + + debug (" pci_init_board: devdisr=%x\n", devdisr); + +#ifdef CONFIG_PCIE1 + pcie_configured = is_serdes_configured(PCIE1); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) { + set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_1); + set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_1); + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf (" PCIE1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */ +#endif + +#ifdef CONFIG_PCIE2 + pcie_configured = is_serdes_configured(PCIE2); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) { + set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_2); + set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_2); + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected to Slot 3 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf (" PCIE2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */ +#endif + +#ifdef CONFIG_PCIE3 + pcie_configured = is_serdes_configured(PCIE3); + + if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) { + set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, + LAW_TRGT_IF_PCIE_3); + set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, + LAW_TRGT_IF_PCIE_3); + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf(" PCIE3 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + } else { + printf (" PCIE3: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ +#endif +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c new file mode 100644 index 0000000..1ae0416 --- /dev/null +++ b/board/freescale/corenet_ds/tlb.c @@ -0,0 +1,112 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 489f90b..423e9d7 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -236,7 +236,7 @@ void reset_phy (void) #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); + miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index d86ca12..fee310a 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -60,6 +60,8 @@ int checkboard(void) return 0; } +const char *board_hwconfig = "foo:bar=baz"; +const char *cpu_hwconfig = "foo:bar=baz"; phys_size_t initdram(int board_type) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b9c0cb2..9a1b075 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -12,7 +12,7 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> -static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address) { i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } @@ -22,7 +22,7 @@ unsigned int fsl_ddr_get_mem_data_rate(void) return get_ddr_freq(0); } -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { unsigned int i; @@ -51,27 +51,26 @@ typedef struct { * cpo 2-0x1E (30) */ - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][20] = { { /* memory controller 0 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 10, 5, 0}, - {681, 850, 2, 1, 12, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} +#ifdef CONFIG_FSL_DDR2 + { 0, 333, 2, 4, 0x1f, 2, 0}, + {334, 400, 2, 4, 0x1f, 2, 0}, + {401, 549, 2, 4, 0x1f, 2, 0}, + {550, 680, 2, 4, 0x1f, 3, 0}, + {681, 850, 2, 4, 0x1f, 4, 0}, + { 0, 333, 1, 4, 0x1f, 2, 0}, + {334, 400, 1, 4, 0x1f, 2, 0}, + {401, 549, 1, 4, 0x1f, 2, 0}, + {550, 680, 1, 4, 0x1f, 3, 0}, + {681, 850, 1, 4, 0x1f, 4, 0} +#else + { 0, 850, 2, 6, 0x1f, 4, 0}, + { 0, 850, 1, 4, 0x1f, 4, 0} +#endif }, }; @@ -92,18 +91,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i&1) { /* odd CS */ popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 0; - } else { /* even CS */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 4; - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - popts->cs_local_opts[i].odt_rd_cfg = 3; - popts->cs_local_opts[i].odt_wr_cfg = 3; - } - } + popts->cs_local_opts[i].odt_wr_cfg = 1; } /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr @@ -127,4 +116,13 @@ void fsl_ddr_board_options(memctl_options_t *popts, * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; + popts->wrlvl_en = 1; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xa; + popts->wrlvl_start = 0x8; + /* Rtt and Rtt_WR override */ + popts->rtt_override = 1; + popts->rtt_override_value = DDR3_RTT_120_OHM; + popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */ } diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3fd1b34..608ff91 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -69,13 +69,16 @@ int checkboard(void) return 0; } +const char *board_hwconfig = "foo:bar=baz"; +const char *cpu_hwconfig = "foo:bar=baz"; + phys_size_t initdram(int board_type) { phys_size_t dram_size = 0; puts("Initializing...."); -#ifdef CONFIG_SPD_EEPROM +#ifdef CONFIG_DDR_SPD dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); @@ -94,7 +97,7 @@ phys_size_t initdram(int board_type) return dram_size; } -#if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_DDR_SPD) /* * Fixed sdram init -- doesn't use serial presence detect. */ diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index 36ad086..824b3b2 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -28,19 +28,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index 889ba3f..e856ada 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -198,7 +198,7 @@ void reset_phy (void) iop->pdat |= 0x00080000; for (i=0; i<100; i++) { udelay(20000); - if (bb_miiphy_read("FCC1 ETHERNET", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) { + if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) { break; } } diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 8b15e51..713b699 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -91,7 +91,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index b37a0f2..d175858 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -132,7 +132,7 @@ int checkboard (void) char buf[64]; int i; - i = getenv_r ("board_id", buf, sizeof (buf)); + i = getenv_f("board_id", buf, sizeof (buf)); s = (i > 0) ? buf : NULL; if (s) { @@ -141,7 +141,7 @@ int checkboard (void) printf ("<unknown> "); } - i = getenv_r ("serial#", buf, sizeof (buf)); + i = getenv_f("serial#", buf, sizeof (buf)); s = (i > 0) ? buf : NULL; if (s) { @@ -276,7 +276,7 @@ int last_stage_init (void) /* * Read the environment to see what to do with the beeper */ - i = getenv_r ("beeper", buf, sizeof (buf)); + i = getenv_f("beeper", buf, sizeof (buf)); if (i > 0) { do_beeper (buf); } diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index e6eee9b..aeb0fcc 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index 27b79ec..fc498d6 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -187,7 +187,7 @@ int misc_init_f (void) char tmp[10]; int i, br; - i = getenv_r("brightness", tmp, sizeof(tmp)); + i = getenv_f("brightness", tmp, sizeof(tmp)); br = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) : CONFIG_SYS_BRIGHTNESS; diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c index e2a1851..adff2b2 100644 --- a/board/ip860/ip860.c +++ b/board/ip860/ip860.c @@ -114,7 +114,7 @@ int checkboard (void) puts ("Board: "); - i = getenv_r ("serial#", (char *)buf, sizeof (buf)); + i = getenv_f("serial#", (char *)buf, sizeof (buf)); s = (i > 0) ? buf : NULL; if (!s || strncmp ((char *)s, "IP860", 5)) { diff --git a/board/keymile/common/keymile_hdlc_enet.c b/board/keymile/common/keymile_hdlc_enet.c index ce5e4d6..a545211 100644 --- a/board/keymile/common/keymile_hdlc_enet.c +++ b/board/keymile/common/keymile_hdlc_enet.c @@ -40,7 +40,7 @@ extern char keymile_slot; /* our slot number in the backplane */ #define TOUT_LOOP 50000 /* - * Since, except during initialization, ethact is always HDLC ETHERNET + * Since, except during initialization, ethact is always HDLC * while we're in the driver, just use serial_printf() everywhere for * output. This avoids possible conflicts when netconsole is being * used. @@ -124,7 +124,7 @@ int keymile_hdlc_enet_initialize(bd_t *bis) seth = dev; #endif - sprintf(dev->name, "HDLC ETHERNET"); + sprintf(dev->name, "HDLC"); dev->init = keymile_hdlc_enet_init; dev->halt = keymile_hdlc_enet_halt; dev->send = keymile_hdlc_enet_send; diff --git a/board/keymile/km8xx/km8xx_hdlc_enet.c b/board/keymile/km8xx/km8xx_hdlc_enet.c index 0478288..ca00576 100644 --- a/board/keymile/km8xx/km8xx_hdlc_enet.c +++ b/board/keymile/km8xx/km8xx_hdlc_enet.c @@ -34,7 +34,7 @@ char keymile_slot; /* our slot number in the backplane */ /* - * Since, except during initialization, ethact is always HDLC ETHERNET + * Since, except during initialization, ethact is always HDLC * while we're in the driver, just use serial_printf() everywhere for * output. This avoids possible conflicts when netconsole is being * used. diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c index 2418d59..38259a5 100644 --- a/board/kup/common/kup.c +++ b/board/kup/common/kup.c @@ -24,49 +24,61 @@ #include <common.h> #include <mpc8xx.h> #include "kup.h" +#include <asm/io.h> -int misc_init_f (void) + +int misc_init_f(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf8xx_t *siu = &immap->im_siu_conf; - while (siu->sc_sipend & 0x20000000) { - /* printf("waiting for 5V VCC\n"); */ - ; + while (in_be32(&siu->sc_sipend) & 0x20000000) { + debug("waiting for 5V VCC\n"); } /* RS232 / RS485 default is RS232 */ - immap->im_ioport.iop_padat &= ~(PA_RS485); - immap->im_ioport.iop_papar &= ~(PA_RS485); - immap->im_ioport.iop_paodr &= ~(PA_RS485); - immap->im_ioport.iop_padir |= (PA_RS485); + clrbits_be16(&immap->im_ioport.iop_padat, PA_RS485); + clrbits_be16(&immap->im_ioport.iop_papar, PA_RS485); + clrbits_be16(&immap->im_ioport.iop_paodr, PA_RS485); + setbits_be16(&immap->im_ioport.iop_padir, PA_RS485); + + /* IO Reset min 1 msec */ + setbits_be16(&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16(&immap->im_ioport.iop_papar, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16(&immap->im_ioport.iop_paodr, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + setbits_be16(&immap->im_ioport.iop_padir, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + udelay(1000); + clrbits_be16(&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); return (0); } - #ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) +void ide_led(uchar led, uchar status) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); - } else { - immap->im_ioport.iop_padat |= (PA_LED_YELLOW); - } + if (status) + clrbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); + else + setbits_be16(&immap->im_ioport.iop_padat, PA_LED_YELLOW); } #endif -void poweron_key (void) +void poweron_key(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); - immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); + clrbits_be16(&immap->im_ioport.iop_pcpar, PC_SWITCH1); + clrbits_be16(&immap->im_ioport.iop_pcdir, PC_SWITCH1); - if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) - setenv ("key1", "off"); + if (in_be16(&immap->im_ioport.iop_pcdat) & (PC_SWITCH1)) + setenv("key1", "off"); else - setenv ("key1", "on"); + setenv("key1", "on"); } diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h index b736283..455848c 100644 --- a/board/kup/common/kup.h +++ b/board/kup/common/kup.h @@ -24,23 +24,33 @@ #ifndef __KUP_H #define __KUP_H -#define PA_8 0x0080 -#define PA_11 0x0010 -#define PA_12 0x0008 - -#define PB_14 0x00020000 -#define PB_17 0x00004000 - -#define PC_9 0x0040 - -#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 -#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ -#define PB_LCD_PWM PB_17 /* PB 17 */ -#define PC_SWITCH1 PC_9 /* Reboot switch */ - -extern void poweron_key (void); - +#define PA_8 0x0080 +#define PA_9 0x0040 +#define PA_10 0x0020 +#define PA_11 0x0010 +#define PA_12 0x0008 + +#define PB_14 0x00020000 +#define PB_15 0x00010000 +#define PB_16 0x00008000 +#define PB_17 0x00004000 + +#define PC_4 0x0800 +#define PC_5 0x0400 +#define PC_9 0x0040 + +#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ +#define PA_LED_YELLOW PA_8 +#define PA_RESET_IO_01 PA_9 /* Reset left IO */ +#define PA_RESET_IO_02 PA_10 /* Reset right IO */ +#define PB_PROG_IO_01 PB_15 /* Program left IO */ +#define PB_PROG_IO_02 PB_16 /* Program right IO */ +#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */ +#define PB_LCD_PWM PB_17 /* PB 17 */ +#define PC_SWITCH1 PC_9 /* Reboot switch */ + + +extern void poweron_key(void); extern void load_sernum_ethaddr(void); #endif /* __KUP_H */ diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 98f5f5a..267821c 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -23,35 +23,20 @@ */ #include <common.h> +#include <command.h> +#include <libfdt.h> #include <mpc8xx.h> +#include <hwconfig.h> +#include <i2c.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO - #include "s1d13706.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -#ifdef DEBUG -# define debugk(fmt,args...) printf(fmt ,##args) -#else -# define debugk(fmt,args...) -#endif - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; +#include <asm/io.h> +static unsigned char swapbyte(unsigned char c); +static int read_diag(void); -/* ------------------------------------------------------------------------- */ - -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo(bd_t *bd); -#endif - +DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ +/* ----------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF @@ -60,7 +45,7 @@ const uint sdram_table[] = { * Single Read. (Offset 0 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ + 0x1FF77C47, /* last */ /* * SDRAM Initialization (offset 5 in UPMA RAM) @@ -70,28 +55,28 @@ const uint sdram_table[] = { * sequence, which is executed by a RUN command. * */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ /* * Burst Read. (Offset 8 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, @@ -99,156 +84,169 @@ const uint sdram_table[] = { * Refresh (Offset 30 in UPMA RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -/* ------------------------------------------------------------------------- */ - +/* ----------------------------------------------------------------------- */ /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - uchar *latch,rev,mod; + uchar rev,mod,tmp,pcf,ak_rev,ak_mod; /* * Init ChipSelect #4 (CAN + HW-Latch) */ - immap->im_memctl.memc_or4 = 0xFFFF8926; - immap->im_memctl.memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch=(uchar *)0x90000200; - rev = (*latch & 0xF8) >> 3; - mod=(*latch & 0x03); - printf ("Board: KUP4K Rev %d.%d\n",rev,mod); - return (0); -} + out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); + + /* + * Init ChipSelect #5 (S1D13768) + */ + out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5); + out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5); -/* ------------------------------------------------------------------------- */ + tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR)); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); + if (read_diag()) + gd->flags &= ~GD_FLG_SILENT; + printf("Board: KUP4K Rev %d.%d AK:",rev,mod); /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. + * TI Application report: Before using the IO as an input, + * a high must be written to the IO first */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; + pcf = 0xFF; + i2c_write(0x21, 0, 0 , &pcf, 1); + if (i2c_read(0x21, 0, 0, &pcf, 1)) { + puts("n/a\n"); + } else { + ak_rev = (pcf & 0xF8) >> 3; + ak_mod = (pcf & 0x07); + printf("%d.%d\n", ak_rev, ak_mod); + } + return 0; +} - memctl->memc_mar = 0x00000088; +/* ----------------------------------------------------------------------- */ + + +phys_size_t initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size = 0; + uchar *latch,rev,mod,tmp; /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. + * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision + * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ - -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ + out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); + latch = (uchar *)0x90000200; + tmp = swapbyte(*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + upmconfig(UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); - udelay (200); + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - /* perform SDRAM initializsation sequence */ + out_be32(&memctl->memc_mar, 0x00000088); + /* no refresh yet */ + if(rev >= 7) { + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE))); + } else { + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE))); + } - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); - -#if 0 /* 3 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; -#else /* 3 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFC000A00; - memctl->memc_br3 = 0x02000081; -#endif + udelay(200); - udelay (10000); + /* perform SDRAM initializsation sequence */ - return (size_b0 + size_b1 + size_b2); + /* SDRAM bank 0 */ + out_be32(&memctl->memc_mcr, 0x80002105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 1 */ + out_be32(&memctl->memc_mcr, 0x80004105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 2 */ + out_be32(&memctl->memc_mcr, 0x80006105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ + udelay(1000); + + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + udelay(1000); + if(rev >= 7) { + size = 32 * 3 * 1024 * 1024; + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL); + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL); + out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL); + out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL); + out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL); + out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL); + } else { + size = 16 * 3 * 1024 * 1024; + out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL); + out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL); + out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL); + out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL); + out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL); + out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL); + } + return (size); } -/* ------------------------------------------------------------------------- */ +/* ----------------------------------------------------------------------- */ -int misc_init_r (void) + +int misc_init_r(void) { -#ifdef CONFIG_STATUS_LED volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#endif -#ifdef CONFIG_KUP4K_LOGO - bd_t *bd = gd->bd; - lcd_logo (bd); -#endif /* CONFIG_KUP4K_LOGO */ #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ + setbits_be16(&immap->im_ioport.iop_padir, PA_8); + setbits_be16(&immap->im_ioport.iop_paodr, PA_8); + clrbits_be16(&immap->im_ioport.iop_papar, PA_8); + setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ #endif load_sernum_ethaddr(); setenv("hw","4k"); @@ -256,149 +254,51 @@ int misc_init_r (void) return (0); } -#ifdef CONFIG_KUP4K_LOGO - -void lcd_logo (bd_t * bd) +static int read_diag(void) { - FB_INFO_S1D13xxx fb_info; - S1D_INDEX s1dReg; - S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl; - ushort i; - uchar *fb; - int rs, gs, bs; - int r = 8, g = 8, b = 4; - int r1, g1, b1; - int n; - char tmp[64]; /* long enough for environment variables */ - int tft = 0; - - immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); - -/*----------------------------------------------------------------------------- */ -/* Initialize the chip and the frame buffer driver. */ -/*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; - - - /* - * Init ChipSelect #5 (S1D13768) - */ - memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ - __asm__ ("eieio"); - - fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); - fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); - - if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { - printf ("Warning:LCD Controller S1D13706 not found\n"); - setenv ("lcd", "none"); - return; - } - - - for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { - s1dReg = aS1DRegs_prelimn[i].Index; - s1dValue = aS1DRegs_prelimn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - - n = getenv_r ("lcd", tmp, sizeof (tmp)); - if (n > 0) { - if (!strcmp ("tft", tmp)) - tft = 1; + int diag; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */ + clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */ + clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */ + udelay(500); + if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) { + clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */ + udelay(500); + if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4) + diag = 0; else - tft = 0; - } -#if 0 - if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) - tft = 0; - else - tft = 1; -#endif - - debugk ("Port=0x%02x -> TFT=%d\n", tft, - ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); - - /* init controller */ - if (!tft) { - for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { - s1dReg = aS1DRegs_stn[i].Index; - s1dValue = aS1DRegs_stn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_stn[i].Index, - aS1DRegs_stn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = - s1dValue; - } - n = getenv_r ("contrast", tmp, sizeof (tmp)); - ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = - (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; - switch (bd->bi_busfreq) { - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; - } - /* setenv("lcd","stn"); */ + diag = 1; } else { - for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { - s1dReg = aS1DRegs_tft[i].Index; - s1dValue = aS1DRegs_tft[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_tft[i].Index, - aS1DRegs_tft[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } - - switch (bd->bi_busfreq) { - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; - break; - } - /* setenv("lcd","tft"); */ + diag = 0; } + clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */ + return (diag); +} + +static unsigned char swapbyte(unsigned char c) +{ + unsigned char result = 0; + int i = 0; - /* create and set colormap */ - rs = 256 / (r - 1); - gs = 256 / (g - 1); - bs = 256 / (b - 1); - for (i = 0; i < 256; i++) { - r1 = (rs * ((i / (g * b)) % r)) * 255; - g1 = (gs * ((i / b) % g)) * 255; - b1 = (bs * ((i) % b)) * 255; - debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); - S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); + for(i = 0; i < 8; ++i) { + result = result << 1; + result |= (c & 1); + c = c >> 1; } + return result; +} - /* copy bitmap */ - fb = (uchar *) (fb_info.VmemAddr); - memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); } -#endif /* CONFIG_KUP4K_LOGO */ +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h deleted file mode 100644 index cd5eccc..0000000 --- a/board/kup/kup4k/s1d13706.h +++ /dev/null @@ -1,174 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - - -static S1D_REGS aS1DRegs_prelimn[] = -{ - {0x10,0x00}, /* PANEL Type Register */ - {0xA8,0x00}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - -}; - -static S1D_REGS aS1DRegs_stn[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; - -static S1D_REGS aS1DRegs_tft[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x05,0x42}, /* PCLK Config Register */ - {0x10,0x61}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x12,0x30}, /* Horizontal Total Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xFA}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x00}, /* Vertical Sync Pulse Width Register */ - {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x03}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c index 65a222b..1686eff 100644 --- a/board/kup/kup4x/kup4x.c +++ b/board/kup/kup4x/kup4x.c @@ -26,28 +26,8 @@ #include <mpc8xx.h> #include <post.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO -/* #include "s1d13706.h" */ -#endif - -#define KUP4X_USB - - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - -/* ------------------------------------------------------------------------- */ - -int usb_init_kup4x (void); - +#include <asm/io.h> -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo (bd_t * bd); -#endif - -/* ------------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF @@ -106,207 +86,116 @@ const uint sdram_table[] = { _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -/* ------------------------------------------------------------------------- */ /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile uchar *latch; - uchar rev, mod; + uchar latch, rev, mod; /* * Init ChipSelect #4 (CAN + HW-Latch) */ - memctl->memc_or4 = 0xFFFF8926; - memctl->memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch = (volatile uchar *) 0x90000200; - rev = (*latch & 0xF8) >> 3; - mod = (*latch & 0x03); - printf ("Board: KUP4X Rev %d.%d\n",rev,mod); - return (0); + out_be32(&memctl->memc_or4, 0xFFFF8926); + out_be32(&memctl->memc_br4, 0x90000401); + + latch = in_8( (unsigned char *) LATCH_ADDR); + rev = (latch & 0xF8) >> 3; + mod = (latch & 0x03); + + printf("Board: KUP4X Rev %d.%d\n", rev, mod); + + return 0; } -/* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; - long int size_b3 = 0; - upmconfig (UPMA, (uint *) sdram_table, + upmconfig(UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_mar = 0x00000088; + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ + out_be32(&memctl->memc_mar, 0x00000088); -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ + out_be32(&memctl->memc_mamr, + CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */ - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); + udelay(200); /* perform SDRAM initializsation sequence */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ - udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ - udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ - udelay (1); - memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ - udelay (1); - memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); -#if 0 /* 4 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - size_b3 = 0x00800000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; - memctl->memc_or6 = 0xFE000A00; - memctl->memc_br6 = 0x01800081; -#else /* 4 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - size_b3 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFD000A00; - memctl->memc_br3 = 0x02000081; - memctl->memc_or6 = 0xFC000A00; - memctl->memc_br6 = 0x03000081; -#endif - udelay (10000); - - return (size_b0 + size_b1 + size_b2 + size_b3); + /* SDRAM bank 0 */ + out_be32(&memctl->memc_mcr, 0x80002105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 1 */ + out_be32(&memctl->memc_mcr, 0x80004105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 2 */ + out_be32(&memctl->memc_mcr, 0x80006105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + /* SDRAM bank 3 */ + out_be32(&memctl->memc_mcr, 0x8000C105); + udelay(1); + out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */ + udelay(1); + out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */ + udelay(1); + + setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ + + udelay(1000); + /* 4 x 16 MB */ + out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR); + udelay(1000); + out_be32(&memctl->memc_or1, 0xFF000A00); + out_be32(&memctl->memc_br1, 0x00000081); + out_be32(&memctl->memc_or2, 0xFE000A00); + out_be32(&memctl->memc_br2, 0x01000081); + out_be32(&memctl->memc_or3, 0xFD000A00); + out_be32(&memctl->memc_br3, 0x02000081); + out_be32(&memctl->memc_or6, 0xFC000A00); + out_be32(&memctl->memc_br6, 0x03000081); + udelay(10000); + + return (4 * 16 * 1024 * 1024); } -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -#if 0 -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) +int misc_init_r(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} -#endif -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ -#endif -#ifdef KUP4X_USB - usb_init_kup4x (); + setbits_be16(&immap->im_ioport.iop_padir, PA_8); + setbits_be16(&immap->im_ioport.iop_paodr, PA_8); + clrbits_be16(&immap->im_ioport.iop_papar, PA_8); + setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */ #endif load_sernum_ethaddr(); - setenv ("hw", "4x"); - poweron_key (); - return (0); + setenv("hw", "4x"); + poweron_key(); + return 0; } diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index b369219..47ef6e5 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -90,8 +90,8 @@ void reset_phy(void) { unsigned short mode_control; - miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control); - miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, + miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control); + miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15, mode_control & 0xfffe); return; } diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index b4343d8..624c708 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -284,13 +284,13 @@ void set_backup_values(int overwrite) } } memcpy(back.signature,"MPL\0",4); - i = getenv_r("serial#",back.serial_name,16); + i = getenv_f("serial#",back.serial_name,16); if(i < 0) { puts("Not possible to write Backup\n"); return; } back.serial_name[16]=0; - i = getenv_r("ethaddr",back.eth_addr,20); + i = getenv_f("ethaddr",back.eth_addr,20); if(i < 0) { puts("Not possible to write Backup\n"); return; diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c index 92c33ba..68973f9 100644 --- a/board/mpl/common/memtst.c +++ b/board/mpl/common/memtst.c @@ -29,7 +29,7 @@ int testdram (void) unsigned char s[32]; int i; - i = getenv_r ("testmem", s, 32); + i = getenv_f("testmem", s, 32); if (i != 0) { i = (int) simple_strtoul (s, NULL, 10); if ((i > 0) && (i < 0xf)) { diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index af3a98a..7400ca6 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -589,7 +589,7 @@ int checkboard (void) puts ("Board: "); get_pcbrev_var(&bc,&var); - i = getenv_r ("serial#", (char *)s, 32); + i = getenv_f("serial#", (char *)s, 32); if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) { get_backup_values (b); if (strncmp (b->signature, "MPL\0", 4) != 0) { diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index e12bc42..7f1164a 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -353,7 +353,7 @@ int checkboard (void) puts ("\nBoard: "); reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING); rev=(char)(SYSCNTR_BREV(reg)+'A'); - i = getenv_r ("serial#", s, 32); + i = getenv_f("serial#", s, 32); if ((i == -1)) { puts ("### No HW ID - assuming " BOARD_NAME); printf(" Rev. %c\n",rev); diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 792eccc..7b48c06 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -579,7 +579,7 @@ int checkboard (void) puts ("Board: "); - i = getenv_r ("serial#", (char *)s, 32); + i = getenv_f("serial#", (char *)s, 32); if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { get_backup_values (b); if (strncmp (b->signature, "MPL\0", 4) != 0) { diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 1835677..eaeec82 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -295,7 +295,7 @@ int checkboard(void) int i; backup_t *b = (backup_t *) s; - i = getenv_r("serial#", s, 32); + i = getenv_f("serial#", s, 32); if ((i < 0) || strncmp (s, "VCMA9", 5)) { get_backup_values (b); if (strncmp (b->signature, "MPL\0", 4) != 0) { @@ -340,7 +340,7 @@ void print_vcma9_info(void) char s[50]; int i; - if ((i = getenv_r("serial#", s, 32)) < 0) { + if ((i = getenv_f("serial#", s, 32)) < 0) { puts ("### No HW ID - assuming VCMA9"); printf("i %d", i*24); } else { diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 5f02bd4..0f7a892 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -82,10 +82,10 @@ lowlevel_init: /* * PLL Settings */ -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 /* start counting at zero */ -WTCSR_D: .long 0xA507 /* divide by 4096 */ - +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 /* start counting at zero */ +WTCSR_D: .word 0xA507 /* divide by 4096 */ +.align 2 /* * Spansion S29GL256N11 @ 48 MHz */ diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S index 7593811..3df25b6 100644 --- a/board/ms7720se/lowlevel_init.S +++ b/board/ms7720se/lowlevel_init.S @@ -114,10 +114,10 @@ FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ WTCNT_A: .long 0xA415FF84 WTCSR_A: .long 0xA415FF86 UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 -WTCSR_D: .long 0xA506 -UCLKCR_D: .long 0xA5C0 +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 +WTCSR_D: .word 0xA506 +UCLKCR_D: .word 0xA5C0 #define BSC_BASE 0xA4FD0000 CMNCR_A: .long BSC_BASE @@ -164,7 +164,8 @@ SDCR_D1: .long 0x00000011 RTCSR_D: .long 0xA55A0010 RTCNT_D: .long 0xA55A001F RTCOR_D: .long 0xA55A001F -SDMR3_D: .long 0x0000 +SDMR3_D: .word 0x0000 +.align 2 SDCR_D2: .long 0x00000811 #define PFC_BASE 0xA4050100 @@ -178,15 +179,16 @@ PTCR_A: .long PFC_BASE + 0x1E PVCR_A: .long PFC_BASE + 0x22 PSELA_A: .long PFC_BASE + 0x24 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PPCR_D: .long 0x00AA -PTCR_D: .long 0x0280 -PVCR_D: .long 0x0000 -PSELA_D: .long 0x0000 +PCCR_D: .word 0x0000 +PDCR_D: .word 0x0000 +PECR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PPCR_D: .word 0x00AA +PTCR_D: .word 0x0280 +PVCR_D: .word 0x0000 +PSELA_D: .word 0x0000 +.align 2 CCR_A: .long 0xFFFFFFEC !CCR_D: .long 0x0000000D diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 5e09a39..3041e64 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -120,13 +120,14 @@ CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R - .long 0x00000e1a /* 12:3:3 */ + .word 0x0e1a /* 12:3:3 */ #else /* CONFIG_CPU_TYPE_R */ #ifdef CONFIG_GOOD_SESH4 - .long 0x00000e13 /* 6:2:1 */ + .word 0x00e13 /* 6:2:1 */ #else - .long 0x00000e23 /* 6:1:1 */ + .word 0x00e23 /* 6:1:1 */ #endif +.align 2 #endif /* CONFIG_CPU_TYPE_R */ BCR1_A: .long BCR1 @@ -140,15 +141,19 @@ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR3_A: .long WCR3 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ RTCSR_A: .long RTCSR -RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ +RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ +.align 2 RTCNT_A: .long RTCNT -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR -RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ +RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ +.align 2 SDMR3_A: .long SDMR3_ADDRESS SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE RFCR_A: .long RFCR -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ +.align 2 diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 9a6cd1b..358cc54 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c index 1808abd..bf0188c 100644 --- a/board/ppmc8260/ppmc8260.c +++ b/board/ppmc8260/ppmc8260.c @@ -285,7 +285,7 @@ int misc_init_r (void) int res; if ((ds != 0) && (ds != 0xff)) { - res = getenv_r ("ethaddr", (char *)tmp, sizeof (tmp)); + res = getenv_f("ethaddr", (char *)tmp, sizeof (tmp)); if (res > 0) { ss = ((ds >> 4) & 0x0f); ss += ss < 0x0a ? '0' : ('a' - 10); diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index 8fcc155..567ae99 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -99,9 +99,9 @@ int mv64460_eth_receive (struct eth_device *dev); int mv64460_eth_xmit (struct eth_device *, volatile void *packet, int length); -int mv_miiphy_read(char *devname, unsigned char phy_addr, +int mv_miiphy_read(const char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short *value); -int mv_miiphy_write(char *devname, unsigned char phy_addr, +int mv_miiphy_write(const char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short value); int phy_setup_aneg (char *devname, unsigned char addr); @@ -298,7 +298,7 @@ void mv6446x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -397,7 +397,7 @@ void mv6446x_eth_initialize (bd_t * bis) return; } - temp = getenv_r (s, buf, sizeof (buf)); + temp = getenv_f(s, buf, sizeof (buf)); s = (temp > 0) ? buf : NULL; #ifdef DEBUG @@ -2544,7 +2544,7 @@ static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, return true; } -int mv_miiphy_read(char *devname, unsigned char phy_addr, +int mv_miiphy_read(const char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short *value) { unsigned int reg_value; @@ -2629,7 +2629,7 @@ static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, return true; } -int mv_miiphy_write(char *devname, unsigned char phy_addr, +int mv_miiphy_write(const char *devname, unsigned char phy_addr, unsigned char phy_reg, unsigned short value) { unsigned int reg_value; diff --git a/board/purple/flash.c b/board/purple/flash.c index 37c7bec..5cee35e 100644 --- a/board/purple/flash.c +++ b/board/purple/flash.c @@ -448,7 +448,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) FPWV *addr; int flag, prot, sect; ulong start, now, last; - int rcode = 0; FUNCPTR_WR absEntry; load_cmd(IN_RAM_CMD_WRITE); @@ -490,7 +489,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = get_timer(0); /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { + for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] != 0) /* protected, skip it */ continue; @@ -523,7 +522,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } printf (" done\n"); - return rcode; + return 0; } /*----------------------------------------------------------------------- diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 1881e65..542601a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index ad058ca..bd16786 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 0daf25a..04cfef1 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -119,15 +119,16 @@ lowlevel_init: DRVCRA_A: .long DRVCRA DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 +DRVCRA_D: .word 0x4555 +DRVCRB_D: .word 0x0005 RWTCSR_A: .long RWTCSR RWTCNT_A: .long RWTCNT FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 +RWTCSR_D1: .word 0xa507 +RWTCSR_D2: .word 0xa504 +RWTCNT_D: .word 0x5a00 +.align 2 FRQCR_D: .long 0x0b04474a SBSC_SDCR_A: .long SBSC_SDCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 76d3cfc..f3392f0 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -94,11 +94,14 @@ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .word 0xA534 /* RTCOR Write Code */ +.align 2 RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +RTCSR_D: .word 0xA510 /* RTCSR Write Code */ +.align 2 SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D0: .long 0x55 SDMR3_D1: .long 0x00 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 7b9ecd8..30ef5ab 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -73,7 +73,7 @@ init_bsc_cs0: write32 CMNCR_A, CMNCR_D - write32 SC0BCR_A, SC0BCR_D + write32 CS0BCR_A, CS0BCR_D write32 CS0WCR_A, CS0WCR_D @@ -122,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -190,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 3747bf6..5b18200 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -266,8 +266,8 @@ SDR4_D: .long 0x00000300 SDMR00308_D: .long 0x00000000 SDMR00B08_D: .long 0x00000000 SDMR02000_D: .long 0x00000000 -PSEL0_D: .long 0x00000001 -PSEL1_D: .long 0x00000244 +PSEL0_D: .word 0x00000001 +PSEL1_D: .word 0x00000244 SR_MASK_D: .long 0xEFFFFF0F WDTST_D: .long 0x5A000FFF WDTCSR_D: .long 0xA5000000 diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 40d9b08..86f6783 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -68,22 +68,22 @@ lowlevel_init: wait_timer WAIT_200US /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D write16 PHCR_A, PHCR_D write16 PJCR_A, PJCR_D write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D + write16 PLCR_A, PXCR_D write16 PMCR_A, PMCR_D write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D write8 PEPUPR_A, PEPUPR_D write8 PHPUPR_A, PHPUPR_D @@ -179,22 +179,14 @@ lbsc_end: .align 4 /*------- GPIO -------*/ -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 PEPUPR_D: .long 0xff PHPUPR_D: .long 0x00 @@ -203,10 +195,10 @@ PKPUPR_D: .long 0x00 PLPUPR_D: .long 0x00 PMPUPR_D: .long 0xfc PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 #define GPIO_BASE 0xffe70000 PACR_A: .long GPIO_BASE + 0x00 diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 74e6204..33b4d11 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -79,7 +79,7 @@ int misc_init_r (void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c index f5f23be..33ce1a4 100644 --- a/board/sbc8260/sbc8260.c +++ b/board/sbc8260/sbc8260.c @@ -267,7 +267,7 @@ int misc_init_r (void) int res; if ((ds != 0) && (ds != 0xff)) { - res = getenv_r ("ethaddr", tmp, sizeof (tmp)); + res = getenv_f("ethaddr", tmp, sizeof (tmp)); if (res > 0) { ss = ((ds >> 4) & 0x0f); ss += ss < 0x0a ? '0' : ('a' - 10); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 10ba62f..77abde5 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -225,7 +225,7 @@ void reset_phy (void) #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); + miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); diff --git a/board/sc3/config.mk b/board/sc3/config.mk index 1bdf5e4..a46b197 100644 --- a/board/sc3/config.mk +++ b/board/sc3/config.mk @@ -21,4 +21,4 @@ # MA 02111-1307 USA # -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFFA0000 diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index 8053da4..e91ceb0 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -102,7 +102,7 @@ int checkboard (void) unsigned char *s; unsigned char buf[64]; - s = (getenv_r ("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; + s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL; puts ("Board: Siemens CCM"); diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index e0611fe..926e491 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -209,7 +209,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c index cc8eaad..43f7495 100644 --- a/board/snmc/qs850/qs850.c +++ b/board/snmc/qs850/qs850.c @@ -100,7 +100,7 @@ int checkboard (void) char buf[64]; int i; - i = getenv_r("serial#", buf, sizeof(buf)); + i = getenv_f("serial#", buf, sizeof(buf)); s = (i>0) ? buf : NULL; if (!s || strncmp(s, BOARD_IDENTITY, 5)) { diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c index b272d80..fa88707 100644 --- a/board/snmc/qs860t/qs860t.c +++ b/board/snmc/qs860t/qs860t.c @@ -93,7 +93,7 @@ int checkboard (void) char buf[64]; int i; - i = getenv_r("serial#", buf, sizeof(buf)); + i = getenv_f("serial#", buf, sizeof(buf)); s = (i>0) ? buf : NULL; if (!s || strncmp(s, "QS860T", 6)) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 3804fe0..25d5211 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -239,7 +239,7 @@ reset_phy(void) #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); + miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 0b2584c..1e0acab 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -238,7 +238,7 @@ reset_phy(void) #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) /* reset PHY */ - miiphy_reset("FCC1 ETHERNET", 0x0); + miiphy_reset("FCC1", 0x0); /* change PHY address to 0x02 */ bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028); diff --git a/board/stx/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c index 717dbe2..6693a70 100644 --- a/board/stx/stxxtc/stxxtc.c +++ b/board/stx/stxxtc/stxxtc.c @@ -481,12 +481,12 @@ void reset_phys(void) mii_init(); for (phyno = 0; phyno < 32; ++phyno) { - miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v); + miiphy_read("FEC", phyno, PHY_PHYIDR1, &v); if (v == 0xFFFF) continue; - miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD); + miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_POWD); udelay(10000); - miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + miiphy_write("FEC", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); udelay(10000); } } diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100644 index 0000000..87d2234 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100644 index 0000000..c661f0b --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100644 index 0000000..04d2f9d --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,170 @@ +/* + * (c) 2010 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mb86r0x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) + MB86R0x_CCNT_BASE; + + /* We select mode 0 for group 2 and mode 1 for group 4 */ + writel(0x00000010, &ccnt->cmux_md); + + gd->flags = 0; + gd->bd->bi_arch_number = MACH_TYPE_JADECPU; + gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; + + icache_enable(); + + return 0; +} + +static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, + unsigned long pwm_base) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; + const char *e; + + writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); + + e = getenv(pwm_opts); + if (e != NULL) { + const char *s; + uint32_t freq, init; + + freq = 0; + init = 0; + + s = strchr(e, 'f'); + if (s != NULL) + freq = simple_strtol(s + 2, NULL, 0); + + s = strchr(e, 'i'); + if (s != NULL) + init = simple_strtol(s + 2, NULL, 0); + + if (freq > 0) { + writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, + &pwm->bcr); + writel(1002, &pwm->tpr); + writel(1, &pwm->pr); + writel(init * 10 + 1, &pwm->dr); + writel(1, &pwm->cr); + writel(1, &pwm->sr); + } + } +} + +int board_late_init(void) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + uint32_t in_word; + +#ifdef CONFIG_VIDEO_MB86R0xGDC + /* Check if we have valid display settings and turn on power if so */ + /* Display 0 */ + if (getenv("gs_dsp_0_param") || getenv("videomode")) + setup_display_power((1 << 3), "gs_dsp_0_pwm", + MB86R0x_PWM0_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); + + /* Display 1 */ + if (getenv("gs_dsp_1_param") || getenv("videomode1")) + setup_display_power((1 << 4), "gs_dsp_1_pwm", + MB86R0x_PWM1_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); +#endif /* CONFIG_VIDEO_MB86R0xGDC */ + + /* 5V enable */ + writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); + writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); + + /* We have special boot options if told by GPIOs */ + in_word = readl(&gpio->gpdr1); + + if ((in_word & 0xC0) == 0xC0) { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + setenv("preboot", "run gs_slow_boot"); + } else if ((in_word & 0xC0) != 0) { + setenv("stdout", "vga"); + setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" + "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" + "bootelf 0x40000000; bootelf 0x10080000"); + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + if (getenv("gs_devel")) { + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("gs_bootcmd", "bootelf 0x10080000"); + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +/* + * DRAM configuration + */ +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100644 index 0000000..5ad4dce --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,265 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/mb86r0x.h> +#include <asm/arch/asm-offsets.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/* + * Initialize Clock Reset Generator (CRG) + */ + + ldr r0, =MB86R0x_CRG_BASE + + /* Not change the initial value that is set by external pin.*/ +WAIT_PLL: + ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ + tst r2, #MB86R0x_CRG_CRPR_PLLRDY + beq WAIT_PLL + + /* Set clock gate control */ + ldr r1, =CONFIG_SYS_CRG_CRHA_INIT + str r1, [r0, #CRG_CRHA] + ldr r1, =CONFIG_SYS_CRG_CRPA_INIT + str r1, [r0, #CRG_CRPA] + ldr r1, =CONFIG_SYS_CRG_CRPB_INIT + str r1, [r0, #CRG_CRPB] + ldr r1, =CONFIG_SYS_CRG_CRHB_INIT + str r1, [r0, #CRG_CRHB] + ldr r1, =CONFIG_SYS_CRG_CRAM_INIT + str r1, [r0, #CRG_CRAM] + +/* + * Initialize External Bus Interface + */ + ldr r0, =MB86R0x_MEMC_BASE + + ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT + str r1, [r0, #MEMC_MCFMODE0] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT + str r1, [r0, #MEMC_MCFMODE2] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT + str r1, [r0, #MEMC_MCFMODE4] + + ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT + str r1, [r0, #MEMC_MCFTIM0] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT + str r1, [r0, #MEMC_MCFTIM2] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT + str r1, [r0, #MEMC_MCFTIM4] + + ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT + str r1, [r0, #MEMC_MCFAREA0] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT + str r1, [r0, #MEMC_MCFAREA2] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT + str r1, [r0, #MEMC_MCFAREA4] + +/* + * Initialize DDR2 Controller + */ + + /* Wait for PLL LOCK up time or more */ + wait_timer 20 + + /* + * (2) Initialize DDRIF + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT + strh r1, [r0, #DDR2_DRIMS] + + /* + * (3) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (4) IRESET/IUSRRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 + str r1, [r0, #CCNT_CDCRC] + + /* + * (5) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (6) IDLLRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 + str r1, [r0, #CCNT_CDCRC] + + /* + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) + */ + wait_timer 33536 + + /* + * (9) MCKE ON + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT + strh r1, [r0, #DDR2_DRCA] + ldr r1, =MB86R0x_DDR2_DRCI_INIT + strh r1, [r0, #DDR2_DRIC] + + /* + * (10) Initialize SDRAM + */ + + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 67 /* 400ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 18 /* 105ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 /* MRS to OCD: 200clock */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT + strh r1, [r0, #DDR2_DRCM] + + ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT + strh r1, [r0, #DDR2_DRCST1] + + ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT + strh r1, [r0, #DDR2_DRCST2] + + ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT + strh r1, [r0, #DDR2_DRCR] + + ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT + strh r1, [r0, #DDR2_DRCF] + + ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT + strh r1, [r0, #DDR2_DRASR] + + /* + * (11) ODT setting + */ + ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT + strh r1, [r0, #DDR2_DROBS] + ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT + strh r1, [r0, #DDR2_DROABA] + ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT + strh r1, [r0, #DDR2_DRIBSODT1] + + /* + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode + */ + ldr r1, =CONFIG_SYS_DDR2_DROS_INIT + strh r1, [r0, #DDR2_DROS] + ldr r1, =MB86R0x_DDR2_DRCI_NORMAL + strh r1, [r0, #DDR2_DRIC] + + mov pc, lr diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 917bbec..1b8153b 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -24,6 +24,8 @@ #include <common.h> #include <asm/arch/sys_proto.h> +#include "panda.h" + DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { @@ -61,3 +63,27 @@ int misc_init_r(void) { return 0; } + +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +/** + * @brief set_muxconf_regs Setting up the configuration Mux registers + * specific to the board. + */ +void set_muxconf_regs(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, + sizeof(core_padconf_array) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, + sizeof(wkup_padconf_array) / + sizeof(struct pad_conf_entry)); +} diff --git a/board/ti/panda/panda.h b/board/ti/panda/panda.h new file mode 100644 index 0000000..8f6a6b1 --- /dev/null +++ b/board/ti/panda/panda.h @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy <balajitk@ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PANDA_H_ +#define _PANDA_H_ + +#include <asm/io.h> +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array[] = { + {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ + {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ + {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ + {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ + {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ + {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ + {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ + {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48 */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ + {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ + {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ + {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ + {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ + {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ + {UNIPRO_TX2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_0 */ + {UNIPRO_TY2, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_1 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (IEN | M5)}, /* dispc2_data3 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +}; + +const struct pad_conf_entry wkup_padconf_array[] = { + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +}; + +#endif + diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 8ed7873..7039bd5 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -25,6 +25,8 @@ #include <common.h> #include <asm/arch/sys_proto.h> +#include "sdp.h" + DECLARE_GLOBAL_DATA_PTR; const struct omap_sysinfo sysinfo = { @@ -62,3 +64,27 @@ int misc_init_r(void) { return 0; } + +void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) +{ + int i; + struct pad_conf_entry *pad = (struct pad_conf_entry *) array; + + for (i = 0; i < size; i++, pad++) + writew(pad->val, base + pad->offset); +} + +/** + * @brief set_muxconf_regs Setting up the configuration Mux registers + * specific to the board. + */ +void set_muxconf_regs(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array, + sizeof(core_padconf_array) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array, + sizeof(wkup_padconf_array) / + sizeof(struct pad_conf_entry)); +} diff --git a/board/ti/sdp4430/sdp.h b/board/ti/sdp4430/sdp.h new file mode 100644 index 0000000..803e3d3 --- /dev/null +++ b/board/ti/sdp4430/sdp.h @@ -0,0 +1,265 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy <balajitk@ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SDP_H_ +#define _SDP_H_ + +#include <asm/io.h> +#include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array[] = { + {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ + {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ + {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ + {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ + {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ + {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ + {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ + {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48 */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ + {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ + {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ + {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ + {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | M1)}, /* abe_slimbus1_clock */ + {ABE_MCBSP1_DR, (IEN | M1)}, /* abe_slimbus1_data */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ + {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ + {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M3)}, /* gpio_27 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +}; + +const struct pad_conf_entry wkup_padconf_array[] = { + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +}; + +#endif + diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c index 3039999..95073b8 100644 --- a/board/tqc/tqm8260/tqm8260.c +++ b/board/tqc/tqm8260/tqm8260.c @@ -196,7 +196,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof (str)); + int i = getenv_f("serial#", str, sizeof (str)); puts ("Board: "); diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 53f79e8..cde780b 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -745,13 +745,13 @@ int last_stage_init(void) return 0; for (i = 0; i < 2; i++) { - ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, ®); + ret = miiphy_read("FEC", phy[i], PHY_BMCR, ®); if (ret) { printf("Cannot read BMCR on PHY %d\n", phy[i]); return 0; } /* Auto-negotiation off, hard set full duplex, 100Mbps */ - ret = miiphy_write("FEC ETHERNET", phy[i], + ret = miiphy_write("FEC", phy[i], PHY_BMCR, (reg | PHY_BMCR_100MB | PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON); if (ret) { diff --git a/board/trab/trab.c b/board/trab/trab.c index 12fe120..828facd 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -414,7 +414,7 @@ static void tsc2000_set_brightness(void) spi_init(); tsc2000_write(1, 2, 0x0); /* Power up DAC */ - i = getenv_r("brightness", tmp, sizeof(tmp)); + i = getenv_f("brightness", tmp, sizeof(tmp)); br = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) : CONFIG_SYS_BRIGHTNESS; diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c index 4dba290..bdee4de 100644 --- a/board/uc100/uc100.c +++ b/board/uc100/uc100.c @@ -150,7 +150,7 @@ int board_switch(void) int checkboard (void) { char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_f("serial#", str, sizeof(str)); puts ("Board: "); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 8ba1b19..2272ff0 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -101,7 +101,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index 0f3eacd..c6f4c7c 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -24,25 +24,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := vpac270.o +COBJS := vpac270.o SOBJS := lowlevel_init.o -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 48e93ab..18e47e2 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; |