diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/cray/L1/L1.c | 302 | ||||
| -rw-r--r-- | board/cray/L1/L1.h | 44 | ||||
| -rw-r--r-- | board/evb64260/local.h | 60 | ||||
| -rw-r--r-- | board/genietv/genietv.h | 25 | ||||
| -rw-r--r-- | board/pn62/pn62.h | 161 |
5 files changed, 592 insertions, 0 deletions
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c new file mode 100644 index 0000000..f5dfba4 --- /dev/null +++ b/board/cray/L1/L1.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <405gp_i2c.h> +#include <command.h> +#include <cmd_nvedit.h> +#include <cmd_bootm.h> +#include <rtc.h> +#include <net.h> +#include <malloc.h> + +#define L1_MEMSIZE (32*1024*1024) + +/* the std. DHCP stufff */ +#define DHCP_ROUTER 3 +#define DHCP_NETMASK 1 +#define DHCP_BOOTFILE 67 +#define DHCP_ROOTPATH 17 +#define DHCP_HOSTNAME 12 + +/* some extras used by CRAY + * + * on the server this looks like: + * + * option L1-initrd-image code 224 = string; + * option L1-initrd-image "/opt/craysv2/craymcu/l1/flash/initrd.image" + */ +#define DHCP_L1_INITRD 224 + +/* new, [better?] way via official vendor-extensions, defining an option + * space. + * on the server this looks like: + * + * option space U-Boot; + * option U-Boot.initrd code 3 = string; + * option U-Boot.bootcmd code 4 = string; + * option U-Boot.bootflags code 5 = string; + * option U-Boot.rootdev code 6 = string; + */ +#define DHCP_VENDOR_SPECX 43 +#define DHCP_VX_INITRD 3 +#define DHCP_VX_BOOTCMD 4 +#define DHCP_VX_BOOTFLAGS 5 +#define DHCP_VX_ROOTDEV 6 + +/* Things DHCP server can tellme about. If there's no flash address, then + * they dont participate in 'update' to flash, and we force their values + * back to '0' every boot to be sure to get them fresh from DHCP. Yes, I + * know this is a pain... + * + * If I get no bootfile, boot from flash. If rootpath, use that. If no + * rootpath use initrd in flash. + */ +typedef struct dhcp_item_s { + u8 dhcp_option; + u8 dhcp_vendor_option; + char *dhcpvalue; + char *envname; +} dhcp_item_t; +static dhcp_item_t Things[] = { + {DHCP_ROUTER, 0, NULL, "gateway"}, + {DHCP_NETMASK, 0, NULL, "netmask"}, + {DHCP_BOOTFILE, 0, NULL, "bootfile"}, + {DHCP_ROOTPATH, 0, NULL, "rootpath"}, + {DHCP_HOSTNAME, 0, NULL, "hostname"}, + {DHCP_L1_INITRD, 0, NULL, "initrd"}, +/* and the other way.. */ + {DHCP_VENDOR_SPECX, DHCP_VX_INITRD, NULL, "initrd"}, + {DHCP_VENDOR_SPECX, DHCP_VX_BOOTCMD, NULL, "bootcmd"}, + {DHCP_VENDOR_SPECX, DHCP_VX_BOOTFLAGS, NULL, NULL}, + {DHCP_VENDOR_SPECX, DHCP_VX_ROOTDEV, NULL, NULL}, +}; + +#define N_THINGS ((sizeof(Things))/(sizeof(dhcp_item_t))) + +static void init_ecc_sdram (void); + +/* ------------------------------------------------------------------------- */ +int board_pre_init (void) +{ + init_ecc_sdram (); + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ + mtdcr (uictr, 0x10000000); /* set int trigger levels */ + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + return 0; +} + +/* ------------------------------------------------------------------------- */ +int checkboard (void) +{ + return (0); +} + +/* ------------------------------------------------------------------------- */ +int misc_init_r (void) +{ + unsigned char *s, *e; + image_header_t *hdr; + time_t timestamp; + struct rtc_time tm; + + hdr = (image_header_t *) (CFG_MONITOR_BASE - sizeof (image_header_t)); + timestamp = (time_t) hdr->ih_time; + to_tm (timestamp, &tm); + printf ("Welcome to U-Boot on Cray L1. Compiled %4d-%02d-%02d %2d:%02d:%02d (UTC)\n", tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); + +#define FACTORY_SETTINGS 0xFFFC0000 + if ((s = getenv ("ethaddr")) == NULL) { + e = (unsigned char *) (FACTORY_SETTINGS); + if (*(e + 0) != '0' + || *(e + 1) != '0' + || *(e + 2) != ':' + || *(e + 3) != '4' || *(e + 4) != '0' || *(e + 17) != '\0') { + printf ("No valid MAC address in flash location 0x3C0000!\n"); + } else { + printf ("Factory MAC: %s\n", e); + setenv ("ethaddr", e); + } + } + return (0); +} + +/* ------------------------------------------------------------------------- */ +long int initdram (int board_type) +{ + return (L1_MEMSIZE); +} + +/* ------------------------------------------------------------------------- */ +/* stubs so we can print dates w/o any nvram RTC.*/ +void rtc_get (struct rtc_time *tmp) +{ + return; +} +void rtc_set (struct rtc_time *tmp) +{ + return; +} +void rtc_reset (void) +{ + return; +} + +/* ------------------------------------------------------------------------- */ +/* Do sdram bank init in C so I can read it.. + */ +static void init_ecc_sdram (void) +{ + unsigned long tmp, *p; + + /* write SDRAM bank 0 register */ + mtdcr (memcfga, mem_mb0cf); + mtdcr (memcfgd, 0x00062001); + +/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ +/* To set the appropriate timings, we need to know the SDRAM speed. */ +/* We can use the PLB speed since the SDRAM speed is the same as */ +/* the PLB speed. The PLB speed is the FBK divider times the */ +/* 405GP reference clock, which on the L1 is 25Mhz. */ +/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ +/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ + + /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ + +/* write SDRAM timing for 100Mhz. */ + mtdcr (memcfga, mem_sdtr1); + mtdcr (memcfgd, 0x0086400D); + +/* write SDRAM refresh interval register */ + mtdcr (memcfga, mem_rtr); + mtdcr (memcfgd, 0x05F00000); + udelay (200); + +/* sdram controller.*/ + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, 0x90800000); + udelay (200); + +/* disable ECC on all banks */ + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + tmp &= 0xff0fffff; + mtdcr (memcfga, mem_ecccf); + mtdcr (memcfgd, tmp); + +/* set up SDRAM Controller with ECC enabled */ + mtdcr (memcfga, mem_mcopt1); + tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; + mtdcr (memcfga, mem_mcopt1); + mtdcr (memcfgd, tmp); + udelay (600); + +/* fill all the memory */ + for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); + *p++ = 0L); + udelay (400); + mtdcr (memcfga, mem_ecccf); + tmp = mfdcr (memcfgd); + +/* enable ECC on bank 0 */ + tmp |= 0x00800000; + mtdcr (memcfgd, tmp); + udelay (400); + + return; +} + +/* ------------------------------------------------------------------------- */ +static u8 *dhcp_env_update (u8 thing, u8 * pop) +{ + u8 i, oplen; + + oplen = *(pop + 1); + + if ((Things[thing].dhcpvalue = malloc (oplen)) == NULL) { + printf ("Whoops! failed to malloc space for DHCP thing %s\n", + Things[thing].envname); + return NULL; + } + for (i = 0; (i < oplen); i++) + if ((*(Things[thing].dhcpvalue + i) = *(pop + 2 + i)) == ' ') + break; + *(Things[thing].dhcpvalue + i) = '\0'; + +/* set env. */ + if (Things[thing].envname) + setenv (Things[thing].envname, Things[thing].dhcpvalue); + return (Things[thing].dhcpvalue); +} + +/* ------------------------------------------------------------------------- */ +u8 *dhcp_vendorex_prep (u8 * e) +{ + u8 thing; + +/* ask for the things I want. */ + *e++ = 55; /* Parameter Request List */ + *e++ = N_THINGS; + for (thing = 0; thing < N_THINGS; thing++) + *e++ = Things[thing].dhcp_option; + *e++ = 255; + + return e; +} + +/* ------------------------------------------------------------------------- */ +/* .. return NULL means it wasnt mine, non-null means I got it..*/ +u8 *dhcp_vendorex_proc (u8 * pop) +{ + u8 oplen, *sub_op, sub_oplen, *retval; + u8 thing = 0; + + retval = NULL; + oplen = *(pop + 1); +/* if pop is vender spec indicator, there are sub-options. */ + if (*pop == DHCP_VENDOR_SPECX) { + for (sub_op = pop + 2; + oplen && (sub_oplen = *(sub_op + 1)); + oplen -= sub_oplen, sub_op += (sub_oplen + 2)) { + for (thing = 0; thing < N_THINGS; thing++) { + if (*sub_op == Things[thing].dhcp_vendor_option) { + if (!(retval = dhcp_env_update (thing, sub_op))) { + return NULL; + } + } + } + } + } else { + for (thing = 0; thing < N_THINGS; thing++) { + if (*pop == Things[thing].dhcp_option) + if (!(retval = dhcp_env_update (thing, pop))) + return NULL; + } + } + return (thing >= N_THINGS ? NULL : pop); +} diff --git a/board/cray/L1/L1.h b/board/cray/L1/L1.h new file mode 100644 index 0000000..1b41824 --- /dev/null +++ b/board/cray/L1/L1.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/**************************************************************************** + * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip + * + * Start Address Length + * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- + * | Failsafe Linux Image | (1M) + * +=======================+ 0xFFD0_0000 + * | (Reserved FlashFiles) | (1M) + * +=======================+ 0xFFE0_0000 + * | Failsafe RootFS | (1M) + * +=======================+ 0xFFF0_0000 + * | | + * | U N U S E D | + * | | + * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) + * | environment settings | (64k) + * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) + * | U-Boot | 0xFFFE_0040 _start of U-Boot + * | | 0xFFFE_FFFC reset vector - branch to _start + * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- + *****************************************************************************/ diff --git a/board/evb64260/local.h b/board/evb64260/local.h new file mode 100644 index 0000000..6d1fb4c --- /dev/null +++ b/board/evb64260/local.h @@ -0,0 +1,60 @@ +/* + * include/local.h - local configuration options, board specific + */ + +#ifndef __LOCAL_H +#define __LOCAL_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +/* This tells U-Boot that the config options are compiled in */ +/* #undef ENV_IS_EMBEDDED */ +/* Don't touch this! U-Boot figures this out based on other + * magic. */ + +/* Uncomment and define any of the below options */ + +/* #define CONFIG_750CX */ /* The 750CX doesn't support as many things in L2CR */ + /* Note: If you defined CONFIG_EVB64260_750CX this */ + /* gets defined automatically. */ + +/* These want string arguments */ +/* #define CONFIG_BOOTARGS */ +/* #define CONFIG_BOOTCOMMAND */ +/* #define CONFIG_RAMBOOTCOMMAND */ +/* #define CONFIG_NFSBOOTCOMMAND */ +/* #define CFG_AUTOLOAD */ +/* #define CONFIG_PREBOOT */ + +/* These don't */ + +/* #define CONFIG_BOOTDELAY */ +/* #define CONFIG_BAUDRATE */ +/* #define CONFIG_LOADS_ECHO */ +/* #define CONFIG_ETHADDR */ +/* #define CONFIG_ETH2ADDR */ +/* #define CONFIG_ETH3ADDR */ +/* #define CONFIG_IPADDR */ +/* #define CONFIG_SERVERIP */ +/* #define CONFIG_ROOTPATH */ +/* #define CONFIG_GATEWAYIP */ +/* #define CONFIG_NETMASK */ +/* #define CONFIG_HOSTNAME */ +/* #define CONFIG_BOOTFILE */ +/* #define CONFIG_LOADADDR */ + +/* these hardware addresses are pretty bogus, please change them to + suit your needs */ + +/* first ethernet */ +#define CONFIG_ETHADDR 00:11:22:33:44:55 + +/* next two ethernet hwaddrs */ +#define CONFIG_ETH1ADDR 00:11:22:33:44:66 +#define CONFIG_ETH2ADDR 00:11:22:33:44:77 + +#define CONFIG_ENV_OVERWRITE +#endif /* __CONFIG_H */ diff --git a/board/genietv/genietv.h b/board/genietv/genietv.h new file mode 100644 index 0000000..7c95b56 --- /dev/null +++ b/board/genietv/genietv.h @@ -0,0 +1,25 @@ +/* + * The GENIETV is using the following physical memorymap (copied from + * the FADS configuration): + * + * ff020000 -> ff02ffff : pcmcia + * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM + * ff000000 -> ff00ffff : IMAP internal in the cpu + * 02800000 -> 0287ffff : flash connected to CS0 + * 00000000 -> nnnnnnnn : sdram setup by U-Boot + * + * CS pins are connected as follows: + * + * CS0 -512Kb boot flash + * CS1 - SDRAM #1 + * CS2 - SDRAM #2 + * CS3 - Flash #1 + * CS4 - Flash #2 + * CS5 - LON (if present) + * CS6 - PCMCIA #1 + * CS7 - PCMCIA #2 + * + * Ports are configured as follows: + * + * PA7 - SDRAM banks enable + */ diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h new file mode 100644 index 0000000..7bda0ad --- /dev/null +++ b/board/pn62/pn62.h @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PN62_H_ +#define _PN62_H_ + +/* + * Definitions for the Intel Bridge 21554 or 21555. + */ +#define I2155X_VPD_ADDR 0xe6 +#define I2155X_VPD_DATA 0xe8 + +#define I2155X_VPD_START 0x80 +#define I2155X_VPD_SN_START 0x80 +#define I2155X_VPD_SN_SIZE 0x10 +#define I2155X_VPD_MAC0_START 0x90 +#define I2155X_VPD_MAC1_START 0x96 + +#define I2155X_SCRAPAD_ADDR 0xa8 +#define I2155X_SCRAPAD_MAX 8 + +#define I2155X_BAR2_BASE 0x98 +#define I2155X_BAR3_BASE 0x9c +#define I2155X_BAR4_BASE 0xa0 + +#define I2155X_BAR2_SETUP 0xb0 +#define I2155X_BAR3_SETUP 0xb4 +#define I2155X_BAR4_SETUP 0xb8 + +/* + * Interrupt request numbers + */ +#define PN62_IRQ_HOST 0x0 +#define PN62_IRQ_PLX9054 0x1 +#define PN62_IRQ_ETH0 0x2 +#define PN62_IRQ_ETH1 0x3 +#define PN62_IRQ_COM1 0x4 +#define PN62_IRQ_COM2 0x4 + +/* + * Miscellaneous definitons. + */ +#define PN62_SMEM_DEFAULT 0x1f00000 + +/* + * Definitions for boot protocol using Scratchpad registers. + */ +#define BOOT_DONE 0 +#define BOOT_DONE_CLEAR 0x00dead00 +#define BOOT_DONE_ERROR 0xbad0dead +#define BOOT_DONE_U_BOOT 0x12345678 +#define BOOT_DONE_LINUX 0x87654321 +#define BOOT_CMD 1 +#define BOOT_CMD_MOVE 0x1 +#define BOOT_CMD_BOOT 0x2 +#define BOOT_DATA 2 +#define BOOT_PROTO 3 +#define BOOT_PROTO_READY 0x23456789 +#define BOOT_PROTO_CLEAR 0x00000000 +#define BOOT_STATUS 4 + +/* + * LED Definitions: + */ +#define PN62_LED_BASE 0xff800300 +#define PN62_LED_MAX 12 + +/* + * LED0 - 7 mounted on top of board, D1 - D8 + * LED8 - 11 upper four LEDs on the front panel of the board. + */ +#define LED_0 0x00 /* OFF */ +#define LED_1 0x01 /* ON */ +#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */ +#define LED_nSLOW_CLOCK 0x03 /* inverse of above */ +#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */ +#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */ + +/* + * LED's currently setup in AMD79C973 device as the following: + * LED0 100Mbit + * LED1 LNKSE + * LED2 TX Activity + * LED3 RX Activity + */ +#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */ +#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */ +#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */ +#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */ +#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */ +#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */ +#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */ +#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */ +#define LED_STROBE0 0x10 /* Processor Strobe 0 */ +#define LED_STROBE1 0x11 /* Processor Strobe 1 */ +#define LED_STROBE2 0x12 /* Processor Strobe 2 */ +#define LED_STROBE3 0x13 /* Processor Strobe 3 */ +#define LED_STROBE4 0x14 /* Processor Strobe 4 */ +#define LED_STROBE5 0x15 /* Processor Strobe 5 */ +#define LED_STROBE6 0x16 /* Processor Strobe 6 */ +#define LED_STROBE7 0x17 /* Processor Strobe 7 */ +#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */ +#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */ +#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */ +#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */ +#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */ +#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */ +#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */ +#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */ +#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */ +#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */ +#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */ +#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */ +#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */ +#define LED_UART0_CS 0x25 /* UART 0 Chip Select */ +#define LED_UART1_CS 0x26 /* UART 1 Chip Select */ +#define LED_SRAM_CS 0x27 /* SRAM Chip Select */ +#define LED_SRAM_WR 0x28 /* SRAM WR Signal */ +#define LED_SRAM_RD 0x29 /* SRAM RD Signal */ +#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */ +#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */ +#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */ +#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */ +#define LED_LAST_FUNCTION LED_HOST_INT /* last function */ + +/* + * Forward declarations + */ +int i2155x_init (void); +void i2155x_write_scrapad(int idx, u32 val); +u32 i2155x_read_scrapad (int idx); +void i2155x_set_bar_base (int bar, u32 addr); +int i2155x_read_vpd (int offset, int size, unsigned char *data); + +int am79c95x_init (void); + +void set_led (unsigned int number, unsigned int function); +void fatal_error (unsigned int error_code); +void show_startup_phase (int phase); + + +#endif /* _PN62_H_ */ |