diff options
Diffstat (limited to 'board')
32 files changed, 3802 insertions, 125 deletions
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 3d4ac85..45bcd4b 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -90,7 +90,7 @@ tlbtab: /* * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I - */ + */ #ifndef CONFIG_NAND_SPL tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) #else diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 53f728d..77f1438 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -1,5 +1,12 @@ /* * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -18,10 +25,352 @@ * MA 02111-1307 USA */ +/* define DEBUG for debug output */ +#undef DEBUG + #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <ppc440.h> +#include "sdram.h" + +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ + defined(CONFIG_DDR_DATA_EYE) +/*-----------------------------------------------------------------------------+ + * wait_for_dlllock. + +----------------------------------------------------------------------------*/ +static int wait_for_dlllock(void) +{ + unsigned long val; + int wait = 0; + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} +#endif + +#if defined(CONFIG_DDR_DATA_EYE) +/*-----------------------------------------------------------------------------+ + * wait_for_dram_init_complete. + +----------------------------------------------------------------------------*/ +int wait_for_dram_init_complete(void) +{ + unsigned long val; + int wait = 0; + + /* --------------------------------------------------------------+ + * Wait for 'DRAM initialization complete' bit in status register + * -------------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + + debug("DRAM initialization complete bit in status register did not rise\n"); + + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +/*-----------------------------------------------------------------------------+ + * denali_core_search_data_eye. + +----------------------------------------------------------------------------*/ +void denali_core_search_data_eye(unsigned long memory_size) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE); + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { + /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j=0; j<NUM_TRIES; j++) { + ram_pointer[j] = test[j]; + + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); + } + + /* read values back */ + for (j=0; j<NUM_TRIES; j++) { + for (k=0; k<NUM_READS; k++) { + /* clear any cache at ram location */ + __asm__("dcbf 0,%0": :"r" (&ram_pointer[j])); + + if (ram_pointer[j] != test[j]) + break; + } + + /* read error */ + if (k != NUM_READS) + break; + } + + /* See if the dll_dqs_delay_X value passed.*/ + if (j < NUM_TRIES) { + /* Failed */ + passing_cases = 0; + /* break; */ + } else { + /* Passed */ + if (passing_cases == 0) + dll_dqs_delay_X_sw_val = dll_dqs_delay_X; + passing_cases++; + if (passing_cases >= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; + dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = dll_dqs_delay_X; + } + } + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* -----------------------------------------------------------+ + * Largest passing window is now detected. + * ----------------------------------------------------------*/ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* -----------------------------------------------------------+ + * De-assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* -----------------------------------------------------------+ + * Set 'wr_dqs_shift' + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + * ----------------------------------------------------------*/ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Set 'dll_dqs_delay_X'. + * ----------------------------------------------------------*/ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* -----------------------------------------------------------+ + * Assert 'start' parameter. + * ----------------------------------------------------------*/ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* -----------------------------------------------------------+ + * Wait for the DCC master delay line to finish calibration + * ----------------------------------------------------------*/ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* CONFIG_DDR_DATA_EYE */ + /************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core @@ -30,8 +379,6 @@ long int initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - volatile ulong val; - mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); @@ -64,14 +411,15 @@ long int initdram (int board_type) mtsdram(DDR0_44, 0x00000005); mtsdram(DDR0_02, 0x00000001); - /* - * Wait for DCC master delay line to finish calibration - */ - mfsdram(DDR0_17, val); - while (((val >> 8) & 0x000007f) == 0) { - mfsdram(DDR0_17, val); - } + wait_for_dlllock(); #endif /* #ifndef CONFIG_NAND_U_BOOT */ +#ifdef CONFIG_DDR_DATA_EYE + /* -----------------------------------------------------------+ + * Perform data eye search if requested. + * ----------------------------------------------------------*/ + denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20); +#endif + return (CFG_MBYTES_SDRAM << 20); } diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h new file mode 100644 index 0000000..48966cf --- /dev/null +++ b/board/amcc/sequoia/sdram.h @@ -0,0 +1,508 @@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPD_SDRAM_DENALI_H_ +#define _SPD_SDRAM_DENALI_H_ + +#define ppcMsync sync +#define ppcMbar eieio + +/* General definitions */ +#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */ +#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */ +#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */ +#define SDRAM_NONE 0 /* No DIMM detected in Slot */ +#define MAXRANKS 2 /* 2 ranks maximum */ + +/* Supported PLB Frequencies */ +#define PLB_FREQ_133MHZ 133333333 +#define PLB_FREQ_152MHZ 152000000 +#define PLB_FREQ_160MHZ 160000000 +#define PLB_FREQ_166MHZ 166666666 + +/* Denali Core Registers */ +#define SDRAM_DCR_BASE 0x10 + +#define DDR_DCR_BASE 0x10 +#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */ +#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */ + +/*-----------------------------------------------------------------------------+ + | Values for ddrcfga register - indirect addressing of these regs + +-----------------------------------------------------------------------------*/ + +#define DDR0_00 0x00 +#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */ +#define DDR0_00_INT_ACK_ALL 0x7F000000 +#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_13 0x0D + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_15 0x0F + +#define DDR0_16 0x10 + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) + +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + + + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_29 0x1D + +#define DDR0_30 0x1E + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index ccf6f0c..b2b82c7 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -31,11 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +ulong flash_get_size (ulong base, int banknum); + int board_early_init_f(void) { - unsigned long sdr0_cust0; - unsigned long sdr0_pfc1, sdr0_pfc2; - register uint reg; + u32 sdr0_cust0; + u32 sdr0_pfc1, sdr0_pfc2; + u32 reg; mtdcr(ebccfga, xbcfg); mtdcr(ebccfgd, 0xb8400000); @@ -140,6 +142,7 @@ int misc_init_r(void) { uint pbcr; int size_val = 0; + u32 reg; #ifdef CONFIG_440EPX unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; @@ -152,6 +155,11 @@ int misc_init_r(void) */ /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) mtdcr(ebccfga, pb3cr); #else @@ -192,9 +200,10 @@ int misc_init_r(void) #endif mtdcr(ebccfgd, pbcr); - /* adjust flash start and offset */ - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; - gd->bd->bi_flashoffset = 0; + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); #ifdef CFG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ @@ -327,18 +336,33 @@ int misc_init_r(void) } #endif /* CONFIG_440EPX */ + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; + mtdcr(plb4_acr, reg); + return 0; } int checkboard(void) { char *s = getenv("serial#"); + u8 rev; + u8 val; #ifdef CONFIG_440EPX printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); #else printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif + + rev = *(u8 *)(CFG_CPLD + 0); + val = *(u8 *)(CFG_CPLD + 5) & 0x01; + printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + if (s != NULL) { puts(", serial# "); puts(s); diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c index 754ae44..04f58e0 100644 --- a/board/amcc/yellowstone/yellowstone.c +++ b/board/amcc/yellowstone/yellowstone.c @@ -39,24 +39,6 @@ int board_early_init_f(void) reg = mfdcr(ebccfgd); mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ - - mtebc(pb1ap, 0x00000000); - mtebc(pb1cr, 0x00000000); - - mtebc(pb2ap, 0x04814500); - /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ - - mtebc(pb3ap, 0x00000000); - mtebc(pb3cr, 0x00000000); - - mtebc(pb4ap, 0x00000000); - mtebc(pb4cr, 0x00000000); - - mtebc(pb5ap, 0x00000000); - mtebc(pb5cr, 0x00000000); - /*-------------------------------------------------------------------- * Setup the GPIO pins *-------------------------------------------------------------------*/ @@ -190,8 +172,15 @@ int misc_init_r (void) int checkboard(void) { char *s = getenv("serial#"); + u8 rev; + u8 val; printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); + + rev = *(u8 *)(CFG_CPLD + 0); + val = *(u8 *)(CFG_CPLD + 5) & 0x01; + printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + if (s != NULL) { puts(", serial# "); puts(s); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 588ee90..d47219c 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -39,24 +39,6 @@ int board_early_init_f(void) reg = mfdcr(ebccfgd); mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ - - mtebc(pb1ap, 0x00000000); - mtebc(pb1cr, 0x00000000); - - mtebc(pb2ap, 0x04814500); - /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ - - mtebc(pb3ap, 0x00000000); - mtebc(pb3cr, 0x00000000); - - mtebc(pb4ap, 0x00000000); - mtebc(pb4cr, 0x00000000); - - mtebc(pb5ap, 0x00000000); - mtebc(pb5cr, 0x00000000); - /*-------------------------------------------------------------------- * Setup the GPIO pins *-------------------------------------------------------------------*/ @@ -186,8 +168,15 @@ int misc_init_r (void) int checkboard(void) { char *s = getenv("serial#"); + u8 rev; + u8 val; printf("Board: Yosemite - AMCC PPC440EP Evaluation Board"); + + rev = *(u8 *)(CFG_CPLD + 0); + val = *(u8 *)(CFG_CPLD + 5) & 0x01; + printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); + if (s != NULL) { puts(", serial# "); puts(s); diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c index 40a827c..f5c3dd9 100644 --- a/board/dave/PPChameleonEVB/nand.c +++ b/board/dave/PPChameleonEVB/nand.c @@ -105,7 +105,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { nand->hwcontrol = ppchameleonevb_hwcontrol; @@ -113,5 +113,6 @@ void board_nand_init(struct nand_chip *nand) nand->eccmode = NAND_ECC_SOFT; nand->chip_delay = NAND_BIG_DELAY_US; nand->options = NAND_SAMSUNG_LP_OPTIONS; + return 0; } #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/delta/nand.c b/board/delta/nand.c index fe648fc..d170938 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -448,7 +448,7 @@ static void dfc_gpio_init(void) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; @@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand) nand->cmdfunc = dfc_cmdfunc; nand->autooob = &delta_oob; nand->badblock_pattern = &delta_bbt_descr; + return 0; } #else diff --git a/board/idmr/Makefile b/board/idmr/Makefile new file mode 100644 index 0000000..cf07cf4 --- /dev/null +++ b/board/idmr/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o flash.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/idmr/config.mk b/board/idmr/config.mk new file mode 100644 index 0000000..f7c2258 --- /dev/null +++ b/board/idmr/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xff800000 diff --git a/board/idmr/flash.c b/board/idmr/flash.c new file mode 100644 index 0000000..ba9b009 --- /dev/null +++ b/board/idmr/flash.c @@ -0,0 +1,356 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#define PHYS_FLASH_1 CFG_FLASH_BASE +#define FLASH_BANK_SIZE 0x800000 +#define EN29LV640 0x227e227e + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (AMD_MANUFACT & FLASH_VENDMASK): + printf ("AMD: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (EN29LV640 & FLASH_TYPEMASK): + printf ("EN29LV640 (16Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + + Done: + return; +} + + +unsigned long flash_init (void) +{ + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_info[i].flash_id = + (AMD_MANUFACT & FLASH_VENDMASK) | + (EN29LV640 & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured to many flash banks!\n"); + + for (j = 0; j < flash_info[i].sector_count; j++) { + flash_info[i].start[j] = flashbase + 0x10000 * j; + } + size += flash_info[i].size; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + 0x30000, &flash_info[0]); + + return size; +} + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (AMD_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts (); + + printf ("\n"); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = + (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + if (!chip1 + && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + + outahere: + /* allow flash to settle - wait 10 ms */ + printf("Waiting 10 ms..."); + udelay (10000); + +/* for (i = 0; i < 10 * 1000 * 1000; ++i) + asm(" nop"); +*/ + + printf("done\n"); + if (iflag) + enable_interrupts (); + + + return rc; +} + +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + set_timer (0); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + return rc; +} + + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + } + +#if 0 + if (cnt & 1) { + printf ("odd transfer sizes not supported\n"); + return ERR_ALIGN; + } +#endif + + wp = addr; + + if (addr & 1) { + data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) + src); + if ((rc = write_word (info, wp - 1, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src) << 8) | + *((volatile u8 *) (wp + 1)); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + } + + return ERR_OK; +} diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c new file mode 100644 index 0000000..58cdba1 --- /dev/null +++ b/board/idmr/idmr.c @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/m5271.h> +#include <asm/immap_5271.h> + +int checkboard (void) { + puts ("Board: iDMR\n"); + return 0; +}; + +long int initdram (int board_type) { + int i; + + /* + * After reset, CS0 is configured to cover entire address space. We + * need to configure it to its proper values, so that writes to + * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do + * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). + */ + + /* Flash chipselect, CS0 */ + /* ;CSAR0: Flash at 0xFF800000 */ + mbar_writeShort(0x0080, 0xFF80); + + /* CSCR0: Flash 6 waits, 16bit */ + mbar_writeShort(0x008A, 0x1980); + + /* CSMR0: Flash 8MB, R/W, valid */ + mbar_writeLong(0x0084, 0x007F0001); + + + /* + * SDRAM configuration proper + */ + + /* + * Address/Data Pin Assignment Reg.: enable address lines 23-21; do + * not enable data pins D[15:0], as we have 16 bit port to SDRAM + */ + mbar_writeByte(MCF_GPIO_PAR_AD, + MCF_GPIO_AD_ADDR23 | + MCF_GPIO_AD_ADDR22 | + MCF_GPIO_AD_ADDR21); + + /* No need to configure BS pins - reset values are OK */ + + /* Chip Select Pin Assignment Reg.: set CS[1-7] to GPIO */ + mbar_writeByte(MCF_GPIO_PAR_CS, 0x00); + + /* SDRAM Control Pin Assignment Reg. */ + mbar_writeByte(MCF_GPIO_PAR_SDRAM, + MCF_GPIO_SDRAM_CSSDCS_00 | /* no matter: PAR_CS=0 */ + MCF_GPIO_SDRAM_SDWE | + MCF_GPIO_SDRAM_SCAS | + MCF_GPIO_SDRAM_SRAS | + MCF_GPIO_SDRAM_SCKE | + MCF_GPIO_SDRAM_SDCS_01); + + /* + * Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5 + * iterations will do, but we do 10 just to be safe. + */ + for (i = 0; i < 10; ++i) + asm(" nop"); + + + /* 1. Initialize DRAM Control Register: DCR */ + mbar_writeShort(MCF_SDRAMC_DCR, + MCF_SDRAMC_DCR_RTIM(0x10) | /* 65ns */ + MCF_SDRAMC_DCR_RC(0x60)); /* 1562 cycles */ + + + /* + * 2. Initialize DACR0 + * + * CL: 11 (CL=3: 0x03, 0x02; CL=2: 0x1) + * CBM: cmd at A20, bank select bits 21 and up + * PS: 16 bit + */ + mbar_writeLong(MCF_SDRAMC_DACR0, + MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) | + MCF_SDRAMC_DACRn_BA(0x00) | + MCF_SDRAMC_DACRn_CASL(0x03) | + MCF_SDRAMC_DACRn_CBM(0x03) | + MCF_SDRAMC_DACRn_PS(0x03)); + + /* Initialize DMR0 */ + mbar_writeLong(MCF_SDRAMC_DMR0, + MCF_SDRAMC_DMRn_BAM_16M | + MCF_SDRAMC_DMRn_V); + + + /* 3. Set IP bit in DACR to initiate PALL command */ + mbar_writeLong(MCF_SDRAMC_DACR0, + mbar_readLong(MCF_SDRAMC_DACR0) | + MCF_SDRAMC_DACRn_IP); + + /* Write to this block to initiate precharge */ + *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5; + + /* + * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We + * wait a wee longer, just to be safe. + */ + for (i = 0; i < 5; ++i) + asm(" nop"); + + + /* 4. Set RE bit in DACR */ + mbar_writeLong(MCF_SDRAMC_DACR0, + mbar_readLong(MCF_SDRAMC_DACR0) | + MCF_SDRAMC_DACRn_RE); + + /* + * Wait for at least 8 auto refresh cycles to occur, i.e. at least + * 781 bus cycles. + */ + for (i = 0; i < 1000; ++i) + asm(" nop"); + + /* Finish the configuration by issuing the MRS */ + mbar_writeLong(MCF_SDRAMC_DACR0, + mbar_readLong(MCF_SDRAMC_DACR0) | + MCF_SDRAMC_DACRn_MRS); + + /* + * Write to the SDRAM Mode Register A0-A11 = 0x400 + * + * Write Burst Mode = Programmed Burst Length + * Op Mode = Standard Op + * CAS Latency = 3 + * Burst Type = Sequential + * Burst Length = 1 + */ + *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; + + return CFG_SDRAM_SIZE * 1024 * 1024; +}; + + +int testdram (void) { + + /* TODO: XXX XXX XXX */ + printf ("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds new file mode 100644 index 0000000..69f3179 --- /dev/null +++ b/board/idmr/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +GROUP(libgcc.a) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf52x2/start.o (.text) + lib_m68k/traps.o (.text) + cpu/mcf52x2/interrupts.o (.text) + common/dlmalloc.o (.text) + lib_generic/zlib.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.ppcenv) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 786543e..f1bb721 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -79,8 +79,7 @@ #define AU_FIRMWARE "u-boot.img" #define AU_KERNEL "kernel.img" -struct flash_layout -{ +struct flash_layout { long start; long end; }; @@ -122,10 +121,10 @@ struct flash_layout aufl_layout[AU_MAXFILES] = { \ #define I2C_PSOC_KEYPAD_ADDR 0x53 /* keypad mask */ -#define KEYPAD_ROW 3 -#define KEYPAD_COL 3 -#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))&0xFF) -#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*4-4)))>>8) +#define KEYPAD_ROW 2 +#define KEYPAD_COL 2 +#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF) +#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8) /* externals */ extern int fat_register_device(block_dev_desc_t *, int); @@ -139,33 +138,28 @@ extern int flash_write (char *, ulong, ulong); extern block_dev_desc_t *get_dev (char*, int); extern int u_boot_hush_start(void); -int -au_check_cksum_valid(int idx, long nbytes) +int au_check_cksum_valid(int idx, long nbytes) { image_header_t *hdr; unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; - if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) - { + if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) { printf ("Image %s bad total SIZE\n", aufile[idx]); return -1; } /* check the data CRC */ checksum = ntohl(hdr->ih_dcrc); - if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) - != checksum) - { + if (crc32 (0, (uchar *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) != checksum) { printf ("Image %s bad data checksum\n", aufile[idx]); return -1; } return 0; } -int -au_check_header_valid(int idx, long nbytes) +int au_check_header_valid(int idx, long nbytes) { image_header_t *hdr; unsigned long checksum; @@ -180,13 +174,11 @@ au_check_header_valid(int idx, long nbytes) printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); #endif - if (nbytes < sizeof(*hdr)) - { + if (nbytes < sizeof(*hdr)) { printf ("Image %s bad header SIZE\n", aufile[idx]); return -1; } - if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) - { + if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) { printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]); return -1; } @@ -222,9 +214,7 @@ au_check_header_valid(int idx, long nbytes) return 0; } - -int -au_do_update(int idx, long sz) +int au_do_update(int idx, long sz) { image_header_t *hdr; char *addr; @@ -303,14 +293,12 @@ au_do_update(int idx, long sz) return 0; } - /* * this is called from board_init() after the hardware has been set up * and is usable. That seems like a good time to do this. * Right now the return value is ignored. */ -int -do_auto_update(void) +int do_auto_update(void) { block_dev_desc_t *stor_dev; long sz; diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 67969a6..554c51d 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -228,10 +228,6 @@ int misc_init_r (void) { ulong flash_sup_end, snum; -#ifdef CONFIG_AUTO_UPDATE - /* this has priority over all else */ - do_auto_update(); -#endif /* * Adjust flash start and offset to detected values */ @@ -294,6 +290,9 @@ int misc_init_r (void) flash_info[0].sector_count = snum; } +#ifdef CONFIG_AUTO_UPDATE + do_auto_update(); +#endif return (0); } diff --git a/board/nc650/nand.c b/board/nc650/nand.c index de54386..6bb7c31 100644 --- a/board/nc650/nand.c +++ b/board/nc650/nand.c @@ -106,12 +106,13 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { nand->hwcontrol = nc650_hwcontrol; nand->eccmode = NAND_ECC_SOFT; nand->chip_delay = 12; /* nand->options = NAND_SAMSUNG_LP_OPTIONS;*/ + return 0; } #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/netstar/nand.c b/board/netstar/nand.c index f470c1a..7852365 100644 --- a/board/netstar/nand.c +++ b/board/netstar/nand.c @@ -55,12 +55,13 @@ static int netstar_nand_ready(struct mtd_info *mtd) } ***/ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { nand->options = NAND_SAMSUNG_LP_OPTIONS; nand->eccmode = NAND_ECC_SOFT; nand->hwcontrol = netstar_nand_hwcontrol; /* nand->dev_ready = netstar_nand_ready; */ nand->chip_delay = 18; + return 0; } #endif diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 2389561..5abc87d 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -77,8 +77,12 @@ int board_early_init_f (void) mtdcr (uicb0tr, 0x00000000); /* */ mtdcr (uicb0vr, 0x00000001); /* */ + /* Setup shutdown/SSD empty interrupt as inputs */ + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); + /* Setup GPIO/IRQ multiplexing */ - mtsdr(sdr_pfc0, 0x01a03e00); + mtsdr(sdr_pfc0, 0x01a33e00); return 0; } @@ -105,26 +109,11 @@ int last_stage_init(void) static int board_rev(void) { - int rev; - u32 pfc0; - - /* Setup GPIO14 & 15 as GPIO */ - mfsdr(sdr_pfc0, pfc0); - pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1; - mtsdr(sdr_pfc0, pfc0); - /* Setup as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0)); - - rev = (in32(GPIO0_IR) >> 16) & 0x3; - - /* Setup GPIO14 & 15 as non GPIO again */ - mfsdr(sdr_pfc0, pfc0); - pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1); - mtsdr(sdr_pfc0, pfc0); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); - return rev; + return (in32(GPIO0_IR) >> 16) & 0x3; } int checkboard (void) diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index e63c921..d66b088 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -154,7 +154,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd) return 1; } -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; @@ -169,5 +169,7 @@ void board_nand_init(struct nand_chip *nand) nand->read_buf = alpr_nand_read_buf; nand->verify_buf = alpr_nand_verify_buf; nand->dev_ready = alpr_nand_dev_ready; + + return 0; } #endif diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c index 1931d64..92f9c01 100644 --- a/board/prodrive/pdnb3/nand.c +++ b/board/prodrive/pdnb3/nand.c @@ -148,7 +148,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd) return 1; } -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE; @@ -167,5 +167,6 @@ void board_nand_init(struct nand_chip *nand) nand->read_buf = pdnb3_nand_read_buf; nand->verify_buf = pdnb3_nand_verify_buf; nand->dev_ready = pdnb3_nand_dev_ready; + return 0; } #endif diff --git a/board/spc1920/Makefile b/board/spc1920/Makefile index 424ab1c..0c48c3a 100644 --- a/board/spc1920/Makefile +++ b/board/spc1920/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o +COBJS = $(BOARD).o hpi.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c new file mode 100644 index 0000000..3c36f79 --- /dev/null +++ b/board/spc1920/hpi.c @@ -0,0 +1,603 @@ +/* + * (C) Copyright 2006 + * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Host Port Interface (HPI) + */ + +/* debug levels: + * 0 : errors + * 1 : usefull info + * 2 : lots of info + * 3 : noisy + */ + +#define DEBUG 0 + +#include <config.h> +#include <common.h> +#include <mpc8xx.h> + +#include "pld.h" +#include "hpi.h" + +#define _NOT_USED_ 0xFFFFFFFF + +/* original table: + * - inserted loops to achieve long CS low and high Periods (~217ns) + * - move cs high 2/4 to the right + */ +const uint dsp_table_slow[] = +{ + /* single read (offset 0x00 in upm ram) */ + 0x8fffdc04, 0x0fffdc84, 0x0fffdc84, 0x0fffdc00, + 0x3fffdc04, 0xffffdc84, 0xffffdc84, 0xffffdc05, + + /* burst read (offset 0x08 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* single write (offset 0x18 in upm ram) */ + 0x8fffd004, 0x0fffd084, 0x0fffd084, 0x3fffd000, + 0xffffd084, 0xffffd084, 0xffffd005, _NOT_USED_, + + /* burst write (offset 0x20 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* refresh (offset 0x30 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* exception (offset 0x3C in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* dsp hpi upm ram table + * works fine for noninc access, failes on incremental. + * - removed first word + */ +const uint dsp_table_fast[] = +{ + /* single read (offset 0x00 in upm ram) */ + 0x8fffdc04, 0x0fffdc04, 0x0fffdc00, 0x3fffdc04, + 0xffffdc05, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* burst read (offset 0x08 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* single write (offset 0x18 in upm ram) */ + 0x8fffd004, 0x0fffd004, 0x3fffd000, 0xffffd005, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* burst write (offset 0x20 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* refresh (offset 0x30 in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + /* exception (offset 0x3C in upm ram) */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + + +#ifdef CONFIG_SPC1920_HPI_TEST +#undef HPI_TEST_OSZI + +#define HPI_TEST_CHUNKSIZE 0x1000 +#define HPI_TEST_PATTERN 0x00000000 +#define HPI_TEST_START 0x0 +#define HPI_TEST_END 0x30000 + +#define TINY_AUTOINC_DATA_SIZE 16 /* 32bit words */ +#define TINY_AUTOINC_BASE_ADDR 0x0 + +static int hpi_activate(void); +static void hpi_inactivate(void); +static void dsp_reset(void); + +static int hpi_write_inc(u32 addr, u32 *data, u32 count); +static int hpi_read_inc(u32 addr, u32 *buf, u32 count); +static int hpi_write_noinc(u32 addr, u32 data); +static u32 hpi_read_noinc(u32 addr); + +int hpi_test(void); +static int hpi_write_addr_test(u32 addr); +static int hpi_read_write_test(u32 addr, u32 data); +static int hpi_tiny_autoinc_test(void); +#endif /* CONFIG_SPC1920_HPI_TEST */ + + +/* init the host port interface on UPMA */ +int hpi_init(void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + + upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint)); + udelay(100); + + memctl->memc_mamr = CFG_MAMR; + memctl->memc_or3 = CFG_OR3; + memctl->memc_br3 = CFG_BR3; + + /* reset dsp */ + dsp_reset(); + + /* activate hpi switch*/ + pld->dsp_hpi_on = 0x1; + + udelay(100); + + return 0; +} + +#ifdef CONFIG_SPC1920_HPI_TEST +/* activate the Host Port interface */ +static int hpi_activate(void) +{ + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + + /* turn on hpi */ + pld->dsp_hpi_on = 0x1; + + udelay(5); + + /* turn on the power EN_DSP_POWER high*/ + /* currently always on TBD */ + + /* setup hpi control register */ + HPI_HPIC_1 = (u16) 0x0008; + HPI_HPIC_2 = (u16) 0x0008; + + udelay(100); + + return 0; +} + +/* turn off the host port interface */ +static void hpi_inactivate(void) +{ + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + + /* deactivate hpi */ + pld->dsp_hpi_on = 0x0; + + /* reset the dsp */ + /* pld->dsp_reset = 0x0; */ + + /* turn off the power EN_DSP_POWER# high*/ + /* currently always on TBD */ + +} + +/* reset the DSP */ +static void dsp_reset(void) +{ + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + pld->dsp_reset = 0x1; + pld->dsp_hpi_on = 0x0; + + udelay(300000); + + pld->dsp_reset = 0x0; + pld->dsp_hpi_on = 0x1; +} + + +/* write using autoinc (count is number of 32bit words) */ +static int hpi_write_inc(u32 addr, u32 *data, u32 count) +{ + int i; + u16 addr1, addr2; + + addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ + addr2 = (u16) (addr & 0xffff); + + /* write address */ + HPI_HPIA_1 = addr1; + HPI_HPIA_2 = addr2; + + debugX(4, "writing from data=0x%x to 0x%x\n", data, (data+count)); + + for(i=0; i<count; i++) { + HPI_HPID_INC_1 = (u16) ((data[i] >> 16) & 0xffff); + HPI_HPID_INC_2 = (u16) (data[i] & 0xffff); + debugX(4, "hpi_write_inc: data1=0x%x, data2=0x%x\n", + (u16) ((data[i] >> 16) & 0xffff), + (u16) (data[i] & 0xffff)); + } +#if 0 + while(data_ptr < (u16*) (data + count)) { + HPI_HPID_INC_1 = *(data_ptr++); + HPI_HPID_INC_2 = *(data_ptr++); + } +#endif + + /* return number of bytes written */ + return count; +} + +/* + * read using autoinc (count is number of 32bit words) + */ +static int hpi_read_inc(u32 addr, u32 *buf, u32 count) +{ + int i; + u16 addr1, addr2, data1, data2; + + addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ + addr2 = (u16) (addr & 0xffff); + + /* write address */ + HPI_HPIA_1 = addr1; + HPI_HPIA_2 = addr2; + + for(i=0; i<count; i++) { + data1 = HPI_HPID_INC_1; + data2 = HPI_HPID_INC_2; + debugX(4, "hpi_read_inc: data1=0x%x, data2=0x%x\n", data1, data2); + buf[i] = (((u32) data1) << 16) | (data2 & 0xffff); + } + +#if 0 + while(buf_ptr < (u16*) (buf + count)) { + *(buf_ptr++) = HPI_HPID_INC_1; + *(buf_ptr++) = HPI_HPID_INC_2; + } +#endif + + /* return number of bytes read */ + return count; +} + + +/* write to non- auto inc regs */ +static int hpi_write_noinc(u32 addr, u32 data) +{ + + u16 addr1, addr2, data1, data2; + + addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ + addr2 = (u16) (addr & 0xffff); + + /* printf("hpi_write_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ + + HPI_HPIA_1 = addr1; + HPI_HPIA_2 = addr2; + + data1 = (u16) ((data >> 16) & 0xffff); + data2 = (u16) (data & 0xffff); + + /* printf("hpi_write_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ + + HPI_HPID_NOINC_1 = data1; + HPI_HPID_NOINC_2 = data2; + + return 0; +} + +/* read from non- auto inc regs */ +static u32 hpi_read_noinc(u32 addr) +{ + u16 addr1, addr2, data1, data2; + u32 ret; + + addr1 = (u16) ((addr >> 16) & 0xffff); /* First HW is most significant */ + addr2 = (u16) (addr & 0xffff); + + HPI_HPIA_1 = addr1; + HPI_HPIA_2 = addr2; + + /* printf("hpi_read_noinc: addr1=0x%x, addr2=0x%x\n", addr1, addr2); */ + + data1 = HPI_HPID_NOINC_1; + data2 = HPI_HPID_NOINC_2; + + /* printf("hpi_read_noinc: data1=0x%x, data2=0x%x\n", data1, data2); */ + + ret = (((u32) data1) << 16) | (data2 & 0xffff); + return ret; + +} + +/* + * Host Port Interface Tests + */ + +#ifndef HPI_TEST_OSZI +/* main test function */ +int hpi_test(void) +{ + int err = 0; + u32 i, ii, pattern, tmp; + + pattern = HPI_TEST_PATTERN; + + u32 test_data[HPI_TEST_CHUNKSIZE]; + u32 read_data[HPI_TEST_CHUNKSIZE]; + + debugX(2, "hpi_test: activating hpi..."); + hpi_activate(); + debugX(2, "OK.\n"); + +#if 0 + /* Dump the first 1024 bytes + * + */ + for(i=0; i<1024; i+=4) { + if(i%16==0) + printf("\n0x%08x: ", i); + printf("0x%08x ", hpi_read_noinc(i)); + } +#endif + + /* HPIA read-write test + * + */ + debugX(1, "hpi_test: starting HPIA read-write tests...\n"); + err |= hpi_write_addr_test(0xdeadc0de); + err |= hpi_write_addr_test(0xbeefd00d); + err |= hpi_write_addr_test(0xabcd1234); + err |= hpi_write_addr_test(0xaaaaaaaa); + if(err) { + debugX(1, "hpi_test: HPIA read-write tests: *** FAILED ***\n"); + return -1; + } + debugX(1, "hpi_test: HPIA read-write tests: OK\n"); + + + /* read write test using nonincremental data regs + * + */ + debugX(1, "hpi_test: starting nonincremental tests...\n"); + for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { + err |= hpi_read_write_test(i, pattern); + + /* stolen from cmd_mem.c */ + if(pattern & 0x80000000) { + pattern = -pattern; /* complement & increment */ + } else { + pattern = ~pattern; + } + err |= hpi_read_write_test(i, pattern); + + if(err) { + debugX(1, "hpi_test: nonincremental tests *** FAILED ***\n"); + return -1; + } + } + debugX(1, "hpi_test: nonincremental test OK\n"); + + /* read write a chunk of data using nonincremental data regs + * + */ + debugX(1, "hpi_test: starting nonincremental chunk tests...\n"); + pattern = HPI_TEST_PATTERN; + for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { + hpi_write_noinc(i, pattern); + + /* stolen from cmd_mem.c */ + if(pattern & 0x80000000) { + pattern = -pattern; /* complement & increment */ + } else { + pattern = ~pattern; + } + } + pattern = HPI_TEST_PATTERN; + for(i=HPI_TEST_START; i<HPI_TEST_END; i+=4) { + tmp = hpi_read_noinc(i); + + if(tmp != pattern) { + debugX(1, "hpi_test: noninc chunk test *** FAILED *** @ 0x%x, written=0x%x, read=0x%x\n", i, pattern, tmp); + err = -1; + } + /* stolen from cmd_mem.c */ + if(pattern & 0x80000000) { + pattern = -pattern; /* complement & increment */ + } else { + pattern = ~pattern; + } + } + if(err) + return -1; + debugX(1, "hpi_test: nonincremental chunk test OK\n"); + + +#ifdef DO_TINY_TEST + /* small verbose test using autoinc and nonautoinc to compare + * + */ + debugX(1, "hpi_test: tiny_autoinc_test...\n"); + hpi_tiny_autoinc_test(); + debugX(1, "hpi_test: tiny_autoinc_test done\n"); +#endif /* DO_TINY_TEST */ + + + /* $%& write a chunk of data using the autoincremental regs + * + */ + debugX(1, "hpi_test: starting autoinc test %d chunks with 0x%x bytes...\n", + ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE), + HPI_TEST_CHUNKSIZE); + + for(i=HPI_TEST_START; + i < ((HPI_TEST_END - HPI_TEST_START) / HPI_TEST_CHUNKSIZE); + i++) { + /* generate the pattern data */ + debugX(3, "generating pattern data: "); + for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { + debugX(3, "0x%x ", pattern); + + test_data[ii] = pattern; + read_data[ii] = 0x0; /* zero to be sure */ + + /* stolen from cmd_mem.c */ + if(pattern & 0x80000000) { + pattern = -pattern; /* complement & increment */ + } else { + pattern = ~pattern; + } + } + debugX(3, "done\n"); + + debugX(2, "Writing autoinc data @ 0x%x\n", i); + hpi_write_inc(i, test_data, HPI_TEST_CHUNKSIZE); + + debugX(2, "Reading autoinc data @ 0x%x\n", i); + hpi_read_inc(i, read_data, HPI_TEST_CHUNKSIZE); + + /* compare */ + for(ii = 0; ii < HPI_TEST_CHUNKSIZE; ii++) { + debugX(3, "hpi_test_autoinc: @ 0x%x, written=0x%x, read=0x%x", i+ii, test_data[ii], read_data[ii]); + if(read_data[ii] != test_data[ii]) { + debugX(0, "hpi_test: autoinc test @ 0x%x, written=0x%x, read=0x%x *** FAILED ***\n", i+ii, test_data[ii], read_data[ii]); + return -1; + } + } + } + debugX(1, "hpi_test: autoinc test OK\n"); + + return 0; +} +#else /* HPI_TEST_OSZI */ +int hpi_test(void) +{ + int i; + u32 read_data[TINY_AUTOINC_DATA_SIZE]; + + unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { + 0x11112222, 0x33334444, 0x55556666, 0x77778888, + 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, + 0x00010002, 0x00030004, 0x00050006, 0x00070008, + 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 + }; + + debugX(0, "hpi_test: activating hpi..."); + hpi_activate(); + debugX(0, "OK.\n"); + + while(1) { + led9(1); + debugX(0, " writing to autoinc...\n"); + hpi_write_inc(TINY_AUTOINC_BASE_ADDR, + dummy_data, TINY_AUTOINC_DATA_SIZE); + + debugX(0, " reading from autoinc...\n"); + hpi_read_inc(TINY_AUTOINC_BASE_ADDR, + read_data, TINY_AUTOINC_DATA_SIZE); + + for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { + debugX(0, " written=0x%x, read(inc)=0x%x\n", + dummy_data[i], read_data[i]); + } + led9(0); + udelay(2000000); + } + return 0; +} +#endif + +/* test if Host Port Address Register can be written correctly */ +static int hpi_write_addr_test(u32 addr) +{ + u32 read_back; + /* write address */ + HPI_HPIA_1 = ((u16) (addr >> 16)); /* First HW is most significant */ + HPI_HPIA_2 = ((u16) addr); + + read_back = (((u32) HPI_HPIA_1)<<16) | ((u32) HPI_HPIA_2); + + if(read_back == addr) { + debugX(2, " hpi_write_addr_test OK: written=0x%x, read=0x%x\n", + addr, read_back); + return 0; + } else { + debugX(0, " hpi_write_addr_test *** FAILED ***: written=0x%x, read=0x%x\n", + addr, read_back); + return -1; + } + + return 0; +} + +/* test if a simple read/write sequence succeeds */ +static int hpi_read_write_test(u32 addr, u32 data) +{ + u32 read_back; + + hpi_write_noinc(addr, data); + read_back = hpi_read_noinc(addr); + + if(read_back == data) { + debugX(2, " hpi_read_write_test: OK, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); + return 0; + } else { + debugX(0, " hpi_read_write_test: *** FAILED ***, addr=0x%x written=0x%x, read=0x%x\n", addr, data, read_back); + return -1; + } + + return 0; +} + +static int hpi_tiny_autoinc_test(void) +{ + int i; + u32 read_data[TINY_AUTOINC_DATA_SIZE]; + u32 read_data_noinc[TINY_AUTOINC_DATA_SIZE]; + + unsigned int dummy_data[TINY_AUTOINC_DATA_SIZE] = { + 0x11112222, 0x33334444, 0x55556666, 0x77778888, + 0x9999aaaa, 0xbbbbcccc, 0xddddeeee, 0xffff1111, + 0x00010002, 0x00030004, 0x00050006, 0x00070008, + 0x0009000a, 0x000b000c, 0x000d000e, 0x000f0001 + }; + + printf(" writing to autoinc...\n"); + hpi_write_inc(TINY_AUTOINC_BASE_ADDR, dummy_data, TINY_AUTOINC_DATA_SIZE); + + printf(" reading from autoinc...\n"); + hpi_read_inc(TINY_AUTOINC_BASE_ADDR, read_data, TINY_AUTOINC_DATA_SIZE); + + printf(" reading from noinc for comparison...\n"); + for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) + read_data_noinc[i] = hpi_read_noinc(TINY_AUTOINC_BASE_ADDR+i*4); + + for(i=0; i < (TINY_AUTOINC_DATA_SIZE); i++) { + printf(" written=0x%x, read(inc)=0x%x, read(noinc)=0x%x\n", + dummy_data[i], read_data[i], read_data_noinc[i]); + } + return 0; +} + +#endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/board/spc1920/hpi.h b/board/spc1920/hpi.h new file mode 100644 index 0000000..4503873 --- /dev/null +++ b/board/spc1920/hpi.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2006 + * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +int hpi_init(void); + +#ifdef CONFIG_SPC1920_HPI_TEST +int hpi_test(void); +#endif diff --git a/board/spc1920/pld.h b/board/spc1920/pld.h index 3254f82..5beb71b 100644 --- a/board/spc1920/pld.h +++ b/board/spc1920/pld.h @@ -5,8 +5,8 @@ typedef struct spc1920_pld { uchar com1_en; uchar dsp_reset; uchar dsp_hpi_on; + uchar superv_mode; uchar codec_dsp_power_en; - uchar clk2_en; uchar clk3_select; uchar clk4_select; } spc1920_pld_t; diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c index 028f4c6..1f5dcb5 100644 --- a/board/spc1920/spc1920.c +++ b/board/spc1920/spc1920.c @@ -27,9 +27,9 @@ #include <common.h> #include <mpc8xx.h> #include "pld.h" +#include "hpi.h" #define _NOT_USED_ 0xFFFFFFFF -/* #define debug(fmt,args...) printf (fmt ,##args) */ static long int dram_size (long int, long int *, long int); @@ -172,10 +172,12 @@ long int initdram (int board_type) memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; udelay (1000); + /* initalize the DSP Host Port Interface */ + hpi_init(); - /* PLD Setup */ - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; + /* FRAM Setup */ + memctl->memc_or4 = CFG_OR4; + memctl->memc_br4 = CFG_BR4; udelay(1000); return (size_b0); @@ -207,13 +209,31 @@ int board_early_init_f(void) { volatile immap_t *immap = (immap_t *) CFG_IMMR; + /* Set Go/NoGo led (PA15) to color red */ + immap->im_ioport.iop_papar &= ~0x1; + immap->im_ioport.iop_paodr &= ~0x1; + immap->im_ioport.iop_padir |= 0x1; + immap->im_ioport.iop_padat |= 0x1; +#if 0 /* Turn on LED PD9 */ immap->im_ioport.iop_pdpar &= ~(0x0040); immap->im_ioport.iop_pddir |= 0x0040; immap->im_ioport.iop_pddat |= 0x0040; +#endif + + /* + * Enable console on SMC1. This requires turning on + * the com2_en signal and SMC1_DISABLE + */ + + /* SMC1_DISABLE: PB17 */ + immap->im_cpm.cp_pbodr &= ~0x4000; + immap->im_cpm.cp_pbpar &= ~0x4000; + immap->im_cpm.cp_pbdir |= 0x4000; + immap->im_cpm.cp_pbdat &= ~0x4000; - /* Enable PD10 (COM2_EN) */ + /* COM2_EN: PD10 */ immap->im_ioport.iop_pdpar &= ~0x0020; immap->im_ioport.iop_pddir &= ~0x4000; immap->im_ioport.iop_pddir |= 0x0020; @@ -228,6 +248,14 @@ int board_early_init_f(void) return 0; } +int last_stage_init(void) +{ +#ifdef CONFIG_SPC1920_HPI_TEST + printf("CMB1920 Host Port Interface Test: %s\n", + hpi_test() ? "Failed!" : "OK"); +#endif + return 0; +} int checkboard (void) { diff --git a/board/tqm5200/cam5200_flash.c b/board/tqm5200/cam5200_flash.c index 8c3f62e..b3f095d 100644 --- a/board/tqm5200/cam5200_flash.c +++ b/board/tqm5200/cam5200_flash.c @@ -25,7 +25,7 @@ #include <mpc5xxx.h> #include <asm/processor.h> -#ifdef CONFIG_CAM5200 +#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) #if 0 #define DEBUGF(x...) printf(x) @@ -783,4 +783,4 @@ unsigned long flash_init(void) return total_b; } -#endif /* ifdef CONFIG_CAM5200 */ +#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */ diff --git a/board/tqm8272/Makefile b/board/tqm8272/Makefile new file mode 100644 index 0000000..3dbf913 --- /dev/null +++ b/board/tqm8272/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/tqm8272/config.mk b/board/tqm8272/config.mk new file mode 100644 index 0000000..af7a81e --- /dev/null +++ b/board/tqm8272/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# TQM8272 boards +# + +# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# for the "final" configuration, with U-Boot in flash, or the address +# in RAM where U-Boot is loaded at for debugging. +# +TEXT_BASE = 0x40000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR) diff --git a/board/tqm8272/tqm8272.c b/board/tqm8272/tqm8272.c new file mode 100644 index 0000000..8257c77 --- /dev/null +++ b/board/tqm8272/tqm8272.c @@ -0,0 +1,1234 @@ +/* + * (C) Copyright 2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +#include <command.h> +#ifdef CONFIG_PCI +#include <pci.h> +#include <asm/m8260_pci.h> +#endif +#if CONFIG_OF_FLAT_TREE +#include <ft_build.h> +#include <image.h> +#endif + +#if 0 +#define deb_printf(fmt,arg...) \ + printf ("TQM8272 %s %s: " fmt,__FILE__, __FUNCTION__, ##arg) +#else +#define deb_printf(fmt,arg...) \ + do { } while (0) +#endif + +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) +unsigned long board_get_cpu_clk_f (void); +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */ + /* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */ + /* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */ + /* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */ + /* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */ + /* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */ + /* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */ + /* PC17 */ { 1, 0, 0, 1, 0, 0 }, /* PC17 MDC */ + /* PC16 */ { 1, 0, 0, 0, 0, 0 }, /* PC16 MDIO*/ + /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */ + /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* PC10 */ + /* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* PC9 */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* PC5 SMC1 TXD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* PC4 SMC1 RXD */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ +#if defined(CONFIG_SOFT_I2C) + /* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */ +#else +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else /* normal I/O port pins */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#endif +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + +#define _NOT_USED_ 0xFFFFFFFF + +/* UPM pattern for bus clock = 66.7 MHz */ +static const uint upmTable67[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const uint upmTable100[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const uint upmTable133[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +static int chipsel = 0; + +/* UPM pattern for slow init */ +static const uint upmTableSlow[] = +{ + /* Offset UPM Read Single RAM array entry */ + /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcf00, 0x00ffdc00, + /* 0x04 */ 0x00ffce80, 0x00ffcc00, 0x00ffee00, 0x3fffcc07, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry */ + /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffef00, 0x00fffc80, + /* 0x1C */ 0x00fffe00, 0x00ffec00, 0x0fffef00, 0x3fffec05, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for fast init */ +static const uint upmTableFast[] = +{ + /* Offset UPM Read Single RAM array entry */ + /* 0x00 */ 0xffffee00, 0x00ffcc80, 0x00ffcd80, 0x00ffdc00, + /* 0x04 */ 0x00ffdc00, 0x00ffcf00, 0x00ffec00, 0x3fffcc07, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry */ + /* 0x18 */ 0xffffee00, 0x00ffec80, 0x00ffee80, 0x00fffc00, + /* 0x1C */ 0x00fffc00, 0x00ffec00, 0x0fffef00, 0x3fffec05, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + + +/* ------------------------------------------------------------------------- */ + +/* Check Board Identity: + */ +int checkboard (void) +{ + char *p = (char *) HWIB_INFO_START_ADDR; + + puts ("Board: "); + if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + puts (p); + } else { + puts ("No HWIB assuming TQM8272"); + } + putc ('\n'); + + return 0; +} + +/* ------------------------------------------------------------------------- */ +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) +static int get_cas_latency (void) +{ + /* get it from the option -ts in CIB */ + /* default is 3 */ + int ret = 3; + int pos = 0; + char *p = (char *) CIB_INFO_START_ADDR; + + while ((*p != '\0') && (pos < CIB_INFO_LEN)) { + if (*p < ' ' || *p > '~') { /* ASCII strings! */ + return ret; + } + if (*p == '-') { + if ((p[1] == 't') && (p[2] == 's')) { + return (p[4] - '0'); + } + } + p++; + pos++; + } + return ret; +} +#endif + +static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) +{ +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) + int clk = board_get_cpu_clk_f (); + volatile immap_t *immr = (immap_t *)CFG_IMMR; + int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); + int cas; + + sdmr = sdmr & ~(PSDMR_RFRC_MSK | PSDMR_PRETOACT_MSK | PSDMR_WRC_MSK | \ + PSDMR_BUFCMD); + if (busmode) { + switch (clk) { + case 66666666: + sdmr |= (PSDMR_RFRC_66MHZ_60X | \ + PSDMR_PRETOACT_66MHZ_60X | \ + PSDMR_WRC_66MHZ_60X | \ + PSDMR_BUFCMD_66MHZ_60X); + break; + case 100000000: + sdmr |= (PSDMR_RFRC_100MHZ_60X | \ + PSDMR_PRETOACT_100MHZ_60X | \ + PSDMR_WRC_100MHZ_60X | \ + PSDMR_BUFCMD_100MHZ_60X); + break; + + } + } else { + switch (clk) { + case 66666666: + sdmr |= (PSDMR_RFRC_66MHZ_SINGLE | \ + PSDMR_PRETOACT_66MHZ_SINGLE | \ + PSDMR_WRC_66MHZ_SINGLE | \ + PSDMR_BUFCMD_66MHZ_SINGLE); + break; + case 100000000: + sdmr |= (PSDMR_RFRC_100MHZ_SINGLE | \ + PSDMR_PRETOACT_100MHZ_SINGLE | \ + PSDMR_WRC_100MHZ_SINGLE | \ + PSDMR_BUFCMD_100MHZ_SINGLE); + break; + case 133333333: + sdmr |= (PSDMR_RFRC_133MHZ_SINGLE | \ + PSDMR_PRETOACT_133MHZ_SINGLE | \ + PSDMR_WRC_133MHZ_SINGLE | \ + PSDMR_BUFCMD_133MHZ_SINGLE); + break; + } + } + cas = get_cas_latency(); + sdmr &=~ (PSDMR_CL_MSK | PSDMR_LDOTOPRE_MSK); + sdmr |= cas; + sdmr |= ((cas - 1) << 6); + return sdmr; +#else + return sdmr; +#endif +} + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base, int col) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff)) / 2; + + /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + * we are configuring CS1 if base != 0 + */ + sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; + orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1; + + *orx_ptr = orx; + sdmr = set_sdram_timing (sdmr_ptr, sdmr, col); + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + +#ifndef CFG_RAMBOOT + long size8, size9; +#endif + long psize, lsize; + + psize = 16 * 1024 * 1024; + lsize = 0; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE, 8); + size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, + (uchar *) CFG_SDRAM_BASE, 9); + + if (size8 < size9) { + psize = size9; + printf ("(60x:9COL - %ld MB, ", psize >> 20); + } else { + psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, + (uchar *) CFG_SDRAM_BASE, 8); + printf ("(60x:8COL - %ld MB, ", psize >> 20); + } + +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + + +static inline int scanChar (char *p, int len, unsigned long *number) +{ + int akt = 0; + + *number = 0; + while (akt < len) { + if ((*p >= '0') && (*p <= '9')) { + *number *= 10; + *number += *p - '0'; + p += 1; + } else { + if (*p == '-') return akt; + return -1; + } + akt ++; + } + return akt; +} + +typedef struct{ + int Bus; + int flash; + int flash_nr; + int ram; + int ram_cs; + int nand; + int nand_cs; + int eeprom; + int can; + unsigned long cpunr; + unsigned long option; + int SecEng; + int cpucl; + int cpmcl; + int buscl; + int busclk_real_ok; + int busclk_real; + unsigned char OK; + unsigned char ethaddr[20]; +} HWIB_INFO; + +HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, + 0, 0, 0, 0, 0, 0}; + +static int dump_hwib(void) +{ + HWIB_INFO *hw = &hwinf; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + char *s = getenv("serial#"); + + if (hw->OK) { + printf ("HWIB on %x\n", HWIB_INFO_START_ADDR); + printf ("serial : %s\n", s); + printf ("ethaddr: %s\n", hw->ethaddr); + printf ("FLASH : %x nr:%d\n", hw->flash, hw->flash_nr); + printf ("RAM : %x cs:%d\n", hw->ram, hw->ram_cs); + printf ("CPU : %d\n", hw->cpunr); + printf ("CAN : %d\n", hw->can); + if (hw->eeprom) printf ("EEprom : %x\n", hw->eeprom); + else printf ("No EEprom\n"); + if (hw->nand) { + printf ("NAND : %x\n", hw->nand); + printf ("NAND CS: %d\n", hw->nand_cs); + } else { printf ("No NAND\n");} + printf ("Bus %s mode.\n", (hw->Bus ? "60x" : "Single PQII")); + printf (" real : %s\n", (immr->im_siu_conf.sc_bcr & BCR_EBM ? \ + "60x" : "Single PQII")); + printf ("Option : %x\n", hw->option); + printf ("%s Security Engine\n", (hw->SecEng ? "with" : "no")); + printf ("CPM Clk: %d\n", hw->cpmcl); + printf ("CPU Clk: %d\n", hw->cpucl); + printf ("Bus Clk: %d\n", hw->buscl); + if (hw->busclk_real_ok) { + printf (" real Clk: %d\n", hw->busclk_real); + } + printf ("CAS : %d\n", get_cas_latency()); + } else { + printf("HWIB @%x not OK\n", HWIB_INFO_START_ADDR); + } + return 0; +} + +static inline int search_real_busclk (int *clk) +{ + int part = 0, pos = 0; + char *p = (char *) CIB_INFO_START_ADDR; + int ok = 0; + + while ((*p != '\0') && (pos < CIB_INFO_LEN)) { + if (*p < ' ' || *p > '~') { /* ASCII strings! */ + return 0; + } + switch (part) { + default: + if (*p == '-') { + ++part; + } + break; + case 3: + if (*p == '-') { + ++part; + break; + } + if (*p == 'b') { + ok = 1; + p++; + break; + } + if (ok) { + switch (*p) { + case '6': + *clk = 66666666; + return 1; + break; + case '1': + if (p[1] == '3') { + *clk = 133333333; + } else { + *clk = 100000000; + } + return 1; + break; + } + } + break; + } + p++; + } + return 0; +} + +int analyse_hwib (void) +{ + char *p = (char *) HWIB_INFO_START_ADDR; + int anz; + int part = 1, i = 0, pos = 0; + HWIB_INFO *hw = &hwinf; + + deb_printf(" %s pointer: %p\n", __FUNCTION__, p); + /* Head = TQM */ + if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) { + deb_printf("No HWIB\n"); + return -1; + } + p += 3; + if (scanChar (p, 4, &hw->cpunr) < 0) { + deb_printf("No CPU\n"); + return -2; + } + p +=4; + + hw->flash = 0x200000 << (*p - 'A'); + p++; + hw->flash_nr = *p - '0'; + p++; + + hw->ram = 0x2000000 << (*p - 'A'); + p++; + if (*p == '2') { + hw->ram_cs = 2; + p++; + } + + if (*p == 'A') hw->can = 1; + if (*p == 'B') hw->can = 2; + p +=1; + p +=1; /* connector */ + if (*p != '0') { + hw->eeprom = 0x100 << (*p - 'A'); + } + p++; + + if ((*p < '0') || (*p > '9')) { + /* NAND before z-option */ + hw->nand = 0x8000000 << (*p - 'A'); + p++; + hw->nand_cs = *p - '0'; + p += 2; + } + /* z-option */ + anz = scanChar (p, 4, &hw->option); + if (anz < 0) { + deb_printf("No option\n"); + return -3; + } + if (hw->option & 0x8) hw->Bus = 1; + p += anz; + if (*p != '-') { + deb_printf("No -\n"); + return -4; + } + p++; + /* C option */ + if (*p == 'E') { + hw->SecEng = 1; + p++; + } + switch (*p) { + case 'M': hw->cpucl = 266666666; + break; + case 'P': hw->cpucl = 300000000; + break; + case 'T': hw->cpucl = 400000000; + break; + default: + deb_printf("No CPU Clk: %c\n", *p); + return -5; + break; + } + p++; + switch (*p) { + case 'I': hw->cpmcl = 200000000; + break; + case 'M': hw->cpmcl = 300000000; + break; + default: + deb_printf("No CPM Clk\n"); + return -6; + break; + } + p++; + switch (*p) { + case 'B': hw->buscl = 66666666; + break; + case 'E': hw->buscl = 100000000; + break; + case 'F': hw->buscl = 133333333; + break; + default: + deb_printf("No BUS Clk\n"); + return -7; + break; + } + p++; + + hw->OK = 1; + /* search MAC Address */ + while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) { + if (*p < ' ' || *p > '~') { /* ASCII strings! */ + return 0; + } + switch (part) { + default: + if (*p == ' ') { + ++part; + i = 0; + } + break; + case 3: /* Copy MAC address */ + if (*p == ' ') { + ++part; + i = 0; + break; + } + hw->ethaddr[i++] = *p; + if ((i % 3) == 2) + hw->ethaddr[i++] = ':'; + break; + + } + p++; + } + + hw->busclk_real_ok = search_real_busclk (&hw->busclk_real); + return 0; +} + +#if defined(CONFIG_GET_CPU_STR_F) +/* !! This routine runs from Flash */ +char get_cpu_str_f (char *buf) +{ + char *p = (char *) HWIB_INFO_START_ADDR; + int i = 0; + + buf[i++] = 'M'; + buf[i++] = 'P'; + buf[i++] = 'C'; + if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + buf[i++] = *&p[3]; + buf[i++] = *&p[4]; + buf[i++] = *&p[5]; + buf[i++] = *&p[6]; + } else { + buf[i++] = '8'; + buf[i++] = '2'; + buf[i++] = '7'; + buf[i++] = 'x'; + } + buf[i++] = 0; + return 0; +} +#endif + +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) +/* !! This routine runs from Flash */ +unsigned long board_get_cpu_clk_f (void) +{ + char *p = (char *) HWIB_INFO_START_ADDR; + int i = 0; + + if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (search_real_busclk (&i)) + return i; + } + return CONFIG_8260_CLKIN; +} +#endif + +#if CONFIG_BOARD_EARLY_INIT_R + +static int can_test (unsigned long off) +{ + volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off); + + *(base + 0x17) = 'T'; + *(base + 0x18) = 'Q'; + *(base + 0x19) = 'M'; + if ((*(base + 0x17) != 'T') || + (*(base + 0x18) != 'Q') || + (*(base + 0x19) != 'M')) { + return 0; + } + return 1; +} + +static int can_config_one (unsigned long off) +{ + volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off); + volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02); + volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f); + unsigned char temp; + + *cpu_if = 0x45; + temp = *ctrl; + temp |= 0x40; + *ctrl = temp; + *clkout = 0x20; + temp = *ctrl; + temp &= ~0x40; + *ctrl = temp; + return 0; +} + +static int can_config (void) +{ + int ret = 0; + can_config_one (0); + if (hwinf.can == 2) { + can_config_one (0x100); + } + /* make Test if they really there */ + ret += can_test (0); + ret += can_test (0x100); + return ret; +} + +static int init_can (void) +{ + volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + int count = 0; + + if ((hwinf.OK) && (hwinf.can)) { + memctl->memc_or4 = CFG_CAN_OR; + memctl->memc_br4 = CFG_CAN_BR; + /* upm Init */ + upmconfig (UPMC, (uint *) upmTableFast, + sizeof (upmTableFast) / sizeof (uint)); + memctl->memc_mcmr = (MxMR_DSx_3_CYCL | + MxMR_GPL_x4DIS | + MxMR_RLFx_2X | + MxMR_WLFx_2X | + MxMR_OP_NORM); + /* can configure */ + count = can_config (); + printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE); + if (hwinf.can != count) printf("!!! difference to HWIB\n"); + } else { + printf ("CAN: No\n"); + } + return 0; +} + +int board_early_init_r(void) +{ + analyse_hwib (); + init_can (); + return 0; +} +#endif + +int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + dump_hwib (); + return 0; +} + +U_BOOT_CMD( + hwib, 1, 1, do_hwib_dump, + "hwib - dump HWIB'\n", + "\n" +); + +#ifdef CFG_UPDATE_FLASH_SIZE +static int get_flash_timing (void) +{ + /* get it from the option -tf in CIB */ + /* default is 0x00000c84 */ + int ret = 0x00000c84; + int pos = 0; + int nr = 0; + char *p = (char *) CIB_INFO_START_ADDR; + + while ((*p != '\0') && (pos < CIB_INFO_LEN)) { + if (*p < ' ' || *p > '~') { /* ASCII strings! */ + return ret; + } + if (*p == '-') { + if ((p[1] == 't') && (p[2] == 'f')) { + p += 6; + ret = 0; + while (nr < 8) { + if ((*p >= '0') && (*p <= '9')) { + ret *= 0x10; + ret += *p - '0'; + p += 1; + nr ++; + } else if ((*p >= 'A') && (*p <= 'F')) { + ret *= 10; + ret += *p - '7'; + p += 1; + nr ++; + } else { + if (nr < 8) return 0x00000c84; + return ret; + } + } + } + } + p++; + pos++; + } + return ret; +} + +/* Update the Flash_Size and the Flash Timing */ +int update_flash_size (int flash_size) +{ + volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + unsigned long reg; + unsigned long tim; + + /* I must use reg, otherwise the board hang */ + reg = memctl->memc_or0; + reg &= ~ORxU_AM_MSK; + reg |= MEG_TO_AM(flash_size >> 20); + tim = get_flash_timing (); + reg &= ~0xfff; + reg |= (tim & 0xfff); + memctl->memc_or0 = reg; + return 0; +} +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> +#include <linux/mtd/mtd.h> + +static u8 hwctl = 0; + +static void upmnand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +{ + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + } +} + +static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + + if (hwctl & 0x1) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); + } else if (hwctl & 0x2) { + WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); + } else { + WRITE_NAND(byte, base); + } +} + +static u_char upmnand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + + return READ_NAND(base); +} + +static int tqm8272_dev_ready(struct mtd_info *mtdinfo) +{ + /* constant delay (see also tR in the datasheet) */ + udelay(12); \ + return 1; +} + +#ifndef CONFIG_NAND_SPL +static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + buf[i] = *base; +} + +static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + *base = buf[i]; +} + +static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); + int i; + + for (i = 0; i < len; i++) + if (buf[i] != *base) + return -1; + return 0; +} +#endif /* #ifndef CONFIG_NAND_SPL */ + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + chipsel = chip; +} + +int board_nand_init(struct nand_chip *nand) +{ + static int UpmInit = 0; + volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + + if (hwinf.nand == 0) return -1; + + /* Setup the UPM */ + if (UpmInit == 0) { + switch (hwinf.busclk_real) { + case 100000000: + upmconfig (UPMB, (uint *) upmTable100, + sizeof (upmTable100) / sizeof (uint)); + break; + case 133333333: + upmconfig (UPMB, (uint *) upmTable133, + sizeof (upmTable133) / sizeof (uint)); + break; + default: + upmconfig (UPMB, (uint *) upmTable67, + sizeof (upmTable67) / sizeof (uint)); + break; + } + UpmInit = 1; + } + + /* Setup the memctrl */ + memctl->memc_or3 = CFG_NAND_OR; + memctl->memc_br3 = CFG_NAND_BR; + memctl->memc_mbmr = (MxMR_OP_NORM); + + nand->eccmode = NAND_ECC_SOFT; + + nand->hwcontrol = upmnand_hwcontrol; + nand->read_byte = upmnand_read_byte; + nand->write_byte = upmnand_write_byte; + nand->dev_ready = tqm8272_dev_ready; + +#ifndef CONFIG_NAND_SPL + nand->write_buf = tqm8272_write_buf; + nand->read_buf = tqm8272_read_buf; + nand->verify_buf = tqm8272_verify_buf; +#endif + + /* + * Select required NAND chip + */ + board_nand_select_device(nand, 0); + return 0; +} + +#endif /* CFG_CMD_NAND */ + +#ifdef CONFIG_PCI +struct pci_controller hose; + +int board_early_init_f (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; + return 0; +} + +extern void pci_mpc8250_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc8250_init(&hose); +} +#endif diff --git a/board/tqm8272/u-boot.lds b/board/tqm8272/u-boot.lds new file mode 100644 index 0000000..05f29c6 --- /dev/null +++ b/board/tqm8272/u-boot.lds @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8260/start.o (.text) + *(.text) + common/environment.o(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index dede996..ace4aa2 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -191,16 +191,8 @@ int checkboard (void) return 0; } - -int board_early_init_r(void) +int board_early_init_f(void) { - /* - * Now, when we are in RAM, enable flash write access for the - * detection process. Note that CS_BOOT cannot be cleared when - * executing in flash. - */ - *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - #ifdef CONFIG_HW_WATCHDOG /* * Enable and configure the direction (output) of PSC3_9 - watchdog @@ -210,6 +202,17 @@ int board_early_init_r(void) *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9; *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9; #endif /* CONFIG_HW_WATCHDOG */ + return 0; +} + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for the + * detection process. Note that CS_BOOT cannot be cleared when + * executing in flash. + */ + *(vu_long *) MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ /* * Enable GPIO_WKUP_7 to "read the status of the actual power diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index 5d2cd65..a417143 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -448,7 +448,7 @@ static void dfc_gpio_init(void) * Members with a "?" were not set in the merged testing-NAND branch, * so they are not set here either. */ -void board_nand_init(struct nand_chip *nand) +int board_nand_init(struct nand_chip *nand) { unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR; @@ -576,6 +576,7 @@ void board_nand_init(struct nand_chip *nand) nand->cmdfunc = dfc_cmdfunc; nand->autooob = &delta_oob; nand->badblock_pattern = &delta_bbt_descr; + return 0; } #else |