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-rw-r--r--board/amcc/sequoia/sequoia.c9
-rw-r--r--board/amcc/sequoia/sequoia.h67
-rw-r--r--board/lwmon5/lwmon5.c17
-rw-r--r--board/lwmon5/sdram.c64
4 files changed, 77 insertions, 80 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b437653..f823117 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,7 +25,6 @@
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
-#include "sequoia.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -226,7 +225,7 @@ int misc_init_r(void)
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
@@ -254,7 +253,7 @@ int misc_init_r(void)
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
@@ -298,7 +297,7 @@ int misc_init_r(void)
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@@ -323,7 +322,7 @@ int misc_init_r(void)
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets*/
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
deleted file mode 100644
index 1d44b16..0000000
--- a/board/amcc/sequoia/sequoia.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-/*----------------------------------------------------------------------------+
- | EBC Configuration Register - EBC0_CFG
- +----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN 0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED 0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK 0x38000000
-#define EBC0_CFG_RTC_16PERCLK 0x00000000
-#define EBC0_CFG_RTC_32PERCLK 0x08000000
-#define EBC0_CFG_RTC_64PERCLK 0x10000000
-#define EBC0_CFG_RTC_128PERCLK 0x18000000
-#define EBC0_CFG_RTC_256PERCLK 0x20000000
-#define EBC0_CFG_RTC_512PERCLK 0x28000000
-#define EBC0_CFG_RTC_1024PERCLK 0x30000000
-#define EBC0_CFG_RTC_2048PERCLK 0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW 0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
-#define EBC0_CFG_EMPL_HIGH 0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW 0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
-#define EBC0_CFG_EMPH_HIGH 0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN 0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW 0x00000000
-#define EBC0_CFG_BPF_TWODW 0x00100000
-#define EBC0_CFG_BPF_FOURDW 0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT 0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED 0x00000000
-#define EBC0_CFG_PME_ENABLED 0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-
-#define SDR0_USB0 0x0320 /* USB Control Register */
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index d5b8f8c..d916284 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -19,9 +19,10 @@
*/
#include <common.h>
-#include <asm/processor.h>
#include <ppc440.h>
+#include <asm/processor.h>
#include <asm/gpio.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -220,6 +221,13 @@ int misc_init_r(void)
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
+ /* Lime memory clock adjusted to 133MHz */
+ out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+ /* Wait untill time expired. Because of requirements in lime manual */
+ udelay(300);
+ /* Write lime controller memory parameters */
+ out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+
/*
* Reset PHY's
*/
@@ -229,13 +237,6 @@ int misc_init_r(void)
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
- /*
- * Reset USB hub
- */
- gpio_write_bit(CFG_GPIO_HUB_RST, 0);
- udelay(100);
- gpio_write_bit(CFG_GPIO_HUB_RST, 1);
-
return 0;
}
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 85811ad..9a4a8ee 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
+#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+ /*
+ * Some boards (like lwmon5) need to preserve the memory
+ * content upon ECC generation (for the log-buffer).
+ * Therefore we don't fill the memory with a pattern or
+ * just zero it, but write the same values back that are
+ * already in the memory cells.
+ */
+ address_increment = CFG_CACHELINE_SIZE;
+ end_address = current_address + num_bytes;
+
+ current_address = start_address;
+ while (current_address < end_address) {
+ ppcDcbi(current_address);
+ ppcDcbf(current_address);
+ current_address += CFG_CACHELINE_SIZE;
+ }
+#else
dcbz_area(start_address, num_bytes);
dflush();
+#endif
}
sync();
@@ -518,6 +537,8 @@ long int initdram (int board_type)
{
u32 val;
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
+ /* CL=3 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
@@ -558,6 +579,49 @@ long int initdram (int board_type)
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#else
+ /* CL=4 */
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+ mtsdram(DDR0_04, 0x0B030300);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0003C812);
+ mtsdram(DDR0_07, 0x00090100);
+ mtsdram(DDR0_08, 0x03c80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000300);
+ mtsdram(DDR0_11, 0x000CC800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1e000000);
+ mtsdram(DDR0_18, 0x1e1e1e1e);
+ mtsdram(DDR0_19, 0x1e1e1e1e);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
+#else
+ mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+ mtsdram(DDR0_23, 0x01000000);
+ mtsdram(DDR0_24, 0x01010001);
+
+ mtsdram(DDR0_26, 0x2D93028A);
+ mtsdram(DDR0_27, 0x0784682B);
+
+ mtsdram(DDR0_28, 0x00000080);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000008);
+
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#endif
wait_for_dlllock();
generated by cgit v1.1 at 2024-12-16 00:02:41 +0000