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-rw-r--r--board/esd/ash405/Makefile4
-rw-r--r--board/esd/ash405/ash405.c44
-rw-r--r--board/esd/cms700/Makefile5
-rw-r--r--board/esd/cms700/cms700.c39
-rw-r--r--board/esd/common/auto_update.c4
-rw-r--r--board/esd/common/esd405ep_nand.c87
-rw-r--r--board/esd/cpci750/cpci750.c89
-rw-r--r--board/esd/cpci750/ide.c2
-rw-r--r--board/esd/hh405/Makefile5
-rw-r--r--board/esd/hh405/hh405.c22
-rw-r--r--board/esd/hub405/Makefile4
-rw-r--r--board/esd/hub405/hub405.c34
-rw-r--r--board/esd/plu405/Makefile5
-rw-r--r--board/esd/plu405/plu405.c56
-rw-r--r--board/esd/voh405/Makefile4
-rw-r--r--board/esd/voh405/voh405.c20
-rw-r--r--board/esd/wuh405/Makefile4
-rw-r--r--board/esd/wuh405/wuh405.c36
-rw-r--r--board/fads/fads.h3
19 files changed, 234 insertions, 233 deletions
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index f41eb7b..8a5b03b 100644
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@@ -33,6 +34,7 @@
#endif
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
@@ -164,18 +166,12 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@@ -218,35 +214,17 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
-int testdram (void)
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
+#ifdef CONFIG_LXT971_NO_SLEEP
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
#endif
+}
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index df48766..0d4ab2d 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -33,7 +33,10 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-COBJS = $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ $(CPLD) \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 635ba2f..2cdd7be 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@@ -68,9 +69,9 @@ int board_early_init_f (void)
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
@@ -94,13 +95,7 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
- /*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
return (0);
}
@@ -153,11 +148,6 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
@@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
break;
}
}
@@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index c4a0957..a76b00f 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -27,7 +27,9 @@
#include <command.h>
#include <image.h>
#include <asm/byteorder.h>
+#if defined(CFG_NAND_LEGACY)
#include <linux/mtd/nand_legacy.h>
+#endif
#include <fat.h>
#include <part.h>
@@ -290,6 +292,8 @@ int au_do_update(int i, long sz)
rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2,
start, nbytes, (size_t *)&total, (uchar *)addr);
debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes);
+#else
+ rc = -1;
#endif
}
if (rc != 0) {
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
new file mode 100644
index 0000000..7bf6847
--- /dev/null
+++ b/board/esd/common/esd405ep_nand.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <asm/io.h>
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ switch(cmd) {
+ case NAND_CTL_SETCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+ break;
+ case NAND_CTL_CLRCLE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+ break;
+ case NAND_CTL_SETALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+ break;
+ case NAND_CTL_CLRALE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+ break;
+ case NAND_CTL_SETNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+ break;
+ case NAND_CTL_CLRNCE:
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+ break;
+ }
+}
+
+
+/*
+ * read device ready pin
+ */
+static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+ return 1;
+ return 0;
+}
+
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /*
+ * Set NAND-FLASH GPIO signals to defaults
+ */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Initialize nand_chip structure
+ */
+ nand->hwcontrol = esd405ep_nand_hwcontrol;
+ nand->dev_ready = esd405ep_nand_device_ready;
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_BIG_DELAY_US;
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+ return 0;
+}
+#endif
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 17e3568..298aa6a 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -55,6 +55,71 @@
#define DP(x)
#endif
+static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */
+ {"PCI0DLL_1 "}, /* 30 */
+ {"PCI0DLL_0 "}, /* 29 */
+ {"PCI1DLL_2 "}, /* 28 */
+ {"PCI1DLL_1 "}, /* 27 */
+ {"PCI1DLL_0 "}, /* 26 */
+ {"BbEP2En "}, /* 25 */
+ {"SDRAMRdDataDel"}, /* 24 */
+ {"SDRAMRdDel "}, /* 23 */
+ {"SDRAMSync "}, /* 22 */
+ {"SDRAMPipeSel_1"}, /* 21 */
+ {"SDRAMPipeSel_0"}, /* 20 */
+ {"SDRAMAddDel "}, /* 19 */
+ {"SDRAMClkSel "}, /* 18 */
+ {"Reserved(1!) "}, /* 17 */
+ {"PCIRty "}, /* 16 */
+ {"BootCSWidth_1 "}, /* 15 */
+ {"BootCSWidth_0 "}, /* 14 */
+ {"PCI1PadsCal "}, /* 13 */
+ {"PCI0PadsCal "}, /* 12 */
+ {"MultiMVId_1 "}, /* 11 */
+ {"MultiMVId_0 "}, /* 10 */
+ {"MultiGTEn "}, /* 09 */
+ {"Int60xArb "}, /* 08 */
+ {"CPUBusConfig_1"}, /* 07 */
+ {"CPUBusConfig_0"}, /* 06 */
+ {"DefIntSpc "}, /* 05 */
+ {0 }, /* 04 */
+ {"SROMAdd_1 "}, /* 03 */
+ {"SROMAdd_0 "}, /* 02 */
+ {"DRAMPadCal "}, /* 01 */
+ {"SInitEn "}, /* 00 */
+ {0 }, /* 31 */
+ {0 }, /* 30 */
+ {0 }, /* 29 */
+ {0 }, /* 28 */
+ {0 }, /* 27 */
+ {0 }, /* 26 */
+ {0 }, /* 25 */
+ {0 }, /* 24 */
+ {0 }, /* 23 */
+ {0 }, /* 22 */
+ {"JTAGCalBy "}, /* 21 */
+ {"GB2Sel "}, /* 20 */
+ {"GB1Sel "}, /* 19 */
+ {"DRAMPLL_MDiv_5"}, /* 18 */
+ {"DRAMPLL_MDiv_4"}, /* 17 */
+ {"DRAMPLL_MDiv_3"}, /* 16 */
+ {"DRAMPLL_MDiv_2"}, /* 15 */
+ {"DRAMPLL_MDiv_1"}, /* 14 */
+ {"DRAMPLL_MDiv_0"}, /* 13 */
+ {"GB0Sel "}, /* 12 */
+ {"DRAMPLLPU "}, /* 11 */
+ {"DRAMPLL_HIKVCO"}, /* 10 */
+ {"DRAMPLLNP "}, /* 09 */
+ {"DRAMPLL_NDiv_7"}, /* 08 */
+ {"DRAMPLL_NDiv_6"}, /* 07 */
+ {"CPUPadCal "}, /* 06 */
+ {"DRAMPLL_NDiv_5"}, /* 05 */
+ {"DRAMPLL_NDiv_4"}, /* 04 */
+ {"DRAMPLL_NDiv_3"}, /* 03 */
+ {"DRAMPLL_NDiv_2"}, /* 02 */
+ {"DRAMPLL_NDiv_1"}, /* 01 */
+ {"DRAMPLL_NDiv_0"}}; /* 00 */
+
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern flash_info_t flash_info[];
@@ -901,21 +966,37 @@ void board_prebootm_init ()
dcache_disable ();
}
-
-int do_show_cfg(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int reset_sample_low;
unsigned int reset_sample_high;
+ unsigned int l, l1, l2;
GT_REG_READ(0x3c4, &reset_sample_low);
GT_REG_READ(0x3d4, &reset_sample_high);
printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
+ l2 = 0;
+ for (l=0; l<63; l++) {
+ if (show_config_tab[l][0] != 0) {
+ printf("%14s:%1x ", show_config_tab[l],
+ ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
+ l2++;
+ if ((l2 % 4) == 0)
+ printf("\n");
+ } else {
+ l1++;
+ }
+ if (l == 32)
+ reset_sample_low = reset_sample_high;
+ }
+ printf("\n");
+
return(0);
}
U_BOOT_CMD(
- show_cfg, 1, 1, do_show_cfg,
- "show_cfg- Show Marvell strapping register\n",
+ show_config, 1, 1, do_show_config,
+ "show_config - Show Marvell strapping register\n",
"Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
);
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 01b90c6..0adafe2 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -43,6 +43,8 @@ int ide_preinit (void)
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
+ if (devbusfn == -1)
+ devbusfn = pci_find_device (0x1095, 0x3114, 0);
if (devbusfn != -1) {
status = 0;
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
index ce7876c..0e5e57a 100644
--- a/board/esd/hh405/Makefile
+++ b/board/esd/hh405/Makefile
@@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 9ef5907..67b5d54 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -5,7 +5,7 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@@ -477,12 +477,6 @@ int misc_init_r (void)
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* Reset touch-screen controller
*/
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
@@ -690,20 +684,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/hub405/Makefile
+++ b/board/esd/hub405/Makefile
@@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index dd3706e..25c8068 100644
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -153,12 +153,6 @@ int misc_init_r (void)
out32(GPIO0_OR, val);
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* check board type and setup AP power
*/
str = getenv("bd_type"); /* this is only set on non prototype hardware */
@@ -242,33 +236,5 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
index ce7876c..0e5e57a 100644
--- a/board/esd/plu405/Makefile
+++ b/board/esd/plu405/Makefile
@@ -28,7 +28,10 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o ../common/auto_update.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
+ ../common/auto_update.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 920f717..f026a7a 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
@@ -31,6 +32,8 @@
#define FPGA_DEBUG
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
@@ -114,6 +117,10 @@ int misc_init_r (void)
int index;
int i;
+ /* adjust flash start and offset */
+ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
+ gd->bd->bi_flashoffset = 0;
+
dst = malloc(CFG_FPGA_MAX_SIZE);
if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
@@ -177,18 +184,12 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
udelay(1000); /* wait 1ms */
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@@ -226,24 +227,10 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
@@ -262,31 +249,6 @@ void ide_set_reset(int on)
#endif /* CONFIG_IDE_RESET */
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
-#ifdef CONFIG_AUTO_UPDATE_SHOW
-void board_auto_update_show(int au_active)
-{
- if (au_active) {
- printf("\n Dies ist die board-funktion: Updating!!!\n");
- } else {
- printf("\n Dies ist die board-funktion: Updating done!!!\n");
- }
-}
-#endif
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/voh405/Makefile
+++ b/board/esd/voh405/Makefile
@@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 3e118e7..2857a0be 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -195,12 +195,6 @@ int misc_init_r (void)
udelay(1000); /* wait 1ms */
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@@ -340,17 +334,3 @@ void ide_set_reset(int on)
}
}
#endif /* CONFIG_IDE_RESET */
-
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
index 4d75868..308f752 100644
--- a/board/esd/wuh405/Makefile
+++ b/board/esd/wuh405/Makefile
@@ -28,7 +28,9 @@ endif
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o ../common/misc.o
+COBJS = $(BOARD).o flash.o \
+ ../common/misc.o \
+ ../common/esd405ep_nand.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index 61d1d6c..dba3ce8 100644
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -170,12 +170,6 @@ int misc_init_r (void)
udelay(1000); /* wait 1ms */
/*
- * Set NAND-FLASH GPIO signals to default
- */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
-
- /*
* Enable interrupts in exar duart mcr[3]
*/
*duart0_mcr = 0x08;
@@ -218,35 +212,5 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CFG_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
diff --git a/board/fads/fads.h b/board/fads/fads.h
index c6f7ccd..a7fe2e9 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -71,7 +71,10 @@
#undef CONFIG_BOOTARGS
#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#if !defined(CONFIG_MPC885ADS)
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
+#endif
/*
* New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
generated by cgit v1.1 at 2024-12-24 13:36:11 +0000