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-rw-r--r--board/bc3450/bc3450.c19
-rw-r--r--board/bc3450/cmd_bc3450.c712
-rw-r--r--board/cobra5272/flash.c1
-rw-r--r--board/delta/delta.c208
-rw-r--r--board/m5271evb/Makefile (renamed from board/mpc8349ads/Makefile)17
-rw-r--r--board/m5271evb/config.mk (renamed from board/mpc8349ads/config.mk)10
-rw-r--r--board/m5271evb/m5271evb.c125
-rw-r--r--board/m5271evb/u-boot.lds145
-rw-r--r--board/m5272c3/flash.c1
-rw-r--r--board/m5282evb/flash.c1
-rw-r--r--board/mpc8349ads/mpc8349ads.c235
-rw-r--r--board/mpc8349emds/mpc8349emds.c46
-rw-r--r--board/mpc8349emds/pci.c (renamed from board/mpc8349ads/pci.c)9
-rw-r--r--board/nc650/nand.c68
-rw-r--r--board/nc650/nc650.c12
-rw-r--r--board/r5200/Makefile40
-rw-r--r--board/r5200/config.mk25
-rw-r--r--board/r5200/r5200.c125
-rw-r--r--board/r5200/u-boot.lds (renamed from board/mpc8349ads/u-boot.lds)46
-rw-r--r--board/zylonite/Makefile4
-rw-r--r--board/zylonite/config.mk2
-rw-r--r--board/zylonite/lowlevel_init.S2
-rw-r--r--board/zylonite/nand.c584
23 files changed, 1724 insertions, 713 deletions
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
index a030b82..0d86518 100644
--- a/board/bc3450/bc3450.c
+++ b/board/bc3450/bc3450.c
@@ -1,6 +1,4 @@
/*
- * -- Version 1.1 --
- *
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -13,9 +11,6 @@
* (C) Copyright 2006
* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
*
- * History:
- * 1.1 - improved SM501 init to meet spec timing
- *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -51,7 +46,7 @@
#ifdef CONFIG_RTC_MPC5200
#include <rtc.h>
-#endif
+#endif
#ifdef CONFIG_PS2MULT
void ps2mult_early_init(void);
@@ -375,7 +370,7 @@ ulong post_word_load (void)
int board_early_init_r (void)
{
#ifdef CONFIG_RTC_MPC5200
- struct rtc_time t;
+ struct rtc_time t;
/* set to Wed Dec 31 19:00:00 1969 */
t.tm_sec = t.tm_min = 0;
@@ -384,7 +379,7 @@ int board_early_init_r (void)
t.tm_mon = 12;
t.tm_year = 1969;
t.tm_wday = 3;
-
+
rtc_set(&t);
#endif /* CONFIG_RTC_MPC5200 */
@@ -482,7 +477,7 @@ int last_stage_init (void)
} else {
puts ("VGA: SMI501 (Voyager) with 8 MB\n");
}
- /* restore origianl FB content */
+ /* restore origianl FB content */
if (restore) {
*(volatile u16 *)CFG_CS1_START = save;
__asm__ volatile ("sync");
@@ -493,8 +488,8 @@ int last_stage_init (void)
#ifdef CONFIG_VIDEO_SM501
-#define DISPLAY_WIDTH 640
-#define DISPLAY_HEIGHT 480
+#define DISPLAY_WIDTH 640
+#define DISPLAY_HEIGHT 480
#ifdef CONFIG_VIDEO_SM501_8BPP
#error CONFIG_VIDEO_SM501_8BPP not supported.
@@ -633,7 +628,7 @@ unsigned int board_video_init (void)
} else {
ret = SM501_MMIO_BASE;
}
-
+
if (restore) {
*(volatile u16 *)CFG_CS1_START = save;
__asm__ volatile ("sync");
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
index 1442b68..6bbe4e6 100644
--- a/board/bc3450/cmd_bc3450.c
+++ b/board/bc3450/cmd_bc3450.c
@@ -27,7 +27,7 @@
#include <common.h>
#include <command.h>
-/*
+/*
* BC3450 specific commands
*/
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
@@ -39,7 +39,7 @@
# define dprintf(fmt,args...)
#endif
-/*
+/*
* Definitions for DS1620 chip
*/
#define THERM_START_CONVERT 0xee
@@ -57,8 +57,8 @@
#define CFG_STANDALONE 0
struct therm {
- int hi;
- int lo;
+ int hi;
+ int lo;
};
/*
@@ -124,36 +124,46 @@ struct therm {
* Yet, the initialisation sequence is executed only the first
* time the function is called.
*/
-int sm501_gpio_init(void)
+int sm501_gpio_init (void)
{
- static int init_done = 0;
+ static int init_done = 0;
- if(init_done) {
+ if (init_done) {
/* dprintf("sm501_gpio_init: nothing to be done.\n"); */
- return 1;
- }
-
- /* enable SM501 GPIO control (in both power modes) */
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
- *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |= POWER_MODE_GATE_GPIO_PWM_I2C;
-
- /* set up default O/Ps */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~(DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(FP_DATA_TRI);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= (BUZZER | PWR_OFF);
-
- /* configure directions for SM501 GPIO pins */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &= ~(0x3F << 14);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~(DIP | DS1620_DQ);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= (DS1620_RES | DS1620_CLK);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &= ~DS1620_TLOW;
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |= (PWR_OFF | BUZZER | FP_DATA_TRI);
-
- init_done = 1;
+ return 1;
+ }
+
+ /* enable SM501 GPIO control (in both power modes) */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE0_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_POWER_MODE1_GATE) |=
+ POWER_MODE_GATE_GPIO_PWM_I2C;
+
+ /* set up default O/Ps */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~(DS1620_RES | DS1620_CLK);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~(FP_DATA_TRI);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+ (BUZZER | PWR_OFF);
+
+ /* configure directions for SM501 GPIO pins */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_LOW) &= ~(0xFF << 24);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_CTRL_HIGH) &=
+ ~(0x3F << 14);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &=
+ ~(DIP | DS1620_DQ);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |=
+ (DS1620_RES | DS1620_CLK);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) &=
+ ~DS1620_TLOW;
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_HIGH) |=
+ (PWR_OFF | BUZZER | FP_DATA_TRI);
+
+ init_done = 1;
/* dprintf("sm501_gpio_init: done.\n"); */
- return 0;
+ return 0;
}
@@ -163,347 +173,358 @@ int sm501_gpio_init(void)
* read and prints the dip switch
* and/or external config inputs (4bits) 0...0x0F
*/
-int cmd_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- vu_long rc = 0;
+ vu_long rc = 0;
- sm501_gpio_init();
+ sm501_gpio_init ();
- /* read dip switch */
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc = ~rc;
- rc &= DIP;
- rc = (int)(rc >> 24);
+ /* read dip switch */
+ rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+ rc = ~rc;
+ rc &= DIP;
+ rc = (int) (rc >> 24);
- /* plausibility check */
- if (rc > 0x0F)
- return -1;
+ /* plausibility check */
+ if (rc > 0x0F)
+ return -1;
- printf ("0x%x\n", rc);
- return 0;
+ printf ("0x%x\n", rc);
+ return 0;
}
-U_BOOT_CMD(
- dip , 1, 1, cmd_dip,
- "dip - read dip switch and config inputs\n",
- "\n"
- " - prints the state of the dip switch and/or\n"
- " external configuration inputs as hex value.\n"
- " - \"Config 1\" is the LSB\n"
- );
+U_BOOT_CMD (dip, 1, 1, cmd_dip,
+ "dip - read dip switch and config inputs\n",
+ "\n"
+ " - prints the state of the dip switch and/or\n"
+ " external configuration inputs as hex value.\n"
+ " - \"Config 1\" is the LSB\n");
/*
* buz - turns Buzzer on/off
*/
#ifdef CONFIG_BC3450_BUZZER
-static int cmd_buz (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- if (argc != 2) {
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
- }
+ if (argc != 2) {
+ printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+ return 1;
+ }
- sm501_gpio_init();
+ sm501_gpio_init ();
- if (strncmp (argv[1], "on", 2) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~(BUZZER);
- return 0;
- }
- else if (strncmp (argv[1], "off", 3) == 0) {
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |= BUZZER;
- return 0;
- }
- printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
- return 1;
+ if (strncmp (argv[1], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~(BUZZER);
+ return 0;
+ } else if (strncmp (argv[1], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) |=
+ BUZZER;
+ return 0;
+ }
+ printf ("Usage:\nspecify one argument: \"on\" or \"off\"\n");
+ return 1;
}
-U_BOOT_CMD(
- buz , 2, 1, cmd_buz,
- "buz - turns buzzer on/off\n",
- "\n"
- "buz <on/off>\n"
- " - turns the buzzer on or off\n"
- );
+U_BOOT_CMD (buz, 2, 1, cmd_buz,
+ "buz - turns buzzer on/off\n",
+ "\n" "buz <on/off>\n" " - turns the buzzer on or off\n");
#endif /* CONFIG_BC3450_BUZZER */
/*
* fp - front panel commands
*/
-static int cmd_fp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- sm501_gpio_init();
-
- if (strncmp (argv[1], "on", 2) == 0) {
- /* turn on VDD first */
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
- udelay(1000);
- /* then put data on */
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
- /* wait some time and enable backlight */
- udelay(1000);
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
- udelay(1000);
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
- return 0;
- }
- else if (strncmp (argv[1], "off", 3) == 0) {
- /* turn off the backlight first */
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
- udelay(1000);
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
- udelay(200000);
- /* wait some time, then remove data */
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
- udelay(1000);
- /* and remove VDD last */
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_VDDEN;
- return 0;
- }
- else if (strncmp (argv[1], "bl", 2) == 0) {
- /* turn on/off backlight only */
- if (strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
- udelay(1000);
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
- return 0;
- }
- else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
- udelay(1000);
- *(vu_long *)(SM501_MMIO_BASE + SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
- return 0;
+ sm501_gpio_init ();
+
+ if (strncmp (argv[1], "on", 2) == 0) {
+ /* turn on VDD first */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_VDDEN;
+ udelay (1000);
+ /* then put data on */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_DATA;
+ /* wait some time and enable backlight */
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_BIAS;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |= SM501_PDC_FPEN;
+ return 0;
+ } else if (strncmp (argv[1], "off", 3) == 0) {
+ /* turn off the backlight first */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_FPEN;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_BIAS;
+ udelay (200000);
+ /* wait some time, then remove data */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &= ~SM501_PDC_DATA;
+ udelay (1000);
+ /* and remove VDD last */
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_VDDEN;
+ return 0;
+ } else if (strncmp (argv[1], "bl", 2) == 0) {
+ /* turn on/off backlight only */
+ if (strncmp (argv[2], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |=
+ SM501_PDC_BIAS;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) |=
+ SM501_PDC_FPEN;
+ return 0;
+ } else if (strncmp (argv[2], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_FPEN;
+ udelay (1000);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_PANEL_DISPLAY_CONTROL) &=
+ ~SM501_PDC_BIAS;
+ return 0;
+ }
}
- }
#ifdef CONFIG_BC3450_CRT
- else if (strncmp (argv[1], "crt", 3) == 0) {
- /* enables/disables the crt output (debug only) */
- if(strncmp (argv[2], "on", 2) == 0) {
- *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |=
- (SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &=
- ~SM501_CDC_SEL;
- return 0;
- }
- else if (strncmp (argv[2], "off", 3) == 0) {
- *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) &=
- ~(SM501_CDC_TE | SM501_CDC_E);
- *(vu_long *)(SM501_MMIO_BASE + SM501_CRT_DISPLAY_CONTROL) |=
- SM501_CDC_SEL;
- return 0;
+ else if (strncmp (argv[1], "crt", 3) == 0) {
+ /* enables/disables the crt output (debug only) */
+ if (strncmp (argv[2], "on", 2) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) |=
+ (SM501_CDC_TE | SM501_CDC_E);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) &=
+ ~SM501_CDC_SEL;
+ return 0;
+ } else if (strncmp (argv[2], "off", 3) == 0) {
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) &=
+ ~(SM501_CDC_TE | SM501_CDC_E);
+ *(vu_long *) (SM501_MMIO_BASE +
+ SM501_CRT_DISPLAY_CONTROL) |=
+ SM501_CDC_SEL;
+ return 0;
+ }
}
- }
#endif /* CONFIG_BC3450_CRT */
- printf("Usage:%s\n", cmdtp->help);
- return 1;
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
}
-U_BOOT_CMD(
- fp , 3, 1, cmd_fp,
- "fp - front panes access functions\n",
- "\n"
- "fp bl <on/off>\n"
- " - turns the CCFL backlight of the display on/off\n"
- "fp <on/off>\n"
- " - turns the whole display on/off\n"
+U_BOOT_CMD (fp, 3, 1, cmd_fp,
+ "fp - front panes access functions\n",
+ "\n"
+ "fp bl <on/off>\n"
+ " - turns the CCFL backlight of the display on/off\n"
+ "fp <on/off>\n" " - turns the whole display on/off\n"
#ifdef CONFIG_BC3450_CRT
- "fp crt <on/off>\n"
- " - enables/disables the crt output (debug only)\n"
+ "fp crt <on/off>\n"
+ " - enables/disables the crt output (debug only)\n"
#endif /* CONFIG_BC3450_CRT */
- );
+ );
/*
* temp - DS1620 thermometer
*/
/* GERSYS BC3450 specific functions */
-static inline void bc_ds1620_set_clk(int clk)
+static inline void bc_ds1620_set_clk (int clk)
{
- if(clk)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_CLK;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_CLK;
+ if (clk)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+ DS1620_CLK;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~DS1620_CLK;
}
-static inline void bc_ds1620_set_data(int dat)
+static inline void bc_ds1620_set_data (int dat)
{
- if(dat)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_DQ;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_DQ;
+ if (dat)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |=
+ DS1620_DQ;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &=
+ ~DS1620_DQ;
}
-static inline int bc_ds1620_get_data(void)
+static inline int bc_ds1620_get_data (void)
{
- vu_long rc;
- rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
- rc &= DS1620_DQ;
- if(rc != 0)
- rc = 1;
- return (int)rc;
+ vu_long rc;
+
+ rc = *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW);
+ rc &= DS1620_DQ;
+ if (rc != 0)
+ rc = 1;
+ return (int) rc;
}
-static inline void bc_ds1620_set_data_dir(int dir)
+static inline void bc_ds1620_set_data_dir (int dir)
{
- if(dir) /* in */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
- else /* out */
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
+ if (dir) /* in */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) &= ~DS1620_DQ;
+ else /* out */
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_DIR_LOW) |= DS1620_DQ;
}
-static inline void bc_ds1620_set_reset(int res)
+static inline void bc_ds1620_set_reset (int res)
{
- if(res)
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
- else
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
+ if (res)
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) |= DS1620_RES;
+ else
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_LOW) &= ~DS1620_RES;
}
/* hardware independent functions */
-static void ds1620_send_bits(int nr, int value)
+static void ds1620_send_bits (int nr, int value)
{
- int i;
-
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_data(value & 1);
- bc_ds1620_set_clk(0);
- udelay(1);
- bc_ds1620_set_clk(1);
- udelay(1);
-
- value >>= 1;
- }
+ int i;
+
+ for (i = 0; i < nr; i++) {
+ bc_ds1620_set_data (value & 1);
+ bc_ds1620_set_clk (0);
+ udelay (1);
+ bc_ds1620_set_clk (1);
+ udelay (1);
+
+ value >>= 1;
+ }
}
-static unsigned int ds1620_recv_bits(int nr)
+static unsigned int ds1620_recv_bits (int nr)
{
- unsigned int value = 0, mask = 1;
- int i;
+ unsigned int value = 0, mask = 1;
+ int i;
- bc_ds1620_set_data(0);
+ bc_ds1620_set_data (0);
- for (i = 0; i < nr; i++) {
- bc_ds1620_set_clk(0);
- udelay(1);
+ for (i = 0; i < nr; i++) {
+ bc_ds1620_set_clk (0);
+ udelay (1);
- if (bc_ds1620_get_data())
- value |= mask;
+ if (bc_ds1620_get_data ())
+ value |= mask;
- mask <<= 1;
+ mask <<= 1;
- bc_ds1620_set_clk(1);
- udelay(1);
- }
+ bc_ds1620_set_clk (1);
+ udelay (1);
+ }
- return value;
+ return value;
}
-static void ds1620_out(int cmd, int bits, int value)
+static void ds1620_out (int cmd, int bits, int value)
{
- bc_ds1620_set_clk(1);
- bc_ds1620_set_data_dir(0);
+ bc_ds1620_set_clk (1);
+ bc_ds1620_set_data_dir (0);
- bc_ds1620_set_reset(0);
- udelay(1);
- bc_ds1620_set_reset(1);
+ bc_ds1620_set_reset (0);
+ udelay (1);
+ bc_ds1620_set_reset (1);
- udelay(1);
+ udelay (1);
- ds1620_send_bits(8, cmd);
- if (bits)
- ds1620_send_bits(bits, value);
+ ds1620_send_bits (8, cmd);
+ if (bits)
+ ds1620_send_bits (bits, value);
- udelay(1);
+ udelay (1);
- /* go stand alone */
- bc_ds1620_set_data_dir(1);
- bc_ds1620_set_reset(0);
- bc_ds1620_set_clk(0);
+ /* go stand alone */
+ bc_ds1620_set_data_dir (1);
+ bc_ds1620_set_reset (0);
+ bc_ds1620_set_clk (0);
- udelay(10000);
+ udelay (10000);
}
-static unsigned int ds1620_in(int cmd, int bits)
+static unsigned int ds1620_in (int cmd, int bits)
{
- unsigned int value;
+ unsigned int value;
- bc_ds1620_set_clk(1);
- bc_ds1620_set_data_dir(0);
+ bc_ds1620_set_clk (1);
+ bc_ds1620_set_data_dir (0);
- bc_ds1620_set_reset(0);
- udelay(1);
- bc_ds1620_set_reset(1);
+ bc_ds1620_set_reset (0);
+ udelay (1);
+ bc_ds1620_set_reset (1);
- udelay(1);
+ udelay (1);
- ds1620_send_bits(8, cmd);
+ ds1620_send_bits (8, cmd);
- bc_ds1620_set_data_dir(1);
- value = ds1620_recv_bits(bits);
+ bc_ds1620_set_data_dir (1);
+ value = ds1620_recv_bits (bits);
- /* go stand alone */
- bc_ds1620_set_data_dir(1);
- bc_ds1620_set_reset(0);
- bc_ds1620_set_clk(0);
+ /* go stand alone */
+ bc_ds1620_set_data_dir (1);
+ bc_ds1620_set_reset (0);
+ bc_ds1620_set_clk (0);
- return value;
+ return value;
}
-static int cvt_9_to_int(unsigned int val)
+static int cvt_9_to_int (unsigned int val)
{
- if (val & 0x100)
- val |= 0xfffffe00;
+ if (val & 0x100)
+ val |= 0xfffffe00;
- return val;
+ return val;
}
/* set thermostate thresholds */
-static void ds1620_write_state(struct therm *therm)
+static void ds1620_write_state (struct therm *therm)
{
- ds1620_out(THERM_WRITE_TL, 9, therm->lo);
- ds1620_out(THERM_WRITE_TH, 9, therm->hi);
- ds1620_out(THERM_START_CONVERT, 0, 0);
+ ds1620_out (THERM_WRITE_TL, 9, therm->lo);
+ ds1620_out (THERM_WRITE_TH, 9, therm->hi);
+ ds1620_out (THERM_START_CONVERT, 0, 0);
}
-static int cmd_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
- int i;
- struct therm therm;
+ int i;
+ struct therm therm;
- sm501_gpio_init();
+ sm501_gpio_init ();
- /* print temperature */
- if (argc == 1) {
- i = cvt_9_to_int(ds1620_in(THERM_READ_TEMP, 9));
- printf("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
- return 0;
- }
-
- /* set to default operation */
- if (strncmp (argv[1], "set", 3) == 0) {
- if(strncmp (argv[2], "default", 3) == 0) {
- therm.hi = +88;
- therm.lo = -20;
- therm.hi <<= 1;
- therm.lo <<= 1;
- ds1620_write_state(&therm);
- ds1620_out(THERM_WRITE_CONFIG, 8, CFG_STANDALONE);
- return 0;
+ /* print temperature */
+ if (argc == 1) {
+ i = cvt_9_to_int (ds1620_in (THERM_READ_TEMP, 9));
+ printf ("%d.%d C\n", i >> 1, i & 1 ? 5 : 0);
+ return 0;
}
- }
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
+ /* set to default operation */
+ if (strncmp (argv[1], "set", 3) == 0) {
+ if (strncmp (argv[2], "default", 3) == 0) {
+ therm.hi = +88;
+ therm.lo = -20;
+ therm.hi <<= 1;
+ therm.lo <<= 1;
+ ds1620_write_state (&therm);
+ ds1620_out (THERM_WRITE_CONFIG, 8, CFG_STANDALONE);
+ return 0;
+ }
+ }
+
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
}
-U_BOOT_CMD(
- temp , 3, 1, cmd_temp,
- "temp - print current temperature\n",
- "\n"
- "temp\n"
- " - print current temperature\n"
-);
+U_BOOT_CMD (temp, 3, 1, cmd_temp,
+ "temp - print current temperature\n",
+ "\n" "temp\n" " - print current temperature\n");
#ifdef CONFIG_BC3450_CAN
/*
@@ -512,40 +533,40 @@ U_BOOT_CMD(
* return 1 on CAN initialization failure
* return 0 if no failure
*/
-int can_init(void)
+int can_init (void)
{
static int init_done = 0;
int i;
struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+ (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900);
struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+ (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980);
/* GPIO configuration of the CAN pins is done in BC3450.h */
if (!init_done) {
/* init CAN 1 */
can1->canctl1 |= 0x80; /* CAN enable */
- udelay(100);
+ udelay (100);
i = 0;
can1->canctl0 |= 0x02; /* sleep mode */
/* wait until sleep mode reached */
while (!(can1->canctl1 & 0x02)) {
- udelay(10);
- i++;
- if (i == 10) {
- printf ("%s: CAN1 initialize error, "
- "can not enter sleep mode!\n",
- __FUNCTION__);
- return 1;
- }
+ udelay (10);
+ i++;
+ if (i == 10) {
+ printf ("%s: CAN1 initialize error, "
+ "can not enter sleep mode!\n",
+ __FUNCTION__);
+ return 1;
+ }
}
i = 0;
can1->canctl0 = 0x01; /* enter init mode */
/* wait until init mode reached */
while (!(can1->canctl1 & 0x01)) {
- udelay(10);
+ udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN1 initialize error, "
@@ -577,7 +598,7 @@ int can_init(void)
can1->canctl0 &= ~(0x02);
/* wait until init and sleep mode left */
while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
- udelay(10);
+ udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN1 initialize error, "
@@ -589,13 +610,13 @@ int can_init(void)
/* init CAN 2 */
can2->canctl1 |= 0x80; /* CAN enable */
- udelay(100);
+ udelay (100);
i = 0;
can2->canctl0 |= 0x02; /* sleep mode */
/* wait until sleep mode reached */
- while (!(can2->canctl1 & 0x02)) {
- udelay(10);
+ while (!(can2->canctl1 & 0x02)) {
+ udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
@@ -607,8 +628,8 @@ int can_init(void)
i = 0;
can2->canctl0 = 0x01; /* enter init mode */
/* wait until init mode reached */
- while (!(can2->canctl1 & 0x01)) {
- udelay(10);
+ while (!(can2->canctl1 & 0x01)) {
+ udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
@@ -640,7 +661,7 @@ int can_init(void)
i = 0;
/* wait until init mode left */
while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
- udelay(10);
+ udelay (10);
i++;
if (i == 10) {
printf ("%s: CAN2 initialize error, "
@@ -661,13 +682,13 @@ int can_init(void)
* return 1 on CAN failure
* return 0 if no failure
*/
-int do_can(char *argv[])
+int do_can (char *argv[])
{
int i;
- struct mpc5xxx_mscan *can1 =
- (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
- struct mpc5xxx_mscan *can2 =
- (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+ struct mpc5xxx_mscan *can1 =
+ (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900);
+ struct mpc5xxx_mscan *can2 =
+ (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980);
/* send a message on CAN1 */
can1->cantbsel = 0x01;
@@ -685,30 +706,27 @@ int do_can(char *argv[])
i++;
if (i == 10) {
printf ("%s: CAN1 send timeout, "
- "can not send message!\n",
- __FUNCTION__);
+ "can not send message!\n", __FUNCTION__);
return 1;
}
- udelay(1000);
+ udelay (1000);
}
- udelay(1000);
+ udelay (1000);
i = 0;
- while (!(can2->canrflg & 0x01)) {
+ while (!(can2->canrflg & 0x01)) {
i++;
if (i == 10) {
printf ("%s: CAN2 receive timeout, "
- "no message received!\n",
- __FUNCTION__);
+ "no message received!\n", __FUNCTION__);
return 1;
}
- udelay(1000);
+ udelay (1000);
}
-
+
if (can2->canrxfg.dsr[0] != 0xCC) {
printf ("%s: CAN2 receive error, "
- "data mismatch!\n",
- __FUNCTION__);
+ "data mismatch!\n", __FUNCTION__);
return 1;
}
@@ -728,24 +746,22 @@ int do_can(char *argv[])
i++;
if (i == 10) {
printf ("%s: CAN2 send error, "
- "can not send message!\n",
- __FUNCTION__);
+ "can not send message!\n", __FUNCTION__);
return 1;
}
- udelay(1000);
+ udelay (1000);
}
- udelay(1000);
+ udelay (1000);
i = 0;
- while (!(can1->canrflg & 0x01)) {
+ while (!(can1->canrflg & 0x01)) {
i++;
if (i == 10) {
printf ("%s: CAN1 receive timeout, "
- "no message received!\n",
- __FUNCTION__);
+ "no message received!\n", __FUNCTION__);
return 1;
}
- udelay(1000);
+ udelay (1000);
}
if (can1->canrxfg.dsr[0] != 0xCC) {
@@ -761,53 +777,51 @@ int do_can(char *argv[])
/*
* test - BC3450 HW test routines
*/
-int cmd_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
#ifdef CONFIG_BC3450_CAN
- int rcode;
- can_init();
+ int rcode;
+
+ can_init ();
#endif /* CONFIG_BC3450_CAN */
- sm501_gpio_init();
+ sm501_gpio_init ();
- if (argc != 2) {
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
- }
+ if (argc != 2) {
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
+ }
- if (strncmp (argv[1], "unit-off", 8) == 0) {
- printf ("waiting 2 seconds...\n");
- udelay(2000000);
- *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &= ~PWR_OFF;
- return 0;
- }
+ if (strncmp (argv[1], "unit-off", 8) == 0) {
+ printf ("waiting 2 seconds...\n");
+ udelay (2000000);
+ *(vu_long *) (SM501_MMIO_BASE + SM501_GPIO_DATA_HIGH) &=
+ ~PWR_OFF;
+ return 0;
+ }
#ifdef CONFIG_BC3450_CAN
- else if (strncmp (argv[1], "can", 2) == 0) {
- rcode = do_can (argv);
- if (simple_strtoul(argv[2], NULL, 10) == 2) {
- if (rcode == 0)
- printf ("OK\n");
- else
- printf ("Error\n");
+ else if (strncmp (argv[1], "can", 2) == 0) {
+ rcode = do_can (argv);
+ if (simple_strtoul (argv[2], NULL, 10) == 2) {
+ if (rcode == 0)
+ printf ("OK\n");
+ else
+ printf ("Error\n");
+ }
+ return rcode;
}
- return rcode;
- }
#endif /* CONFIG_BC3450_CAN */
- printf ("Usage:%s\n", cmdtp->help);
- return 1;
+ printf ("Usage:%s\n", cmdtp->help);
+ return 1;
}
-U_BOOT_CMD(
- test , 2, 1, cmd_test,
- "test - unit test routines\n",
- "\n"
+U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n"
#ifdef CONFIG_BC3450_CAN
- "test can\n"
- " - connect CAN1 (X8) with CAN2 (X9) for this test\n"
+ "test can\n"
+ " - connect CAN1 (X8) with CAN2 (X9) for this test\n"
#endif /* CONFIG_BC3450_CAN */
- "test unit-off\n"
- " - turns off the BC3450 unit\n"
- " WARNING: Unsaved environment variables will be lost!\n"
- );
+ "test unit-off\n"
+ " - turns off the BC3450 unit\n"
+ " WARNING: Unsaved environment variables will be lost!\n");
#endif /* CFG_CMD_BSP */
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 73cc2f2..82452e2 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info)
printf ("\n");
Done:
+ return;
}
diff --git a/board/delta/delta.c b/board/delta/delta.c
index b7671dd..b127ac8 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -28,6 +28,8 @@
#include <common.h>
#include <i2c.h>
#include <da9030.h>
+#include <malloc.h>
+#include <command.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -35,6 +37,9 @@ DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
static void init_DA9030(void);
+static void keys_init(void);
+static void get_pressed_keys(uchar *s);
+static uchar *key_match(uchar *kbd_data);
/*
* Miscelaneous platform dependent initialisations
@@ -56,13 +61,216 @@ int board_init (void)
int board_late_init(void)
{
+#ifdef DELTA_CHECK_KEYBD
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ char *str;
+ int i;
+#endif /* DELTA_CHECK_KEYBD */
+
setenv("stdout", "serial");
setenv("stderr", "serial");
+
+#ifdef DELTA_CHECK_KEYBD
+ keys_init();
+
+ memset(kbd_data, '\0', KEYBD_DATALEN);
+
+ /* check for pressed keys and setup keybd_env */
+ get_pressed_keys(kbd_data);
+
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ }
+ setenv ("keybd", keybd_env);
+
+ str = strdup ((char *)key_match (kbd_data)); /* decode keys */
+
+# ifdef CONFIG_PREBOOT /* automatically configure "preboot" command on key match */
+ setenv ("preboot", str); /* set or delete definition */
+# endif /* CONFIG_PREBOOT */
+ if (str != NULL) {
+ free (str);
+ }
+#endif /* DELTA_CHECK_KEYBD */
+
init_DA9030();
return 0;
}
+/*
+ * Magic Key Handling, mainly copied from board/lwmon/lwmon.c
+ */
+#ifdef DELTA_CHECK_KEYBD
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+/*
+ * Get pressed keys
+ * s is a buffer of size KEYBD_DATALEN-1
+ */
+static void get_pressed_keys(uchar *s)
+{
+ unsigned long val;
+ val = GPLR3;
+
+ if(val & (1<<31))
+ *s++ = KEYBD_KP_DKIN0;
+ if(val & (1<<18))
+ *s++ = KEYBD_KP_DKIN1;
+ if(val & (1<<29))
+ *s++ = KEYBD_KP_DKIN2;
+ if(val & (1<<22))
+ *s++ = KEYBD_KP_DKIN5;
+}
+
+static void keys_init()
+{
+ CKENB |= CKENB_7_GPIO;
+ udelay(100);
+
+ /* Configure GPIOs */
+ GPIO127 = 0xa840; /* KP_DKIN0 */
+ GPIO114 = 0xa840; /* KP_DKIN1 */
+ GPIO125 = 0xa840; /* KP_DKIN2 */
+ GPIO118 = 0xa840; /* KP_DKIN5 */
+
+ /* Configure GPIOs as inputs */
+ GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22);
+ GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22);
+
+ udelay(100);
+}
+
+static int compare_magic (uchar *kbd_data, uchar *str)
+{
+ /* uchar compare[KEYBD_DATALEN-1]; */
+ uchar compare[KEYBD_DATALEN];
+ char *nxt;
+ int i;
+
+ /* Don't include modifier byte */
+ /* memcpy (compare, kbd_data+1, KEYBD_DATALEN-1); */
+ memcpy (compare, kbd_data, KEYBD_DATALEN);
+
+ for (; str != NULL; str = (*nxt) ? (uchar *)(nxt+1) : (uchar *)nxt) {
+ uchar c;
+ int k;
+
+ c = (uchar) simple_strtoul ((char *)str, (char **) (&nxt), 16);
+
+ if (str == (uchar *)nxt) { /* invalid character */
+ break;
+ }
+
+ /*
+ * Check if this key matches the input.
+ * Set matches to zero, so they match only once
+ * and we can find duplicates or extra keys
+ */
+ for (k = 0; k < sizeof(compare); ++k) {
+ if (compare[k] == '\0') /* only non-zero entries */
+ continue;
+ if (c == compare[k]) { /* found matching key */
+ compare[k] = '\0';
+ break;
+ }
+ }
+ if (k == sizeof(compare)) {
+ return -1; /* unmatched key */
+ }
+ }
+
+ /*
+ * A full match leaves no keys in the `compare' array,
+ */
+ for (i = 0; i < sizeof(compare); ++i) {
+ if (compare[i])
+ {
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+
+static uchar *key_match (uchar *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ uchar *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can pe appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix=(uchar *)kbd_magic_keys; *suffix || suffix==(uchar *)kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+#if 0
+ printf ("### Check magic \"%s\"\n", magic);
+#endif
+ if (compare_magic(kbd_data, (uchar *)getenv(magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+
+ cmd = getenv (cmd_name);
+#if 0
+ printf ("### Set PREBOOT to $(%s): \"%s\"\n",
+ cmd_name, cmd ? cmd : "<<NULL>>");
+#endif
+ *kbd_data = *suffix;
+ return ((uchar *)cmd);
+ }
+ }
+#if 0
+ printf ("### Delete PREBOOT\n");
+#endif
+ *kbd_data = '\0';
+ return (NULL);
+}
+
+int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ uchar kbd_data[KEYBD_DATALEN];
+ char keybd_env[2 * KEYBD_DATALEN + 1];
+ int i;
+
+ /* Read keys */
+ get_pressed_keys(kbd_data);
+ puts ("Keys:");
+ for (i = 0; i < KEYBD_DATALEN; ++i) {
+ sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
+ printf (" %02x", kbd_data[i]);
+ }
+ putc ('\n');
+ setenv ("keybd", keybd_env);
+ return 0;
+}
+
+U_BOOT_CMD(
+ kbd, 1, 1, do_kbd,
+ "kbd - read keyboard status\n",
+ NULL
+);
+
+#endif /* DELTA_CHECK_KEYBD */
+
+
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
diff --git a/board/mpc8349ads/Makefile b/board/m5271evb/Makefile
index f865f9c..34de983 100644
--- a/board/mpc8349ads/Makefile
+++ b/board/m5271evb/Makefile
@@ -1,5 +1,6 @@
#
-# Copyright 2004 Freescale Semiconductor, Inc.
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -24,22 +25,16 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS := $(BOARD).o pci.o
+OBJS = $(BOARD).o
-$(LIB): $(OBJS) $(SOBJS)
+$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
-clean:
- rm -f $(SOBJS) $(OBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak .depend
-
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
- $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
--include .depend
+sinclude .depend
#########################################################################
diff --git a/board/mpc8349ads/config.mk b/board/m5271evb/config.mk
index 4602169..9a7af7c 100644
--- a/board/mpc8349ads/config.mk
+++ b/board/m5271evb/config.mk
@@ -1,5 +1,7 @@
#
-# Copyright 2004 Freescale Semiconductor, Inc.
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -20,8 +22,4 @@
# MA 02111-1307 USA
#
-#
-# MPC83xxADS
-#
-
-TEXT_BASE = 0xFE700000
+TEXT_BASE = 0xffe00000
diff --git a/board/m5271evb/m5271evb.c b/board/m5271evb/m5271evb.c
new file mode 100644
index 0000000..d364bd6
--- /dev/null
+++ b/board/m5271evb/m5271evb.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+
+int checkboard (void) {
+ puts ("Board: Freescale M5271EVB\n");
+ return 0;
+};
+
+long int initdram (int board_type) {
+
+ int i;
+
+ /* Enable Address lines 23-21 and lower 16bits of data path */
+ mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
+ MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
+ MCF_GPIO_AD_DATAL);
+
+ /* Set CS2 pin to be SD_CS0 */
+ mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
+ | MCF_GPIO_PAR_CS_PAR_CS2);
+
+ /* Configure SDRAM Control Pin Assignemnt Register */
+ mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
+ MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
+ MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
+ MCF_GPIO_SDRAM_SDCS_11);
+
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE))
+ {
+ /* Initialize DRAM Control Register: DCR */
+ mbar_writeShort(MCF_SDRAMC_DCR,
+ MCF_SDRAMC_DCR_RTIM(0x01)
+ | MCF_SDRAMC_DCR_RC(0x30));
+
+ /*
+ * Initialize DACR0
+ *
+ * CASL: 01
+ * CBM: cmd at A20, bank select bits 21 and up
+ * PS: 32bit port size
+ */
+ mbar_writeLong(MCF_SDRAMC_DACR0,
+ MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+ | MCF_SDRAMC_DACRn_CASL(1)
+ | MCF_SDRAMC_DACRn_CBM(3)
+ | MCF_SDRAMC_DACRn_PS(0));
+
+ /* Initialize DMR0 */
+ mbar_writeLong(MCF_SDRAMC_DMR0,
+ MCF_SDRAMC_DMRn_BAM_16M
+ | MCF_SDRAMC_DMRn_V);
+
+ /* Set IP bit in DACR */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_IP);
+
+ /* Wait at least 20ns to allow banks to precharge */
+ for (i = 0; i < 5; i++)
+ asm(" nop");
+
+ /* Write to this block to initiate precharge */
+ *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
+
+ /* Set RE bit in DACR */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_RE);
+
+ /* Wait for at least 8 auto refresh cycles to occur */
+ for (i = 0; i < 2000; i++)
+ asm(" nop");
+
+ /* Finish the configuration by issuing the MRS */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_MRS);
+
+ /*
+ * Write to the SDRAM Mode Register A0-A11 = 0x400
+ *
+ * Write Burst Mode = Programmed Burst Length
+ * Op Mode = Standard Op
+ * CAS Latency = 2
+ * Burst Type = Sequential
+ * Burst Length = 1
+ */
+ *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+ }
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void) {
+
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/m5271evb/u-boot.lds b/board/m5271evb/u-boot.lds
new file mode 100644
index 0000000..69f3179
--- /dev/null
+++ b/board/m5271evb/u-boot.lds
@@ -0,0 +1,145 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+GROUP(libgcc.a)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ lib_m68k/traps.o (.text)
+ cpu/mcf52x2/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.ppcenv)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ _sbss = .;
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/m5272c3/flash.c b/board/m5272c3/flash.c
index f156342..ea0b1fd 100644
--- a/board/m5272c3/flash.c
+++ b/board/m5272c3/flash.c
@@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info)
printf ("\n");
Done:
+ return;
}
diff --git a/board/m5282evb/flash.c b/board/m5282evb/flash.c
index 95f35ad..36a7c31 100644
--- a/board/m5282evb/flash.c
+++ b/board/m5282evb/flash.c
@@ -65,6 +65,7 @@ void flash_print_info (flash_info_t * info)
printf ("\n");
Done:
+ return;
}
diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c
deleted file mode 100644
index 9841298..0000000
--- a/board/mpc8349ads/mpc8349ads.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Copyright Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Change log:
- * 20050101: Eran Liberty (liberty@freescale.com)
- * Initial file creating (porting from 85XX & 8260)
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc83xx.h>
-#include <asm/mpc8349_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include <spd_sdram.h>
-#endif
-int fixed_sdram(void);
-void sdram_init(void);
-
-int board_early_init_f (void)
-{
- volatile u8* bcsr = (volatile u8*)CFG_BCSR;
-
- /* Enable flash write */
- bcsr[1] &= ~0x01;
-
- return 0;
-}
-
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
-
-long int initdram (int board_type)
-{
- volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
- u32 msize = 0;
-
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
-#if defined(CONFIG_SPD_EEPROM)
- msize = spd_sdram();
-#else
- msize = fixed_sdram();
-#endif
- /*
- * Initialize SDRAM if it is on local bus.
- */
- sdram_init();
- puts(" DDR RAM: ");
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-int fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
- u32 msize = 0;
- u32 ddr_size;
- u32 ddr_size_log2;
-
- msize = CFG_DDR_SIZE;
- for (ddr_size = msize << 20, ddr_size_log2 = 0;
- (ddr_size > 1);
- ddr_size = ddr_size>>1, ddr_size_log2++) {
- if (ddr_size & 1) {
- return -1;
- }
- }
- im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 256)
-#warning Currenly any ddr size other than 256 is not supported
-#endif
-
- im->ddr.csbnds[0].csbnds = 0x00100017;
- im->ddr.csbnds[1].csbnds = 0x0018001f;
- im->ddr.csbnds[2].csbnds = 0x00000007;
- im->ddr.csbnds[3].csbnds = 0x0008000f;
- im->ddr.cs_config[0] = CFG_DDR_CONFIG;
- im->ddr.cs_config[1] = CFG_DDR_CONFIG;
- im->ddr.cs_config[2] = CFG_DDR_CONFIG;
- im->ddr.cs_config[3] = CFG_DDR_CONFIG;
- im->ddr.timing_cfg_1 =
- 3 << TIMING_CFG1_PRETOACT_SHIFT |
- 7 << TIMING_CFG1_ACTTOPRE_SHIFT |
- 3 << TIMING_CFG1_ACTTORW_SHIFT |
- 4 << TIMING_CFG1_CASLAT_SHIFT |
- 3 << TIMING_CFG1_REFREC_SHIFT |
- 3 << TIMING_CFG1_WRREC_SHIFT |
- 2 << TIMING_CFG1_ACTTOACT_SHIFT |
- 1 << TIMING_CFG1_WRTORD_SHIFT;
- im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT;
- im->ddr.sdram_cfg =
- SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
- | SDRAM_CFG_2T_EN
-#endif
- | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
- im->ddr.sdram_mode =
- 0x2000 << SDRAM_MODE_ESD_SHIFT |
- 0x0162 << SDRAM_MODE_SD_SHIFT;
-
- im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT |
- 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT;
- udelay(200);
-
- im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
-
- return msize;
-}
-#endif/*!CFG_SPD_EEPROM*/
-
-
-int checkboard (void)
-{
- puts("Board: Freescale MPC8349ADS\n");
- return 0;
-}
-
-/*
- * if MPC8349ADS is soldered with SDRAM
- */
-#if defined(CFG_BR2_PRELIM) \
- && defined(CFG_OR2_PRELIM) \
- && defined(CFG_LBLAWBAR2_PRELIM) \
- && defined(CFG_LBLAWAR2_PRELIM)
-/*
- * Initialize SDRAM memory on the Local Bus.
- */
-
-void
-sdram_init(void)
-{
- volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile lbus8349_t *lbc= &immap->lbus;
- uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
-
- puts("\n SDRAM on Local Bus: ");
- print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
- /*
- * Setup SDRAM Base and Option Registers, already done in cpu_init.c
- */
-
- /*setup mtrpt, lsrt and lbcr for LB bus*/
- lbc->lbcr = CFG_LBC_LBCR;
- lbc->mrtpr = CFG_LBC_MRTPR;
- lbc->lsrt = CFG_LBC_LSRT;
- asm("sync");
-
- /*
- * Configure the SDRAM controller Machine Mode Register.
- */
- lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/
-
- lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
- asm("sync");
- /*1 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*2 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*3 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*4 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*5 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*6 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*7 times*/
- *sdram_addr = 0xff;
- udelay(100);
- /*8 times*/
- *sdram_addr = 0xff;
- udelay(100);
-
- /* 0x58636733;mode register write operation */
- lbc->lsdmr = CFG_LBC_LSDMR_4;
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-
- lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/
- asm("sync");
- *sdram_addr = 0xff;
- udelay(100);
-}
-#else
-void
-sdram_init(void)
-{
- put("SDRAM on Local Bus is NOT available!\n");
-}
-#endif
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index 7ece7db..b5ccb53 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
@@ -30,9 +30,6 @@
#include <spd.h>
#include <miiphy.h>
#include <command.h>
-#if defined(CONFIG_PCI)
-#include <pci.h>
-#endif
#if defined(CONFIG_SPD_EEPROM)
#include <spd_sdram.h>
#endif
@@ -50,6 +47,11 @@ int board_early_init_f (void)
/* Enable flash write */
bcsr[1] &= ~0x01;
+#ifdef CFG_USE_MPC834XSYS_USB_PHY
+ /* Use USB PHY on SYS board */
+ bcsr[5] |= 0x02;
+#endif
+
return 0;
}
@@ -152,44 +154,6 @@ int checkboard (void)
return 0;
}
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc8349emds_config_table[] = {
- {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMON_MEMORY | PCI_COMMAND_MASTER
- } },
- {}
-}
-#endif
-
-volatile static struct pci_controller hose[] = {
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- },
- {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc8349emds_config_table,
-#endif
- }
-};
-#endif /* CONFIG_PCI */
-
-void pci_init_board(void)
-{
-#ifdef CONFIG_PCI
- extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
-
- pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
-}
-
/*
* if MPC8349EMDS is soldered with SDRAM
*/
diff --git a/board/mpc8349ads/pci.c b/board/mpc8349emds/pci.c
index 319e35c..63e4405 100644
--- a/board/mpc8349ads/pci.c
+++ b/board/mpc8349emds/pci.c
@@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc83xxads_config_table[] = {
+static struct pci_config_table pci_mpc8349emds_config_table[] = {
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_IDSEL_NUMBER, PCI_ANY_ID,
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
@@ -50,12 +50,12 @@ static struct pci_config_table pci_mpc83xxads_config_table[] = {
static struct pci_controller pci_hose[] = {
{
#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxads_config_table,
+ config_table:pci_mpc8349emds_config_table,
#endif
},
{
#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc83xxads_config_table,
+ config_table:pci_mpc8349emds_config_table,
#endif
}
};
@@ -188,7 +188,7 @@ pci_init_board(void)
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
+ pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
/*
* Configure PCI Outbound Translation Windows
@@ -378,4 +378,5 @@ pci_init_board(void)
#endif
}
+
#endif /* CONFIG_PCI */
diff --git a/board/nc650/nand.c b/board/nc650/nand.c
index f27e536..de54386 100644
--- a/board/nc650/nand.c
+++ b/board/nc650/nand.c
@@ -37,22 +37,22 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
struct nand_chip *this = mtd->priv;
switch(cmd) {
- case NAND_CTL_SETCLE:
- this->IO_ADDR_W += 2;
- break;
- case NAND_CTL_CLRCLE:
- this->IO_ADDR_W -= 2;
- break;
- case NAND_CTL_SETALE:
- this->IO_ADDR_W += 1;
- break;
- case NAND_CTL_CLRALE:
- this->IO_ADDR_W -= 1;
- break;
- case NAND_CTL_SETNCE:
- case NAND_CTL_CLRNCE:
- /* nop */
- break;
+ case NAND_CTL_SETCLE:
+ this->IO_ADDR_W += 2;
+ break;
+ case NAND_CTL_CLRCLE:
+ this->IO_ADDR_W -= 2;
+ break;
+ case NAND_CTL_SETALE:
+ this->IO_ADDR_W += 1;
+ break;
+ case NAND_CTL_CLRALE:
+ this->IO_ADDR_W -= 1;
+ break;
+ case NAND_CTL_SETNCE:
+ case NAND_CTL_CLRNCE:
+ /* nop */
+ break;
}
}
#elif defined(CONFIG_IDS852_REV2)
@@ -64,24 +64,24 @@ static void nc650_hwcontrol(struct mtd_info *mtd, int cmd)
struct nand_chip *this = mtd->priv;
switch(cmd) {
- case NAND_CTL_SETCLE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
- break;
- case NAND_CTL_CLRCLE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_SETALE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
- break;
- case NAND_CTL_CLRALE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_SETNCE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
- break;
- case NAND_CTL_CLRNCE:
- *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
- break;
+ case NAND_CTL_SETCLE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0xa) = 0;
+ break;
+ case NAND_CTL_CLRCLE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_SETALE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x9) = 0;
+ break;
+ case NAND_CTL_CLRALE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_SETNCE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0x8) = 0;
+ break;
+ case NAND_CTL_CLRNCE:
+ *(((volatile __u8 *) this->IO_ADDR_W) + 0xc) = 0;
+ break;
}
}
#else
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index c90ac9c..8a6b5b0 100644
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -265,8 +265,8 @@ int misc_init_r(void)
int iCompatMode = 0;
char *pParam = NULL;
char *envlb;
-
- /*
+
+ /*
First byte in CPLD read address space signals compatibility mode
0 - cp850
1 - kp852
@@ -274,9 +274,9 @@ int misc_init_r(void)
pParam = (char*)(CFG_CPLD_BASE);
if( *pParam != 0)
iCompatMode = 1;
-
+
if ( iCompatMode != 0) {
- /*
+ /*
In KP852 compatibility mode we have to write to
DPRAM as early as possible the binary coded
line config and board name.
@@ -288,7 +288,7 @@ int misc_init_r(void)
setenv( DPRAM_VARNAME, DEFAULT_LB);
envlb = DEFAULT_LB;
}
-
+
/* Status string */
printf("Mode: KP852(LB=%s)\n", envlb);
@@ -305,7 +305,7 @@ int misc_init_r(void)
} else {
puts("Mode: CP850\n");
}
-
+
return 0;
}
#endif
diff --git a/board/r5200/Makefile b/board/r5200/Makefile
new file mode 100644
index 0000000..d0364ed
--- /dev/null
+++ b/board/r5200/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/r5200/config.mk b/board/r5200/config.mk
new file mode 100644
index 0000000..8fc5319
--- /dev/null
+++ b/board/r5200/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x10000000
diff --git a/board/r5200/r5200.c b/board/r5200/r5200.c
new file mode 100644
index 0000000..e51ad25
--- /dev/null
+++ b/board/r5200/r5200.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5271.h>
+#include <asm/immap_5271.h>
+
+
+int checkboard (void) {
+ puts ("Board: R5200 Ethernet Module\n");
+ return 0;
+};
+
+long int initdram (int board_type) {
+ int i;
+
+ /*
+ * Set CS2 pin to be SD_CS0
+ */
+ mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
+ | MCF_GPIO_PAR_CS_PAR_CS2);
+
+ mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
+ | MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
+
+ /*
+ * Check to see if the SDRAM has already been initialized
+ * by a run control tool
+ */
+ if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE))
+ {
+ /*
+ * Initialize DRAM Control Register: DCR
+ */
+ mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
+ | MCF_SDRAMC_DCR_RC(0x30));
+
+ /*
+ * Initialize DACR0
+ */
+ mbar_writeLong(MCF_SDRAMC_DACR0,
+ MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+ | MCF_SDRAMC_DACRn_CASL(0)
+ | MCF_SDRAMC_DACRn_CBM(3)
+ | MCF_SDRAMC_DACRn_PS(2));
+
+ /*
+ * Initialize DMR0
+ */
+ mbar_writeLong(MCF_SDRAMC_DMR0,
+ MCF_SDRAMC_DMRn_BAM_8M
+ | MCF_SDRAMC_DMRn_V);
+
+ /*
+ * Set IP bit in DACR
+ */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_IP);
+
+ /*
+ * Wait at least 20ns to allow banks to precharge
+ */
+ for (i = 0; i < 5; i++)
+ asm(" nop");
+
+ /*
+ * Write to this block to initiate precharge
+ */
+ *(u16 *)(CFG_SDRAM_BASE) = 0x9696;
+
+ /*
+ * Set RE bit in DACR
+ */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_RE);
+
+
+ /*
+ * Wait for at least 8 auto refresh cycles to occur
+ */
+ for (i = 0; i < 2000; i++)
+ asm(" nop");
+
+ /*
+ * Finish the configuration by issuing the MRS.
+ */
+ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
+ | MCF_SDRAMC_DACRn_MRS);
+
+
+ /*
+ * Write to the SDRAM Mode Register
+ */
+ *(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
+ }
+
+ return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void) {
+ /* TODO: XXX XXX XXX */
+ printf ("DRAM test not implemented!\n");
+
+ return (0);
+}
diff --git a/board/mpc8349ads/u-boot.lds b/board/r5200/u-boot.lds
index 020cfa6..f7dc070 100644
--- a/board/mpc8349ads/u-boot.lds
+++ b/board/r5200/u-boot.lds
@@ -1,5 +1,6 @@
/*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -20,7 +21,10 @@
* MA 02111-1307 USA
*/
-OUTPUT_ARCH(powerpc)
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -49,34 +53,50 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
- cpu/mpc83xx/start.o (.text)
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mcf52x2/start.o (.text)
+ lib_m68k/traps.o (.text)
+ cpu/mcf52x2/interrupts.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/zlib.o (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o (.text)
+
*(.text)
*(.fixup)
*(.got1)
- . = ALIGN(16);
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
*(.rodata)
*(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
+ . = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
+
.reloc :
{
+ __got_start = .;
*(.got)
+ __got_end = .;
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
@@ -101,22 +121,24 @@ SECTIONS
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
- . = ALIGN(4096);
+ . = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
- . = ALIGN(4096);
+ . = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
+ _sbss = .;
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
}
_end = . ;
PROVIDE (end = .);
}
-ENTRY(_start)
diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile
index 999647f..f3ad674 100644
--- a/board/zylonite/Makefile
+++ b/board/zylonite/Makefile
@@ -1,4 +1,3 @@
-
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,12 +20,11 @@
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
-
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS := zylonite.o flash.o
+OBJS := zylonite.o nand.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk
index 09b0f71..b5d5955 100644
--- a/board/zylonite/config.mk
+++ b/board/zylonite/config.mk
@@ -2,3 +2,5 @@
#TEXT_BASE = 0xa1700000
#TEXT_BASE = 0xa3080000
TEXT_BASE = 0xa3008000
+
+BOARDLIBS = drivers/nand/libnand.a
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
index c3bb4eb..da01765 100644
--- a/board/zylonite/lowlevel_init.S
+++ b/board/zylonite/lowlevel_init.S
@@ -235,6 +235,7 @@ mem_init:
orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
str r1, [r0]
+#ifndef CFG_SKIP_DRAM_SCRUB
/* scrub/init SDRAM if enabled/present */
/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
@@ -254,6 +255,7 @@ mem_init:
stmia r8!, {r0-r7}
beq 15f
b 10b
+#endif /* CFG_SKIP_DRAM_SCRUB */
15:
/* Mask all interrupts */
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
new file mode 100644
index 0000000..5d2cd65
--- /dev/null
+++ b/board/zylonite/nand.c
@@ -0,0 +1,584 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y) ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+ .eccbytes = 6,
+ .eccpos = {2, 3, 4, 5, 6, 7},
+ .oobfree = { {8, 2}, {12, 4} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+ if(NDSR & NDSR_RDY)
+ return 1;
+ else
+ return 0;
+ return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+ int i;
+
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ NDDB = *long_buf;
+ }
+ }
+ if(rest) {
+ printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+ }
+ return;
+}
+
+
+/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+ printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+ int i=0, j;
+
+ /* we have to be carefull not to overflow the buffer if len is
+ * not a multiple of 4 */
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+
+ DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+ /* if there are any, first copy multiple of 4 bytes */
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ *long_buf = NDDB;
+ }
+ }
+
+ /* ...then the rest */
+ if(rest) {
+ unsigned long rest_data = NDDB;
+ for(j=0;j<rest; j++)
+ buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+ }
+
+ return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+ printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+ unsigned char byte;
+ unsigned long dummy;
+
+ if(bytes_read < 0) {
+ read_buf = NDDB;
+ dummy = NDDB;
+ bytes_read = 0;
+ }
+ byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+ if(bytes_read >= 4)
+ bytes_read = -1;
+
+ DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+ return byte;
+}
+
+/* calculate delta between OSCR values start and now */
+static unsigned long get_delta(unsigned long start)
+{
+ unsigned long cur = OSCR;
+
+ if(cur < start) /* OSCR overflowed */
+ return (cur + (start^0xffffffff));
+ else
+ return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+ unsigned long start = OSCR;
+ us *= OSCR_CLK_FREQ;
+
+ while (get_delta(start) < us) {
+ /* do nothing */
+ }
+}
+
+static void dfc_clear_nddb(void)
+{
+ NDCR &= ~NDCR_ND_RUN;
+ wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+ unsigned long ndsr, timeout, start = OSCR;
+
+ if(!event)
+ return 0xff000000;
+ else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+ timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ else
+ timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+
+ while(1) {
+ ndsr = NDSR;
+ if(ndsr & event) {
+ NDSR |= event;
+ break;
+ }
+ if(get_delta(start) > timeout) {
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ return 0xff000000;
+ }
+
+ }
+ return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd(void)
+{
+ int retry = 0;
+ unsigned long status;
+
+ while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ /* Clear NDSR */
+ NDSR = 0xFFF;
+
+ /* set NDCR[NDRUN] */
+ if(!(NDCR & NDCR_ND_RUN))
+ NDCR |= NDCR_ND_RUN;
+
+ status = dfc_wait_event(NDSR_WRCMDREQ);
+
+ if(status & NDSR_WRCMDREQ)
+ return;
+
+ DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+ dfc_clear_nddb();
+ }
+ DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+ unsigned long ndsr=0, event=0;
+
+ if(state == FL_WRITING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ } else if(state == FL_ERASING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ }
+
+ ndsr = dfc_wait_event(event);
+
+ if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+ return(0x1); /* Status Read error */
+ return 0;
+}
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ /* register struct nand_chip *this = mtd->priv; */
+ unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+ /* clear the ugly byte read buffer */
+ bytes_read = -1;
+ read_buf = 0;
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (NAND_CMD_READ0 | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_READ1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+ goto end;
+ case NAND_CMD_READOOB:
+ DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+ goto end;
+ case NAND_CMD_READID:
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+ ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_PAGEPROG:
+ /* sent as a multicommand in NAND_CMD_SEQIN */
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_ERASE1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+ ndcb1 = (page_addr & 0x00ffffff);
+ goto write_cmd;
+ case NAND_CMD_ERASE2:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_SEQIN:
+ /* send PAGE_PROG command(0x1080) */
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_WRDREQ;
+ goto write_cmd;
+ case NAND_CMD_STATUS:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+ dfc_new_cmd();
+ ndcb0 = NAND_CMD_STATUS | (4<<21);
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_RESET:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+ ndcb0 = NAND_CMD_RESET | (5<<21);
+ event = NDSR_CS0_CMDD;
+ goto write_cmd;
+ default:
+ printk("dfc_cmdfunc: error, unsupported command.\n");
+ goto end;
+ }
+
+ write_cmd:
+ NDCB0 = ndcb0;
+ NDCB0 = ndcb1;
+ NDCB0 = ndcb2;
+
+ /* wait_event: */
+ dfc_wait_event(event);
+ end:
+ return;
+}
+
+static void dfc_gpio_init(void)
+{
+ DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see zylonite.c */
+ GPIO4 = 0x1;
+
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+ /* set up GPIO Control Registers */
+ dfc_gpio_init();
+
+ /* turn on the NAND Controller Clock (104 MHz @ D0) */
+ CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
+#ifndef CFG_TIMING_TIGHT
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+ DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+ /* tRP value is split in the register */
+ if(tRP & (1 << 4)) {
+ tRP_high = 1;
+ tRP &= ~(1 << 4);
+ } else {
+ tRP_high = 0;
+ }
+
+ NDTR0CS0 = (tCH << 19) |
+ (tCS << 16) |
+ (tWH << 11) |
+ (tWP << 8) |
+ (tRP_high << 6) |
+ (tRH << 3) |
+ (tRP << 0);
+
+ NDTR1CS0 = (tR << 16) |
+ (tWHR << 4) |
+ (tAR << 0);
+
+ /* If it doesn't work (unlikely) think about:
+ * - ecc enable
+ * - chip select don't care
+ * - read id byte count
+ *
+ * Intentionally enabled by not setting bits:
+ * - dma (DMA_EN)
+ * - page size = 512
+ * - cs don't care, see if we can enable later!
+ * - row address start position (after second cycle)
+ * - pages per block = 32
+ * - ND_RDY : clears command buffer
+ */
+ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
+
+ NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ NDCR_DWIDTH_C | /* 16bit DFC data bus width */
+ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
+ (2 << 16) | /* read id count = 7 ???? mk@tbd */
+ NDCR_ND_ARB_EN | /* enable bus arbiter */
+ NDCR_RDYM | /* flash device ready ir masked */
+ NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
+ NDCR_CS1_PAGEDM |
+ NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
+ NDCR_CS1_CMDDM |
+ NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
+ NDCR_CS1_BBDM |
+ NDCR_DBERRM | /* double bit error ir masked */
+ NDCR_SBERRM | /* single bit error ir masked */
+ NDCR_WRDREQM | /* write data request ir masked */
+ NDCR_RDDREQM | /* read data request ir masked */
+ NDCR_WRCMDREQM); /* write command request ir masked */
+
+
+ /* wait 10 us due to cmd buffer clear reset */
+ /* wait(10); */
+
+
+ nand->hwcontrol = dfc_hwcontrol;
+/* nand->dev_ready = dfc_device_ready; */
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->options = NAND_BUSWIDTH_16;
+ nand->waitfunc = dfc_wait;
+ nand->read_byte = dfc_read_byte;
+ nand->write_byte = dfc_write_byte;
+ nand->read_word = dfc_read_word;
+ nand->write_word = dfc_write_word;
+ nand->read_buf = dfc_read_buf;
+ nand->write_buf = dfc_write_buf;
+
+ nand->cmdfunc = dfc_cmdfunc;
+ nand->autooob = &delta_oob;
+ nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif
generated by cgit v1.1 at 2024-12-05 02:12:28 +0000