3 files changed, 41 insertions, 1 deletions
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 2eff3b3..7b16f8a 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -104,6 +104,13 @@ int checkboard(void)
 	return  0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+u32 ddr_clktr(u32 default_val) {
+	return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+}
 
 /*************************************************************************
  *  int testdram()
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 7316c34..d08fcf3 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -562,6 +562,40 @@ int checkboard (void)
 	return 0;
 }
 
+/*
+ * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * board specific values.
+ */
+static int ppc440spe_rev_a(void)
+{
+	if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
+		return 1;
+	else
+		return 0;
+}
+
+u32 ddr_wrdtr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_WRDTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
+
+	return default_val;
+}
+
+u32 ddr_clktr(u32 default_val) {
+	/*
+	 * Yucca boards with 440SPe rev. A need a slightly different setup
+	 * for the MCIF0_CLKTR register.
+	 */
+	if (ppc440spe_rev_a())
+		return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
+
+	return default_val;
+}
+
 #if defined(CFG_DRAM_TEST)
 int testdram (void)
 {
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 9a4a8ee..b6863b6 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -54,7 +54,6 @@
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
 #endif
 
-void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);