diff options
Diffstat (limited to 'board')
24 files changed, 725 insertions, 1012 deletions
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index a220ad4..da6cf47 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -170,22 +170,26 @@ static struct pci_controller pci2_hose; static struct pci_controller pcie1_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ - gur->clkocr |= MPC85xx_ATUM_CLKOCR; + setbits_be32(&gur->clkocr, MPC85xx_ATUM_CLKOCR); if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) @@ -199,145 +203,79 @@ pci_init_board(void) } #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); +#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE2, + pci_set_region(&pcie1_hose.regions[0], + CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie1_hose.region_count = 1; +#endif + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ + pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); + pci_info[num].regs); - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI1: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; - struct pci_controller *hose = &pci2_hose; - struct pci_region *r = hose->regions; - if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { - pci_set_region(r++, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, - PCI_REGION_MEM); + SET_STD_PCI_INFO(pci_info[num], 2); + pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs); - pci_set_region(r++, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, - CONFIG_SYS_PCI2_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + puts (" PCI2\n"); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI2: disabled\n"); } -} + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif } diff --git a/board/davinci/da830evm/da830evm.c b/board/davinci/da830evm/da830evm.c index bb8cc3c..7cf6013 100644 --- a/board/davinci/da830evm/da830evm.c +++ b/board/davinci/da830evm/da830evm.c @@ -65,6 +65,11 @@ const struct pinmux_config i2c_pins[] = { { pinmux[9], 2, 4 } }; +/* USB0_DRVVBUS pin muxer settings */ +const struct pinmux_config usb_pins[] = { + { pinmux[9], 1, 1 } +}; + int board_init(void) { #ifndef CONFIG_USE_IRQ @@ -118,6 +123,9 @@ int board_init(void) if (davinci_configure_pin_mux(i2c_pins, ARRAY_SIZE(i2c_pins)) != 0) return 1; + if (davinci_configure_pin_mux(usb_pins, ARRAY_SIZE(usb_pins)) != 0) + return 1; + /* enable the console UART */ writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | DAVINCI_UART_PWREMU_MGMT_UTRST), diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c index d15203c..94fd32a 100644 --- a/board/esd/vme8349/pci.c +++ b/board/esd/vme8349/pci.c @@ -2,6 +2,9 @@ * pci.c -- esd VME8349 PCI board support. * Copyright (c) 2006 Wind River Systems, Inc. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> * * Based on MPC8349 PCI support but w/o PIB related code. * @@ -32,6 +35,7 @@ #include <pci.h> #include <i2c.h> #include <asm/fsl_i2c.h> +#include "vme8349pin.h" DECLARE_GLOBAL_DATA_PTR; @@ -93,17 +97,22 @@ pci_init_board(void) udelay(2000); /* - * Assert/deassert PCI reset + * Assert/deassert VME reset */ - setbits_be32(&immr->gpio[0].dat, 0x00800000); - setbits_be32(&immr->gpio[0].dir, 0x00800000); - setbits_be32(&immr->gpio[1].dir, 0x08800000); + clrsetbits_be32(&immr->gpio[1].dat, + GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N, + GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N); + setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N | + GPIO2_TSI_POWERUP_RESET_N | + GPIO2_VME_RESET_N | + GPIO2_L_RESET_EN_N); + clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08000000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N); udelay(200); - setbits_be32(&immr->gpio[1].dat, 0x08800000); + setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N); udelay(600000); - clrbits_be32(&immr->gpio[1].dat, 0x00100000); + clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N); /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; @@ -114,6 +123,14 @@ pci_init_board(void) udelay(2000); - if (monarch == 0) + if (monarch == 0) { mpc83xx_pci_init(1, reg, 0); + } else { + /* + * Release PCI RST Output signal + */ + out_be32(&immr->pci_ctrl[0].gcr, 0); + udelay(2000); + out_be32(&immr->pci_ctrl[0].gcr, 1); + } } diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index e3bc151..b0ebad7 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,63 +38,13 @@ #endif #include <asm/io.h> #include <asm/mmu.h> +#include <spd.h> +#include <spd_sdram.h> +#include <i2c.h> +#include <netdev.h> void ddr_enable_ecc(unsigned int dram_size); -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CONFIG_SYS_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size>>1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - -#if (CONFIG_SYS_DDR_SIZE == 512) - im->ddr.csbnds[0].csbnds = 0x0000001f; -#else -#warning Currently any DDR size other than 512MiB is not supported -#endif - im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000; - - /* currently we use only one CS, so disable the other banks */ - im->ddr.csbnds[1].csbnds = 0x00000000; - im->ddr.csbnds[2].csbnds = 0x00000000; - im->ddr.csbnds[3].csbnds = 0x00000000; - im->ddr.cs_config[1] = 0; - im->ddr.cs_config[2] = 0; - im->ddr.cs_config[3] = 0; - - im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - - im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - - im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - sync(); - udelay(200); - - /* enable DDR controller */ - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return msize; -} - phys_size_t initdram(int board_type) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -103,10 +53,10 @@ phys_size_t initdram(int board_type) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; - /* DDR SDRAM - Main SODIMM */ + /* DDR SDRAM - Main memory */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); + msize = spd_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* @@ -124,17 +74,148 @@ phys_size_t initdram(int board_type) int checkboard(void) { - puts("Board: esd VME8349\n"); +#ifdef VME_CADDY2 + puts("Board: esd VME-CADDY/2\n"); +#else + puts("Board: esd VME-CPU/8349\n"); +#endif return 0; } +#ifdef VME_CADDY2 +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + #ifdef CONFIG_PCI ft_pci_setup(blob, bd); #endif } #endif + +int misc_init_r() +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); + + return 0; +} + +/* + * Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 + * and VME-CADDY/2) have different SDRAM configurations. + */ +#ifdef VME_CADDY2 +#define SMALL_RAM 0xff +#define LARGE_RAM 0x00 +#else +#define SMALL_RAM 0x00 +#define LARGE_RAM 0xff +#endif + +#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) + +static spd_eeprom_t default_spd_eeprom = { + SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ + SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ + SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ + SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ + SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ + SPD_VAL(0x00, 0x00), /* 05 */ + SPD_VAL(0x40, 0x40), /* 06 */ + SPD_VAL(0x00, 0x00), /* 07 */ + SPD_VAL(0x05, 0x05), /* 08 */ + SPD_VAL(0x30, 0x30), /* 09 */ + SPD_VAL(0x45, 0x45), /* 10 */ + SPD_VAL(0x02, 0x02), /* 11 ecc used */ + SPD_VAL(0x82, 0x82), /* 12 */ + SPD_VAL(0x10, 0x10), /* 13 */ + SPD_VAL(0x08, 0x08), /* 14 */ + SPD_VAL(0x00, 0x00), /* 15 */ + SPD_VAL(0x0c, 0x0c), /* 16 */ + SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ + SPD_VAL(0x38, 0x38), /* 18 */ + SPD_VAL(0x00, 0x00), /* 19 */ + SPD_VAL(0x02, 0x02), /* 20 */ + SPD_VAL(0x00, 0x00), /* 21 */ + SPD_VAL(0x03, 0x03), /* 22 */ + SPD_VAL(0x3d, 0x3d), /* 23 */ + SPD_VAL(0x45, 0x45), /* 24 */ + SPD_VAL(0x50, 0x50), /* 25 */ + SPD_VAL(0x45, 0x45), /* 26 */ + SPD_VAL(0x3c, 0x3c), /* 27 */ + SPD_VAL(0x28, 0x28), /* 28 */ + SPD_VAL(0x3c, 0x3c), /* 29 */ + SPD_VAL(0x2d, 0x2d), /* 30 */ + SPD_VAL(0x20, 0x80), /* 31 */ + SPD_VAL(0x20, 0x20), /* 32 */ + SPD_VAL(0x27, 0x27), /* 33 */ + SPD_VAL(0x10, 0x10), /* 34 */ + SPD_VAL(0x17, 0x17), /* 35 */ + SPD_VAL(0x3c, 0x3c), /* 36 */ + SPD_VAL(0x1e, 0x1e), /* 37 */ + SPD_VAL(0x1e, 0x1e), /* 38 */ + SPD_VAL(0x00, 0x00), /* 39 */ + SPD_VAL(0x00, 0x06), /* 40 */ + SPD_VAL(0x37, 0x37), /* 41 */ + SPD_VAL(0x4b, 0x7f), /* 42 */ + SPD_VAL(0x80, 0x80), /* 43 */ + SPD_VAL(0x18, 0x18), /* 44 */ + SPD_VAL(0x22, 0x22), /* 45 */ + SPD_VAL(0x00, 0x00), /* 46 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + SPD_VAL(0x10, 0x10), /* 62 */ + SPD_VAL(0x7e, 0x1d), /* 63 */ + { 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, + SPD_VAL(0x00, 0x00), /* 72 */ +#ifdef VME_CADDY2 + { "vme-caddy/2 ram " } +#else + { "vme-cpu/2 ram " } +#endif +}; + +int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int old_bus = I2C_GET_BUS(); + unsigned int l, sum; + int valid = 0; + + I2C_SET_BUS(0); + + if (i2c_read(chip, addr, alen, buffer, len) == 0) + if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum == buffer[63]) + valid = 1; + else + printf("Invalid checksum in EEPROM %02x %02x\n", + sum, buffer[63]); + } + + if (valid == 0) { + memcpy(buffer, (void *)&default_spd_eeprom, len); + sum = 0; + for (l = 0; l < 63; l++) + sum = (sum + buffer[l]) & 0xff; + if (sum != buffer[63]) + printf("Invalid checksum in FLASH %02x %02x\n", + sum, buffer[63]); + buffer[63] = sum; + } + + I2C_SET_BUS(old_bus); + + return 0; +} diff --git a/board/esd/vme8349/vme8349pin.h b/board/esd/vme8349/vme8349pin.h new file mode 100644 index 0000000..d1fd1b2 --- /dev/null +++ b/board/esd/vme8349/vme8349pin.h @@ -0,0 +1,36 @@ +/* + * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition. + * Copyright (c) 2009 esd gmbh. + * + * Reinhard Arlt <reinhard.arlt@esd-electronics.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __VME8349PIN_H__ +#define __VME8349PIN_H__ + +#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */ +#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */ +#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */ +#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */ +#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/ + +#endif /* of ifndef __VME8349PIN_H__ */ diff --git a/board/freescale/mpc8315erdb/config.mk b/board/freescale/mpc8315erdb/config.mk index f768264..bf972fb 100644 --- a/board/freescale/mpc8315erdb/config.mk +++ b/board/freescale/mpc8315erdb/config.mk @@ -1 +1,9 @@ +ifndef NAND_SPL +ifeq ($(CONFIG_MK_NAND), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +endif +endif + +ifndef TEXT_BASE TEXT_BASE = 0xFE000000 +endif diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index dea4d6f..d5e71dc 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -32,6 +32,8 @@ #include <mpc83xx.h> #include <netdev.h> #include <asm/io.h> +#include <ns16550.h> +#include <nand.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,6 +47,8 @@ int board_early_init_f(void) return 0; } +#ifndef CONFIG_NAND_SPL + static u8 read_board_info(void) { u8 val8; @@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); /* Initialize TSECs first */ return pci_eth_init(bis); } + +#else /* CONFIG_NAND_SPL */ + +int checkboard(void) +{ + puts("Board: Freescale MPC8315ERDB\n"); + return 0; +} + +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); +} + +#endif /* CONFIG_NAND_SPL */ diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index ead7b1e..fe8ec1e 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -54,6 +54,7 @@ static void resume_from_sleep(void) * This is useful for faster booting in configs where the RAM is unlikely * to be changed, or for things like NAND booting where space is tight. */ +#ifndef CONFIG_SYS_RAMBOOT static long fixed_sdram(void) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; @@ -68,7 +69,7 @@ static long fixed_sdram(void) * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], * or the DDR2 controller may fail to initialize correctly. */ - udelay(50000); + __udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; @@ -100,6 +101,12 @@ static long fixed_sdram(void) return msize; } +#else +static long fixed_sdram(void) +{ + return CONFIG_SYS_DDR_SIZE * 1024 * 1024; +} +#endif /* CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) { diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index da72916..f8292cf 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -189,20 +189,26 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +#ifdef CONFIG_PCI +void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint sdrs2_io_sel = - (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\ - host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + + debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", + devdisr, sdrs2_io_sel, io_sel); if (sdrs2_io_sel == 7) printf(" Serdes2 disalbed\n"); @@ -212,233 +218,102 @@ pci_init_board(void) } else if (sdrs2_io_sel == 6) printf(" eTSEC1 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE3 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); + printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); } else { printf (" PCIE3: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE1_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS2, - CONFIG_SYS_PCIE1_MEM_PHYS2, - CONFIG_SYS_PCIE1_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE2_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS2, - CONFIG_SYS_PCIE2_MEM_PHYS2, - CONFIG_SYS_PCIE2_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); } else { printf (" PCIE2: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); - uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = 1; - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCI1_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS2, - CONFIG_SYS_PCI1_MEM_PHYS2, - CONFIG_SYS_PCI1_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; + pci_info[num].regs); - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif } +#endif int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 1; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 244a197..35a8063 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -101,18 +101,23 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) @@ -120,55 +125,29 @@ pci_init_board(void) if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); } + puts("\n"); #ifdef CONFIG_PCIE3 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE3 connected to ULI as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie3_hose.regions[0], CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie3_hose.region_count = 1; +#endif + printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake @@ -178,187 +157,99 @@ pci_init_board(void) } else { printf (" PCIE3: disabled\n"); } - - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie1_hose.regions[0], CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie1_hose.region_count = 1; +#endif + printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ - pci_set_region(r++, + pci_set_region(&pcie2_hose.regions[0], CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + pcie2_hose.region_count = 1; +#endif + printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); } else { printf (" PCIE2: disabled\n"); } - } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif - #ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; - - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); - uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ - uint pci_32 = 1; - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", - (uint)pci - ); + pci_info[num].regs); - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - -#ifdef CONFIG_SYS_PCIE3_MEM_BUS2 - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS2, - CONFIG_SYS_PCIE3_MEM_PHYS2, - CONFIG_SYS_PCIE3_MEM_SIZE2, - PCI_REGION_MEM); -#endif - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif } diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 73e7c21..38cbc8b 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007 Freescale Semiconductor. + * Copyright 2004, 2007, 200 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -262,62 +262,47 @@ static struct pci_controller pci2_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno=0; - -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - - -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + struct fsl_pci_info pci_info[4]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured; - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); + #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { + if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); @@ -330,14 +315,15 @@ pci_init_board(void) } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCI2 { - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", @@ -347,60 +333,29 @@ pci_init_board(void) } } #else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } - } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif - } int last_stage_init(void) diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index e2dc69e..60e22de 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * @@ -311,8 +311,6 @@ static struct pci_controller pci1_hose = { static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno = 0; - /* * pib_init() -- Initialize the PCA9555 IO expander on the PIB board */ @@ -356,117 +354,72 @@ pib_init(void) } #ifdef CONFIG_PCI -void -pci_init_board(void) +void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCI1 -{ - pib_init(); - - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel; + u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; + int first_free_busno = 0; + int num = 0; - uint pci_32 = 1; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + int pcie_ep, pcie_configured; - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = 66666000; + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", +#ifdef CONFIG_PCI1 + pci_speed = 66666000; + pci_32 = 1; + pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); + printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); + pci_arb ? "arbiter" : "external-arbiter", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index cdd7813..56854ca 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -437,6 +437,11 @@ int board_mmc_init(bd_t *bd) console_assign(stdin, "eserial1"); printf("Switched to UART1 (initial log has been printed to " "UART0).\n"); + + clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, + PLPPAR1_ESDHC_4BITS_VAL); + clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, + PLPDIR1_ESDHC_4BITS_VAL); bcsr6 |= BCSR6_SD_CARD_4BITS; } else { printf("should be disabled.\n"); @@ -483,6 +488,15 @@ static void fdt_board_fixup_esdhc(void *blob, bd_t *bd) break; } } + + if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { + off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); + if (off < 0) { + printf("WARNING: could not find esdhc node\n"); + return; + } + fdt_delprop(blob, off, "sdhci,1-bit-only"); + } } #else static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {} @@ -514,77 +528,43 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd) static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno = 0; - #ifdef CONFIG_PCI -void -pci_init_board(void) -{ - volatile ccsr_gur_t *gur; - uint io_sel; - uint host_agent; - - gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - -#ifdef CONFIG_PCIE1 +void pci_init_board(void) { - volatile ccsr_fsl_pci_t *pci; - struct pci_controller *hose; - int pcie_ep; - struct pci_region *r; - int pcie_configured; - - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - r = hose->regions; - pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[1]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; - hose->region_count = r - hose->regions; + int pcie_ep, pcie_configured; - hose->first_busno=first_free_busno; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - first_free_busno=hose->last_busno+1; +#ifdef CONFIG_PCIE1 + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf (" PCIE1: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif + } #endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 933dd12..64e164b 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2008 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -165,7 +165,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, host_agent, temp32; + u32 devdisr, pordevsr, io_sel, temp32; int first_free_busno = 0; int num = 0; @@ -174,10 +174,8 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); @@ -190,11 +188,11 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE3 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -222,11 +220,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -242,11 +240,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -266,7 +264,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index d832f89..6a2a0b5 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index f42c316..2d4b9ad 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -224,158 +224,83 @@ static struct pci_controller pcie1_hose; static struct pci_controller pcie2_hose; #endif -int first_free_busno = 0; - void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) - >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) - >> MPC8610_PORBMSR_HA_SHIFT; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel; + int first_free_busno = 0; + int num = 0; + + int pci_agent, pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC8610_PORDEVSR_IO_SEL) + >> MPC8610_PORDEVSR_IO_SEL_SHIFT; - printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); #ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { - printf(" PCIe 1 connected to Uli as %s (base address %x)\n", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) - pci->pme_msg_det = 0xffffffff; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI-Express 1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - - } else - puts(" PCI-Express 1: Disabled\n"); - } -#else - puts("PCI-Express 1: Disabled\n"); -#endif /* CONFIG_PCIE1 */ + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf (" PCIE1: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE1); /* disable */ +#endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - - if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { - printf(" PCI-Express 2 connected to slot as %s" \ - " (base address %x)\n", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) - pci->pme_msg_det = 0xffffffff; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI-Express 2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - } else - puts(" PCI-Express 2: Disabled\n"); - } -#else - puts("PCI-Express 2: Disabled\n"); -#endif /* CONFIG_PCIE2 */ + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf (" PCIE2: disabled\n"); + } + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCIE2); /* disable */ +#endif #ifdef CONFIG_PCI1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - struct pci_region *r = hose->regions; - - if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { + if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { + SET_STD_PCI_INFO(pci_info[num], 1); + pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf(" PCI connected to PCI slots as %s" \ - " (base address %x)\n", + " (base address %lx)\n", pci_agent ? "Agent" : "Host", - (uint)pci); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BUS, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BUS, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno + 1; - printf(" PCI on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); + } else { + printf (" PCI: disabled\n"); + } - } else - puts(" PCI: Disabled\n"); - } -#endif /* CONFIG_PCI1 */ + puts("\n"); +#else + setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ +#endif } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 4c03468..3af660e 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -131,7 +131,7 @@ int checkboard (void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash region to caching-inhibited diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 4c08f9e..6fd6963 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -43,7 +43,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[2]; - u32 devdisr, pordevsr, io_sel, host_agent; + u32 devdisr, pordevsr, io_sel; int first_free_busno = 0; int num = 0; @@ -52,21 +52,19 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -81,11 +79,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913..93d0bf7 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index e38c014..599caa2 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -197,7 +197,7 @@ void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[3]; - u32 devdisr, pordevsr, io_sel, host_agent; + u32 devdisr, pordevsr, io_sel; int first_free_busno = 0; int num = 0; @@ -206,10 +206,8 @@ void pci_init_board(void) devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", - devdisr, io_sel, host_agent); + debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf(" eTSEC2 is in sgmii mode.\n"); @@ -218,11 +216,11 @@ void pci_init_board(void) puts("\n"); #ifdef CONFIG_PCIE2 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -258,11 +256,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE3 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); + pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -277,11 +275,11 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); @@ -300,7 +298,7 @@ void pci_init_board(void) int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - const u8 flash_esel = 2; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); /* * Remap Boot flash + PROMJET region to caching-inhibited diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index b2e562a..36ad086 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index bc88e5a..35c4e60 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -31,6 +31,7 @@ #include <i2c.h> #include <command.h> #include "ppc440gx_i2c.h" +#include <asm-ppc/io.h> #ifdef CONFIG_I2C_BUS1 @@ -47,16 +48,18 @@ static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; #endif +static struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_REGISTERS_BUS1_BASE_ADDRESS; + static void _i2c_bus1_reset (void) { int i, status; /* Reset status register */ /* write 1 in SCMP and IRQA to clear these fields */ - out8 (IIC_STS1, 0x0A); + out_8 (IIC_STS1, 0x0A); /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ - out8 (IIC_EXTSTS1, 0x8F); + out_8 (IIC_EXTSTS1, 0x8F); __asm__ volatile ("eieio"); /* @@ -66,36 +69,36 @@ static void _i2c_bus1_reset (void) i = 10; do { /* Get status */ - status = in8 (IIC_STS1); + status = in_8 (IIC_STS1); udelay (500); /* 500us */ i--; } while ((status & IIC_STS_PT) && (i > 0)); /* Soft reset controller */ - status = in8 (IIC_XTCNTLSS1); - out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); + status = in_8 (IIC_XTCNTLSS1); + out_8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); __asm__ volatile ("eieio"); /* make sure where in initial state, data hi, clock hi */ - out8 (IIC_DIRECTCNTL1, 0xC); + out_8 (IIC_DIRECTCNTL1, 0xC); for (i = 0; i < 10; i++) { - if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { + if ((in_8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { /* clock until we get to known state */ - out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ + out_8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ udelay (100); /* 100us */ - out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ + out_8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ udelay (100); /* 100us */ } else { break; } } /* send start condition */ - out8 (IIC_DIRECTCNTL1, 0x4); + out_8 (IIC_DIRECTCNTL1, 0x4); udelay (1000); /* 1ms */ /* send stop condition */ - out8 (IIC_DIRECTCNTL1, 0xC); + out_8 (IIC_DIRECTCNTL1, 0xC); udelay (1000); /* 1ms */ /* Unreset controller */ - out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); + out_8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); udelay (1000); /* 1ms */ } @@ -117,16 +120,16 @@ void i2c1_init (int speed, int slaveadd) _i2c_bus1_reset (); /* clear lo master address */ - out8 (IIC_LMADR1, 0); + out_8 (IIC_LMADR1, 0); /* clear hi master address */ - out8 (IIC_HMADR1, 0); + out_8 (IIC_HMADR1, 0); /* clear lo slave address */ - out8 (IIC_LSADR1, 0); + out_8 (IIC_LSADR1, 0); /* clear hi slave address */ - out8 (IIC_HSADR1, 0); + out_8 (IIC_HSADR1, 0); /* Clock divide Register */ /* get OPB frequency */ @@ -136,25 +139,25 @@ void i2c1_init (int speed, int slaveadd) divisor = (freqOPB - 1) / 10000000; if (divisor == 0) divisor = 1; - out8 (IIC_CLKDIV1, divisor); + out_8 (IIC_CLKDIV1, divisor); /* no interrupts */ - out8 (IIC_INTRMSK1, 0); + out_8 (IIC_INTRMSK1, 0); /* clear transfer count */ - out8 (IIC_XFRCNT1, 0); + out_8 (IIC_XFRCNT1, 0); /* clear extended control & stat */ /* write 1 in SRC SRS SWC SWS to clear these fields */ - out8 (IIC_XTCNTLSS1, 0xF0); + out_8 (IIC_XTCNTLSS1, 0xF0); /* Mode Control Register Flush Slave/Master data buffer */ - out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + out_8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); __asm__ volatile ("eieio"); - val = in8(IIC_MDCNTL1); + val = in_8(IIC_MDCNTL1); __asm__ volatile ("eieio"); /* Ignore General Call, slave transfers are ignored, @@ -167,10 +170,10 @@ void i2c1_init (int speed, int slaveadd) if( speed >= 400000 ){ val |= IIC_MDCNTL_FSM; } - out8 (IIC_MDCNTL1, val); + out_8 (IIC_MDCNTL1, val); /* clear control reg */ - out8 (IIC_CNTL1, 0x00); + out_8 (IIC_CNTL1, 0x00); __asm__ volatile ("eieio"); } @@ -178,7 +181,7 @@ void i2c1_init (int speed, int slaveadd) /* This code tries to use the features of the 405GP i2c controller. It will transfer up to 4 bytes in one pass - on the loop. It only does out8(lbz) to the buffer when it + on the loop. It only does out_8(lbz) to the buffer when it is possible to do out16(lhz) transfers. cmd_type is 0 for write 1 for read. @@ -232,12 +235,12 @@ int i2c_transfer1(unsigned char cmd_type, } /*Clear Stop Complete Bit*/ - out8(IIC_STS1,IIC_STS_SCMP); + out_8(IIC_STS1,IIC_STS_SCMP); /* Check init */ i=10; do { /* Get status */ - status = in8(IIC_STS1); + status = in_8(IIC_STS1); __asm__ volatile("eieio"); i--; } while ((status & IIC_STS_PT) && (i>0)); @@ -247,12 +250,12 @@ int i2c_transfer1(unsigned char cmd_type, return(result); } /*flush the Master/Slave Databuffers*/ - out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + out_8(IIC_MDCNTL1, ((in_8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); /*need to wait 4 OPB clocks? code below should take that long*/ /* 7-bit adressing */ - out8(IIC_HMADR1,0); - out8(IIC_LMADR1, chip); + out_8(IIC_HMADR1,0); + out_8(IIC_LMADR1, chip); __asm__ volatile("eieio"); tran = 0; @@ -280,11 +283,11 @@ int i2c_transfer1(unsigned char cmd_type, else { for(j=0; j<bc; j++) { /* Set buffer */ - out8(IIC_MDBUF1,ptr[tran+j]); + out_8(IIC_MDBUF1,ptr[tran+j]); __asm__ volatile("eieio"); } } - out8(IIC_CNTL1, creg ); + out_8(IIC_CNTL1, creg ); __asm__ volatile("eieio"); /* Transfer is in progress @@ -297,7 +300,7 @@ int i2c_transfer1(unsigned char cmd_type, i=2*5*8; do { /* Get status */ - status = in8(IIC_STS1); + status = in_8(IIC_STS1); __asm__ volatile("eieio"); udelay (10); i--; @@ -306,7 +309,7 @@ int i2c_transfer1(unsigned char cmd_type, if (status & IIC_STS_ERR) { result = IIC_NOK; - status = in8 (IIC_EXTSTS1); + status = in_8 (IIC_EXTSTS1); /* Lost arbitration? */ if (status & IIC_EXTSTS_LA) result = IIC_NOK_LA; @@ -331,7 +334,7 @@ int i2c_transfer1(unsigned char cmd_type, */ udelay (1); for(j=0;j<bc;j++) { - ptr[tran+j] = in8(IIC_MDBUF1); + ptr[tran+j] = in_8(IIC_MDBUF1); __asm__ volatile("eieio"); } } else diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 90f27ca..0676c0e 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -34,21 +34,21 @@ #define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) #define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR -#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) -#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) -#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR) -#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR) -#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL) -#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL) -#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS) -#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) -#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) -#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV) -#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) -#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) -#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) -#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL) +#define IIC_MDBUF1 (&i2c->mdbuf) +#define IIC_SDBUF1 (&i2c->sdbuf) +#define IIC_LMADR1 (&i2c->lmadr) +#define IIC_HMADR1 (&i2c->hmadr) +#define IIC_CNTL1 (&i2c->cntl) +#define IIC_MDCNTL1 (&i2c->mdcntl) +#define IIC_STS1 (&i2c->sts) +#define IIC_EXTSTS1 (&i2c->extsts) +#define IIC_LSADR1 (&i2c->lsadr) +#define IIC_HSADR1 (&i2c->hsadr) +#define IIC_CLKDIV1 (&i2c->clkdiv) +#define IIC_INTRMSK1 (&i2c->intrmsk) +#define IIC_XFRCNT1 (&i2c->xfrcnt) +#define IIC_XTCNTLSS1 (&i2c->xtcntlss) +#define IIC_DIRECTCNTL1 (&i2c->directcntl) void i2c1_init (int speed, int slaveadd); int i2c_probe1 (uchar chip); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 3931ec5..aa7827e 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -549,7 +549,6 @@ static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCI1 - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; @@ -561,7 +560,7 @@ static inline void init_pci1(void) /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); + int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ @@ -626,14 +625,15 @@ static inline void init_pcie1(void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_ep; struct pci_region *r = hose->regions; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR); + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", pcie_ep ? "End point" : "Root complex", (uint)pci); |