diff options
Diffstat (limited to 'board')
90 files changed, 3437 insertions, 1435 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 00c793a..c4eace5 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0x00, /* Module data width continued: +0 */ 0x04, /* 2.5 Volt */ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + 0x00, /* SDRAM Access from clock */ #ifdef CONFIG_DDR_ECC 0x02, /* ECC ON : 02 OFF : 00 */ #else 0x00, /* ECC ON : 02 OFF : 00 */ #endif - 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ - 0, + 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ 0, 0, 0x01, /* wcsbc = 1 */ diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds index be03092..b08c999 100644 --- a/board/amcc/bubinga/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index 5a1c5b1..e32b030 100644 --- a/board/amcc/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ebony/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a49066f..25c9a22 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -24,21 +24,16 @@ #include <common.h> #include <ppc4xx.h> -#include <asm/processor.h> #include <i2c.h> -#include <asm-ppc/io.h> -#include <asm-ppc/gpio.h> - -#include "../cpu/ppc4xx/440spe_pcie.h" - -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/4xx_pcie.h> DECLARE_GLOBAL_DATA_PTR; -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - int board_early_init_f (void) { unsigned long mfr; @@ -224,10 +219,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ -/* SDR0_MFR should be part of Ethernet init */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); mtsdr(SDR0_PFC0, CFG_PFC0); @@ -396,6 +390,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -409,12 +404,13 @@ void pcie_setup_hoses(int busno) if (!katmai_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - if (ppc440spe_init_pcie_endport(i)) { -#else - if (ppc440spe_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } @@ -428,35 +424,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc440spe_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif } } #endif /* defined(CONFIG_PCI) */ @@ -541,3 +535,24 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile new file mode 100644 index 0000000..b8da25f --- /dev/null +++ b/board/amcc/kilauea/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o cmd_pll.o memory.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c new file mode 100644 index 0000000..b2666dd --- /dev/null +++ b/board/amcc/kilauea/cmd_pll.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * ehnus: change pll frequency. + * Wed Sep 5 11:45:17 CST 2007 + * hsun@udtech.com.cn + */ + + +#include <common.h> +#include <config.h> +#include <command.h> +#include <i2c.h> + +#ifdef CONFIG_CMD_EEPROM + +#define EEPROM_CONF_OFFSET 0 +#define EEPROM_TEST_OFFSET 16 +#define EEPROM_SDSTP_PARAM 16 + +#define PLL_NAME_MAX 12 +#define BUF_STEP 8 + +/* eeprom_wirtes 8Byte per op. */ +#define EEPROM_ALTER_FREQ(freq) \ + do { \ + int __i; \ + for (__i = 0; __i < 2; __i++) \ + eeprom_write (CFG_I2C_EEPROM_ADDR, \ + EEPROM_CONF_OFFSET + __i*BUF_STEP, \ + pll_select[freq], \ + BUF_STEP + __i*BUF_STEP); \ + } while (0) + +#define PDEBUG +#ifdef PDEBUG +#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) +#else +#define PLL_DEBUG +#endif + +typedef enum { + PLL_ebc20, + PLL_333, + PLL_4001, + PLL_4002, + PLL_533, + PLL_600, + PLL_666, /* For now, kilauea can't support */ + RCONF, + WTEST, + PLL_TOTAL +} pll_freq_t; + +static const char +pll_name[][PLL_NAME_MAX] = { + "PLL_ebc20", + "PLL_333", + "PLL_400@1", + "PLL_400@2", + "PLL_533", + "PLL_600", + "PLL_666", + "RCONF", + "WTEST", + "" +}; + +/* + * ehnus: + */ +static uchar +pll_select[][EEPROM_SDSTP_PARAM] = { + /* 0: CPU 333MHz EBC 20MHz, for test only */ + { + 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 0: 333 */ + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 1: 400_266 */ + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 2: 400 */ + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 3: 533 */ + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 4: 600 */ + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 5: 666 */ + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + {} +}; + +static uchar +testbuf[EEPROM_SDSTP_PARAM] = { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff +}; + +static void +pll_debug(int off) +{ + int i; + uchar buffer[EEPROM_SDSTP_PARAM]; + + memset(buffer, 0, sizeof(buffer)); + eeprom_read(CFG_I2C_EEPROM_ADDR, off, + buffer, EEPROM_SDSTP_PARAM); + + printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); + for (i = 0; i < EEPROM_SDSTP_PARAM; i++) + printf("%02x ", buffer[i]); + printf("\n"); +} + +static void +test_write(void) +{ + printf("Debug: test eeprom_write ... "); + + /* + * Write twice, 8 bytes per write + */ + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + testbuf, 8); + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + testbuf, 16); + printf("done\n"); + + pll_debug(EEPROM_TEST_OFFSET); +} + +int +do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char c = '\0'; + pll_freq_t pll_freq; + if (argc < 2) { + printf("Usage: \n%s\n", cmdtp->usage); + goto ret; + } + + for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) + if (!strcmp(pll_name[pll_freq], argv[1])) + break; + + switch (pll_freq) { + case PLL_ebc20: + case PLL_333: + case PLL_4001: + case PLL_4002: + case PLL_533: + case PLL_600: + EEPROM_ALTER_FREQ(pll_freq); + break; + + case PLL_666: /* not support */ + printf("Choose this option will result in a boot failure." + "\nContinue? (Y/N): "); + + c = getc(); putc('\n'); + + if ((c == 'y') || (c == 'Y')) { + EEPROM_ALTER_FREQ(pll_freq); + break; + } + goto ret; + + case RCONF: + pll_debug(EEPROM_CONF_OFFSET); + goto ret; + case WTEST: + printf("DEBUG: write test\n"); + test_write(); + goto ret; + + default: + printf("Invalid options" + "\n\nUsage: \n%s\n", cmdtp->usage); + goto ret; + } + + printf("PLL set to %s, " + "reset the board to take effect\n", pll_name[pll_freq]); + + PLL_DEBUG; +ret: + return 0; +} + +U_BOOT_CMD( + pllalter, CFG_MAXARGS, 1, do_pll_alter, + "pllalter- change pll frequence \n", + "pllalter <selection> - change pll frequence \n\n\ + ** New freq take effect after reset. ** \n\ + ----------------------------------------------\n\ + PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ + \t Same as PLL_333 \n\ + \t except \n\ + \t EBC: 20 MHz \n\ + ----------------------------------------------\n\ + PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 666 MHz \n\ + \t CPU: 333 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 83 MHz \n\ + ------------------------------------------------\n\ + PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 133 MHz \n\ + \t OPB: 66 MHz \n\ + \t DDR: 133 MHz \n\ + ------------------------------------------------\n\ + PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1066 MHz \n\ + \t CPU: 533 MHz \n\ + \t PLB: 177 MHz \n\ + \t OPB: 88 MHz \n\ + \t DDR: 177 MHz \n\ + ----------------------------------------------\n\ + PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1200 MHz \n\ + \t CPU: 600 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1333 MHz \n\ + \t CPU: 666 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 166 MHz \n\ + -----------------------------------------------\n\ + RCONF: Read current eeprom configuration. \n\ + -----------------------------------------------\n\ + WTEST: Test EEPROM write with predefined values\n\ + -----------------------------------------------\n" + ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ diff --git a/board/amcc/kilauea/config.mk b/board/amcc/kilauea/config.mk new file mode 100644 index 0000000..f5800eb --- /dev/null +++ b/board/amcc/kilauea/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S new file mode 100644 index 0000000..4338744 --- /dev/null +++ b/board/amcc/kilauea/init.S @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on code provided from UDTech and AMCC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <ppc4xx.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#define mtsdram_as(reg, value) \ + addi r4,0,reg ; \ + mtdcr memcfga,r4 ; \ + addis r4,0,value@h ; \ + ori r4,r4,value@l ; \ + mtdcr memcfgd,r4 ; + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + + /* + * DDR2 setup + */ + + /* Following the DDR Core Manual, here is the initialization */ + + /* Step 1 */ + + /* Step 2 */ + + /* Step 3 */ + + /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */ + mtsdram_as(SDRAM_MB0CF, 0x00006701); + + /* SET SDRAM_MB1CF - Not enabled */ + mtsdram_as(SDRAM_MB1CF, 0x00000000); + + /* SET SDRAM_MB2CF - Not enabled */ + mtsdram_as(SDRAM_MB2CF, 0x00000000); + + /* SET SDRAM_MB3CF - Not enabled */ + mtsdram_as(SDRAM_MB3CF, 0x00000000); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram_as(SDRAM_CLKTR, 0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram_as(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram_as(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram_as(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram_as(SDRAM_MMODE, 0x00000442); + mtsdram_as(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram_as(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram_as(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram_as(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram_as(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram_as(SDRAM_INITPLR11, 0x81000442); + mtsdram_as(SDRAM_INITPLR12, 0x81010780); + mtsdram_as(SDRAM_INITPLR13, 0x81010400); + mtsdram_as(SDRAM_INITPLR14, 0x00000000); + mtsdram_as(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram_as(SDRAM_CODT, 0x0080f837); + mtsdram_as(SDRAM_MODT0, 0x01800000); + mtsdram_as(SDRAM_MODT1, 0x00000000); + + mtsdram_as(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram_as(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + lis r3,0x1 /* 400000 = wait 100ms */ + mtctr r3 + +pll_wait: + bdnz pll_wait + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram_as(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram_as(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram_as(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram_as(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mtsdram_as(SDRAM_MCOPT2, 0x28000000); +#endif /* #ifndef CONFIG_NAND_U_BOOT */ + + blr diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c new file mode 100644 index 0000000..2ee896a --- /dev/null +++ b/board/amcc/kilauea/kilauea.c @@ -0,0 +1,392 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc405.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> + +#if defined(CONFIG_PCI) +#include <pci.h> +#include <asm/4xx_pcie.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Board early initialization function + */ +int board_early_init_f (void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts */ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic1er, 0x00000000); /* disable all interrupts */ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ + + /* Configure 405EX for NAND usage */ + val = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NRB_BUSY | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, val); + + /* + * Configure PFC (Pin Function Control) registers + * -> Enable USB + */ + val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int misc_init_r(void) +{ +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +int board_emac_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + +static int board_pcie_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + u32 pvr = get_pvr(); + + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); + else + printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller * hose ) +{ + return 0; +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_PCI +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + bus = busno; + char *env; + unsigned int delay; + + for (i = 0; i < board_pcie_count(); i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c new file mode 100644 index 0000000..1d7a3fa --- /dev/null +++ b/board/amcc/kilauea/memory.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <i2c.h> + +void sdram_init(void) +{ + return; +} + +long int initdram(int board_type) +{ + return (CFG_MBYTES_SDRAM << 20); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + printf ("testdram\n"); +#if defined (CONFIG_NAND_U_BOOT) + return 0; +#endif + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x00001000; + uint *p; + + for (p = pstart; p < pend; p++) { + *p = 0xaaaaaaaa; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } + + for (p = pstart; p < pend; p++) { + *p = 0x55555555; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test passed!!!\n"); +#endif + return 0; +} +#endif diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/kilauea/u-boot-nand.lds index 474f922..a5dae0e 100644 --- a/board/amcc/yucca/u-boot.lds.debug +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002-2004 + * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -23,8 +23,6 @@ OUTPUT_ARCH(powerpc) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ @@ -33,43 +31,36 @@ SECTIONS .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } .plt : { *(.plt) } .text : { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) - board/amcc/yucca/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + cpu/ppc4xx/start.o (.text) -/* common/environment.o(.text) */ + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); *(.text) *(.fixup) @@ -82,14 +73,13 @@ SECTIONS *(.rodata) *(.rodata1) *(.rodata.str1.4) - *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; + . = (. + 0x00FF) & 0xFFFFFF00; _erotext = .; PROVIDE (erotext = .); .reloc : @@ -141,6 +131,7 @@ SECTIONS *(.bss) *(COMMON) } + _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/kilauea/u-boot.lds b/board/amcc/kilauea/u-boot.lds new file mode 100644 index 0000000..390b3f3 --- /dev/null +++ b/board/amcc/kilauea/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* To compile successfully, uncomment the following section. + * To go in ram, remove the section. + * Added by SunHe. + */ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 0067ce0..f964511 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,6 +39,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { + u32 mfr; + mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -64,6 +66,10 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); + return 0; } diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile new file mode 100644 index 0000000..b8da25f --- /dev/null +++ b/board/amcc/makalu/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o cmd_pll.o memory.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c new file mode 100644 index 0000000..b2666dd --- /dev/null +++ b/board/amcc/makalu/cmd_pll.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * ehnus: change pll frequency. + * Wed Sep 5 11:45:17 CST 2007 + * hsun@udtech.com.cn + */ + + +#include <common.h> +#include <config.h> +#include <command.h> +#include <i2c.h> + +#ifdef CONFIG_CMD_EEPROM + +#define EEPROM_CONF_OFFSET 0 +#define EEPROM_TEST_OFFSET 16 +#define EEPROM_SDSTP_PARAM 16 + +#define PLL_NAME_MAX 12 +#define BUF_STEP 8 + +/* eeprom_wirtes 8Byte per op. */ +#define EEPROM_ALTER_FREQ(freq) \ + do { \ + int __i; \ + for (__i = 0; __i < 2; __i++) \ + eeprom_write (CFG_I2C_EEPROM_ADDR, \ + EEPROM_CONF_OFFSET + __i*BUF_STEP, \ + pll_select[freq], \ + BUF_STEP + __i*BUF_STEP); \ + } while (0) + +#define PDEBUG +#ifdef PDEBUG +#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) +#else +#define PLL_DEBUG +#endif + +typedef enum { + PLL_ebc20, + PLL_333, + PLL_4001, + PLL_4002, + PLL_533, + PLL_600, + PLL_666, /* For now, kilauea can't support */ + RCONF, + WTEST, + PLL_TOTAL +} pll_freq_t; + +static const char +pll_name[][PLL_NAME_MAX] = { + "PLL_ebc20", + "PLL_333", + "PLL_400@1", + "PLL_400@2", + "PLL_533", + "PLL_600", + "PLL_666", + "RCONF", + "WTEST", + "" +}; + +/* + * ehnus: + */ +static uchar +pll_select[][EEPROM_SDSTP_PARAM] = { + /* 0: CPU 333MHz EBC 20MHz, for test only */ + { + 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 0: 333 */ + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 1: 400_266 */ + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 2: 400 */ + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 3: 533 */ + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 4: 600 */ + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 5: 666 */ + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + {} +}; + +static uchar +testbuf[EEPROM_SDSTP_PARAM] = { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff +}; + +static void +pll_debug(int off) +{ + int i; + uchar buffer[EEPROM_SDSTP_PARAM]; + + memset(buffer, 0, sizeof(buffer)); + eeprom_read(CFG_I2C_EEPROM_ADDR, off, + buffer, EEPROM_SDSTP_PARAM); + + printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); + for (i = 0; i < EEPROM_SDSTP_PARAM; i++) + printf("%02x ", buffer[i]); + printf("\n"); +} + +static void +test_write(void) +{ + printf("Debug: test eeprom_write ... "); + + /* + * Write twice, 8 bytes per write + */ + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + testbuf, 8); + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + testbuf, 16); + printf("done\n"); + + pll_debug(EEPROM_TEST_OFFSET); +} + +int +do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char c = '\0'; + pll_freq_t pll_freq; + if (argc < 2) { + printf("Usage: \n%s\n", cmdtp->usage); + goto ret; + } + + for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) + if (!strcmp(pll_name[pll_freq], argv[1])) + break; + + switch (pll_freq) { + case PLL_ebc20: + case PLL_333: + case PLL_4001: + case PLL_4002: + case PLL_533: + case PLL_600: + EEPROM_ALTER_FREQ(pll_freq); + break; + + case PLL_666: /* not support */ + printf("Choose this option will result in a boot failure." + "\nContinue? (Y/N): "); + + c = getc(); putc('\n'); + + if ((c == 'y') || (c == 'Y')) { + EEPROM_ALTER_FREQ(pll_freq); + break; + } + goto ret; + + case RCONF: + pll_debug(EEPROM_CONF_OFFSET); + goto ret; + case WTEST: + printf("DEBUG: write test\n"); + test_write(); + goto ret; + + default: + printf("Invalid options" + "\n\nUsage: \n%s\n", cmdtp->usage); + goto ret; + } + + printf("PLL set to %s, " + "reset the board to take effect\n", pll_name[pll_freq]); + + PLL_DEBUG; +ret: + return 0; +} + +U_BOOT_CMD( + pllalter, CFG_MAXARGS, 1, do_pll_alter, + "pllalter- change pll frequence \n", + "pllalter <selection> - change pll frequence \n\n\ + ** New freq take effect after reset. ** \n\ + ----------------------------------------------\n\ + PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ + \t Same as PLL_333 \n\ + \t except \n\ + \t EBC: 20 MHz \n\ + ----------------------------------------------\n\ + PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 666 MHz \n\ + \t CPU: 333 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 83 MHz \n\ + ------------------------------------------------\n\ + PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 133 MHz \n\ + \t OPB: 66 MHz \n\ + \t DDR: 133 MHz \n\ + ------------------------------------------------\n\ + PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1066 MHz \n\ + \t CPU: 533 MHz \n\ + \t PLB: 177 MHz \n\ + \t OPB: 88 MHz \n\ + \t DDR: 177 MHz \n\ + ----------------------------------------------\n\ + PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1200 MHz \n\ + \t CPU: 600 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1333 MHz \n\ + \t CPU: 666 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 166 MHz \n\ + -----------------------------------------------\n\ + RCONF: Read current eeprom configuration. \n\ + -----------------------------------------------\n\ + WTEST: Test EEPROM write with predefined values\n\ + -----------------------------------------------\n" + ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ diff --git a/board/amcc/makalu/config.mk b/board/amcc/makalu/config.mk new file mode 100644 index 0000000..a46b197 --- /dev/null +++ b/board/amcc/makalu/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFA0000 diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S new file mode 100644 index 0000000..57c1774 --- /dev/null +++ b/board/amcc/makalu/init.S @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on code provided from Senao and AMCC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <ppc4xx.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#define mtsdram_as(reg, value) \ + addi r4,0,reg ; \ + mtdcr memcfga,r4 ; \ + addis r4,0,value@h ; \ + ori r4,r4,value@l ; \ + mtdcr memcfgd,r4 ; + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + + /* + * DDR2 setup + */ + + /* Following the DDR Core Manual, here is the initialization */ + + /* Step 1 */ + + /* Step 2 */ + + /* Step 3 */ + + /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram_as(SDRAM_MB0CF, 0x00005201); + + /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram_as(SDRAM_CLKTR,0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram_as(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram_as(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram_as(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram_as(SDRAM_MMODE, 0x00000442); + mtsdram_as(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram_as(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram_as(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram_as(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram_as(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram_as(SDRAM_INITPLR11, 0x81000442); + mtsdram_as(SDRAM_INITPLR12, 0x81010780); + mtsdram_as(SDRAM_INITPLR13, 0x81010400); + mtsdram_as(SDRAM_INITPLR14, 0x00000000); + mtsdram_as(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram_as(SDRAM_CODT, 0x0080f837); + mtsdram_as(SDRAM_MODT0, 0x01800000); +#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */ + mtsdram_as(SDRAM_MODT1, 0x00000000); +#endif + + mtsdram_as(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram_as(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + lis r3,0x1 /* 400000 = wait 100ms */ + mtctr r3 + +pll_wait: + bdnz pll_wait + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram_as(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram_as(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram_as(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram_as(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mtsdram_as(SDRAM_MCOPT2, 0x28000000); + + blr diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c new file mode 100644 index 0000000..15e51f4 --- /dev/null +++ b/board/amcc/makalu/makalu.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc405.h> +#include <libfdt.h> +#include <asm/processor.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#if defined(CONFIG_PCI) +#include <pci.h> +#include <asm/4xx_pcie.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Board early initialization function + */ +int board_early_init_f (void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts */ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic1er, 0x00000000); /* disable all interrupts */ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* Reset PCIe slots */ + gpio_write_bit(CFG_GPIO_PCIE_RST, 0); + udelay(100); + gpio_write_bit(CFG_GPIO_PCIE_RST, 1); + + /* + * Configure PFC (Pin Function Control) registers + * -> Enable USB + */ + val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int misc_init_r(void) +{ +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + + printf("Board: Makalu - AMCC PPC405EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller * hose ) +{ + return 0; +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_PCI +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + bus = busno; + char *env; + unsigned int delay; + + for (i = 0; i < 2; i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c new file mode 100644 index 0000000..b03b60b --- /dev/null +++ b/board/amcc/makalu/memory.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +void sdram_init(void) +{ + return; +} + +long int initdram(int board_type) +{ + /* + * Same as on Kilauea, Makalu generates exception 0x200 + * (machine check) after trap_init() in board_init_f, + * when SDRAM is initialized here (late) and d-cache is + * used earlier as INIT_RAM. + * So for now, initialize DDR2 in init.S very early and + * also use it for INIT_RAM. Then this exception doesn't + * occur. + */ +#if 0 + u32 val; + + /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram(SDRAM_MB0CF, 0x00005201); + + /* SET SDRAM_MB1CF - Not enabled */ + mtsdram(SDRAM_MB1CF, 0x00000000); + + /* SET SDRAM_MB2CF - Not enabled */ + mtsdram(SDRAM_MB2CF, 0x00000000); + + /* SET SDRAM_MB3CF - Not enabled */ + mtsdram(SDRAM_MB3CF, 0x00000000); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram(SDRAM_CLKTR, 0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram(SDRAM_MMODE, 0x00000442); + mtsdram(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram(SDRAM_INITPLR11, 0x81000442); + mtsdram(SDRAM_INITPLR12, 0x81010780); + mtsdram(SDRAM_INITPLR13, 0x81010400); + mtsdram(SDRAM_INITPLR14, 0x00000000); + mtsdram(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram(SDRAM_CODT, 0x0080f837); + mtsdram(SDRAM_MODT0, 0x01800000); + mtsdram(SDRAM_MODT1, 0x00000000); + + mtsdram(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP); + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mfsdram(SDRAM_MCOPT2, val); + val |= SDRAM_MCOPT2_DCEN_ENABLE; + mtsdram(SDRAM_MCOPT2, val); +#endif + return (CFG_MBYTES_SDRAM << 20); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + printf ("testdram\n"); +#if defined (CONFIG_NAND_U_BOOT) + return 0; +#endif + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x00001000; + uint *p; + + for (p = pstart; p < pend; p++) { + *p = 0xaaaaaaaa; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } + + for (p = pstart; p < pend; p++) { + *p = 0x55555555; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test passed!!!\n"); +#endif + return 0; +} +#endif diff --git a/board/amcc/makalu/u-boot.lds b/board/amcc/makalu/u-boot.lds new file mode 100644 index 0000000..390b3f3 --- /dev/null +++ b/board/amcc/makalu/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* To compile successfully, uncomment the following section. + * To go in ram, remove the section. + * Added by SunHe. + */ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 316fee8..0daca70 100644 --- a/board/amcc/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ocotea/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 5fe3af9..ff6ae66 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -20,57 +20,9 @@ */ #include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> #include <config.h> -/* General */ -#define TLB_VALID 0x00000200 -#define _256M 0x10000000 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_8M 0x00000060 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - /************************************************************************** * TLB TABLE * @@ -98,7 +50,11 @@ tlbtab: #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/board/amcc/sequoia/sdram.h b/board/amcc/sequoia/sdram.h index 7f847aa..6a7bf01 100644 --- a/board/amcc/sequoia/sdram.h +++ b/board/amcc/sequoia/sdram.h @@ -395,8 +395,8 @@ #define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) #define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) #define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) #define DDR0_27 0x1B #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 4e47ab3..37b4f31 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -23,9 +23,11 @@ */ #include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <ppc440.h> #include <asm/processor.h> #include <asm/io.h> -#include <ppc440.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,31 +48,31 @@ int board_early_init_f(void) * Setup the GPIO pins *-------------------------------------------------------------------*/ /* test-only: take GPIO init from pcs440ep ???? in config file */ - out32(GPIO0_OR, 0x00000000); - out32(GPIO0_TCR, 0x0000000f); - out32(GPIO0_OSRL, 0x50015400); - out32(GPIO0_OSRH, 0x550050aa); - out32(GPIO0_TSRL, 0x50015400); - out32(GPIO0_TSRH, 0x55005000); - out32(GPIO0_ISR1L, 0x50000000); - out32(GPIO0_ISR1H, 0x00000000); - out32(GPIO0_ISR2L, 0x00000000); - out32(GPIO0_ISR2H, 0x00000100); - out32(GPIO0_ISR3L, 0x00000000); - out32(GPIO0_ISR3H, 0x00000000); - - out32(GPIO1_OR, 0x00000000); - out32(GPIO1_TCR, 0xc2000000); - out32(GPIO1_OSRL, 0x5c280000); - out32(GPIO1_OSRH, 0x00000000); - out32(GPIO1_TSRL, 0x0c000000); - out32(GPIO1_TSRH, 0x00000000); - out32(GPIO1_ISR1L, 0x00005550); - out32(GPIO1_ISR1H, 0x00000000); - out32(GPIO1_ISR2L, 0x00050000); - out32(GPIO1_ISR2H, 0x00000000); - out32(GPIO1_ISR3L, 0x01400000); - out32(GPIO1_ISR3H, 0x00000000); + out_be32((u32 *) GPIO0_OR, 0x00000000); + out_be32((u32 *) GPIO0_TCR, 0x0000000f); + out_be32((u32 *) GPIO0_OSRL, 0x50015400); + out_be32((u32 *) GPIO0_OSRH, 0x550050aa); + out_be32((u32 *) GPIO0_TSRL, 0x50015400); + out_be32((u32 *) GPIO0_TSRH, 0x55005000); + out_be32((u32 *) GPIO0_ISR1L, 0x50000000); + out_be32((u32 *) GPIO0_ISR1H, 0x00000000); + out_be32((u32 *) GPIO0_ISR2L, 0x00000000); + out_be32((u32 *) GPIO0_ISR2H, 0x00000100); + out_be32((u32 *) GPIO0_ISR3L, 0x00000000); + out_be32((u32 *) GPIO0_ISR3H, 0x00000000); + + out_be32((u32 *) GPIO1_OR, 0x00000000); + out_be32((u32 *) GPIO1_TCR, 0xc2000000); + out_be32((u32 *) GPIO1_OSRL, 0x5c280000); + out_be32((u32 *) GPIO1_OSRH, 0x00000000); + out_be32((u32 *) GPIO1_TSRL, 0x0c000000); + out_be32((u32 *) GPIO1_TSRH, 0x00000000); + out_be32((u32 *) GPIO1_ISR1L, 0x00005550); + out_be32((u32 *) GPIO1_ISR1H, 0x00000000); + out_be32((u32 *) GPIO1_ISR2L, 0x00050000); + out_be32((u32 *) GPIO1_ISR2H, 0x00000000); + out_be32((u32 *) GPIO1_ISR3L, 0x01400000); + out_be32((u32 *) GPIO1_ISR3H, 0x00000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -100,16 +102,16 @@ int board_early_init_f(void) mtdcr(uic2sr, 0xffffffff); /* clear all */ /* 50MHz tmrclk */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00); /* clear write protects */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00); /* enable Ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; + out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00); /* enable USB device */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; + out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20); /* select Ethernet pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -583,3 +585,24 @@ int post_hotkeys_pressed(void) return 0; /* No hotkeys supported */ } #endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds index be03092..b08c999 100644 --- a/board/amcc/taihu/u-boot.lds +++ b/board/amcc/taihu/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 57b9d1c..040b800 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,25 +33,25 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfclk(clk_pllc,reg); + mfcpr(clk_pllc,reg); printf("cpr_pllc = %#010x\n",reg); - mfclk(clk_plld,reg); + mfcpr(clk_plld,reg); printf("cpr_plld = %#010x\n",reg); - mfclk(clk_primad,reg); + mfcpr(clk_primad,reg); printf("cpr_primad = %#010x\n",reg); - mfclk(clk_primbd,reg); + mfcpr(clk_primbd,reg); printf("cpr_primbd = %#010x\n",reg); - mfclk(clk_opbd,reg); + mfcpr(clk_opbd,reg); printf("cpr_opbd = %#010x\n",reg); - mfclk(clk_perd,reg); + mfcpr(clk_perd,reg); printf("cpr_perd = %#010x\n",reg); - mfclk(clk_mald,reg); + mfcpr(clk_mald,reg); printf("cpr_mald = %#010x\n",reg); /* read sdr register */ diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds index 664716e..b2be352 100644 --- a/board/amcc/taishan/u-boot.lds +++ b/board/amcc/taishan/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/taishan/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds index 1dcbab5..fa75dde 100644 --- a/board/amcc/walnut/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds index a9a7b0a..978319f 100644 --- a/board/amcc/yosemite/u-boot.lds +++ b/board/amcc/yosemite/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yosemite/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds index 9df4f92..c9cf4db 100644 --- a/board/amcc/yucca/u-boot.lds +++ b/board/amcc/yucca/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yucca/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d7cc384..52486cc 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -27,29 +27,17 @@ #include <common.h> #include <ppc4xx.h> -#include <asm/processor.h> #include <i2c.h> -#include <asm-ppc/io.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/4xx_pcie.h> #include "yucca.h" -#include "../cpu/ppc4xx/440spe_pcie.h" DECLARE_GLOBAL_DATA_PTR; -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ - void fpga_init (void); -void get_sys_info(PPC440_SYS_INFO *board_cfg ); -int compare_to_true(char *str ); -char *remove_l_w_space(char *in_str ); -char *remove_t_w_space(char *in_str ); -int get_console_port(void); - -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -541,10 +529,10 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - /* SDR0_MFR should be part of Ethernet init */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; - /*mtsdr(sdr_mfr, mfr);*/ + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); + fpga_init(); return 0; @@ -850,6 +838,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -863,14 +852,16 @@ void pcie_setup_hoses(int busno) if (!yucca_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - yucca_setup_pcie_fpga_endpoint(i); - if (ppc440spe_init_pcie_endport(i)) { -#else - yucca_setup_pcie_fpga_rootpoint(i); - if (ppc440spe_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); + if (is_end_point(i)) { + yucca_setup_pcie_fpga_endpoint(i); + ret = ppc4xx_init_pcie_endport(i); + } else { + yucca_setup_pcie_fpga_rootpoint(i); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } @@ -884,35 +875,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc440spe_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); - } + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } } } #endif /* defined(CONFIG_PCI) */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index 109e7fe..3d5b575 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds index cf4bbb9..6d3e171 100644 --- a/board/cray/L1/u-boot.lds +++ b/board/cray/L1/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS board/cray/L1/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds index d75d6d1..a664d0f 100644 --- a/board/csb272/u-boot.lds +++ b/board/csb272/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds index 14ac3fb..8765016 100644 --- a/board/csb472/u-boot.lds +++ b/board/csb472/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 481d291..d40ee62 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds index 4a0e5b4..de51b3f 100644 --- a/board/eric/u-boot.lds +++ b/board/eric/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/apc405/u-boot.lds +++ b/board/esd/apc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds index 3b9aa7c..64293d2 100644 --- a/board/esd/ar405/u-boot.lds +++ b/board/esd/ar405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds index 95854f2..b49e3ff 100644 --- a/board/esd/ash405/u-boot.lds +++ b/board/esd/ash405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds index ff15b3f..aaaccbe 100644 --- a/board/esd/canbt/u-boot.lds +++ b/board/esd/canbt/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cms700/u-boot.lds +++ b/board/esd/cms700/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpci2dp/u-boot.lds +++ b/board/esd/cpci2dp/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpci405/u-boot.lds +++ b/board/esd/cpci405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c deleted file mode 100644 index 43d8a3b..0000000 --- a/board/esd/cpci440/cpci440.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2002 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> -#include <asm/processor.h> - - -extern void lxt971_no_sleep(void); - - -long int fixed_sdram( void ); - -int board_early_init_f (void) -{ - uint reg; - - /*-------------------------------------------------------------------- - * Setup the external bus controller/chip selects - *-------------------------------------------------------------------*/ - mtdcr( ebccfga, xbcfg ); - reg = mfdcr( ebccfgd ); - mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */ - - mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */ - mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */ - /* test-only: other regs still missing... */ - - /*-------------------------------------------------------------------- - * Setup the interrupt controller polarities, triggers, etc. - *-------------------------------------------------------------------*/ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - mtdcr( uic0er, 0x00000000 ); /* disable all */ - mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */ - mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */ - mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */ - mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic0sr, 0xffffffff ); /* clear all */ - - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - mtdcr( uic1er, 0x00000000 ); /* disable all */ - mtdcr( uic1cr, 0x00000000 ); /* all non-critical */ - mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */ - mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */ - mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */ - mtdcr( uic1sr, 0xffffffff ); /* clear all */ - - return 0; -} - - -int checkboard (void) -{ - sys_info_t sysinfo; - get_sys_info(&sysinfo); - - printf("Board: esd CPCI-440\n"); - printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000); - printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); - printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); - printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); - printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - - return (0); -} - - -long int initdram (int board_type) -{ - long dram_size = 0; - - dram_size = fixed_sdram(); - return dram_size; -} - - -/************************************************************************* - * fixed sdram init -- doesn't use serial presence detect. - * - * Assumes: 64 MB, non-ECC, non-registered - * PLB @ 133 MHz - * - ************************************************************************/ -long int fixed_sdram( void ) -{ - uint reg; - -#if 1 /* test-only */ - /*-------------------------------------------------------------------- - * Setup some default - *------------------------------------------------------------------*/ - mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */ - mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */ - mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */ - mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */ - mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */ - - /*-------------------------------------------------------------------- - * Setup for board-specific specific mem - *------------------------------------------------------------------*/ - /* - * Following for CAS Latency = 2.5 @ 133 MHz PLB - */ - mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/ - mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ - /* RA=10 RD=3 */ - mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */ - udelay( 400 ); /* Delay 200 usecs (min) */ - - /*-------------------------------------------------------------------- - * Enable the controller, then wait for DCEN to complete - *------------------------------------------------------------------*/ - mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */ - for(;;) - { - mfsdram( mem_mcsts, reg ); - if( reg & 0x80000000 ) - break; - } - - return( 64 * 1024 * 1024 ); /* 64 MB */ -#else - return( 32 * 1024 * 1024 ); /* 64 MB */ -#endif -} diff --git a/board/esd/cpci440/init.S b/board/esd/cpci440/init.S deleted file mode 100644 index 82f37fd..0000000 --- a/board/esd/cpci440/init.S +++ /dev/null @@ -1,94 +0,0 @@ -/* -* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> -* -* See file CREDITS for list of people who contributed to this -* project. -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License as -* published by the Free Software Foundation; either version 2 of -* the License, or (at your option) any later version. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 59 Temple Place, Suite 330, Boston, -* MA 02111-1307 USA -*/ - -#include <ppc_asm.tmpl> -#include <config.h> - -/* General */ -#define TLB_VALID 0x00000200 - -/* Supported page sizes */ - -#define SZ_1K 0x00000000 -#define SZ_4K 0x00000010 -#define SZ_16K 0x00000020 -#define SZ_64K 0x00000030 -#define SZ_256K 0x00000040 -#define SZ_1M 0x00000050 -#define SZ_16M 0x00000070 -#define SZ_256M 0x00000090 - -/* Storage attributes */ -#define SA_W 0x00000800 /* Write-through */ -#define SA_I 0x00000400 /* Caching inhibited */ -#define SA_M 0x00000200 /* Memory coherence */ -#define SA_G 0x00000100 /* Guarded */ -#define SA_E 0x00000080 /* Endian */ - -/* Access control */ -#define AC_X 0x00000024 /* Execute */ -#define AC_W 0x00000012 /* Write */ -#define AC_R 0x00000009 /* Read */ - -/* Some handy macros */ - -#define EPN(e) ((e) & 0xfffffc00) -#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) -#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) -#define TLB2(a) ( (a)&0x00000fbf ) - -#define tlbtab_start\ - mflr r1 ;\ - bl 0f ; - -#define tlbtab_end\ - .long 0, 0, 0 ; \ -0: mflr r0 ; \ - mtlr r1 ; \ - blr ; - -#define tlbentry(epn,sz,rpn,erpn,attr)\ - .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) - - -/************************************************************************** - * TLB TABLE - * - * This table is used by the cpu boot code to setup the initial tlb - * entries. Rather than make broad assumptions in the cpu source tree, - * this table lets each board set things up however they like. - * - * Pointer to the table is returned in r1 - * - *************************************************************************/ - - .section .bootpg,"ax" - .globl tlbtab - -tlbtab: - tlbtab_start - tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X ) - tlbtab_end diff --git a/board/esd/cpci440/strataflash.c b/board/esd/cpci440/strataflash.c deleted file mode 100644 index 2f055c2..0000000 --- a/board/esd/cpci440/strataflash.c +++ /dev/null @@ -1,755 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for U-Boot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - - -#define FLASH_MAN_CFI 0x01000000 - - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - - -/*----------------------------------------------------------------------- - * Functions - */ - - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n"); - printf (" %08lX%5s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * - */ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpciiser4/u-boot.lds +++ b/board/esd/cpciiser4/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index fef5b52..497177d 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/iop480_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/dp405/u-boot.lds +++ b/board/esd/dp405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds index 1cf375f..21c5044 100644 --- a/board/esd/du405/u-boot.lds +++ b/board/esd/du405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds index 98338e9..852e9ed 100644 --- a/board/esd/hub405/u-boot.lds +++ b/board/esd/hub405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index 4177f68..f83dfe8 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -25,7 +25,7 @@ #include <command.h> #include <pci.h> #include <pci_ids.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #if defined(CONFIG_CMD_BSP) diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds index 476b4a0..8ff25fa 100644 --- a/board/esd/ocrtc/u-boot.lds +++ b/board/esd/ocrtc/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 5b5ad8c..9a0bf1e 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -27,7 +27,7 @@ #include <net.h> #include <asm/io.h> #include <pci.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #include <asm/processor.h> #include "pci405.h" diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index e5d2273..c4ab072 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -26,7 +26,7 @@ #include <command.h> #include <malloc.h> #include <pci.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #include "pci405.h" diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/pci405/u-boot.lds +++ b/board/esd/pci405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds index e84d69e..898963c 100644 --- a/board/esd/pmc405/u-boot.lds +++ b/board/esd/pmc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/voh405/u-boot.lds +++ b/board/esd/voh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/vom405/u-boot.lds +++ b/board/esd/vom405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds index 95854f2..b49e3ff 100644 --- a/board/esd/wuh405/u-boot.lds +++ b/board/esd/wuh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index d5dea82..b482aea 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/g2000/u-boot.lds +++ b/board/g2000/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/cpci440/Makefile b/board/korat/Makefile index d13d31c..fa19e6f 100644 --- a/board/esd/cpci440/Makefile +++ b/board/korat/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2002-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -22,13 +22,10 @@ # include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o ../common/misc.o +COBJS = $(BOARD).o SOBJS = init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) @@ -36,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/esd/cpci440/config.mk b/board/korat/config.mk index 8e5f63f..39966e0 100644 --- a/board/esd/cpci440/config.mk +++ b/board/korat/config.mk @@ -20,19 +20,11 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - # -# esd ADCIOP boards +# Korat (PPC440EPx) board # -#TEXT_BASE = 0xFFFE0000 - -ifeq ($(ramsym),1) -TEXT_BASE = 0x07FD0000 -else -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x01fc0000 -endif +TEXT_BASE = 0xFFFA0000 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/korat/init.S b/board/korat/init.S new file mode 100644 index 0000000..bd0e8b4 --- /dev/null +++ b/board/korat/init.S @@ -0,0 +1,80 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <asm-ppc/mmu.h> +#include <config.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + + /* + * TLB entries for SDRAM are not needed on this platform. They are + * generated dynamically in the SPD DDR2 detection routine. + */ + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for EBC */ + tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for Internal Registers & OCM */ + /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ + tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I ) + + /*TLB-entry PCI registers*/ + tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I ) + + /* TLB-entry for peripherals */ + tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry PCI IO Space - from sr@denx.de */ + tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I) + + tlbtab_end diff --git a/board/korat/korat.c b/board/korat/korat.c new file mode 100644 index 0000000..7cb9ee1 --- /dev/null +++ b/board/korat/korat.c @@ -0,0 +1,761 @@ +/* + * (C) Copyright 2007 + * Larry Johnson, lrj@acm.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm-ppc/io.h> +#include <i2c.h> +#include <ppc440.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size(ulong base, int banknum); + +int board_early_init_f(void) +{ + u32 sdr0_pfc1, sdr0_pfc2; + u32 gpio0_ir; + u32 reg; + int eth; + + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, 0xb8400000); + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + * + * Korat GPIO usage: + * + * Init. + * Pin Source I/O value Function + * ------ ------ --- ----- --------------------------------- + * GPIO00 Alt1 I/O x PerAddr07 + * GPIO01 Alt1 I/O x PerAddr06 + * GPIO02 Alt1 I/O x PerAddr05 + * GPIO03 GPIO x x GPIO03 to expansion bus connector + * GPIO04 GPIO x x GPIO04 to expansion bus connector + * GPIO05 GPIO x x GPIO05 to expansion bus connector + * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) + * GPIO07 Alt1 O x PerCS2 (CPLD) + * GPIO08 Alt1 O x PerCS3 to expansion bus connector + * GPIO09 Alt1 O x PerCS4 to expansion bus connector + * GPIO10 Alt1 O x PerCS5 to expansion bus connector + * GPIO11 Alt1 I x PerErr + * GPIO12 GPIO O 0 ATMega !Reset + * GPIO13 GPIO O 1 SPI Atmega !SS + * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) + * GPIO15 GPIO O 0 CPU Run LED !On + * GPIO16 Alt1 O x GMC1TxD0 + * GPIO17 Alt1 O x GMC1TxD1 + * GPIO18 Alt1 O x GMC1TxD2 + * GPIO19 Alt1 O x GMC1TxD3 + * GPIO20 Alt1 O x RejectPkt0 + * GPIO21 Alt1 O x RejectPkt1 + * GPIO22 GPIO I x PGOOD_DDR + * GPIO23 Alt1 O x SCPD0 + * GPIO24 Alt1 O x GMC0TxD2 + * GPIO25 Alt1 O x GMC0TxD3 + * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) + * GPIO27 GPIO O 0 PHY #0 1000BASE-X + * GPIO28 GPIO O 0 PHY #1 1000BASE-X + * GPIO29 GPIO I x Test jumper !Present + * GPIO30 GPIO I x SFP module #0 !Present + * GPIO31 GPIO I x SFP module #1 !Present + * + * GPIO32 GPIO O 1 SFP module #0 Tx !Enable + * GPIO33 GPIO O 1 SFP module #1 Tx !Enable + * GPIO34 Alt2 I x !UART1_CTS + * GPIO35 Alt2 O x !UART1_RTS + * GPIO36 Alt1 I x !UART0_CTS + * GPIO37 Alt1 O x !UART0_RTS + * GPIO38 Alt2 O x UART1_Tx + * GPIO39 Alt2 I x UART1_Rx + * GPIO40 Alt1 I x IRQ0 (Ethernet 0) + * GPIO41 Alt1 I x IRQ1 (Ethernet 1) + * GPIO42 Alt1 I x IRQ2 (PCI interrupt) + * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) + * GPIO44 xxxx x x (grounded through pulldown) + * GPIO45 GPIO O 0 PHY #0 Enable + * GPIO46 GPIO O 0 PHY #1 Enable + * GPIO47 GPIO I x Reset switch !Pressed + * GPIO48 GPIO I x Shutdown switch !Pressed + * GPIO49 xxxx x x (reserved for trace port) + * . . . . . + * . . . . . + * . . . . . + * GPIO63 xxxx x x (reserved for trace port) + *-------------------------------------------------------------------*/ + + out_be32((u32 *) GPIO0_OR, 0x00060000); + out_be32((u32 *) GPIO1_OR, 0xC0000000); + + out_be32((u32 *) GPIO0_OSRL, 0x54055400); + out_be32((u32 *) GPIO0_OSRH, 0x55015000); + out_be32((u32 *) GPIO1_OSRL, 0x02180000); + out_be32((u32 *) GPIO1_OSRH, 0x00000000); + + out_be32((u32 *) GPIO0_TSRL, 0x54055500); + out_be32((u32 *) GPIO0_TSRH, 0x00015000); + out_be32((u32 *) GPIO1_TSRL, 0x00000000); + out_be32((u32 *) GPIO1_TSRH, 0x00000000); + + out_be32((u32 *) GPIO0_TCR, 0x000FF0D8); + out_be32((u32 *) GPIO1_TCR, 0xD6060000); + + out_be32((u32 *) GPIO0_ISR1L, 0x54000100); + out_be32((u32 *) GPIO0_ISR1H, 0x00500000); + out_be32((u32 *) GPIO1_ISR1L, 0x00405500); + out_be32((u32 *) GPIO1_ISR1H, 0x00000000); + + out_be32((u32 *) GPIO0_ISR2L, 0x00000000); + out_be32((u32 *) GPIO0_ISR2H, 0x00000000); + out_be32((u32 *) GPIO1_ISR2L, 0x04010000); + out_be32((u32 *) GPIO1_ISR2H, 0x00000000); + + out_be32((u32 *) GPIO0_ISR3L, 0x00000000); + out_be32((u32 *) GPIO0_ISR3H, 0x00000000); + out_be32((u32 *) GPIO1_ISR3L, 0x00000000); + out_be32((u32 *) GPIO1_ISR3H, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ + mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ + mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ + mtdcr(uic2sr, 0xffffffff); /* clear all */ + + /* take sim card reader and CF controller out of reset */ + out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80); + + /* Configure the two Ethernet PHYs. For each PHY, configure for fiber + * if the SFP module is present, and for copper if it is not present. + */ + gpio0_ir = in_be32((u32 *) GPIO0_IR); + for (eth = 0; eth < 2; ++eth) { + if (gpio0_ir & (0x00000001 << (1 - eth))) { + /* SFP module not present: configure PHY for copper. */ + /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ + out_8((u8 *) CFG_CPLD_BASE + 0x06, + in_8((u8 *) CFG_CPLD_BASE + 0x06) | + 0x06 << (4 * eth)); + } else { + /* SFP module present: configure PHY for fiber and + enable output */ + out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) | + (0x00000001 << (4 - eth))); + out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) & + ~(0x00000001 << (31 - eth))); + } + } + /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ + out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000); + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | + SDR0_PFC1_SELECT_CONFIG_4; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | + SDR0_PFC2_SELECT_CONFIG_4; + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /* PCI arbiter enabled */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); + + return 0; +} + +static int man_data_read(unsigned int addr) +{ + /* + * Read an octet of data from address "addr" in the manufacturer's + * information serial EEPROM, or -1 on error. + */ + u8 data[2]; + + if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) || + 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) { + debug("man_data_read(0x%02X) failed\n", addr); + return -1; + } + debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]); + return data[0]; +} + +static unsigned int man_data_field_addr(unsigned int const field) +{ + /* + * The manufacturer's information serial EEPROM contains a sequence of + * zero-delimited fields. Return the starting address of field "field", + * or 0 on error. + */ + unsigned addr, i; + + if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1)) + /* Only format "A" is currently supported */ + return 0; + + for (addr = 2, i = 1; i < field && addr < 256; ++addr) { + if ('\0' == man_data_read(addr)) + ++i; + } + return (addr < 256) ? addr : 0; +} + +static char *man_data_read_field(char s[], unsigned const field, + unsigned const length) +{ + /* + * Place the null-terminated contents of field "field" of length + * "length" from the manufacturer's information serial EEPROM into + * string "s[length + 1]" and return a pointer to s, or return 0 on + * error. In either case the original contents of s[] is not preserved. + */ + unsigned addr, i; + + addr = man_data_field_addr(field); + if (0 == addr || addr + length >= 255) + return 0; + + for (i = 0; i < length; ++i) { + int const c = man_data_read(addr++); + + if (c <= 0) + return 0; + + s[i] = (char)c; + } + if (0 != man_data_read(addr)) + return 0; + + s[i] = '\0'; + return s; +} + +static void set_serial_number(void) +{ + /* + * If the environmental variable "serial#" is not set, try to set it + * from the manufacturer's information serial EEPROM. + */ + char s[MAN_SERIAL_NO_LENGTH + 1]; + + if (0 == getenv("serial#") && + 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD, + MAN_SERIAL_NO_LENGTH)) + setenv("serial#", s); +} + +static void set_mac_addresses(void) +{ + /* + * If the environmental variables "ethaddr" and/or "eth1addr" are not + * set, try to set them from the manufacturer's information serial + * EEPROM. + */ + char s[MAN_MAC_ADDR_LENGTH + 1]; + + if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) + return; + + if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD, + MAN_MAC_ADDR_LENGTH)) + return; + + if (0 == getenv("ethaddr")) + setenv("ethaddr", s); + + if (0 == getenv("eth1addr")) { + ++s[MAN_MAC_ADDR_LENGTH - 1]; + setenv("eth1addr", s); + } +} + +/*---------------------------------------------------------------------------+ + | misc_init_r. + +---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + uint pbcr; + int size_val = 0; + u32 reg; + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + char *act = getenv("usbact"); + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* + * USB suff... + */ + if (act == NULL || strcmp(act, "hostdev") == 0) { + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */ + + /* To enable the USB 2.0 Device function through the UTMI interface */ + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */ + + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /*clear resets */ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + } else if (strcmp(act, "dev") == 0) { + /*-------------------PATCH-------------------------------*/ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + + udelay(1000); + mtsdr(SDR0_SRST1, 0x672c6000); + + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000080); + + udelay(1000); + mtsdr(SDR0_SRST1, 0x60206000); + + *(unsigned int *)(0xe0000350) = 0x00000001; + + udelay(1000); + mtsdr(SDR0_SRST1, 0x60306000); + /*-------------------PATCH-------------------------------*/ + + /* SDR Setting */ + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + mfsdr(SDR0_USB2D0CR, usb2d0cr); + mfsdr(SDR0_PFC1, sdr0_pfc1); + + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */ + usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */ + + usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */ + + usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; + usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */ + + sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; + sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */ + + mtsdr(SDR0_USB2H0CR, usb2h0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2D0CR, usb2d0cr); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + /*clear resets */ + udelay(1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay(1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Device(int phy)\n"); + } + + mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ + reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); + mtsdr(SDR0_SRST1, reg); + + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; + mtdcr(plb4_acr, reg); + + set_serial_number(); + set_mac_addresses(); + return 0; +} + +int checkboard(void) +{ + char const *const s = getenv("serial#"); + u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); + u32 const gpio0_or = in_be32((u32 *) GPIO0_OR); + + printf("Board: Korat, Rev. %X", rev); + if (s != NULL) + printf(", serial# %s", s); + + printf(", Ethernet PHY 0: "); + if (gpio0_or & 0x00000010) + printf("fiber"); + else + printf("copper"); + + printf(", PHY 1: "); + if (gpio0_or & 0x00000008) + printf("fiber"); + else + printf("copper"); + + printf(".\n"); + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + /* TODO: find correct size of SDRAM */ + for (k = 0; k < CFG_MBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) + printf("%3d MB\r", k / 1024); + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif /* defined(CFG_DRAM_TEST) */ + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers for on-board NEC uPD720101 USB controller + *--------------------------------------------------------------------------*/ + pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Korat is always configured as host. */ + return (1); +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif diff --git a/board/esd/cpci440/u-boot.lds b/board/korat/u-boot.lds index 57220d3..a423f98 100644 --- a/board/esd/cpci440/u-boot.lds +++ b/board/korat/u-boot.lds @@ -28,13 +28,11 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/ SECTIONS { .resetvec 0xFFFFFFFC : -/* .resetvec 0x01FFFFFC :*/ { *(.resetvec) } = 0xffff .bootpg 0xFFFFF000 : -/* .bootpg 0x01FFF000 :*/ { cpu/ppc4xx/start.o (.bootpg) } = 0xffff @@ -69,20 +67,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/esd/cpci440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -95,7 +79,6 @@ SECTIONS *(.rodata) *(.rodata1) *(.rodata.str1.4) - *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } @@ -154,6 +137,9 @@ SECTIONS *(.bss) *(COMMON) } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + _end = . ; PROVIDE (end = .); } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index d4547e2..399da8a 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -71,7 +71,7 @@ static u32 is_ecc_enabled(void) void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) diff --git a/board/lwmon5/sdram.h b/board/lwmon5/sdram.h index 7f847aa..6a7bf01 100644 --- a/board/lwmon5/sdram.h +++ b/board/lwmon5/sdram.h @@ -395,8 +395,8 @@ #define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) #define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) #define DDR0_26_TREF_MASK 0x00003FFF -#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) -#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) #define DDR0_27 0x1B #define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index f8e9e33..26df77b 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 278ad5c..8d4cbe8 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -36,11 +36,11 @@ #ifdef CONFIG_PIP405 #include "../pip405/pip405.h" -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif #ifdef CONFIG_MIP405 #include "../mip405/mip405.h" -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -587,7 +587,7 @@ extern int get_boot_mode(void); void video_get_info_str (int line_number, char *info) { /* init video info strings for graphic console */ - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; char rev; int i,boot; unsigned long pvr; diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index fd43008..6f53192 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -47,7 +47,7 @@ #if defined(CONFIG_PIP405) #include "../pip405/pip405.h" #endif -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #else /* defined(CONFIG_PATI) */ #include <mpc5xx.h> #endif diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index ad5f273..dceb390 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -70,7 +70,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index 11819a4..685f903 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 9ee9ab5..cbb2839 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -72,7 +72,7 @@ void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; mfsdram(DDR0_22, val); val &= DDR0_22_CTRL_RAW_MASK; diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds index 4f04089..697801e 100644 --- a/board/prodrive/alpr/u-boot.lds +++ b/board/prodrive/alpr/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/prodrive/alpr/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 92bb740..0540a46 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/prodrive/p3p440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds index 9e9e990..36420ad 100644 --- a/board/sandburst/karef/u-boot.lds +++ b/board/sandburst/karef/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 47d80fa..b934c89 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds index a17401a..e2178d2 100644 --- a/board/sandburst/metrobox/u-boot.lds +++ b/board/sandburst/metrobox/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index fef4c42..914ff9c 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds index 39fba61..0c5b809 100644 --- a/board/sbc405/u-boot.lds +++ b/board/sbc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds index dc255d2..05052e5 100644 --- a/board/sc3/u-boot.lds +++ b/board/sc3/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 60f0bc2..58bfac0 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -108,7 +108,7 @@ ulong get_PCI_freq(void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPCI; diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds index b6d748e..8c0edb7 100644 --- a/board/xilinx/ml300/u-boot.lds +++ b/board/xilinx/ml300/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds index 0f08637..7484111 100644 --- a/board/xpedite1k/u-boot.lds +++ b/board/xpedite1k/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug index 5066326..6631793 100644 --- a/board/xpedite1k/u-boot.lds.debug +++ b/board/xpedite1k/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) |