diff options
Diffstat (limited to 'board')
31 files changed, 2014 insertions, 12 deletions
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a0b6fbd..9e3f677 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -133,7 +133,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 7e40c5c..e6025c8 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index c562fc9..90e89bc 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -125,7 +125,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 33685c1..53d5a93 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -308,7 +308,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 3730818..ac7778e 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -337,7 +337,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index bc93be8..7a23b33 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -188,7 +188,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index fa0a336..bf270f4 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { + if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index fed0ed4..5353d73 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -150,7 +150,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 932f112..b14a3d3 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -306,7 +306,7 @@ local_bus_init(void) */ get_sys_info(&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 8c073cb..519b0f7 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -126,7 +126,7 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & 0x0f) * 2; + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d83dc7d..df9696e 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -156,7 +156,7 @@ void local_bus_init (void) uint lcrr = CONFIG_SYS_LBC_LCRR; get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; + clkdiv = lbc->lcrr & LCRR_CLKDIV; lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 73f1d01..cda8208 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -361,7 +361,7 @@ uint get_lbc_clock (void) { volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; - ulong clkdiv = lbc->lcrr & 0x0f; + ulong clkdiv = lbc->lcrr & LCRR_CLKDIV; get_sys_info (&sys_info); diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile new file mode 100644 index 0000000..e7620f4 --- /dev/null +++ b/board/xes/common/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o +COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o +COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o +COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c new file mode 100644 index 0000000..465aeb0 --- /dev/null +++ b/board/xes/common/actl_nand.c @@ -0,0 +1,65 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This driver support NAND devices which have address lines + * connected as ALE and CLE inputs. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +/* + * Hardware specific access to control-lines + */ +static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | + CONFIG_SYS_NAND_ACTL_ALE | + CONFIG_SYS_NAND_ACTL_NCE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; + if (ctrl & NAND_NCE) + IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; + + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = nand_addr_hwcontrol; + nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; + + return 0; +} diff --git a/board/xes/common/fsl_8572_clk.c b/board/xes/common/fsl_8572_clk.c new file mode 100644 index 0000000..f5df2da --- /dev/null +++ b/board/xes/common/fsl_8572_clk.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +/* + * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config + */ +unsigned long get_board_sys_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 gpporcr = gur->gpporcr; + + if (gpporcr & 0x10000) + return 66666666; + else + return 50000000; +} + +/* + * Return DDR input clock - synchronous with SYSCLK or 66 MHz + */ +unsigned long get_board_ddr_clk(ulong dummy) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; + + if (ddr_ratio == 0x7) + return get_board_sys_clk(dummy); + + return 66666666; +} diff --git a/board/xes/common/fsl_85xx_ddr.c b/board/xes/common/fsl_85xx_ddr.c new file mode 100644 index 0000000..30b4767 --- /dev/null +++ b/board/xes/common/fsl_85xx_ddr.c @@ -0,0 +1,93 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/mmu.h> + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + +#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) +void board_add_ram_info(int use_default) +{ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); +#endif + + puts(" ("); + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + /* Print interleaving information */ + if (ddr1->cs0_config & 0x20000000) { + switch ((ddr1->cs0_config >> 24) & 0xf) { + case 0: + puts("cache line"); + break; + case 1: + puts("page"); + break; + case 2: + puts("bank"); + break; + case 3: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } else { + puts("no"); + } + + puts(" interleaving"); +#endif + +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) + puts(", "); +#endif + +#if defined(CONFIG_DDR_ECC) + puts("ECC enabled"); +#endif + + puts(")"); +} +#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */ diff --git a/board/xes/common/fsl_85xx_pci.c b/board/xes/common/fsl_85xx_pci.c new file mode 100644 index 0000000..9673a02 --- /dev/null +++ b/board/xes/common/fsl_85xx_pci.c @@ -0,0 +1,379 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> + +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_config_unlock(struct pci_controller *hose); +extern void fsl_pci_init(struct pci_controller *hose); + +int first_free_busno = 0; + +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif +#ifdef CONFIG_PCIE2 +static struct pci_controller pcie2_hose; +#endif +#ifdef CONFIG_PCIE3 +static struct pci_controller pcie3_hose; +#endif + +#ifdef CONFIG_MPC8572 +/* Correlate host/agent POR bits to usable info. Table 4-14 */ +struct host_agent_cfg_t { + uchar pcie_root[3]; + uchar rio_host; +} host_agent_cfg[8] = { + {{0, 0, 0}, 0}, + {{0, 1, 1}, 1}, + {{1, 0, 1}, 0}, + {{1, 1, 0}, 1}, + {{0, 0, 1}, 0}, + {{0, 1, 0}, 1}, + {{1, 0, 0}, 0}, + {{1, 1, 1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-15 */ +struct io_port_cfg_t { + uchar pcie_width[3]; + uchar rio_width; +} io_port_cfg[16] = { + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 0}, + {{4, 4, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 4}, + {{4, 2, 2}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{0, 0, 0}, 0}, + {{4, 0, 0}, 4}, + {{4, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{0, 0, 0}, 4}, + {{8, 0, 0}, 0}, +}; +#elif defined CONFIG_MPC8548 +/* Correlate host/agent POR bits to usable info. Table 4-12 */ +struct host_agent_cfg_t { + uchar pci_host[2]; + uchar pcie_root[1]; + uchar rio_host; +} host_agent_cfg[8] = { + {{1, 1}, {0}, 0}, + {{1, 1}, {1}, 0}, + {{1, 1}, {0}, 1}, + {{0, 0}, {0}, 0}, /* reserved */ + {{0, 1}, {1}, 0}, + {{1, 1}, {1}, 0}, + {{0, 1}, {1}, 1}, + {{1, 1}, {1}, 1} +}; + +/* Correlate port width POR bits to usable info. Table 4-13 */ +struct io_port_cfg_t { + uchar pcie_width[1]; + uchar rio_width; +} io_port_cfg[8] = { + {{0}, 0}, + {{0}, 0}, + {{0}, 0}, + {{4}, 4}, + {{4}, 4}, + {{0}, 4}, + {{0}, 4}, + {{8}, 0}, +}; +#endif + +void pci_init_board(void) +{ + struct pci_controller *hose; + volatile ccsr_fsl_pci_t *pci; + int width; + int host; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct pci_region *r; + +#ifdef CONFIG_PCI1 + uint pci_spd_norm = (gur->pordevsr & MPC85xx_PORDEVSR_PCI1_SPD); + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pcix = gur->pordevsr & MPC85xx_PORDEVSR_PCI1; + uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; + + width = 0; /* Silence compiler warning... */ + io_sel &= 0xf; /* Silence compiler warning... */ + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; + hose = &pci1_hose; + host = host_agent_cfg[host_agent].pci_host[0]; + r = hose->regions; + + + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", + pci_32 ? 32 : 64, + pcix ? "PCIX" : "PCI", + pci_spd_norm ? ">=" : "<=", + pcix ? freq * 2 : freq, + host ? "host" : "agent", + pci_arb ? "arbiter" : "external-arbiter"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCI1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } else { + printf(" PCI1: disabled\n"); + } +#elif defined CONFIG_MPC8548 + /* PCI1 not present on MPC8572 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif +#ifdef CONFIG_PCIE1 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; + hose = &pcie1_hose; + host = host_agent_cfg[host_agent].pcie_root[0]; + width = io_port_cfg[io_sel].pcie_width[0]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) { + printf("\n PCIE1 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int) &pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE1 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ + +#ifdef CONFIG_PCIE2 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; + hose = &pcie2_hose; + host = host_agent_cfg[host_agent].pcie_root[1]; + width = io_port_cfg[io_sel].pcie_width[1]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { + printf("\n PCIE2 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE2 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ +#endif /* CONFIG_PCIE2 */ + +#ifdef CONFIG_PCIE3 + pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; + hose = &pcie3_hose; + host = host_agent_cfg[host_agent].pcie_root[2]; + width = io_port_cfg[io_sel].pcie_width[2]; + r = hose->regions; + + if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { + printf("\n PCIE3 connected as %s (x%d)", + host ? "Root Complex" : "End Point", width); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + printf("\n"); + + /* inbound */ + r += fsl_pci_setup_inbound_windows(r); + + /* outbound memory */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init(hose); + + /* Unlock inbound PCI configuration cycles */ + if (!host) + fsl_pci_config_unlock(hose); + + first_free_busno = hose->last_busno + 1; + printf(" PCIE3 on bus %02x - %02x\n", + hose->first_busno, hose->last_busno); + } +#else + gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ +#endif /* CONFIG_PCIE3 */ +} + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + +void ft_board_pci_setup(void *blob, bd_t *bd) +{ + /* TODO - make node name (eg pci0) dynamic */ +#ifdef CONFIG_PCI1 + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); +#endif +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); +#endif +#ifdef CONFIG_PCIE3 + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); +#endif +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/xes/xpedite5200/Makefile b/board/xes/xpedite5200/Makefile new file mode 100644 index 0000000..02fe8fc --- /dev/null +++ b/board/xes/xpedite5200/Makefile @@ -0,0 +1,55 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk new file mode 100644 index 0000000..be5a5c3 --- /dev/null +++ b/board/xes/xpedite5200/config.mk @@ -0,0 +1,34 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2004, 2007 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5200 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 +PLATFORM_CPPFLAGS += -mrelocatable diff --git a/board/xes/xpedite5200/ddr.c b/board/xes/xpedite5200/ddr.c new file mode 100644 index 0000000..c5616d5 --- /dev/null +++ b/board/xes/xpedite5200/ddr.c @@ -0,0 +1,91 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); + + /* We use soldered memory, but use an SPD EEPROM to describe it. + * The SPD has an unspecified dimm type, but the DDR2 initialization + * code requires a specific type to be specified. This sets the type + * as a standard unregistered SO-DIMM. */ + if (spd->dimm_type == 0) { + spd->dimm_type = 0x4; + ((uchar *)spd)[63] += 0x4; + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + + if (ctrl_num) { + printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 7; + + /* + * Factors to consider for CPO: + * - frequency + * - ddr1 vs. ddr2 + */ + popts->cpo_override = 9; + + /* + * Factors to consider for write data delay: + * - number of DIMMs + * + * 1 = 1/4 clock delay + * 2 = 1/2 clock delay + * 3 = 3/4 clock delay + * 4 = 1 clock delay + * 5 = 5/4 clock delay + * 6 = 3/2 clock delay + */ + popts->write_data_delay = 3; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c new file mode 100644 index 0000000..386f9c5 --- /dev/null +++ b/board/xes/xpedite5200/law.c @@ -0,0 +1,51 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#if CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1), +#endif +#if CONFIG_SYS_PCI2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/tlb.c b/board/xes/xpedite5200/tlb.c new file mode 100644 index 0000000..bd7bff8 --- /dev/null +++ b/board/xes/xpedite5200/tlb.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#if CONFIG_PCI1 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#if CONFIG_PCI2 + /* *I*G* - PCI MEM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2) + /* *I*G* - PCI IO */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_16M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5200/u-boot.lds b/board/xes/xpedite5200/u-boot.lds new file mode 100644 index 0000000..bd952d2 --- /dev/null +++ b/board/xes/xpedite5200/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5200/xpedite5200.c b/board/xes/xpedite5200/xpedite5200.c new file mode 100644 index 0000000..e266d1d --- /dev/null +++ b/board/xes/xpedite5200/xpedite5200.c @@ -0,0 +1,125 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pca953x.h> + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + char *s; + + printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + ecm->eedr = 0xffffffff; /* Clear ecm errors */ + ecm->eeer = 0xffffffff; /* Enable ecm errors */ + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif diff --git a/board/xes/xpedite5370/Makefile b/board/xes/xpedite5370/Makefile new file mode 100644 index 0000000..919397c --- /dev/null +++ b/board/xes/xpedite5370/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xes/xpedite5370/config.mk b/board/xes/xpedite5370/config.mk new file mode 100644 index 0000000..39469b2 --- /dev/null +++ b/board/xes/xpedite5370/config.mk @@ -0,0 +1,35 @@ +# +# Copyright 2008 Extreme Engineering Solutions, Inc. +# Copyright 2007-2008 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# xpedite5370 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfff80000 +endif + +PLATFORM_RELFLAGS += -mrelocatable + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8572=1 diff --git a/board/xes/xpedite5370/ddr.c b/board/xes/xpedite5370/ddr.c new file mode 100644 index 0000000..4d3f255 --- /dev/null +++ b/board/xes/xpedite5370/ddr.c @@ -0,0 +1,270 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +{ + i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, + sizeof(ddr2_spd_eeprom_t)); +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + if (ctrl_num == 0) + i2c_address = SPD_EEPROM_ADDRESS1; + if (ctrl_num == 1) + i2c_address = SPD_EEPROM_ADDRESS2; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} + +/* + * There are four board-specific SDRAM timing parameters which must be + * calculated based on the particular PCB artwork. These are: + * 1.) CPO (Read Capture Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths and + * chip-specific internal delays. + * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay) + * - TIMING_CFG_2 register + * Source: Calculation based on board trace lengths. + * Unless clock and DQ lanes are very different + * lengths (>2"), this should be set to the nominal value + * of 1/2 clock delay. + * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control) + * - DDR_SDRAM_CLK_CNTL register + * Source: Signal Integrity Simulations + * 4.) 2T Timing on Addr/Ctl + * - TIMING_CFG_2 register + * Source: Signal Integrity Simulations + * Usually only needed with heavy load/very high speed (>DDR2-800) + * + * ====== XPedite5370 DDR2-600 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps + * = 3808ps + * = 3.808ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 400ps + 2.4" * 180 + 2080ps + 2914ps + * = 6240ps + * = 6.240ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps + * = 3288ps + * = 3.288ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 400ps + 1.1" * 180 + 2080ps + 2595ps + * = 5536ps + * = 5.536ns + * + * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target) + * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target) + * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7) + * + * + * ====== XPedite5370 DDR2-800 read delay calculations ====== + * + * See Freescale's App Note AN2583 as refrence. This document also + * contains the chip-specific delays for 8548E, 8572, etc. + * + * For MPC8572E + * Minimum chip delay (Ch 0): 1.372ns + * Maximum chip delay (Ch 0): 2.914ns + * Minimum chip delay (Ch 1): 1.220ns + * Maximum chip delay (Ch 1): 2.595ns + * + * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps + * + * Minimum delay calc (Ch 0): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps + * = 3341ps + * = 3.341ns + * + * Maximum delay calc (Ch 0): + * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly + * 2.3" * 180 + 350ps + 2.4" * 180 + 1563ps + 2914ps + * = 5673ps + * = 5.673ns + * + * Minimum delay calc (Ch 1): + * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps + * = 2822ps + * = 2.822ns + * + * Maximum delay calc (Ch 1): + * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly + * 1.46" * 180+ 350ps + 1.1" * 180 + 1563ps + 2595ps + * = 4968ps + * = 4.968ns + * + * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target) + * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9) + * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target) + * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8) + * + * Write latency (WR_DATA_DELAY) is calculated by doing the following: + * + * The DDR SDRAM specification requires DQS be received no sooner than + * 75% of an SDRAM clock period—and no later than 125% of a clock + * period—from the capturing clock edge of the command/address at the + * SDRAM. + * + * Based on the above tracelengths, the following are calculated: + * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns + * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns + * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns + * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns + * + * Difference in arrival time CLK vs. DQS: + * Ch. 0 0.072ns + * Ch. 1 0.138ns + * + * Both of these values are much less than 25% of the clock + * period at DDR2-600 or DDR2-800, so no additional delay is needed over + * the 1/2 cycle which normally aligns the first DQS transition + * exactly WL (CAS latency minus one cycle) after the CAS strobe. + * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's + * terminology corresponds to exactly one clock period delay after + * the CAS strobe. (due to the fact that the "delay" is referenced + * from the *falling* edge of the CLK, just after the rising edge + * which the CAS strobe is latched on. + */ + +typedef struct board_memctl_options { + uint16_t datarate_mhz_low; + uint16_t datarate_mhz_high; + uint8_t clk_adjust; + uint8_t cpo_override; + uint8_t write_data_delay; +} board_memctl_options_t; + +static struct board_memctl_options bopts_ctrl[][2] = { + { + /* Controller 0 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 9, + .write_data_delay = 2, + }, + }, + { + /* Controller 1 */ + { + /* DDR2 600/667 */ + .datarate_mhz_low = 500, + .datarate_mhz_high = 750, + .clk_adjust = 5, + .cpo_override = 7, + .write_data_delay = 2, + }, + { + /* DDR2 800 */ + .datarate_mhz_low = 750, + .datarate_mhz_high = 850, + .clk_adjust = 5, + .cpo_override = 8, + .write_data_delay = 2, + }, + }, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + struct board_memctl_options *bopts = bopts_ctrl[ctrl_num]; + sys_info_t sysinfo; + int i; + unsigned int datarate; + + get_sys_info(&sysinfo); + datarate = sysinfo.freqDDRBus / 1000 / 1000; + + for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { + if ((bopts[i].datarate_mhz_low <= datarate) && + (bopts[i].datarate_mhz_high >= datarate)) { + debug("controller %d:\n", ctrl_num); + debug(" clk_adjust = %d\n", bopts[i].clk_adjust); + debug(" cpo = %d\n", bopts[i].cpo_override); + debug(" write_data_delay = %d\n", + bopts[i].write_data_delay); + popts->clk_adjust = bopts[i].clk_adjust; + popts->cpo_override = bopts[i].cpo_override; + popts->write_data_delay = bopts[i].write_data_delay; + } + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; +} diff --git a/board/xes/xpedite5370/law.c b/board/xes/xpedite5370/law.c new file mode 100644 index 0000000..daee676 --- /dev/null +++ b/board/xes/xpedite5370/law.c @@ -0,0 +1,54 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif +#ifdef CONFIG_SYS_PCIE2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2), +#endif +#ifdef CONFIG_SYS_PCIE3_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c new file mode 100644 index 0000000..caafa30 --- /dev/null +++ b/board/xes/xpedite5370/tlb.c @@ -0,0 +1,94 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* W**G* - NOR flashes */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + /* *I*G* - NAND flash */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_PCIE1 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCIE2 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), +#endif + +#ifdef CONFIG_PCIE3 + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif + +#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) + /* *I*G* - PCIe */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/xes/xpedite5370/u-boot.lds b/board/xes/xpedite5370/u-boot.lds new file mode 100644 index 0000000..cb39912 --- /dev/null +++ b/board/xes/xpedite5370/u-boot.lds @@ -0,0 +1,145 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x7f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x7fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x80000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xes/xpedite5370/xpedite5370.c b/board/xes/xpedite5370/xpedite5370.c new file mode 100644 index 0000000..4875095 --- /dev/null +++ b/board/xes/xpedite5370/xpedite5370.c @@ -0,0 +1,128 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pca953x.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void ft_board_pci_setup(void *blob, bd_t *bd); + +int checkboard(void) +{ + char *s; + + printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME); + printf(" "); + s = getenv("board_rev"); + if (s) + printf("Rev %s, ", s); + s = getenv("serial#"); + if (s) + printf("Serial# %s, ", s); + s = getenv("board_cfg"); + if (s) + printf("Cfg %s", s); + printf("\n"); + + return 0; +} + +static void flash_cs_fixup(void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + int flash_sel; + + /* + * Print boot dev and swap flash flash chip selects if booted from 2nd + * flash. Swapping chip selects presents user with a common memory + * map regardless of which flash was booted from. + */ + flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) & + CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS)); + printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1); + + if (flash_sel) { + lbc->br0 = CONFIG_SYS_BR1_PRELIM; + lbc->or0 = CONFIG_SYS_OR1_PRELIM; + + lbc->br1 = CONFIG_SYS_BR0_PRELIM; + lbc->or1 = CONFIG_SYS_OR0_PRELIM; + } +} + +int board_early_init_r(void) +{ + /* Initialize PCA9557 devices */ + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); + + /* + * Remap NOR flash region to caching-inhibited + * so that flash can be erased/programmed properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* Invalidate existing TLB entry for NOR flash */ + disable_tlb(0); + set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1); + + flash_cs_fixup(); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_PCI + ft_board_pci_setup(blob, bd); +#endif + ft_cpu_setup(blob, bd); +} +#endif + +#ifdef CONFIG_MP +extern void cpu_mp_lmb_reserve(struct lmb *lmb); + +void board_lmb_reserve(struct lmb *lmb) +{ + cpu_mp_lmb_reserve(lmb); +} +#endif |