diff options
Diffstat (limited to 'board')
286 files changed, 19873 insertions, 6190 deletions
diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake Binary files differindex 4d6ccb3..4d6ccb3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/dmake diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp Binary files differindex d372949..d372949 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_cp diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo Binary files differindex 6f65d41..6f65d41 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_echo diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm Binary files differindex 7de5030..7de5030 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/k_rm diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep Binary files differindex 5451b22..5451b22 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/makedep diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm Binary files differindex fbd3352..fbd3352 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/nasm diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm Binary files differindex dd14a7a..dd14a7a 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/ndisasm diff --git a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans Binary files differindex a1aea4f..a1aea4f 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans +++ b/board/MAI/bios_emulator/scitech/bin-linux/glibc/trans diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake Binary files differindex f198f29..f198f29 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake +++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/dmake diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm Binary files differindex e312a0b..e312a0b 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm +++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/nasm diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm Binary files differindex 9fe81a3..9fe81a3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm +++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/ndisasm diff --git a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans Binary files differindex e536c04..e536c04 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin-linux/libc/trans +++ b/board/MAI/bios_emulator/scitech/bin-linux/libc/trans diff --git a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat index 776d138..776d138 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc31-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat index d2939f4..d2939f4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat index 246517d..246517d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat index cbb2c79..cbb2c79 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-d32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat index 14d7c05..14d7c05 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat index 50bd3cb..50bd3cb 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat index 4b59fa4..4b59fa4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-vxd.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat index 4d799b4..4d799b4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat index a6c199f..a6c199f 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc45-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat index 6a0fde2..6a0fde2 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat index 23b5038..23b5038 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat index 0521f93..0521f93 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-d32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat index e3241ff..e3241ff 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-smx.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat index ab3acd2..ab3acd2 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat index 4dcc372..4dcc372 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat index 2356911..2356911 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-vxd.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat index cd79d86..cd79d86 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat index 8b8cec9..8b8cec9 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat index ebfeb2e..ebfeb2e 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/bc50-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat index 6e09428..6e09428 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat index aa13e7d..aa13e7d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat index d0017d4..d0017d4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-d32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat index 2b969a9..2b969a9 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-smx.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat index d7b8ff2..d7b8ff2 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat index 1de3601..1de3601 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat index 28de58c..28de58c 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-vxd.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat index c30d004..c30d004 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat index 18760e1..18760e1 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat index 198c1a2..198c1a2 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/bcb5-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/build b/board/MAI/bios_emulator/scitech/bin/build index ff1973d..ff1973d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/build +++ b/board/MAI/bios_emulator/scitech/bin/build diff --git a/board/MAI/bios_emulator/scitech/bin/build.bat b/board/MAI/bios_emulator/scitech/bin/build.bat index ee29093..ee29093 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/build.bat +++ b/board/MAI/bios_emulator/scitech/bin/build.bat diff --git a/board/MAI/bios_emulator/scitech/bin/build_db.bat b/board/MAI/bios_emulator/scitech/bin/build_db.bat index 2b32529..2b32529 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/build_db.bat +++ b/board/MAI/bios_emulator/scitech/bin/build_db.bat diff --git a/board/MAI/bios_emulator/scitech/bin/build_it.bat b/board/MAI/bios_emulator/scitech/bin/build_it.bat index 5a619b4..5a619b4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/build_it.bat +++ b/board/MAI/bios_emulator/scitech/bin/build_it.bat diff --git a/board/MAI/bios_emulator/scitech/bin/cddrv.bat b/board/MAI/bios_emulator/scitech/bin/cddrv.bat index b64f4d7..b64f4d7 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/cddrv.bat +++ b/board/MAI/bios_emulator/scitech/bin/cddrv.bat diff --git a/board/MAI/bios_emulator/scitech/bin/cdit b/board/MAI/bios_emulator/scitech/bin/cdit index b22023d..b22023d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/cdit +++ b/board/MAI/bios_emulator/scitech/bin/cdit diff --git a/board/MAI/bios_emulator/scitech/bin/cdit.bat b/board/MAI/bios_emulator/scitech/bin/cdit.bat index 950b648..950b648 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/cdit.bat +++ b/board/MAI/bios_emulator/scitech/bin/cdit.bat diff --git a/board/MAI/bios_emulator/scitech/bin/findint3.bat b/board/MAI/bios_emulator/scitech/bin/findint3.bat index 2e1506c..2e1506c 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/findint3.bat +++ b/board/MAI/bios_emulator/scitech/bin/findint3.bat diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh index 61ffd93..61ffd93 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh +++ b/board/MAI/bios_emulator/scitech/bin/gcc-beos.sh diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh index 3816a5d..3816a5d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh +++ b/board/MAI/bios_emulator/scitech/bin/gcc-freebsd.sh diff --git a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh index 27a4c49..27a4c49 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh +++ b/board/MAI/bios_emulator/scitech/bin/gcc-linux.sh diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat index 13c4783..13c4783 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat index 97cb8bd..97cb8bd 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-dos.bat diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat index ceb2ab8..ceb2ab8 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-linux.bat diff --git a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat index bdb31aa..bdb31aa 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/gcc2-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/makelib.bat b/board/MAI/bios_emulator/scitech/bin/makelib.bat index 6316734..6316734 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/makelib.bat +++ b/board/MAI/bios_emulator/scitech/bin/makelib.bat diff --git a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh index fd1804b..fd1804b 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/meltobjs.sh +++ b/board/MAI/bios_emulator/scitech/bin/meltobjs.sh diff --git a/board/MAI/bios_emulator/scitech/bin/ntddk.bat b/board/MAI/bios_emulator/scitech/bin/ntddk.bat index 07c0d78..07c0d78 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/ntddk.bat +++ b/board/MAI/bios_emulator/scitech/bin/ntddk.bat diff --git a/board/MAI/bios_emulator/scitech/bin/qnx4.sh b/board/MAI/bios_emulator/scitech/bin/qnx4.sh index 843c4d9..843c4d9 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/qnx4.sh +++ b/board/MAI/bios_emulator/scitech/bin/qnx4.sh diff --git a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh index c114f9e..c114f9e 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/qnxnto.sh +++ b/board/MAI/bios_emulator/scitech/bin/qnxnto.sh diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh index 0a272d6..0a272d6 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-beos.sh diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh index c920748..c920748 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-freebsd.sh diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh index 35cbf1d..35cbf1d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-linux.sh diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh index 1d73109..1d73109 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh +++ b/board/MAI/bios_emulator/scitech/bin/set-vars-qnx.sh diff --git a/board/MAI/bios_emulator/scitech/bin/set-vars.bat b/board/MAI/bios_emulator/scitech/bin/set-vars.bat index 2a2101d..2a2101d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/set-vars.bat +++ b/board/MAI/bios_emulator/scitech/bin/set-vars.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat index 71f7d8e..71f7d8e 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat index 9817493..9817493 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat index 62e3521..62e3521 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drv9x.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat index 83b6780..83b6780 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-drvnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat index 7997044..7997044 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat index b0fc936..b0fc936 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat index 2849a20..2849a20 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat index d93a624..d93a624 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat index a420a54..a420a54 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc40-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat index 62d27b9..62d27b9 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat index c789c50..c789c50 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat index 27a4a14..27a4a14 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drv9x.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat index 17b2f25..17b2f25 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-drvnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat index afb2fb1..afb2fb1 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-rtt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat index 22d2e13..22d2e13 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat index 6b09199..6b09199 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat index 52ab495..52ab495 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat index 07bc5e5..07bc5e5 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat index fe286bd..fe286bd 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc50-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat index e98417d..e98417d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat index 10855e0..10855e0 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat index 27a4a14..27a4a14 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drv9x.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat index 17b2f25..17b2f25 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat index f304293..f304293 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-drvw2k.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat index 5348ef9..5348ef9 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat index 1d8b5e3..1d8b5e3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat index 70175c3..70175c3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat index 2f8e7ab..2f8e7ab 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat index 57b23d2..57b23d2 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/vc60-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat index 92858d1..92858d1 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/w2kddk.bat +++ b/board/MAI/bios_emulator/scitech/bin/w2kddk.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat index 2d738f3..2d738f3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat index 5c53a90..5c53a90 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat index a5c7210..a5c7210 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-d32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat index 579dece..579dece 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat index 3404b42..3404b42 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-o32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat index 57057de..57057de 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-p32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat index 46f8659..46f8659 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-qnx.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat index 1fde624..1fde624 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat index d12f042..d12f042 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat index e8ba871..e8ba871 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat index 839bdde..839bdde 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat index fc783d8..fc783d8 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat index 6e0c24d..6e0c24d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ac32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat index f9ecb67..f9ecb67 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat index d52b79a..d52b79a 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ad32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat index ba7351d..ba7351d 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat index f3caa59..f3caa59 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ao32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat index 8d21c62..8d21c62 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10ap32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat index 28f857c..28f857c 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10asnp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat index a2b3219..a2b3219 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10atnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat index 94011cc..94011cc 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat index 1e14dbc..1e14dbc 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc10aw32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat index e753129..e753129 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-c32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat index 4338ada..4338ada 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat index e5a54d4..e5a54d4 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-d32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat index d46754a..d46754a 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat index 37f5dc7..37f5dc7 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-o32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat index 348cbbd..348cbbd 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-p32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat index 1fd60fe..1fd60fe 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-qnx.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat index 6d2ac57..6d2ac57 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-snp.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat index 44dbf24..44dbf24 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-tnt.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat index e65c70e..e65c70e 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w16.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat index 764cdbd..764cdbd 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-w32.bat diff --git a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat index c2569a3..c2569a3 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat +++ b/board/MAI/bios_emulator/scitech/bin/wc11-x11.bat diff --git a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat index 3c7f017..3c7f017 100644..100755 --- a/board/MAI/bios_emulator/scitech/bin/win32sdk.bat +++ b/board/MAI/bios_emulator/scitech/bin/win32sdk.bat diff --git a/board/alaska/flash.c b/board/alaska/flash.c index 48c9472..383491f 100644 --- a/board/alaska/flash.c +++ b/board/alaska/flash.c @@ -64,7 +64,6 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV; #define FLASH_CYCLE2 0x02aa #define WR_BLOCK 0x20 - /*----------------------------------------------------------------------- * Functions */ @@ -74,6 +73,9 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest); static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); static void flash_get_offsets (ulong base, flash_info_t * info); void inline spin_wheel (void); +static void flash_sync_real_protect (flash_info_t * info); +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); +static unsigned char same_chip_banks (int bank1, int bank2); /*----------------------------------------------------------------------- */ @@ -115,6 +117,9 @@ unsigned long flash_init (void) break; } size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); } /* Protect monitor and environment sectors @@ -167,7 +172,6 @@ static void flash_get_offsets (ulong base, flash_info_t * info) if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { for (i = 0; i < info->sector_count; i++) { info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE); - info->protect[i] = 0; } } } @@ -305,6 +309,98 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) } +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +static void flash_sync_real_protect (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + case FLASH_AM040: + default: + /* no h/w protect support */ + break; + } +} + + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + udelay(1); + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer (0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* wait at least 35ns (W12) before reading */ + udelay(1); + + /* Intel example code uses offset of 4 for 8-bit flash */ + lock_conf_addr = (FPWV *) info->start[sector] + 4; + ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + + +/* + * Checks if "bank1" and "bank2" are on the same chip. Returns 1 if they + * are and 0 otherwise. + */ +static unsigned char same_chip_banks (int bank1, int bank2) +{ + unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = { + {1, 1, 0, 0}, + {1, 1, 0, 0}, + {0, 0, 1, 1}, + {0, 0, 1, 1} + }; + return same_chip[bank1][bank2]; +} + + /*----------------------------------------------------------------------- */ int flash_erase (flash_info_t * info, int s_first, int s_last) @@ -729,7 +825,9 @@ void inline spin_wheel (void) int flash_real_protect (flash_info_t * info, long sector, int prot) { ulong start; - int i; + int i, j; + int curr_bank; + int bank; int rc = 0; FPWV *addr = (FPWV *) (info->start[sector]); int flag = disable_interrupts (); @@ -779,23 +877,54 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) * we have to restore lock bits of protected sectors. */ if (!prot) { - for (i = 0; i < info->sector_count; i++) { - if (info->protect[i]) { - start = get_timer (0); - addr = (FPWV *) (info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != - INTEL_FINISHED) { - if (get_timer (start) > - CFG_FLASH_UNLOCK_TOUT) { - printf ("Flash lock bit operation timed out\n"); - rc = 1; - break; + /* + * re-locking must be done for all banks that belong on one + * FLASH chip, as all the sectors on the chip were unlocked + * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope + * that banks never span chips, in particular chips which + * support h/w protection differently). + */ + + /* find the current bank number */ + curr_bank = CFG_MAX_FLASH_BANKS + 1; + for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) { + if (&flash_info[j] == info) { + curr_bank = j; + } + } + if (curr_bank == CFG_MAX_FLASH_BANKS + 1) { + printf("Error: can't determine bank number!\n"); + } + + for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) { + if (!same_chip_banks(curr_bank, bank)) { + continue; + } + info = &flash_info[bank]; + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) { + start = get_timer (0); + addr = (FPWV *) (info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != + INTEL_FINISHED) { + if (get_timer (start) > + CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } } } } } + + /* + * get the s/w sector protection status in sync with the h/w, + * in case something went wrong during the re-locking. + */ + flash_sync_real_protect(info); /* resets flash to read mode */ } if (flag) diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index fd85706..98ee7a7 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -2,6 +2,9 @@ * (C) Copyright 2003, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt@psyent.com> * + * CompactFlash/IDE: + * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,6 +25,7 @@ */ #include <common.h> +#include <nios-io.h> #if defined(CONFIG_SEVENSEG) #include "../common/sevenseg.h" #endif @@ -50,3 +54,28 @@ long int initdram (int board_type) { return (0); } + +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +int ide_preinit (void) +{ + nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT; + nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER; + nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL; + + /* setup data direction registers */ + present->direction = NIOS_PIO_IN; + power->direction = NIOS_PIO_OUT; + atasel->direction = NIOS_PIO_OUT; + + /* Check for presence of card */ + if (present->data) + return 1; + printf ("Ok\n"); + + /* Finish setup */ + power->data = 1; /* Turn on power FET */ + atasel->data = 0; /* Put in ATA mode */ + + return 0; +} +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ diff --git a/board/amcc/bamboo/Makefile b/board/amcc/bamboo/Makefile new file mode 100644 index 0000000..5654f91 --- /dev/null +++ b/board/amcc/bamboo/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS += flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c new file mode 100644 index 0000000..d02add5 --- /dev/null +++ b/board/amcc/bamboo/bamboo.c @@ -0,0 +1,2091 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <spd_sdram.h> +#include <ppc440.h> +#include "bamboo.h" + +void ext_bus_cntlr_init(void); +void configure_ppc440ep_pins(void); +int is_nand_selected(void); + +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX]; +#if 0 +{ /* GPIO Alternate1 Alternate2 Alternate3 */ + { + /* GPIO Core 0 */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */ + { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */ + { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */ + }, + { + /* GPIO Core 1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */ + { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */ + } +}; +#endif + +/*----------------------------------------------------------------------------+ + | EBC Devices Characteristics + | Peripheral Bank Access Parameters - EBC0_BnAP + | Peripheral Bank Configuration Register - EBC0_BnCR + +----------------------------------------------------------------------------*/ +/* Small Flash */ +#define EBC0_BNAP_SMALL_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(6) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(3) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_SMALL_FLASH_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +#define EBC0_BNCR_SMALL_FLASH_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87F00000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +/* Large Flash or SRAM */ +#define EBC0_BNAP_LARGE_FLASH_OR_SRAM \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(8) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(1) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \ + EBC0_BNCR_BAS_ENCODE(0xFF800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_16BIT + + +#define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \ + EBC0_BNCR_BAS_ENCODE(0x87800000) | \ + EBC0_BNCR_BS_8MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_16BIT + +/* NVRAM - FPGA */ +#define EBC0_BNAP_NVRAM_FPGA \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(9) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(1) | \ + EBC0_BNAP_WBN_ENCODE(1) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(2) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_DELAYED | \ + EBC0_BNAP_BEM_WRITEONLY | \ + EBC0_BNAP_PEN_DISABLED + +#define EBC0_BNCR_NVRAM_FPGA_CS5 \ + EBC0_BNCR_BAS_ENCODE(0x80000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_8BIT + +/* Nand Flash */ +#define EBC0_BNAP_NAND_FLASH \ + EBC0_BNAP_BME_DISABLED | \ + EBC0_BNAP_TWT_ENCODE(3) | \ + EBC0_BNAP_CSN_ENCODE(0) | \ + EBC0_BNAP_OEN_ENCODE(0) | \ + EBC0_BNAP_WBN_ENCODE(0) | \ + EBC0_BNAP_WBF_ENCODE(0) | \ + EBC0_BNAP_TH_ENCODE(1) | \ + EBC0_BNAP_RE_ENABLED | \ + EBC0_BNAP_SOR_NOT_DELAYED | \ + EBC0_BNAP_BEM_RW | \ + EBC0_BNAP_PEN_DISABLED + + +#define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000 + +/* NAND0 */ +#define EBC0_BNCR_NAND_FLASH_CS1 \ + EBC0_BNCR_BAS_ENCODE(0x90000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT +/* NAND1 - Bank2 */ +#define EBC0_BNCR_NAND_FLASH_CS2 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT + +/* NAND1 - Bank3 */ +#define EBC0_BNCR_NAND_FLASH_CS3 \ + EBC0_BNCR_BAS_ENCODE(0x94000000) | \ + EBC0_BNCR_BS_1MB | \ + EBC0_BNCR_BU_RW | \ + EBC0_BNCR_BW_32BIT + +int board_early_init_f(void) +{ + ext_bus_cntlr_init(); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + out32(GPIO0_OSRL, 0x00000400); + out32(GPIO0_OSRH, 0x00000000); + out32(GPIO0_TSRL, 0x00000400); + out32(GPIO0_TSRH, 0x00000000); + out32(GPIO0_ISR1L, 0x00000000); + out32(GPIO0_ISR1H, 0x00000000); + out32(GPIO0_ISR2L, 0x00000000); + out32(GPIO0_ISR2H, 0x00000000); + out32(GPIO0_ISR3L, 0x00000000); + out32(GPIO0_ISR3H, 0x00000000); + + out32(GPIO1_OSRL, 0x0C380000); + out32(GPIO1_OSRH, 0x00000000); + out32(GPIO1_TSRL, 0x0C380000); + out32(GPIO1_TSRH, 0x00000000); + out32(GPIO1_ISR1L, 0x0FC30000); + out32(GPIO1_ISR1H, 0x00000000); + out32(GPIO1_ISR2L, 0x0C010000); + out32(GPIO1_ISR2H, 0x00000000); + out32(GPIO1_ISR3L, 0x01400000); + out32(GPIO1_ISR3H, 0x00000000); + + configure_ppc440ep_pins(); + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#include <linux/mtd/nand.h> +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +/*----------------------------------------------------------------------------+ + | nand_reset. + | Reset Nand flash + | This routine will abort previous cmd + +----------------------------------------------------------------------------*/ +int nand_reset(ulong addr) +{ + int wait=0, stat=0; + + out8(addr + NAND_CMD_REG, NAND0_CMD_RESET); + out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS); + + while ((stat != 0xc0) && (wait != 0xffff)) { + stat = in8(addr + NAND_DATA_REG); + wait++; + } + + if (stat == 0xc0) { + return 0; + } else { + printf("NAND Reset timeout.\n"); + return -1; + } +} + +void board_nand_set_device(int cs, ulong addr) +{ + /* Set NandFlash Core Configuration Register */ + out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24)); + + switch (cs) { + case 1: + /* ------- + * NAND0 + * ------- + * K9F1208U0A : 4 addr cyc, 1 col + 3 Row + * Set NDF1CR - Enable External CS1 in NAND FLASH controller + */ + out32(addr + NAND_CR1_REG, 0x80002222); + break; + + case 2: + /* ------- + * NAND1 + * ------- + * K9K2G0B : 5 addr cyc, 2 col + 3 Row + * Set NDF2CR : Enable External CS2 in NAND FLASH controller + */ + out32(addr + NAND_CR2_REG, 0xC0007777); + break; + } + + /* Perform Reset Command */ + if (nand_reset(addr) != 0) + return; +} + +void nand_init(void) +{ + board_nand_set_device(1, CFG_NAND_ADDR); + + nand_probe(CFG_NAND_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } + +#if 0 /* NAND1 not supported yet */ + board_nand_set_device(2, CFG_NAND2_ADDR); + + nand_probe(CFG_NAND2_ADDR); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + print_size(nand_dev_desc[0].totlen, "\n"); + } +#endif +} +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ + +int checkboard(void) +{ + sys_info_t sysinfo; + unsigned char *s = getenv("serial#"); + + get_sys_info(&sysinfo); + + printf("Board: Bamboo - AMCC PPC440EP Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + + return (0); +} + +/************************************************************************* + * + * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM) + * + * Fixed memory is composed of : + * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, + * 13 row add bits, 10 column add bits (but 12 row used only). + * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, + * 12 row add bits, 10 column add bits. + * Prepare a subset (only the used ones) of SPD data + * + * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of + * the corresponding bank is divided by 2 due to number of Row addresses + * 12 in the ECC module + * + * Assumes: 64 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +void fixed_sdram_init(void) +{ + /* + * clear this first, if the DDR is enabled by a debugger + * then you can not make changes. + */ + mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram(mem_b0cr, 0x00082001); + mtsdram(mem_b1cr, 0x00000000); + mtsdram(mem_b2cr, 0x00000000); + mtsdram(mem_b3cr, 0x00000000); +} + +long int initdram (int board_type) +{ + long dram_size = 0; + + /* + * First init bank0 (onboard sdram) and then configure the DIMM-slots + */ + fixed_sdram_init(); + dram_size = spd_sdram (0); + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long strap; + unsigned long addr; + + /*--------------------------------------------------------------------------+ + * Bamboo is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PAE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return 0; + } + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440 EP PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/*----------------------------------------------------------------------------+ + | is_powerpc440ep_pass1. + +----------------------------------------------------------------------------*/ +int is_powerpc440ep_pass1(void) +{ + unsigned long pvr; + + pvr = get_pvr(); + + if (pvr == PVR_POWERPC_440EP_PASS1) + return TRUE; + else if (pvr == PVR_POWERPC_440EP_PASS2) + return FALSE; + else { + printf("brdutil error 3\n"); + for (;;) + ; + } + + return(FALSE); +} + +/*----------------------------------------------------------------------------+ + | is_nand_selected. + +----------------------------------------------------------------------------*/ +int is_nand_selected(void) +{ +#ifdef CONFIG_BAMBOO_NAND + return TRUE; +#else + return FALSE; +#endif +} + +/*----------------------------------------------------------------------------+ + | config_on_ebc_cs4_is_small_flash => from EPLD + +----------------------------------------------------------------------------*/ +unsigned char config_on_ebc_cs4_is_small_flash(void) +{ + /* Not implemented yet => returns constant value */ + return TRUE; +} + +/*----------------------------------------------------------------------------+ + | Ext_bus_cntlr_init. + | Initialize the external bus controller + +----------------------------------------------------------------------------*/ +void ext_bus_cntlr_init(void) +{ + unsigned long sdr0_pstrp0, sdr0_sdstp1; + unsigned long bootstrap_settings, boot_selection, ebc_boot_size; + int computed_boot_device = BOOT_DEVICE_UNKNOWN; + unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0; + unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0; + unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0; + unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0; + unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0; + + + /*-------------------------------------------------------------------------+ + | + | PART 1 : Initialize EBC Bank 5 + | ============================== + | Bank5 is always associated to the NVRAM/EPLD. + | It has to be initialized prior to other banks settings computation since + | some board registers values may be needed + | + +-------------------------------------------------------------------------*/ + /* NVRAM - FPGA */ + mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); + mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); + + /*-------------------------------------------------------------------------+ + | + | PART 2 : Determine which boot device was selected + | ========================================= + | + | Read Pin Strap Register in PPC440EP + | In case of boot from IIC, read Serial Device Strap Register1 + | + | Result can either be : + | - Boot from EBC 8bits => SMALL FLASH + | - Boot from EBC 16bits => Large Flash or SRAM + | - Boot from NAND Flash + | - Boot from PCI + | + +-------------------------------------------------------------------------*/ + /* Read Pin Strap Register in PPC440EP */ + mfsdr(sdr_pstrp0, sdr0_pstrp0); + bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; + + /*-------------------------------------------------------------------------+ + | PPC440EP Pass1 + +-------------------------------------------------------------------------*/ + if (is_powerpc440ep_pass1() == TRUE) { + switch(bootstrap_settings) { + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: + /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: + /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */ + /* Boot from Nand Flash */ + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: + /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ + /* Read Serial Device Strap Register1 in PPC440EP */ + mfsdr(sdr_sdstp1, sdr0_sdstp1); + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + } + break; + } + } + + /*-------------------------------------------------------------------------+ + | PPC440EP Pass2 + +-------------------------------------------------------------------------*/ + else { + switch(bootstrap_settings) { + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: + /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ + /* Boot from Small Flash */ + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: + /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: + /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */ + /* Boot from Nand Flash */ + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3: + /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */ + /* Boot from Large Flash or SRAM */ + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: + /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */ + /* Boot from Large Flash or SRAM */ + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + + case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6: + /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */ + /* Boot from PCI */ + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN: + case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: + /* Default Strap Settings 5-7 */ + /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ + /* Read Serial Device Strap Register1 in PPC440EP */ + mfsdr(sdr_sdstp1, sdr0_sdstp1); + boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + computed_boot_device = BOOT_FROM_SMALL_FLASH; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + computed_boot_device = BOOT_FROM_PCI; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + computed_boot_device = BOOT_FROM_NAND_FLASH0; + break; + } + break; + } + } + + /*-------------------------------------------------------------------------+ + | + | PART 3 : Compute EBC settings depending on selected boot device + | ====== ====================================================== + | + | Resulting EBC init will be among following configurations : + | + | - Boot from EBC 8bits => boot from SMALL FLASH selected + | EBC-CS0 = Small Flash + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Soft Config + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from EBC 16bits => boot from Large Flash or SRAM selected + | EBC-CS0 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = Small Flash + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from NAND Flash + | EBC-CS0 = NAND Flash0 + | EBC-CS1,2,3 = NAND Flash1 + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + | - Boot from PCI + | EBC-CS0 = ... + | EBC-CS1,2,3 = NAND Flash or + | Exp.Slot depending on Software Configuration + | EBC-CS4 = SRAM/Large Flash or + | Large Flash/SRAM or + | Small Flash depending on jumpers + | EBC-CS5 = NVRAM / EPLD + | + +-------------------------------------------------------------------------*/ + + switch(computed_boot_device) { + /*------------------------------------------------------------------------- */ + case BOOT_FROM_SMALL_FLASH: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_LARGE_FLASH_OR_SRAM: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_NAND_FLASH0: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = 0; + ebc0_cs0_bncr_value = 0; + + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + + /* Large Flash or SRAM */ + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_FROM_PCI: + /*------------------------------------------------------------------------- */ + ebc0_cs0_bnap_value = 0; + ebc0_cs0_bncr_value = 0; + + if ((is_nand_selected()) == TRUE) { + /* NAND Flash */ + ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; + ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } else { + /* Expansion Slot */ + ebc0_cs1_bnap_value = 0; + ebc0_cs1_bncr_value = 0; + ebc0_cs2_bnap_value = 0; + ebc0_cs2_bncr_value = 0; + ebc0_cs3_bnap_value = 0; + ebc0_cs3_bncr_value = 0; + } + + if ((config_on_ebc_cs4_is_small_flash()) == TRUE) { + /* Small Flash */ + ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; + ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; + } else { + /* Large Flash or SRAM */ + ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; + ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4; + } + + break; + + /*------------------------------------------------------------------------- */ + case BOOT_DEVICE_UNKNOWN: + /*------------------------------------------------------------------------- */ + /* Error */ + break; + + } + + + /*-------------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + EBC0_CFG_PTD_ENABLED | + EBC0_CFG_RTC_2048PERCLK | + EBC0_CFG_EMPL_LOW | + EBC0_CFG_EMPH_LOW | + EBC0_CFG_CSTC_DRIVEN | + EBC0_CFG_BPF_ONEDW | + EBC0_CFG_EMS_8BIT | + EBC0_CFG_PME_DISABLED | + EBC0_CFG_PMT_ENCODE(0) ); + + /*-------------------------------------------------------------------------+ + | Initialize EBC Bank 0-4 + +-------------------------------------------------------------------------*/ + /* EBC Bank0 */ + mtebc(pb0ap, ebc0_cs0_bnap_value); + mtebc(pb0cr, ebc0_cs0_bncr_value); + /* EBC Bank1 */ + mtebc(pb1ap, ebc0_cs1_bnap_value); + mtebc(pb1cr, ebc0_cs1_bncr_value); + /* EBC Bank2 */ + mtebc(pb2ap, ebc0_cs2_bnap_value); + mtebc(pb2cr, ebc0_cs2_bncr_value); + /* EBC Bank3 */ + mtebc(pb3ap, ebc0_cs3_bnap_value); + mtebc(pb3cr, ebc0_cs3_bncr_value); + /* EBC Bank4 */ + mtebc(pb4ap, ebc0_cs4_bnap_value); + mtebc(pb4cr, ebc0_cs4_bncr_value); + + return; +} + + +/*----------------------------------------------------------------------------+ + | get_uart_configuration. + +----------------------------------------------------------------------------*/ +uart_config_nb_t get_uart_configuration(void) +{ + return (L4); +} + +/*----------------------------------------------------------------------------+ + | set_phy_configuration_through_fpga => to EPLD + +----------------------------------------------------------------------------*/ +void set_phy_configuration_through_fpga(zmii_config_t config) +{ + + unsigned long fpga_selection_reg; + + fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK; + + switch(config) + { + case ZMII_CONFIGURATION_IS_MII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII; + break; + case ZMII_CONFIGURATION_IS_RMII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII; + break; + case ZMII_CONFIGURATION_IS_SMII: + fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII; + break; + case ZMII_CONFIGURATION_UNKNOWN: + default: + break; + } + out8(FPGA_SELECTION_1_REG,fpga_selection_reg); + +} + +/*----------------------------------------------------------------------------+ + | scp_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void scp_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | iic1_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void iic1_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK; + fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_a_b_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_a_b_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_a_b_unselect_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_a_b_unselect_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_c_d_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_c_d_selection_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | dma_c_d_unselect_in_fpga. + +----------------------------------------------------------------------------*/ +void dma_c_d_unselect_in_fpga(void) +{ + unsigned long fpga_selection_2_reg; + + fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D; + out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_device_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void usb2_device_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_device_reset_through_fpga. + +----------------------------------------------------------------------------*/ +void usb2_device_reset_through_fpga(void) +{ + /* Perform soft Reset pulse */ + unsigned long fpga_reset_reg; + int i; + + fpga_reset_reg = in8(FPGA_RESET_REG); + out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV); + for (i=0; i<500; i++) + udelay(1000); + out8(FPGA_RESET_REG,fpga_reset_reg); +} + +/*----------------------------------------------------------------------------+ + | usb2_host_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void usb2_host_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | ndfc_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void ndfc_selection_in_fpga(void) +{ + unsigned long fpga_selection_1_reg; + + fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK; + fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1; + fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; + out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg); +} + +/*----------------------------------------------------------------------------+ + | uart_selection_in_fpga. + +----------------------------------------------------------------------------*/ +void uart_selection_in_fpga(uart_config_nb_t uart_config) +{ + /* FPGA register */ + unsigned char fpga_selection_3_reg; + + /* Read FPGA Reagister */ + fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG); + + switch (uart_config) + { + case L1: + /* ----------------------------------------------------------------------- */ + /* L1 configuration: UART0 = 8 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + case L2: + /* ----------------------------------------------------------------------- */ + /* L2 configuration: UART0 = 4 pins */ + /* UART1 = 4 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + case L3: + /* ----------------------------------------------------------------------- */ + /* L3 configuration: UART0 = 4 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ + /* ----------------------------------------------------------------------- */ + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + break; + + case L4: + /* Configure FPGA */ + fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK; + fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4; + out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg); + + break; + + default: + /* Unsupported UART configuration number */ + for (;;) + ; + break; + + } +} + + +/*----------------------------------------------------------------------------+ + | init_default_gpio + +----------------------------------------------------------------------------*/ +void init_default_gpio(void) +{ + int i; + + /* Init GPIO0 */ + for(i=0; i<GPIO_MAX; i++) + { + gpio_tab[GPIO0][i].add = GPIO0_BASE; + gpio_tab[GPIO0][i].in_out = GPIO_DIS; + gpio_tab[GPIO0][i].alt_nb = GPIO_SEL; + } + + /* Init GPIO1 */ + for(i=0; i<GPIO_MAX; i++) + { + gpio_tab[GPIO1][i].add = GPIO1_BASE; + gpio_tab[GPIO1][i].in_out = GPIO_DIS; + gpio_tab[GPIO1][i].alt_nb = GPIO_SEL; + } + + /* EBC_CS_N(5) - GPIO0_10 */ + gpio_tab[GPIO0][10].in_out = GPIO_OUT; + gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1; + + /* EBC_CS_N(4) - GPIO0_9 */ + gpio_tab[GPIO0][9].in_out = GPIO_OUT; + gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1; +} + +/*----------------------------------------------------------------------------+ + | update_uart_ios + +------------------------------------------------------------------------------ + | + | Set UART Configuration in PowerPC440EP + | + | +---------------------------------------------------------------------+ + | | Configuartion | Connector | Nb of pins | Pins | Associated | + | | Number | Port Name | available | naming | CORE | + | +-----------------+---------------+------------+--------+-------------+ + | | L1 | Port_A | 8 | UART | UART core 0 | + | +-----------------+---------------+------------+--------+-------------+ + | | L2 | Port_A | 4 | UART1 | UART core 0 | + | | (L2D) | Port_B | 4 | UART2 | UART core 1 | + | +-----------------+---------------+------------+--------+-------------+ + | | L3 | Port_A | 4 | UART1 | UART core 0 | + | | (L3D) | Port_B | 2 | UART2 | UART core 1 | + | | | Port_C | 2 | UART3 | UART core 2 | + | +-----------------+---------------+------------+--------+-------------+ + | | | Port_A | 2 | UART1 | UART core 0 | + | | L4 | Port_B | 2 | UART2 | UART core 1 | + | | (L4D) | Port_C | 2 | UART3 | UART core 2 | + | | | Port_D | 2 | UART4 | UART core 3 | + | +-----------------+---------------+------------+--------+-------------+ + | + | Involved GPIOs + | + | +------------------------------------------------------------------------------+ + | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O | + | +---------+------------------+-----+-----------------+-----+-------------+-----+ + | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O | + | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I | + | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I | + | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O | + | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA | + | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA | + | +------------------------------------------------------------------------------+ + | + | + +----------------------------------------------------------------------------*/ + +void update_uart_ios(uart_config_nb_t uart_config) +{ + switch (uart_config) + { + case L1: + /* ----------------------------------------------------------------------- */ + /* L1 configuration: UART0 = 8 pins */ + /* ----------------------------------------------------------------------- */ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO1][2].in_out = GPIO_IN; + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][3].in_out = GPIO_IN; + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][4].in_out = GPIO_IN; + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][5].in_out = GPIO_OUT; + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][6].in_out = GPIO_OUT; + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][7].in_out = GPIO_IN; + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1; + + break; + + case L2: + /* ----------------------------------------------------------------------- */ + /* L2 configuration: UART0 = 4 pins */ + /* UART1 = 4 pins */ + /* ----------------------------------------------------------------------- */ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO1][2].in_out = GPIO_IN; + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][3].in_out = GPIO_OUT; + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][4].in_out = GPIO_IN; + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][5].in_out = GPIO_OUT; + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][6].in_out = GPIO_OUT; + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][7].in_out = GPIO_IN; + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; + + break; + + case L3: + /* ----------------------------------------------------------------------- */ + /* L3 configuration: UART0 = 4 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ + /* ----------------------------------------------------------------------- */ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO1][2].in_out = GPIO_OUT; + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][3].in_out = GPIO_IN; + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][4].in_out = GPIO_IN; + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][5].in_out = GPIO_OUT; + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][6].in_out = GPIO_OUT; + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][7].in_out = GPIO_IN; + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; + + break; + + case L4: + /* ----------------------------------------------------------------------- */ + /* L4 configuration: UART0 = 2 pins */ + /* UART1 = 2 pins */ + /* UART2 = 2 pins */ + /* UART3 = 2 pins */ + /* ----------------------------------------------------------------------- */ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO1][2].in_out = GPIO_OUT; + gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][3].in_out = GPIO_IN; + gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][4].in_out = GPIO_IN; + gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][5].in_out = GPIO_OUT; + gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3; + + gpio_tab[GPIO1][6].in_out = GPIO_OUT; + gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][7].in_out = GPIO_IN; + gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2; + + break; + + default: + /* Unsupported UART configuration number */ + printf("ERROR - Unsupported UART configuration number.\n\n"); + for (;;) + ; + break; + + } + + /* Set input Selection Register on Alt_Receive for UART Input Core */ + out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000)); + out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000)); + out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000)); +} + +/*----------------------------------------------------------------------------+ + | update_ndfc_ios(void). + +----------------------------------------------------------------------------*/ +void update_ndfc_ios(void) +{ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */ + gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1; + +#if 0 + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */ + gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */ + gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1; +#endif +} + +/*----------------------------------------------------------------------------+ + | update_zii_ios(void). + +----------------------------------------------------------------------------*/ +void update_zii_ios(void) +{ + /* Update GPIO Configuration Table */ + gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */ + gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */ + gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */ + gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */ + gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */ + gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */ + gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */ + gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */ + gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */ + gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */ + gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */ + gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */ + gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */ + gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */ + gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1; + +} + +/*----------------------------------------------------------------------------+ + | update_uic_0_3_irq_ios(). + +----------------------------------------------------------------------------*/ +void update_uic_0_3_irq_ios(void) +{ + gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */ + gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */ + gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */ + gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */ + gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1; +} + +/*----------------------------------------------------------------------------+ + | update_uic_4_9_irq_ios(). + +----------------------------------------------------------------------------*/ +void update_uic_4_9_irq_ios(void) +{ + gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */ + gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */ + gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */ + gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */ + gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */ + gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1; +} + +/*----------------------------------------------------------------------------+ + | update_dma_a_b_ios(). + +----------------------------------------------------------------------------*/ +void update_dma_a_b_ios(void) +{ + gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */ + gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */ + gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */ + gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */ + gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */ + gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2; +} + +/*----------------------------------------------------------------------------+ + | update_dma_c_d_ios(). + +----------------------------------------------------------------------------*/ +void update_dma_c_d_ios(void) +{ + gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */ + gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */ + gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */ + gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */ + gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */ + gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */ + gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2; + +} + +/*----------------------------------------------------------------------------+ + | update_ebc_master_ios(). + +----------------------------------------------------------------------------*/ +void update_ebc_master_ios(void) +{ + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */ + gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */ + gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */ + gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1; +} + +/*----------------------------------------------------------------------------+ + | update_usb2_device_ios(). + +----------------------------------------------------------------------------*/ +void update_usb2_device_ios(void) +{ + gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */ + gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */ + gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */ + gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */ + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */ + gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */ + gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2; + + gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */ + gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1; + + gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */ + gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1; + +} + +/*----------------------------------------------------------------------------+ + | update_pci_patch_ios(). + +----------------------------------------------------------------------------*/ +void update_pci_patch_ios(void) +{ + gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */ + gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1; +} + +/*----------------------------------------------------------------------------+ + | set_chip_gpio_configuration(unsigned char gpio_core) + | Put the core impacted by clock modification and sharing in reset. + | Config the select registers to resolve the sharing depending of the config. + | Configure the GPIO registers. + | + +----------------------------------------------------------------------------*/ +void set_chip_gpio_configuration(unsigned char gpio_core) +{ + unsigned char i=0, j=0, reg_offset = 0; + unsigned long gpio_reg, gpio_core_add; + + /* GPIO config of the GPIOs 0 to 31 */ + for (i=0; i<GPIO_MAX; i++, j++) + { + if (i == GPIO_MAX/2) + { + reg_offset = 4; + j = i-16; + } + + gpio_core_add = gpio_tab[gpio_core][i].add; + + if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) || + (gpio_tab[gpio_core][i].in_out == GPIO_BI )) + { + switch (gpio_tab[gpio_core][i].alt_nb) + { + case GPIO_SEL: + break; + + case GPIO_ALT1: + gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT2: + gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg); + break; + + case GPIO_ALT3: + gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2)); + out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) || + (gpio_tab[gpio_core][i].in_out == GPIO_BI )) + { + + switch (gpio_tab[gpio_core][i].alt_nb) + { + case GPIO_SEL: + break; + case GPIO_ALT1: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + case GPIO_ALT2: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + case GPIO_ALT3: + gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg); + gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2)); + gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2)); + out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg); + break; + } + } + } +} + +/*----------------------------------------------------------------------------+ + | force_bup_core_selection. + +----------------------------------------------------------------------------*/ +void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P) +{ + /* Pointer invalid */ + if (core_select_P == NULL) + { + printf("Configuration invalid pointer 1\n"); + for (;;) + ; + } + + /* L4 Selection */ + *(core_select_P+UART_CORE0) = CORE_SELECTED; + *(core_select_P+UART_CORE1) = CORE_SELECTED; + *(core_select_P+UART_CORE2) = CORE_SELECTED; + *(core_select_P+UART_CORE3) = CORE_SELECTED; + + /* RMII Selection */ + *(core_select_P+RMII_SEL) = CORE_SELECTED; + + /* External Interrupt 0-9 selection */ + *(core_select_P+UIC_0_3) = CORE_SELECTED; + *(core_select_P+UIC_4_9) = CORE_SELECTED; + + *(core_select_P+SCP_CORE) = CORE_SELECTED; + *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED; + *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED; + *(core_select_P+USB1_DEVICE) = CORE_SELECTED; + + if (is_nand_selected()) { + *(core_select_P+NAND_FLASH) = CORE_SELECTED; + } + + *config_val_P = CONFIG_IS_VALID; + +} + +/*----------------------------------------------------------------------------+ + | configure_ppc440ep_pins. + +----------------------------------------------------------------------------*/ +void configure_ppc440ep_pins(void) +{ + uart_config_nb_t uart_configuration; + config_validity_t config_val = CONFIG_IS_INVALID; + + /* Create Core Selection Table */ + core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] = + { + CORE_NOT_SELECTED, /* IIC_CORE, */ + CORE_NOT_SELECTED, /* SPC_CORE, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */ + CORE_NOT_SELECTED, /* UIC_4_9, */ + CORE_NOT_SELECTED, /* USB2_HOST, */ + CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */ + CORE_NOT_SELECTED, /* USB2_DEVICE, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */ + CORE_NOT_SELECTED, /* USB1_DEVICE, */ + CORE_NOT_SELECTED, /* EBC_MASTER, */ + CORE_NOT_SELECTED, /* NAND_FLASH, */ + CORE_NOT_SELECTED, /* UART_CORE0, */ + CORE_NOT_SELECTED, /* UART_CORE1, */ + CORE_NOT_SELECTED, /* UART_CORE2, */ + CORE_NOT_SELECTED, /* UART_CORE3, */ + CORE_NOT_SELECTED, /* MII_SEL, */ + CORE_NOT_SELECTED, /* RMII_SEL, */ + CORE_NOT_SELECTED, /* SMII_SEL, */ + CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */ + CORE_NOT_SELECTED, /* UIC_0_3 */ + CORE_NOT_SELECTED, /* USB1_HOST */ + CORE_NOT_SELECTED /* PCI_PATCH */ + }; + + + /* Table Default Initialisation + FPGA Access */ + init_default_gpio(); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); + + /* Update Table */ + force_bup_core_selection(ppc440ep_core_selection, &config_val); +#if 0 /* test-only */ + /* If we are running PIBS 1, force known configuration */ + update_core_selection_table(ppc440ep_core_selection, &config_val); +#endif + + /*----------------------------------------------------------------------------+ + | SDR + ios table update + fpga initialization + +----------------------------------------------------------------------------*/ + unsigned long sdr0_pfc1 = 0; + unsigned long sdr0_usb0 = 0; + unsigned long sdr0_mfr = 0; + + /* PCI Always selected */ + + /* I2C Selection */ + if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL; + iic1_selection_in_fpga(); + } + + /* SCP Selection */ + if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; + scp_selection_in_fpga(); + } + + /* UIC 0:3 Selection */ + if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED) + { + update_uic_0_3_irq_ios(); + dma_a_b_unselect_in_fpga(); + } + + /* UIC 4:9 Selection */ + if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL; + update_uic_4_9_irq_ios(); + } + + /* DMA AB Selection */ + if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL; + update_dma_a_b_ios(); + dma_a_b_selection_in_fpga(); + } + + /* DMA CD Selection */ + if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED) + { + update_dma_c_d_ios(); + dma_c_d_selection_in_fpga(); + } + + /* EBC Master Selection */ + if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; + update_ebc_master_ios(); + } + + /* PCI Patch Enable */ + if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED) + { + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL; + update_pci_patch_ios(); + } + + /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */ + if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED) + { + /* Not Implemented in PowerPC 440EP Pass1-Pass2 */ + printf("Invalid configuration => USB2 Host selected\n"); + for (;;) + ; + /*usb2_host_selection_in_fpga(); */ + } + + /* USB2.0 Device Selection */ + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) + { + update_usb2_device_ios(); + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; + + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; + mtsdr(sdr_usb0, sdr0_usb0); + + usb2_device_selection_in_fpga(); + } + + /* USB1.1 Device Selection */ + if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) + { + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; + mtsdr(sdr_usb0, sdr0_usb0); + } + + /* USB1.1 Host Selection */ + if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) + { + mfsdr(sdr_usb0, sdr0_usb0); + sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; + sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; + mtsdr(sdr_usb0, sdr0_usb0); + } + + /* NAND Flash Selection */ + if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED) + { + update_ndfc_ios(); + + mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NDFC_ARE_MASK | + SDR0_CUST0_CHIPSELGAT_EN1 | + SDR0_CUST0_CHIPSELGAT_EN2); + + ndfc_selection_in_fpga(); + } + else + { + /* Set Mux on EMAC */ + mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); + } + + /* MII Selection */ + if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); + } + + /* RMII Selection */ + if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); + } + + /* SMII Selection */ + if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) + { + update_zii_ios(); + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; + mtsdr(sdr_mfr, sdr0_mfr); + + set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); + } + + /* UART Selection */ + uart_configuration = get_uart_configuration(); + switch (uart_configuration) + { + case L1: /* L1 Selection */ + /* UART0 8 pins Only */ + /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS; + break; + case L2: /* L2 Selection */ + /* UART0 and UART1 4 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + case L3: /* L3 Selection */ + /* UART0 4 pins, UART1 and UART2 2 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + case L4: /* L4 Selection */ + /* UART0, UART1, UART2 and UART3 2 pins */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR; + break; + } + update_uart_ios(uart_configuration); + + /* UART Selection in all cases */ + uart_selection_in_fpga(uart_configuration); + + /* Packet Reject Function Available */ + if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED) + { + /* Set UPR Bit in SDR0_PFC1 Register */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE; + } + + /* Packet Reject Function Enable */ + if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) + { + mfsdr(sdr_mfr, sdr0_mfr); + sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; + mtsdr(sdr_mfr, sdr0_mfr); + } + + /* Perform effective access to hardware */ + mtsdr(sdr_pfc1, sdr0_pfc1); + set_chip_gpio_configuration(GPIO0); + set_chip_gpio_configuration(GPIO1); + + /* USB2.0 Device Reset must be done after GPIO setting */ + if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED) + usb2_device_reset_through_fpga(); + +} diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h new file mode 100644 index 0000000..5f5fcde --- /dev/null +++ b/board/amcc/bamboo/bamboo.h @@ -0,0 +1,401 @@ +/* + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/*----------------------------------------------------------------------------+ + | FPGA registers and bit definitions + +----------------------------------------------------------------------------*/ +/* + * PowerPC 440EP Board FPGA is reached with physical address 0x80001FF0. + * TLB initialization makes it correspond to logical address 0x80001FF0. + * => Done init_chip.s in bootlib + */ +#define FPGA_BASE_ADDR 0x80002000 + +/*----------------------------------------------------------------------------+ + | Board Jumpers Setting Register + | Board Settings provided by jumpers + +----------------------------------------------------------------------------*/ +#define FPGA_SETTING_REG (FPGA_BASE_ADDR+0x3) +/* Boot from small flash */ +#define FPGA_SET_REG_BOOT_SMALL_FLASH 0x80 +/* Operational Flash versus SRAM position in Memory Map */ +#define FPGA_SET_REG_OP_CODE_SRAM_SEL_MASK 0x40 +#define FPGA_SET_REG_OP_CODE_FLASH_ABOVE 0x40 +#define FPGA_SET_REG_SRAM_ABOVE 0x00 +/* Boot From NAND Flash */ +#define FPGA_SET_REG_BOOT_NAND_FLASH_MASK 0x40 +#define FPGA_SET_REG_BOOT_NAND_FLASH_SELECT 0x00 +/* On Board PCI Arbiter Select */ +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL_MASK 0x10 +#define FPGA_SET_REG_PCI_EXT_ARBITER_SEL 0x00 + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 1 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_1_REG (FPGA_BASE_ADDR+0x4) +#define FPGA_SEL_1_REG_PHY_MASK 0xE0 +#define FPGA_SEL_1_REG_MII 0x80 +#define FPGA_SEL_1_REG_RMII 0x40 +#define FPGA_SEL_1_REG_SMII 0x20 +#define FPGA_SEL_1_REG_USB2_DEV_SEL 0x10 /* USB2 Device Selection */ +#define FPGA_SEL_1_REG_USB2_HOST_SEL 0x08 /* USB2 Host Selection */ +#define FPGA_SEL_1_REG_NF_SELEC_MASK 0x07 /* NF Selection Mask */ +#define FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1 0x04 /* NF0 Selected by NF_CS1 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2 0x02 /* NF1 Selected by NF_CS2 */ +#define FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3 0x01 /* NF1 Selected by NF_CS3 */ + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 2 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_2_REG (FPGA_BASE_ADDR+0x5) +#define FPGA_SEL2_REG_IIC1_SCP_SEL_MASK 0x80 /* IIC1 / SCP Selection */ +#define FPGA_SEL2_REG_SEL_FRAM 0x80 /* FRAM on IIC1 bus selected - SCP Select */ +#define FPGA_SEL2_REG_SEL_SCP 0x80 /* Identical to SCP Selection */ +#define FPGA_SEL2_REG_SEL_IIC1 0x00 /* IIC1 Selection - Default Value */ +#define FPGA_SEL2_REG_SEL_DMA_A_B 0x40 /* DMA A & B channels selected */ +#define FPGA_SEL2_REG_SEL_DMA_C_D 0x20 /* DMA C & D channels selected */ +#define FPGA_SEL2_REG_DMA_EOT_TC_3_SEL 0x10 /* 0 = EOT - input to 440EP */ + /* 1 = TC - output from 440EP */ +#define FPGA_SEL2_REG_DMA_EOT_TC_2_SEL 0x08 /* 0 = EOT (input to 440EP) */ + /* 1 = TC (output from 440EP) */ +#define FPGA_SEL2_REG_SEL_GPIO_1 0x04 /* EBC_GPIO & USB2_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_2 0x02 /* Ether._GPIO & UART_GPIO selected */ +#define FPGA_SEL2_REG_SEL_GPIO_3 0x01 /* DMA_GPIO & Trace_GPIO selected */ + +/*----------------------------------------------------------------------------+ + | Functions Selection Register 3 + +----------------------------------------------------------------------------*/ +#define FPGA_SELECTION_3_REG (FPGA_BASE_ADDR+0x6) +#define FPGA_SEL3_REG_EXP_SLOT_EN 0x80 /* Expansion Slot enabled */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG_MASK 0x70 +#define FPGA_SEL3_REG_SEL_UART_CONFIG1 0x40 /* one 8_pin UART */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG2 0x20 /* two 4_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG3 0x10 /* one 4_pin & two 2_pin UARTs */ +#define FPGA_SEL3_REG_SEL_UART_CONFIG4 0x08 /* four 2_pin UARTs */ +#define FPGA_SEL3_REG_DTR_DSR_MODE_4_PIN_UART 0x00 /* DTR/DSR mode for 4_pin_UART */ +#define FPGA_SEL3_REG_RTS_CTS_MODE_4_PIN_UART 0x04 /* RTS/CTS mode for 4_pin_UART */ + +/*----------------------------------------------------------------------------+ + | Soft Reset Register + +----------------------------------------------------------------------------*/ +#define FPGA_RESET_REG (FPGA_BASE_ADDR+0x7) +#define FPGA_RESET_REG_RESET_USB20_DEV 0x80 /* Hard Reset of the GT3200 */ +#define FPGA_RESET_REG_RESET_DISPLAY 0x40 /* Hard Reset on Display Device */ +#define FPGA_RESET_REG_STATUS_LED_0 0x08 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_1 0x04 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_2 0x02 /* 1 = Led On */ +#define FPGA_RESET_REG_STATUS_LED_3 0x01 /* 1 = Led On */ + + +/*----------------------------------------------------------------------------+ +| SDR Configuration registers ++----------------------------------------------------------------------------*/ +/* Serial Device Strap Reg 0 */ +#define SDR0_SDSTP0 0x0020 +/* Serial Device Strap Reg 1 */ +#define SDR0_SDSTP1 0x0021 +/* Serial Device Strap Reg 2 */ +#define SDR0_SDSTP2 SDR0_STRP2 +/* Serial Device Strap Reg 3 */ +#define SDR0_SDSTP3 SDR0_STRP3 + +#define sdr_pstrp0 0x0040 + +#define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ +#define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ +#define SDR0_SDSTP1_EBC_ROM_BS_8BIT 0x00000000 /* EBC 8 Bits */ + +#define SDR0_SDSTP1_BOOT_SEL_MASK 0x00001800 /* Boot device Selection Mask */ +#define SDR0_SDSTP1_BOOT_SEL_EBC 0x00000000 /* EBC */ +#define SDR0_SDSTP1_BOOT_SEL_PCI 0x00000800 /* PCI */ +#define SDR0_SDSTP1_BOOT_SEL_NDFC 0x00001000 /* NDFC */ + +/* Serial Device Enabled - Addr = 0xA8 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 +/* Serial Device Enabled - Addr = 0xA4 */ +#define SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 + +/* Pin Straps Reg */ +#define SDR0_PSTRP0 0x0040 +#define SDR0_PSTRP0_BOOTSTRAP_MASK 0xE0000000 /* Strap Bits */ + +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS1 0x20000000 /* Default strap settings 1 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS2 0x40000000 /* Default strap settings 2 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS3 0x60000000 /* Default strap settings 3 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS4 0x80000000 /* Default strap settings 4 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS5 0xA0000000 /* Default strap settings 5 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS6 0xC0000000 /* Default strap settings 6 */ +#define SDR0_PSTRP0_BOOTSTRAP_SETTINGS7 0xE0000000 /* Default strap settings 7 */ + +/*----------------------------------------------------------------------------+ +| EBC Configuration Register - EBC0_CFG ++----------------------------------------------------------------------------*/ +/* External Bus Three-State Control */ +#define EBC0_CFG_EBTC_DRIVEN 0x80000000 +/* Device-Paced Time-out Disable */ +#define EBC0_CFG_PTD_ENABLED 0x00000000 +/* Ready Timeout Count */ +#define EBC0_CFG_RTC_MASK 0x38000000 +#define EBC0_CFG_RTC_16PERCLK 0x00000000 +#define EBC0_CFG_RTC_32PERCLK 0x08000000 +#define EBC0_CFG_RTC_64PERCLK 0x10000000 +#define EBC0_CFG_RTC_128PERCLK 0x18000000 +#define EBC0_CFG_RTC_256PERCLK 0x20000000 +#define EBC0_CFG_RTC_512PERCLK 0x28000000 +#define EBC0_CFG_RTC_1024PERCLK 0x30000000 +#define EBC0_CFG_RTC_2048PERCLK 0x38000000 +/* External Master Priority Low */ +#define EBC0_CFG_EMPL_LOW 0x00000000 +#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 +#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 +#define EBC0_CFG_EMPL_HIGH 0x06000000 +/* External Master Priority High */ +#define EBC0_CFG_EMPH_LOW 0x00000000 +#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 +#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 +#define EBC0_CFG_EMPH_HIGH 0x01800000 +/* Chip Select Three-State Control */ +#define EBC0_CFG_CSTC_DRIVEN 0x00400000 +/* Burst Prefetch */ +#define EBC0_CFG_BPF_ONEDW 0x00000000 +#define EBC0_CFG_BPF_TWODW 0x00100000 +#define EBC0_CFG_BPF_FOURDW 0x00200000 +/* External Master Size */ +#define EBC0_CFG_EMS_8BIT 0x00000000 +/* Power Management Enable */ +#define EBC0_CFG_PME_DISABLED 0x00000000 +#define EBC0_CFG_PME_ENABLED 0x00020000 +/* Power Management Timer */ +#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) + +/*----------------------------------------------------------------------------+ +| Peripheral Bank Configuration Register - EBC0_BnCR ++----------------------------------------------------------------------------*/ +/* BAS - Base Address Select */ +#define EBC0_BNCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0) +/* BS - Bank Size */ +#define EBC0_BNCR_BS_MASK 0x000E0000 +#define EBC0_BNCR_BS_1MB 0x00000000 +#define EBC0_BNCR_BS_2MB 0x00020000 +#define EBC0_BNCR_BS_4MB 0x00040000 +#define EBC0_BNCR_BS_8MB 0x00060000 +#define EBC0_BNCR_BS_16MB 0x00080000 +#define EBC0_BNCR_BS_32MB 0x000A0000 +#define EBC0_BNCR_BS_64MB 0x000C0000 +#define EBC0_BNCR_BS_128MB 0x000E0000 +/* BU - Bank Usage */ +#define EBC0_BNCR_BU_MASK 0x00018000 +#define EBC0_BNCR_BU_RO 0x00008000 +#define EBC0_BNCR_BU_WO 0x00010000 +#define EBC0_BNCR_BU_RW 0x00018000 +/* BW - Bus Width */ +#define EBC0_BNCR_BW_MASK 0x00006000 +#define EBC0_BNCR_BW_8BIT 0x00000000 +#define EBC0_BNCR_BW_16BIT 0x00002000 +#define EBC0_BNCR_BW_32BIT 0x00004000 + +/*----------------------------------------------------------------------------+ +| Peripheral Bank Access Parameters - EBC0_BnAP ++----------------------------------------------------------------------------*/ +/* Burst Mode Enable */ +#define EBC0_BNAP_BME_ENABLED 0x80000000 +#define EBC0_BNAP_BME_DISABLED 0x00000000 +/* Transfert Wait */ +#define EBC0_BNAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23) /* Bits 1:8 */ +/* Chip Select On Timing */ +#define EBC0_BNAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18) /* Bits 12:13 */ +/* Output Enable On Timing */ +#define EBC0_BNAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) /* Bits 14:15 */ +/* Write Back Enable On Timing */ +#define EBC0_BNAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14) /* Bits 16:17 */ +/* Write Back Enable Off Timing */ +#define EBC0_BNAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12) /* Bits 18:19 */ +/* Transfert Hold */ +#define EBC0_BNAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9) /* Bits 20:22 */ +/* PerReady Enable */ +#define EBC0_BNAP_RE_ENABLED 0x00000100 +#define EBC0_BNAP_RE_DISABLED 0x00000000 +/* Sample On Ready */ +#define EBC0_BNAP_SOR_DELAYED 0x00000000 +#define EBC0_BNAP_SOR_NOT_DELAYED 0x00000080 +/* Byte Enable Mode */ +#define EBC0_BNAP_BEM_WRITEONLY 0x00000000 +#define EBC0_BNAP_BEM_RW 0x00000040 +/* Parity Enable */ +#define EBC0_BNAP_PEN_DISABLED 0x00000000 +#define EBC0_BNAP_PEN_ENABLED 0x00000020 + +/*----------------------------------------------------------------------------+ +| Define Boot devices ++----------------------------------------------------------------------------*/ +/* */ +#define BOOT_FROM_SMALL_FLASH 0x00 +#define BOOT_FROM_LARGE_FLASH_OR_SRAM 0x01 +#define BOOT_FROM_NAND_FLASH0 0x02 +#define BOOT_FROM_PCI 0x03 +#define BOOT_DEVICE_UNKNOWN 0x04 + + +#define PVR_POWERPC_440EP_PASS1 0x42221850 +#define PVR_POWERPC_440EP_PASS2 0x422218D3 + +#define TRUE 1 +#define FALSE 0 + +#define GPIO_GROUP_MAX 2 +#define GPIO_MAX 32 +#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */ +#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */ +#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */ +#define GPIO_MASK 0xC0000000 /* GPIO_MASK */ +#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */ + /* For the other GPIO number, you must shift */ + +#define GPIO0 0 +#define GPIO1 1 + + +/*#define MAX_SELECTION_NB CORE_NB */ +#define MAX_CORE_SELECT_NB 22 + +/*----------------------------------------------------------------------------+ + | PPC440EP GPIOs addresses. + +----------------------------------------------------------------------------*/ +#define GPIO0_BASE 0xEF600B00 +#define GPIO0_REAL 0xEF600B00 + +#define GPIO1_BASE 0xEF600C00 +#define GPIO1_REAL 0xEF600C00 + +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +/* GPIO0 */ +#define GPIO0_IS1L (GPIO0_BASE+GPIOx_IS1L) +#define GPIO0_IS1H (GPIO0_BASE+GPIOx_IS1H) +#define GPIO0_IS2L (GPIO0_BASE+GPIOx_IS2L) +#define GPIO0_IS2H (GPIO0_BASE+GPIOx_IS2H) +#define GPIO0_IS3L (GPIO0_BASE+GPIOx_IS3L) +#define GPIO0_IS3H (GPIO0_BASE+GPIOx_IS3L) + +/* GPIO1 */ +#define GPIO1_IS1L (GPIO1_BASE+GPIOx_IS1L) +#define GPIO1_IS1H (GPIO1_BASE+GPIOx_IS1H) +#define GPIO1_IS2L (GPIO1_BASE+GPIOx_IS2L) +#define GPIO1_IS2H (GPIO1_BASE+GPIOx_IS2H) +#define GPIO1_IS3L (GPIO1_BASE+GPIOx_IS3L) +#define GPIO1_IS3H (GPIO1_BASE+GPIOx_IS3L) + +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + + +/*----------------------------------------------------------------------------+ + | Declare Configuration values + +----------------------------------------------------------------------------*/ +typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t; +typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; + +typedef struct { unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ +} gpio_param_s; + +/*----------------------------------------------------------------------------+ + | XX XX + | + | XXXXXX XXX XX XXX XXX + | XX XX X XX XX XX + | XX XX X XX XX XX + | XX XX XX XX XX + | XXXXXX XXX XXX XXXX XXXX + +----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------+ + | Defines + +----------------------------------------------------------------------------*/ +typedef enum zmii_config { ZMII_CONFIGURATION_UNKNOWN, + ZMII_CONFIGURATION_IS_MII, + ZMII_CONFIGURATION_IS_RMII, + ZMII_CONFIGURATION_IS_SMII +} zmii_config_t; + +/*----------------------------------------------------------------------------+ + | Declare Configuration values + +----------------------------------------------------------------------------*/ +typedef enum uart_config_nb { L1, L2, L3, L4 } uart_config_nb_t; +typedef enum core_selection { CORE_NOT_SELECTED, CORE_SELECTED} core_selection_t; +typedef enum config_list { IIC_CORE, + SCP_CORE, + DMA_CHANNEL_AB, + UIC_4_9, + USB2_HOST, + DMA_CHANNEL_CD, + USB2_DEVICE, + PACKET_REJ_FUNC_AVAIL, + USB1_DEVICE, + EBC_MASTER, + NAND_FLASH, + UART_CORE0, + UART_CORE1, + UART_CORE2, + UART_CORE3, + MII_SEL, + RMII_SEL, + SMII_SEL, + PACKET_REJ_FUNC_EN, + UIC_0_3, + USB1_HOST, + PCI_PATCH, + CORE_NB +} core_list_t; + +typedef enum block3_value { B3_V1, B3_V2, B3_V3, B3_V4, B3_V5, + B3_V6, B3_V7, B3_V8, B3_V9, B3_V10, + B3_V11, B3_V12, B3_V13, B3_V14, B3_V15, + B3_V16, B3_VALUE_UNKNOWN +} block3_value_t; + +typedef enum config_validity { CONFIG_IS_VALID, + CONFIG_IS_INVALID +} config_validity_t; diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk new file mode 100644 index 0000000..35cb655 --- /dev/null +++ b/board/amcc/bamboo/config.mk @@ -0,0 +1,34 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF80000 + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c new file mode 100644 index 0000000..a30ab7a --- /dev/null +++ b/board/amcc/bamboo/flash.c @@ -0,0 +1,171 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <ppc440.h> +#include "bamboo.h" + +#undef DEBUG + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ + {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ + {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/ + {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/ + {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */ + {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */ + {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + unsigned long val; + unsigned long ebc_boot_size; + unsigned long boot_selection; + + mfsdr(sdr_pstrp0, val); + index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; + + if ((index == 5) || (index == 7)) { + /* + * Boot Settings in IIC EEprom address 0xA8 or 0xA4 + * Read Serial Device Strap Register1 in PPC440EP + */ + mfsdr(sdr_sdstp1, val); + boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; + ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; + + switch(boot_selection) { + case SDR0_SDSTP1_BOOT_SEL_EBC: + switch(ebc_boot_size) { + case SDR0_SDSTP1_EBC_ROM_BS_16BIT: + index = 3; + break; + case SDR0_SDSTP1_EBC_ROM_BS_8BIT: + index = 0; + break; + } + break; + + case SDR0_SDSTP1_BOOT_SEL_PCI: + index = 1; + break; + + case SDR0_SDSTP1_BOOT_SEL_NDFC: + index = 2; + break; + } + } else if (index == 0) { + if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) { + index = 8; /* sram below op code flash -> new index 8 */ + } + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S new file mode 100644 index 0000000..7820107 --- /dev/null +++ b/board/amcc/bamboo/init.S @@ -0,0 +1,113 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds new file mode 100644 index 0000000..c978dba --- /dev/null +++ b/board/amcc/bamboo/u-boot.lds @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/bamboo/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/bubinga405ep/Makefile b/board/amcc/bubinga/Makefile index 97d6a1e..f5bda55 100644 --- a/board/bubinga405ep/Makefile +++ b/board/amcc/bubinga/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o -SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c new file mode 100644 index 0000000..b4e9349 --- /dev/null +++ b/board/amcc/bubinga/bubinga.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +long int spd_sdram(void); + +#include <common.h> +#include <asm/processor.h> + +int board_early_init_f(void) +{ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000010); + mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */ + mtdcr(uictr, 0x00000010); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + unsigned char *s = getenv("serial#"); + + puts("Board: Bubinga - AMCC PPC405EP Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + +/* ------------------------------------------------------------------------- + initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + the necessary info for SDRAM controller configuration + ------------------------------------------------------------------------- */ +long int initdram(int board_type) +{ + long int ret; + + ret = spd_sdram(); + return ret; +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/walnut405/config.mk b/board/amcc/bubinga/config.mk index 8426bb3..1bdf5e4 100644 --- a/board/walnut405/config.mk +++ b/board/amcc/bubinga/config.mk @@ -21,9 +21,4 @@ # MA 02111-1307 USA # -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c new file mode 100644 index 0000000..e4832eb --- /dev/null +++ b/board/amcc/bubinga/flash.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + size_b1 = 0; + flash_info[0].size = size_b0; + } + + /* 2 banks */ + else { + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets(base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - 1, &flash_info[0]); + /* Also protect sector containing initial power-up instruction */ + /* (flash_protect() checks address range - other call ignored) */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = + flash_get_size((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets(base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b1 + size_b1 - CFG_MONITOR_LEN, + base_b1 + size_b1 - 1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + (void)flash_protect(FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - 1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + } /* else 2 banks */ + return (size_b0 + size_b1); +} + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} diff --git a/board/bubinga405ep/u-boot.lds b/board/amcc/bubinga/u-boot.lds index 3894614..b8f08ea 100644 --- a/board/bubinga405ep/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -62,7 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/bubinga405ep/init.o (.text) cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c new file mode 100644 index 0000000..3a50b09 --- /dev/null +++ b/board/amcc/common/flash.c @@ -0,0 +1,917 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) { + return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); + } else { + return flash_get_size_1(addr, info); + } +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + int n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = 0x00400000; break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + /* 1 x 16k boot sector */ + base -= 16 << 10; + --i; + info->start[i] = base; + /* 2 x 8k boot sectors */ + for (n=0; n<2; ++n) { + base -= 8 << 10; + --i; + info->start[i] = base; + } + /* 1 x 32k boot sector */ + base -= 32 << 10; + --i; + info->start[i] = base; + + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ diff --git a/board/ebony/Makefile b/board/amcc/ebony/Makefile index 4a3927b..4a3927b 100644 --- a/board/ebony/Makefile +++ b/board/amcc/ebony/Makefile diff --git a/board/ebony/config.mk b/board/amcc/ebony/config.mk index 84e3e52..e5722dd 100644 --- a/board/ebony/config.mk +++ b/board/amcc/ebony/config.mk @@ -30,7 +30,7 @@ ifeq ($(ramsym),1) TEXT_BASE = 0x07FD0000 else -TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFC0000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/ebony/ebony.c b/board/amcc/ebony/ebony.c index a5b3fb6..f6bb837 100644 --- a/board/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -20,9 +20,7 @@ * MA 02111-1307 USA */ - #include <common.h> -#include "ebony.h" #include <asm/processor.h> #include <spd_sdram.h> @@ -30,99 +28,102 @@ #define FLASH_ONBD_N 2 /* 00000010 */ #define FLASH_SRAM_SEL 1 /* 00000001 */ -long int fixed_sdram (void); +long int fixed_sdram(void); -int board_early_init_f (void) +int board_early_init_f(void) { uint reg; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; unsigned char status; - /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr (ebccfga, xbcfg); - reg = mfdcr (ebccfgd); - mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ - mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */ - mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc (pb7ap, 0x01015280); /* FPGA registers */ - mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ + mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */ + mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ + mtebc(pb7ap, 0x01015280); /* FPGA registers */ + mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ /* read FPGA_REG0 and set the bus controller */ status = *fpga_base; if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */ - mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */ - mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */ + mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ } else { - mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */ - mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ + mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */ + mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ /* set CS2 if FLASH_ONBD_N == 0 */ if (!(status & FLASH_ONBD_N)) { - mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */ - mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */ + mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ } } /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. *-------------------------------------------------------------------*/ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - mtdcr (uic0er, 0x00000000); /* disable all */ - mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ - mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ - mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ - mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic0sr, 0xffffffff); /* clear all */ - - mtdcr (uic1sr, 0xffffffff); /* clear all */ - mtdcr (uic1er, 0x00000000); /* disable all */ - mtdcr (uic1cr, 0x00000000); /* all non-critical */ - mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ - mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ - mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ - mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ return 0; } - -int checkboard (void) +int checkboard(void) { sys_info_t sysinfo; + unsigned char *s = getenv("serial#"); - get_sys_info (&sysinfo); + get_sys_info(&sysinfo); - printf ("Board: IBM 440GP Evaluation Board (Ebony)\n"); - printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); - printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); - printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); return (0); } - -long int initdram (int board_type) +long int initdram(int board_type) { long dram_size = 0; #if defined(CONFIG_SPD_EEPROM) - dram_size = spd_sdram (0); + dram_size = spd_sdram(0); #else - dram_size = fixed_sdram (); + dram_size = fixed_sdram(); #endif return dram_size; } - #if defined(CFG_DRAM_TEST) -int testdram (void) +int testdram(void) { uint *pstart = (uint *) 0x00000000; uint *pend = (uint *) 0x08000000; @@ -133,7 +134,7 @@ int testdram (void) for (p = pstart; p < pend; p++) { if (*p != 0xaaaaaaaa) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -143,7 +144,7 @@ int testdram (void) for (p = pstart; p < pend; p++) { if (*p != 0x55555555) { - printf ("SDRAM test fails at: %08x\n", (uint) p); + printf("SDRAM test fails at: %08x\n", (uint) p); return 1; } } @@ -159,18 +160,18 @@ int testdram (void) * PLB @ 133 MHz * ************************************************************************/ -long int fixed_sdram (void) +long int fixed_sdram(void) { uint reg; /*-------------------------------------------------------------------- * Setup some default *------------------------------------------------------------------*/ - mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ - mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /*-------------------------------------------------------------------- * Setup for board-specific specific mem @@ -178,28 +179,27 @@ long int fixed_sdram (void) /* * Following for CAS Latency = 2.5 @ 133 MHz PLB */ - mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ - mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ /* RA=10 RD=3 */ - mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ - mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ - mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ - udelay (400); /* Delay 200 usecs (min) */ + mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay(400); /* Delay 200 usecs (min) */ /*-------------------------------------------------------------------- * Enable the controller, then wait for DCEN to complete *------------------------------------------------------------------*/ - mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ for (;;) { - mfsdram (mem_mcsts, reg); + mfsdram(mem_mcsts, reg); if (reg & 0x80000000) break; } return (128 * 1024 * 1024); /* 128 MB */ } -#endif /* !defined(CONFIG_SPD_EEPROM) */ - +#endif /* !defined(CONFIG_SPD_EEPROM) */ /************************************************************************* * pci_pre_init @@ -214,23 +214,23 @@ long int fixed_sdram (void) * ************************************************************************/ #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) -int pci_pre_init(struct pci_controller * hose ) +int pci_pre_init(struct pci_controller *hose) { - unsigned long strap; + unsigned long strap; /*--------------------------------------------------------------------------+ * The ebony board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); - if( (strap & 0x00100000) == 0 ){ - printf("PCI: CPC0_STRP1[PAE] not set.\n"); - return 0; - } + strap = mfdcr(cpc0_strp1); + if ((strap & 0x00100000) == 0) { + printf("PCI: CPC0_STRP1[PAE] not set.\n"); + return 0; + } - return 1; + return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ /************************************************************************* * pci_target_init @@ -241,38 +241,37 @@ int pci_pre_init(struct pci_controller * hose ) * ************************************************************************/ #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) -void pci_target_init(struct pci_controller * hose ) +void pci_target_init(struct pci_controller *hose) { DECLARE_GLOBAL_DATA_PTR; /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r(PCIX0_PIM0SA, 0); /* disable */ + out32r(PCIX0_PIM1SA, 0); /* disable */ + out32r(PCIX0_PIM2SA, 0); /* disable */ + out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAH, 0); + out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - out32r( PCIX0_BAR0, 0 ); + out32r(PCIX0_BAR0, 0); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ - +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host @@ -292,7 +291,7 @@ void pci_target_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { - /* The ebony board is always configured as host. */ - return(1); + /* The ebony board is always configured as host. */ + return (1); } -#endif /* defined(CONFIG_PCI) */ +#endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c new file mode 100644 index 0000000..e8fbbc4 --- /dev/null +++ b/board/amcc/ebony/flash.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ + {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ + {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ + {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ + {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ + {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char switch_status; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + /* check the bitmap of switch status */ + if (switch_status & BOOT_SMALL_FLASH) { + index += BOOT_SMALL_FLASH_VAL; + } + if (switch_status & FLASH_ONBD_N) { + index += FLASH_ONBD_N_VAL; + } + if (switch_status & FLASH_SRAM_SEL) { + index += FLASH_SRAM_SEL_VAL; + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) + flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[2]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[2]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/ebony/init.S b/board/amcc/ebony/init.S index cc8f8b4..cc8f8b4 100644 --- a/board/ebony/init.S +++ b/board/amcc/ebony/init.S diff --git a/board/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index 7ea7caf..0ec3fad 100644 --- a/board/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -67,7 +67,7 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/ebony/init.o (.text) + board/amcc/ebony/init.o (.text) cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) diff --git a/board/ocotea/Makefile b/board/amcc/ocotea/Makefile index af223d2..af223d2 100644 --- a/board/ocotea/Makefile +++ b/board/amcc/ocotea/Makefile diff --git a/board/ocotea/config.mk b/board/amcc/ocotea/config.mk index 5543a4e..5543a4e 100644 --- a/board/ocotea/config.mk +++ b/board/amcc/ocotea/config.mk diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c new file mode 100644 index 0000000..5614e20 --- /dev/null +++ b/board/amcc/ocotea/flash.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#undef DEBUG + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ + +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ + {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ + {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ + {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ + {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ + {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ + {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ + {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ +}; + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char switch_status; + unsigned short index = 0; + int i; + + /* read FPGA base register FPGA_REG0 */ + switch_status = *fpga_base; + + /* check the bitmap of switch status */ + if (switch_status & BOOT_SMALL_FLASH) { + index += BOOT_SMALL_FLASH_VAL; + } + if (switch_status & FLASH_ONBD_N) { + index += FLASH_ONBD_N_VAL; + } + if (switch_status & FLASH_SRAM_SEL) { + index += FLASH_SRAM_SEL_VAL; + } + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = + flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/ocotea/init.S b/board/amcc/ocotea/init.S index e33427a..e33427a 100644 --- a/board/ocotea/init.S +++ b/board/amcc/ocotea/init.S diff --git a/board/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 1c532a3..5f436ea 100644 --- a/board/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -1,6 +1,9 @@ /* * Copyright (C) 2004 PaulReynolds@lhsolutions.com * + * (C) Copyright 2005 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -184,10 +187,17 @@ int board_early_init_f (void) int checkboard (void) { sys_info_t sysinfo; + unsigned char *s = getenv ("serial#"); get_sys_info (&sysinfo); - printf ("Board: IBM 440GX Evaluation Board\n"); + printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board"); + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); diff --git a/board/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h index 41bd450..41bd450 100644 --- a/board/ocotea/ocotea.h +++ b/board/amcc/ocotea/ocotea.h diff --git a/board/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 8a54617..a985246 100644 --- a/board/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -67,7 +67,7 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/ocotea/init.o (.text) + board/amcc/ocotea/init.o (.text) cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) diff --git a/board/walnut405/Makefile b/board/amcc/walnut/Makefile index 97d6a1e..f5bda55 100644 --- a/board/walnut405/Makefile +++ b/board/amcc/walnut/Makefile @@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a OBJS = $(BOARD).o flash.o -SOBJS = init.o $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) diff --git a/board/bubinga405ep/config.mk b/board/amcc/walnut/config.mk index 8426bb3..1bdf5e4 100644 --- a/board/bubinga405ep/config.mk +++ b/board/amcc/walnut/config.mk @@ -21,9 +21,4 @@ # MA 02111-1307 USA # -# -# esd ADCIOP boards -# - -#TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xFFFC0000 diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c new file mode 100644 index 0000000..056f9b9 --- /dev/null +++ b/board/amcc/walnut/flash.c @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +/* + * include common flash code (for amcc boards) + */ +#include "../common/flash.c" + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static void flash_get_offsets(ulong base, flash_info_t * info); + +unsigned long flash_init(void) +{ + unsigned long size_b0, size_b1; + int i; + uint pbcr; + unsigned long base_b0, base_b1; + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = + flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0 << 20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) { + /* Setup offsets */ + flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[0]); +#ifdef CFG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); +#endif + + size_b1 = 0; + flash_info[0].size = size_b0; + } else { + /* 2 banks */ + size_b1 = + flash_get_size((vu_long *) FLASH_BASE1_PRELIM, + &flash_info[1]); + + /* Re-do sizing to get full correct info */ + + if (size_b1) { + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb0cr); + base_b1 = -size_b1; + pbcr = + (pbcr & 0x0001ffff) | base_b1 | + (((size_b1 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb1cr = %x\n", pbcr); */ + } + + if (size_b0) { + mtdcr(ebccfga, pb1cr); + pbcr = mfdcr(ebccfgd); + mtdcr(ebccfga, pb1cr); + base_b0 = base_b1 - size_b0; + pbcr = + (pbcr & 0x0001ffff) | base_b0 | + (((size_b0 / 1024 / 1024) - 1) << 17); + mtdcr(ebccfgd, pbcr); + /* printf("pb0cr = %x\n", pbcr); */ + } + + size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); + + flash_get_offsets(base_b0, &flash_info[0]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b0 + size_b0 - monitor_flash_len, + base_b0 + size_b0 - 1, &flash_info[0]); + + if (size_b1) { + /* Re-do sizing to get full correct info */ + size_b1 = + flash_get_size((vu_long *) base_b1, &flash_info[1]); + + flash_get_offsets(base_b1, &flash_info[1]); + + /* monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + base_b1 + size_b1 - + monitor_flash_len, + base_b1 + size_b1 - 1, + &flash_info[1]); + /* monitor protection OFF by default (one is enough) */ + (void)flash_protect(FLAG_PROTECT_CLEAR, + base_b0 + size_b0 - + monitor_flash_len, + base_b0 + size_b0 - 1, + &flash_info[0]); + } else { + flash_info[1].flash_id = FLASH_UNKNOWN; + flash_info[1].sector_count = -1; + } + + flash_info[0].size = size_b0; + flash_info[1].size = size_b1; + } /* else 2 banks */ + return (size_b0 + size_b1); +} + + +static void flash_get_offsets(ulong base, flash_info_t * info) +{ + int i; + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + (info->flash_id == FLASH_AM040)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } +} diff --git a/board/walnut405/u-boot.lds b/board/amcc/walnut/u-boot.lds index 7a75f6a..7107880 100644 --- a/board/walnut405/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -62,7 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/walnut405/init.o (.text) cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c new file mode 100644 index 0000000..9fca0a6 --- /dev/null +++ b/board/amcc/walnut/walnut.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <spd_sdram.h> + +int board_early_init_f(void) +{ + /*-------------------------------------------------------------------------+ + | Interrupt controller setup for the Walnut/Sycamore board. + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive + | IRQ 16 405GP internally generated; active low; level sensitive + | IRQ 17-24 RESERVED + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive + | IRQ 27 (EXT IRQ 2) Not Used + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive + | Note for Walnut board: + | An interrupt taken for the FPGA (IRQ 25) indicates that either + | the Mouse, Keyboard, IRDA, or External Expansion caused the + | interrupt. The FPGA must be read to determine which device + | caused the interrupt. The default setting of the FPGA clears + | + +-------------------------------------------------------------------------*/ + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr(uicpr, 0xFFFFFFE0); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* set UART1 control to select CTS/RTS */ +#define FPGA_BRDC 0xF0300004 + *(volatile char *)(FPGA_BRDC) |= 0x1; + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + unsigned char *s = getenv("serial#"); + uint pvr = get_pvr(); + + if (pvr == PVR_405GPR_RB) { + puts("Board: Sycamore - AMCC PPC405GPr Evaluation Board"); + } else { + puts("Board: Walnut - AMCC PPC405GP Evaluation Board"); + } + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/* + * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! + */ +void sdram_init(void) +{ + return; +} + +/* + * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of + * the necessary info for SDRAM controller configuration + */ +long int initdram(int board_type) +{ + return spd_sdram(0); +} + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("test: xxx MB - ok\n"); + + return (0); +} diff --git a/board/amcc/yellowstone/Makefile b/board/amcc/yellowstone/Makefile new file mode 100644 index 0000000..5654f91 --- /dev/null +++ b/board/amcc/yellowstone/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +OBJS += flash.o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yellowstone/config.mk b/board/amcc/yellowstone/config.mk new file mode 100644 index 0000000..4ab0ea0 --- /dev/null +++ b/board/amcc/yellowstone/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/ocotea/flash.c b/board/amcc/yellowstone/flash.c index bc0d2c9..cd6a2e6 100644 --- a/board/ocotea/flash.c +++ b/board/amcc/yellowstone/flash.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2005 + * (C) Copyright 2002-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> @@ -15,7 +15,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -31,40 +31,35 @@ * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com */ +/* + * Ported to XPedite1000, 1/2 mb boot flash only + * Travis B. Sawyer, <travis.sawyer@sandburst.com> + */ + #include <common.h> #include <ppc4xx.h> #include <asm/processor.h> #undef DEBUG - #ifdef DEBUG #define DEBUGF(x...) printf(x) #else #define DEBUGF(x...) #endif /* DEBUG */ -#define BOOT_SMALL_FLASH 0x40 /* 01000000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ +#define BOOT_SMALL_FLASH 32 /* 00100000 */ +#define FLASH_ONBD_N 2 /* 00000010 */ +#define FLASH_SRAM_SEL 1 /* 00000001 */ -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 +#define BOOT_SMALL_FLASH_VAL 4 +#define FLASH_ONBD_N_VAL 2 +#define FLASH_SRAM_SEL_VAL 1 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +unsigned long flash_addr_table[512][CFG_MAX_FLASH_BANKS] = { + {0xfe000000} -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ - {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ - {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ - {0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */ - {0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */ - {0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */ - {0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */ - {0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */ }; /*----------------------------------------------------------------------- @@ -73,12 +68,9 @@ static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { static ulong flash_get_size(vu_long * addr, flash_info_t * info); static int write_word(flash_info_t * info, ulong dest, ulong data); - -#ifdef CONFIG_OCOTEA -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif +#define ADDR0 0xaaaa +#define ADDR1 0x5554 +#define FLASH_WORD_SIZE unsigned short /*----------------------------------------------------------------------- */ @@ -87,25 +79,9 @@ unsigned long flash_init(void) { unsigned long total_b = 0; unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; - unsigned char switch_status; unsigned short index = 0; int i; - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - DEBUGF("\n"); DEBUGF("FLASH: Index: %d\n", index); @@ -121,11 +97,14 @@ unsigned long flash_init(void) } /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]); + size_b[i] = flash_get_size((vu_long *) + flash_addr_table[index][i], + &flash_info[i]); flash_info[i].size = size_b[i]; if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i] << 20); + printf + ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); flash_info[i].sector_count = -1; flash_info[i].size = 0; } @@ -133,11 +112,9 @@ unsigned long flash_init(void) total_b += flash_info[i].size; } - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, - 0xffffffff, - &flash_info[2]); + /* FLASH protect Monitor */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, 0xFFFFFFFF, &flash_info[0]); return total_b; } @@ -161,9 +138,6 @@ void flash_print_info(flash_info_t * info) case FLASH_MAN_AMD: printf("AMD "); break; - case FLASH_MAN_STM: - printf("STM "); - break; case FLASH_MAN_FUJ: printf("FUJITSU "); break; @@ -176,6 +150,9 @@ void flash_print_info(flash_info_t * info) } switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; case FLASH_AM040: printf("AM29F040 (512 Kbit, uniform sector size)\n"); break; @@ -203,9 +180,6 @@ void flash_print_info(flash_info_t * info) case FLASH_AM320T: printf("AM29LV320T (32 Mbit, top boot sector)\n"); break; - case FLASH_AMDLV033C: - printf("AM29LV033C (32 Mbit, top boot sector)\n"); - break; case FLASH_SST800A: printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); break; @@ -230,7 +204,7 @@ void flash_print_info(flash_info_t * info) else size = info->start[0] + info->size - info->start[i]; erased = 1; - flash = (volatile unsigned long *) info->start[i]; + flash = (volatile unsigned long *)info->start[i]; size = size >> 2; /* divide by 4 for longword access */ for (k = 0; k < size; k++) { if (*flash++ != 0xffffffff) { @@ -252,6 +226,9 @@ void flash_print_info(flash_info_t * info) /*----------------------------------------------------------------------- */ +/*----------------------------------------------------------------------- + */ + /* * The following code cannot be run from FLASH! */ @@ -262,18 +239,19 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) ulong base = (ulong) addr; volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr); + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x00AA; udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = (FLASH_WORD_SIZE) 0x0055; udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; + *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = (FLASH_WORD_SIZE) 0x0090; udelay(1000); value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { @@ -293,96 +271,29 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; info->size = 0; - return (0); /* no or unknown flash */ + return (0); /* no or unknown flash */ } - value = addr2[1]; /* device ID */ +#ifdef CONFIG_ADCIOP + value = addr2[0]; /* device ID */ + debug("\ndev_code=%x\n", value); +#else + value = addr2[1]; /* device ID */ +#endif DEBUGF("\nFLASH DEVICEID: %x\n", value); - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_LV040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) STM_ID_M29W040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV033C: - info->flash_id += FLASH_AMDLV033C; - info->sector_count = 64; - info->size = 0x00400000; - break; /* => 4 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } + info->flash_id = 0; + info->sector_count = CFG_MAX_FLASH_SECT; + info->size = 0x02000000; /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || - ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - - /* For AMD29033C flash we need to resend the command of * - * reading flash protection for upper 8 Mb of flash */ - if ( i == 32 ) { - addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; + info->start[i] = (int)base + (i * 0x00020000); + info->protect[i] = 0; } - /* issue bank reset to return to read mode */ - addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - /* ? ? ? */ - } + *(FLASH_WORD_SIZE *) ((int)addr) = (FLASH_WORD_SIZE) 0x00F0; /* reset bank */ return (info->size); } @@ -391,7 +302,7 @@ int wait_for_DQ7(flash_info_t * info, int sect) { ulong start, now, last; volatile FLASH_WORD_SIZE *addr = - (FLASH_WORD_SIZE *) (info->start[sect]); + (FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; @@ -418,7 +329,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); volatile FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; - int i; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -457,24 +367,31 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); + printf("Erasing sector %p\n", addr2); + *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = + (FLASH_WORD_SIZE) 0x00AA; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = + (FLASH_WORD_SIZE) 0x0055; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = + (FLASH_WORD_SIZE) 0x0080; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr + ADDR0) = + (FLASH_WORD_SIZE) 0x00AA; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr + ADDR1) = + (FLASH_WORD_SIZE) 0x0055; + asm("sync"); + asm("isync"); + addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + asm("sync"); + asm("isync"); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } l_sect = sect; /* * Wait for each sector to complete, it's more @@ -494,6 +411,16 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* wait at least 80us - let's wait 1 ms */ udelay(1000); +#if 0 + /* + * We wait for the last triggered sector + */ + if (l_sect < 0) + goto DONE; + wait_for_DQ7(info, l_sect); + + DONE: +#endif /* reset to read mode */ addr = (FLASH_WORD_SIZE *) info->start[0]; addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ @@ -512,36 +439,45 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) { ulong cp, wp, data; int i, l, rc; + ulong status_value = 0; - wp = (addr & ~3); /* get lower word aligned address */ + wp = (addr & ~3); /* get lower word aligned address */ /* * handle unaligned start bytes */ if ((l = addr - wp) != 0) { data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; } /* * handle word aligned part */ while (cnt >= 4) { + + /*print status if needed */ + if ((wp >= (status_value + 0x20000)) + && (status_value < 0xFFFE0000)) { + status_value = wp; + printf("writing to sector 0x%X\n", status_value); + } + data = 0; for (i = 0; i < 4; ++i) { data = (data << 8) | *src++; @@ -580,14 +516,14 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) */ static int write_word(flash_info_t * info, ulong dest, ulong data) { - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); + vu_long *addr2 = (vu_long *) (info->start[0]); volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; ulong start; int i; /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & + if ((*((volatile FLASH_WORD_SIZE *)dest) & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { return (2); } @@ -598,9 +534,18 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) = + (FLASH_WORD_SIZE) 0x00AA; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR1) = + (FLASH_WORD_SIZE) 0x0055; + asm("sync"); + asm("isync"); + *(FLASH_WORD_SIZE *) ((int)addr2 + ADDR0) = + (FLASH_WORD_SIZE) 0x00A0; + asm("sync"); + asm("isync"); dest2[i] = data2[i]; @@ -621,3 +566,6 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (0); } + +/*----------------------------------------------------------------------- + */ diff --git a/board/amcc/yellowstone/init.S b/board/amcc/yellowstone/init.S new file mode 100644 index 0000000..7ba43c7 --- /dev/null +++ b/board/amcc/yellowstone/init.S @@ -0,0 +1,107 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + /* + 0xf0000000 must be first, before relocation SA_I must be off to use the + dcache as stack. It is patched after relocation to enable SA_I + */ + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/yellowstone/u-boot.lds b/board/amcc/yellowstone/u-boot.lds new file mode 100644 index 0000000..769eed3 --- /dev/null +++ b/board/amcc/yellowstone/u-boot.lds @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yellowstone/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c new file mode 100644 index 0000000..a6b81e6 --- /dev/null +++ b/board/amcc/yellowstone/yellowstone.c @@ -0,0 +1,422 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <spd_sdram.h> + +int board_early_init_f(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /*CPLD cs */ + /*setup Address lines for flash sizes larger than 16Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000); + + /*setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART1 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); + + /*setup USB 2.0 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); + out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + /*clear tmrclk divisor */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /*enable ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + + /*enable usb 1.1 fs device and remove usb 2.0 reset */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; + + /*get rid of flash write protect */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40; + + return 0; +} + +int checkboard(void) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + + printf("Board: AMCC YELLOWSTONE\n"); + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000); + printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); + return (0); +} + +/************************************************************************* + * sdram_init -- doesn't use serial presence detect. + * + * Assumes: 256 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +void sdram_init(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(mem_clktr, 0x40000000); /* ?? */ + mtsdram(mem_wddctr, 0x40000000); /* ?? */ + + /*clear this first, if the DDR is enabled by a debugger + then you can not make changes. */ + mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ + mtsdram(mem_tr0, 0x410a4012); /* ?? */ + mtsdram(mem_tr1, 0x8080080b); /* ?? */ + mtsdram(mem_rtr, 0x04080000); /* ?? */ + mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + udelay(400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram(mem_cfg0, 0x84000000); /* Enable */ + + for (;;) { + mfsdram(mem_mcsts, reg); + if (reg & 0x80000000) + break; + } +} + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram(int board) +{ + sdram_init(); + return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long strap; + unsigned long addr; + + /*--------------------------------------------------------------------------+ + * Bamboo is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PAE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return 0; + } + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440 EP PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ +} +#endif diff --git a/board/amcc/yosemite/Makefile b/board/amcc/yosemite/Makefile new file mode 100644 index 0000000..47116d3 --- /dev/null +++ b/board/amcc/yosemite/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o +SOBJS = init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk new file mode 100644 index 0000000..4ab0ea0 --- /dev/null +++ b/board/amcc/yosemite/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# esd ADCIOP boards +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S new file mode 100644 index 0000000..425ad08 --- /dev/null +++ b/board/amcc/yosemite/init.S @@ -0,0 +1,112 @@ +/* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_8M 0x00000060 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds new file mode 100644 index 0000000..62dc988 --- /dev/null +++ b/board/amcc/yosemite/u-boot.lds @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/amcc/yosemite/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/405gp_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c new file mode 100644 index 0000000..b50e99a --- /dev/null +++ b/board/amcc/yosemite/yosemite.c @@ -0,0 +1,477 @@ +/* + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <spd_sdram.h> + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +int board_early_init_f(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup the external bus controller/chip selects + *-------------------------------------------------------------------*/ + mtdcr(ebccfga, xbcfg); + reg = mfdcr(ebccfgd); + mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + + mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */ + mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */ + + mtebc(pb1ap, 0x00000000); + mtebc(pb1cr, 0x00000000); + + mtebc(pb2ap, 0x04814500); + /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */ + + mtebc(pb3ap, 0x00000000); + mtebc(pb3cr, 0x00000000); + + mtebc(pb4ap, 0x00000000); + mtebc(pb4cr, 0x00000000); + + mtebc(pb5ap, 0x00000000); + mtebc(pb5cr, 0x00000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /*-------------------------------------------------------------------- + * Setup the GPIO pins + *-------------------------------------------------------------------*/ + /*CPLD cs */ + /*setup Address lines for flash sizes larger than 16Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000); + + /*setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /*UART1 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000); + + /*setup USB 2.0 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa); + out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500); + + /*-------------------------------------------------------------------- + * Setup other serial configuration + *-------------------------------------------------------------------*/ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + /*clear tmrclk divisor */ + *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + + /*enable ethernet */ + *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + + /*enable usb 1.1 fs device and remove usb 2.0 reset */ + *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; + + /*get rid of flash write protect */ + *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40; + + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + uint pbcr; + int size_val = 0; + + /* Re-do sizing to get full correct info */ + mtdcr(ebccfga, pb0cr); + pbcr = mfdcr(ebccfgd); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtdcr(ebccfga, pb0cr); + mtdcr(ebccfgd, pbcr); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + + printf("Board: AMCC YOSEMITE\n"); + printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf("\tPER: %lu MHz\n", sysinfo.freqEPB / 1000000); + printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000); + + + return (0); +} + +/************************************************************************* + * sdram_init -- doesn't use serial presence detect. + * + * Assumes: 256 MB, ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +void sdram_init(void) +{ + register uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram(mem_clktr, 0x40000000); /* ?? */ + mtsdram(mem_wddctr, 0x40000000); /* ?? */ + + /*clear this first, if the DDR is enabled by a debugger + then you can not make changes. */ + mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */ + + mtsdram(mem_tr0, 0x410a4012); /* ?? */ + mtsdram(mem_tr1, 0x8080080b); /* ?? */ + mtsdram(mem_rtr, 0x04080000); /* ?? */ + mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */ + udelay(400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram(mem_cfg0, 0x84000000); /* Enable */ + + for (;;) { + mfsdram(mem_mcsts, reg); + if (reg & 0x80000000) + break; + } +} + +/************************************************************************* + * long int initdram + * + ************************************************************************/ +long int initdram(int board) +{ + sdram_init(); + return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_KBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long strap; + unsigned long addr; + + /*--------------------------------------------------------------------------+ + * Bamboo is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { + printf("PCI: SDR0_STRP1[PAE] not set.\n"); + printf("PCI: Configuration aborted.\n"); + return 0; + } + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440 EP PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Bamboo is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * hw_watchdog_reset + * + * This routine is called to reset (keep alive) the watchdog timer + * + ************************************************************************/ +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + +} +#endif diff --git a/board/at91rm9200dk/flash.c b/board/at91rm9200dk/flash.c index 5220fcf..f6228ef 100644 --- a/board/at91rm9200dk/flash.c +++ b/board/at91rm9200dk/flash.c @@ -259,8 +259,7 @@ void flash_print_info (flash_info_t * info) break; default: printf ("Unknown Chip Type\n"); - goto Done; - break; + return; } printf (" Size: %ld MB in %d Sectors\n", @@ -275,8 +274,6 @@ void flash_print_info (flash_info_t * info) info->protect[i] ? " (RO)" : " "); } printf ("\n"); - -Done: ; } /*----------------------------------------------------------------------- diff --git a/board/bubinga405ep/bubinga405ep.c b/board/bubinga405ep/bubinga405ep.c deleted file mode 100644 index 0be7965..0000000 --- a/board/bubinga405ep/bubinga405ep.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -long int spd_sdram (void); - -#include <common.h> -#include <asm/processor.h> - - -int board_early_init_f (void) -{ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000010); - mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ - mtdcr (uictr, 0x00000010); /* set int trigger levels */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - -#if 0 -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) - /* CS1 */ - /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */ - mtebc (pb1ap, 0x02815480); - mtebc (pb1cr, 0xF0018000); - - p = (unsigned int*)0xEF600708; - t = *p; - t = t | 0x00000400; - *p = t; - - /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ - mtebc (pb2ap, 0x04815A80); - mtebc (pb2cr, 0xF0118000); - - /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */ - mtebc (pb3ap, 0x01815280); - mtebc (pb3cr, 0xF0218000); - - /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ - mtebc (pb7ap, 0x01815280); - mtebc (pb7cr, 0xF0318000); - - - /* set UART1 control to select CTS/RTS */ -#define FPGA_BRDC 0xF0300004 - *(volatile char *) (FPGA_BRDC) |= 0x1; - -#endif - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - unsigned char *s = getenv ("serial#"); - - puts ("Board: IBM 405EP Eval Board"); - - if (s != NULL) { - puts (", serial# "); - puts (s); - } - putc ('\n'); - - return (0); -} - - -/* ------------------------------------------------------------------------- - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration - ------------------------------------------------------------------------- */ -long int initdram (int board_type) -{ - long int ret; - - ret = spd_sdram (); - return ret; -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: xxx MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/bubinga405ep/bubinga405ep.h b/board/bubinga405ep/bubinga405ep.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/bubinga405ep/bubinga405ep.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/bubinga405ep/flash.c b/board/bubinga405ep/flash.c deleted file mode 100644 index 85179d0..0000000 --- a/board/bubinga405ep/flash.c +++ /dev/null @@ -1,737 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#ifdef CONFIG_ADCIOP -#define ADDR0 0x0aa9 -#define ADDR1 0x0556 -#define FLASH_WORD_SIZE unsigned char -#endif - -#ifdef CONFIG_CPCI405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short -#endif - -#ifdef CONFIG_WALNUT405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -#ifdef CONFIG_BUBINGA405EP -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 << 20); - } - - /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM + CFG_MONITOR_LEN - 1, - &flash_info[0]); - /* Also protect sector containing initial power-up instruction */ - (void) flash_protect (FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - size_b1 = 0; - flash_info[0].size = size_b0; - } - - /* 2 banks */ - else { - size_b1 = flash_get_size ((vu_long *) FLASH_BASE1_PRELIM, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | - (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | - (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - base_b0 + size_b0 - CFG_MONITOR_LEN, - base_b0 + size_b0 - 1, &flash_info[0]); - /* Also protect sector containing initial power-up instruction */ - /* (flash_protect() checks address range - other call ignored) */ - (void) flash_protect (FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]); - (void) flash_protect (FLAG_PROTECT_SET, - 0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void) flash_protect (FLAG_PROTECT_SET, - base_b1 + size_b1 - CFG_MONITOR_LEN, - base_b1 + size_b1 - 1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void) flash_protect (FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - CFG_MONITOR_LEN, - base_b0 + size_b0 - 1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - } /* else 2 banks */ - return (size_b0 + size_b1); -} - - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count - 1)) - size = info->start[i + 1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *) info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k = 0; k < size; k++) { - if (*flash++ != 0xffffffff) { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); -#if 0 /* test-only */ - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " " -#else - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " " -#endif - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong) addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090; - -#ifdef CONFIG_ADCIOP - value = addr2[2]; -#else - value = addr2[0]; -#endif - - switch (value) { - case (FLASH_WORD_SIZE) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE) FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE) SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - -#ifdef CONFIG_ADCIOP - value = addr2[0]; /* device ID */ - /* printf("\ndev_code=%x\n", value); */ -#else - value = addr2[1]; /* device ID */ -#endif - - switch (value) { - case (FLASH_WORD_SIZE) AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE) AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE) AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE) AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE) SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE) SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - info->protect[i] = addr2[4] & 1; -#else - addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; -#endif - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#if 0 /* test-only */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile unsigned char *) info->start[0]; - addr2[ADDR0] = 0xAA; - addr2[ADDR1] = 0x55; - addr2[ADDR0] = 0xF0; /* reset bank */ -#else - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ -#endif -#else /* test-only */ - addr2 = (FLASH_WORD_SIZE *) info->start[0]; - *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ -#endif /* test-only */ - } - - return (info->size); -} - -int wait_for_DQ7 (flash_info_t * info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[sect]); - - start = get_timer (0); - last = 0; - while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); - printf ("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ - for (i = 0; i < 50; i++) - udelay (1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7 (info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7 (info, l_sect); - - DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i = 0; i < 4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_word (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/bubinga405ep/init.S b/board/bubinga405ep/init.S deleted file mode 100644 index e478525..0000000 --- a/board/bubinga405ep/init.S +++ /dev/null @@ -1,55 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Dummy implementation here - done in C later */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/bubinga405ep/u-boot.lds.debug b/board/bubinga405ep/u-boot.lds.debug deleted file mode 100644 index df50b7d..0000000 --- a/board/bubinga405ep/u-boot.lds.debug +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - -/* - cpu/ppc4xx/start.o (.text) - common/dlmalloc.o (.text) - lib_generic/vsprintf.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) -*/ - cpu/ppc4xx/start.o (.text) - board/bubinga405ep/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/405gp_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - - - common/environment.o(.text) - - *(.text) - *(.fixup) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 3acd68d..6b8aa68 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -26,12 +26,13 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <ioports.h> #include <spd.h> #include "../common/cadmus.h" #include "../common/eeprom.h" -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -40,6 +41,160 @@ extern long int spd_sdram(void); void local_bus_init(void); void sdram_init(void); +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + int board_early_init_f (void) { return 0; @@ -116,7 +271,7 @@ initdram(int board_type) #endif dram_size = spd_sdram(); -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ diff --git a/board/cds/mpc8541cds/u-boot.lds b/board/cds/mpc8541cds/u-boot.lds index f8cee53..bd697d8 100644 --- a/board/cds/mpc8541cds/u-boot.lds +++ b/board/cds/mpc8541cds/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile new file mode 100644 index 0000000..0d4abbd --- /dev/null +++ b/board/cds/mpc8548cds/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o \ + ../common/cadmus.o \ + ../common/eeprom.o + +SOBJS := init.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk new file mode 100644 index 0000000..242a676 --- /dev/null +++ b/board/cds/mpc8548cds/config.mk @@ -0,0 +1,30 @@ +# +# Copyright 2004 Freescale Semiconductor. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# mpc8548cds board +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S new file mode 100644 index 0000000..53dcd0d --- /dev/null +++ b/board/cds/mpc8548cds/init.S @@ -0,0 +1,255 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright 2002,2003, Motorola Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 16M Non-cacheable, guarded + * 0xff000000 16M FLASH + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xa0000000 256M PCI2 MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xb0000000 256M PCI2 MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + * 0xe300_0000 16M PCI2 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 7: 1M Non-cacheable, guarded + * 0xf8000000 1M CADMUS registers + */ + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) + .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M + * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * The defines below are 1-off of the actual LAWAR0 usage. + * So LAWAR3 define uses the LAWAR4 register in the ECM. + */ + +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ +#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + + .section .bootpg, "ax" + .globl law_entry + +law_entry: + entry_start + .long 6 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 + entry_end diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c new file mode 100644 index 0000000..5bc0890 --- /dev/null +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -0,0 +1,329 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <spd.h> + +#include "../common/cadmus.h" +#include "../common/eeprom.h" + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + return 0; +} + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + + /* PCI slot in USER bits CSR[6:7] by convention. */ + uint pci_slot = get_pci_slot (); + + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ + uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ + uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ + + uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + + uint cpu_board_rev = get_cpu_board_revision (); + + printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", + get_board_version (), pci_slot); + + printf ("CPU Board Revision %d.%d (0x%04x)\n", + MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), + MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); + + printf (" PCI1: %d bit, %s MHz, %s\n", + (pci1_32) ? 32 : 64, + (pci1_speed == 33000000) ? "33" : + (pci1_speed == 66000000) ? "66" : "unknown", + pci1_clk_sel ? "sync" : "async"); + + if (pci_dual) { + printf (" PCI2: 32 bit, 66 MHz, %s\n", + pci2_clk_sel ? "sync" : "async"); + } else { + printf (" PCI2: disabled\n"); + } + + /* + * Initialize local bus. + */ + local_bus_init (); + + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ + + return 0; +} + +long int +initdram(int board_type) +{ + long dram_size = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur= &immap->im_gur; + + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay(200); + } +#endif + dram_size = spd_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + /* + * SDRAM Initialization + */ + sdram_init(); + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & 0x0f) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + gur->lbiuiplldcr1 = 0x00078080; + if (clkdiv == 16) { + gur->lbiuiplldcr0 = 0x7c0f1bf0; + } else if (clkdiv == 8) { + gur->lbiuiplldcr0 = 0x6c0f1bf0; + } else if (clkdiv == 4) { + gur->lbiuiplldcr0 = 0x5c0f1bf0; + } + + lbc->lcrr |= 0x00030000; + + asm("sync;isync;msync"); +} + +/* + * Initialize SDRAM memory on the Local Bus. + */ +void +sdram_init(void) +{ +#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) + + uint idx; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + uint cpu_board_rev; + uint lsdmr_common; + + puts(" SDRAM: "); + + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers + */ + lbc->or2 = CFG_OR2_PRELIM; + asm("msync"); + + lbc->br2 = CFG_BR2_PRELIM; + asm("msync"); + + lbc->lbcr = CFG_LBC_LBCR; + asm("msync"); + + + lbc->lsrt = CFG_LBC_LSRT; + lbc->mrtpr = CFG_LBC_MRTPR; + asm("msync"); + + /* + * MPC8548 uses "new" 15-16 style addressing. + */ + cpu_board_rev = get_cpu_board_revision(); + lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + + /* + * Issue PRECHARGE ALL command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue 8 AUTO REFRESH commands. + */ + for (idx = 0; idx < 8; idx++) { + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + } + + /* + * Issue 8 MODE-set command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(100); + + /* + * Issue NORMAL OP command. + */ + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + asm("sync;msync"); + *sdram_addr = 0xff; + ppcDcbf((unsigned long) sdram_addr); + udelay(200); /* Overkill. Must wait > 200 bus cycles */ + +#endif /* enable SDRAM init */ +} + +#if defined(CFG_DRAM_TEST) +int +testdram(void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing DRAM from 0x%08x to 0x%08x\n", + CFG_MEMTEST_START, + CFG_MEMTEST_END); + + printf("DRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("DRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("DRAM test passed.\n"); + return 0; +} +#endif + +#if defined(CONFIG_PCI) + +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxcds_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxcds_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif +} diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds new file mode 100644 index 0000000..36d2407 --- /dev/null +++ b/board/cds/mpc8548cds/u-boot.lds @@ -0,0 +1,146 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/cds/mpc8548cds/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/cds/mpc8548cds/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index a6f0a43..18adf5b 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -24,12 +24,13 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <ioports.h> #include <spd.h> #include "../common/cadmus.h" #include "../common/eeprom.h" -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -38,6 +39,160 @@ extern long int spd_sdram(void); void local_bus_init(void); void sdram_init(void); +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + int board_early_init_f (void) { return 0; @@ -114,7 +269,7 @@ initdram(int board_type) #endif dram_size = spd_sdram(); -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ diff --git a/board/cds/mpc8555cds/u-boot.lds b/board/cds/mpc8555cds/u-boot.lds index d14cb9c..5d45d38 100644 --- a/board/cds/mpc8555cds/u-boot.lds +++ b/board/cds/mpc8555cds/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/cogent/README.cma286 b/board/cogent/README.cma286 index aeebc85..0345fea 100644 --- a/board/cogent/README.cma286 +++ b/board/cogent/README.cma286 @@ -65,5 +65,5 @@ PITRTCLK=65103.515625 (bloody hell!). If anyone finds anything wrong with the stuff above, I would appreciate an email about it. -Murray Jensen <Murray.Jensen@cmst.csiro.au> +Murray Jensen <Murray.Jensen@csiro.au> 21-Aug-00 diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 0bd43bd..1f6512d 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -261,7 +261,7 @@ nand_init(void) debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); totlen += nand_probe (CFG_NAND1_BASE); - printf ("%4lu MB\n", totlen >>20); + printf ("%3lu MB\n", totlen >>20); } #endif diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 1bdf5e4..5856aec 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -21,4 +21,8 @@ # MA 02111-1307 USA # +# Reserve 256 kB for Monitor TEXT_BASE = 0xFFFC0000 + +# Reserve 320 kB for Monitor +#TEXT_BASE = 0xFFFB0000 diff --git a/board/ebony/ebony.h b/board/ebony/ebony.h deleted file mode 100644 index 73d489e..0000000 --- a/board/ebony/ebony.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/ebony/flash.c b/board/ebony/flash.c deleted file mode 100644 index d8b4757..0000000 --- a/board/ebony/flash.c +++ /dev/null @@ -1,743 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> - * Add support for Am29F016D and dynamic switch setting. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - - -#undef DEBUG -#ifdef DEBUG -#define DEBUGF(x...) printf(x) -#else -#define DEBUGF(x...) -#endif /* DEBUG */ - -#define BOOT_SMALL_FLASH 32 /* 00100000 */ -#define FLASH_ONBD_N 2 /* 00000010 */ -#define FLASH_SRAM_SEL 1 /* 00000001 */ - -#define BOOT_SMALL_FLASH_VAL 4 -#define FLASH_ONBD_N_VAL 2 -#define FLASH_SRAM_SEL_VAL 1 - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { - {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ - {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */ - {0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */ - {0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */ - {0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */ - {0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */ -}; - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -#if 0 -static void flash_get_offsets (ulong base, flash_info_t *info); -#endif - -#ifdef CONFIG_ADCIOP -#define ADDR0 0x0aa9 -#define ADDR1 0x0556 -#define FLASH_WORD_SIZE unsigned char -#endif - -#ifdef CONFIG_CPCI405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short -#endif - -#ifdef CONFIG_WALNUT405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -#ifdef CONFIG_EBONY -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) { - unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char * fpga_base = (unsigned char *)CFG_FPGA_BASE; - unsigned char switch_status; - unsigned short index = 0; - int i; - - - /* read FPGA base register FPGA_REG0 */ - switch_status = *fpga_base; - - /* check the bitmap of switch status */ - if (switch_status & BOOT_SMALL_FLASH) { - index += BOOT_SMALL_FLASH_VAL; - } - if (switch_status & FLASH_ONBD_N) { - index += FLASH_ONBD_N_VAL; - } - if (switch_status & FLASH_SRAM_SEL) { - index += FLASH_SRAM_SEL_VAL; - } - - DEBUGF("\n"); - DEBUGF("FLASH: Index: %d\n", index); - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - - /* check whether the address is 0 */ - if (flash_addr_table[index][i] == 0) { - continue; - } - - /* call flash_get_size() to initialize sector address */ - size_b[i] = flash_get_size( - (vu_long *)flash_addr_table[index][i], &flash_info[i]); - flash_info[i].size = size_b[i]; - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", - i, size_b[i], size_b[i]<<20); - flash_info[i].sector_count = -1; - flash_info[i].size = 0; - } - - total_b += flash_info[i].size; - } - - return total_b; -} - - -/*----------------------------------------------------------------------- - */ -#if 0 -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AMD016: printf ("AM29F016D (16 Mbit, uniform sector size)\n"); - break; - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " - ); - } - printf ("\n"); - return; - } - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - static ulong flash_get_size (vu_long *addr, flash_info_t *info) - { - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); - - /* Write auto select command: read Manufacturer ID */ - udelay(10000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - udelay(1000); - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - udelay(1000); - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - udelay(1000); - -#ifdef CONFIG_ADCIOP - value = addr2[2]; -#else - value = addr2[0]; -#endif - - DEBUGF("FLASH MANUFACT: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - case (FLASH_WORD_SIZE)STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - -#ifdef CONFIG_ADCIOP - value = addr2[0]; /* device ID */ - debug ("\ndev_code=%x\n", value); -#else - value = addr2[1]; /* device ID */ -#endif - - DEBUGF("\nFLASH DEVICEID: %x\n", value); - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F016D: - info->flash_id += FLASH_AMD016; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - case (FLASH_WORD_SIZE)STM_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040) || - (info->flash_id == FLASH_AMD016)) { - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[4] & 1; -#else - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; -#endif - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#if 0 /* test-only */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile unsigned char *)info->start[0]; - addr2[ADDR0] = 0xAA; - addr2[ADDR1] = 0x55; - addr2[ADDR0] = 0xF0; /* reset bank */ -#else - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif -#else /* test-only */ - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif /* test-only */ - } - - return (info->size); - } - - int wait_for_DQ7(flash_info_t *info, int sect) - { - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; - } - -/*----------------------------------------------------------------------- - */ - - int flash_erase (flash_info_t *info, int s_first, int s_last) - { - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - - DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; - } - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - - int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) - { - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); - } - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - static int write_word (flash_info_t * info, ulong dest, ulong data) - { - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); - } - -/*----------------------------------------------------------------------- - */ diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S index 3f88bc2..2a9b33e 100644 --- a/board/eltec/bab7xx/asm_init.S +++ b/board/eltec/bab7xx/asm_init.S @@ -24,6 +24,7 @@ */ #include <config.h> +#include <asm/processor.h> #include <74xx_7xx.h> #include <mpc106.h> #include <version.h> diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c index 077f2c9..1e75377 100644 --- a/board/eltec/bab7xx/l2cache.c +++ b/board/eltec/bab7xx/l2cache.c @@ -27,6 +27,7 @@ #include <pci.h> #include <mpc106.h> +#include <asm/processor.h> /* defines L2CR register for MPC750 */ diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S index a5605b7..1b8d399 100644 --- a/board/eltec/elppc/asm_init.S +++ b/board/eltec/elppc/asm_init.S @@ -24,6 +24,7 @@ */ #include <config.h> +#include <asm/processor.h> #include <version.h> #include <mpc106.h> diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile new file mode 100644 index 0000000..8b10993 --- /dev/null +++ b/board/ep8248/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/ep8248/config.mk b/board/ep8248/config.mk new file mode 100644 index 0000000..eda523b --- /dev/null +++ b/board/ep8248/config.mk @@ -0,0 +1,30 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# EP82xx series boards by Embedded Planet +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c new file mode 100644 index 0000000..69975ca --- /dev/null +++ b/board/ep8248/ep8248.c @@ -0,0 +1,263 @@ +/* + * Copyright (C) 2004 Arabella Software Ltd. + * Yuli Barcohen <yuli@arabellasw.com> + * + * Support for Embedded Planet EP8248 boards. + * Tested on EP8248E. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */ + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +int board_early_init_f (void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + bcsr[4] |= 0x30; /* Turn the LEDs off */ + +#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC) + bcsr[6] |= 0x10; +#endif +#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC) + bcsr[7] |= 0x10; +#endif + +#if CFG_FCC1 + bcsr[8] |= 0xC0; +#endif /* CFG_FCC1 */ +#if CFG_FCC2 + bcsr[8] |= 0x30; +#endif /* CFG_FCC2 */ + + return 0; +} + +long int initdram(int board_type) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + long int msize = 16L << (bcsr[2] & 3); + +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + uchar c = 0xFF; + uint psdmr = CFG_PSDMR; + int i; + + immap->im_siu_conf.sc_ppc_acr = 0x02; + immap->im_siu_conf.sc_ppc_alrh = 0x30126745; + immap->im_siu_conf.sc_tescr1 = 0x00004000; + + memctl->memc_mptpr = CFG_MPTPR; + + /* Initialise 60x bus SDRAM */ + memctl->memc_psrt = CFG_PSRT; + memctl->memc_or1 = CFG_SDRAM_OR; + memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ + for (i = 0; i < 8; i++) + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ + *ramaddr = c; + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ + *ramaddr = c; +#endif /* !CFG_RAMBOOT */ + + /* Return total 60x bus SDRAM size */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + vu_char *bcsr = (vu_char *)CFG_BCSR; + + puts("Board: "); + switch (bcsr[0]) { + case 0x0C: + printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]); + break; + default: + printf("unknown: ID=%02X\n", bcsr[0]); + } + + return 0; +} diff --git a/board/ebony/u-boot.lds.debug b/board/ep8248/u-boot.lds index af497b1..d6f35f3 100644 --- a/board/ebony/u-boot.lds.debug +++ b/board/ep8248/u-boot.lds @@ -1,7 +1,9 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Modified by Yuli Barcohen <yuli@arabellasw.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -22,9 +24,6 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ @@ -53,27 +52,14 @@ SECTIONS .plt : { *(.plt) } .text : { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - ppc/vsprintf.o (.text) - ppc/crc32.o (.text) - ppc/extable.o (.text) - - common/environment.o(.text) - + cpu/mpc8260/start.o (.text) *(.text) *(.fixup) *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { + . = ALIGN(16); *(.rodata) *(.rodata1) + *(.rodata.str1.4) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } @@ -91,8 +77,8 @@ SECTIONS _FIXUP_TABLE_ = .; *(.fixup) } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; .data : { @@ -133,3 +119,4 @@ SECTIONS _end = . ; PROVIDE (end = .); } +ENTRY(_start) diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 2aa2b57..7db2a60 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -141,6 +141,20 @@ int board_early_init_f (void) } +int misc_init_r (void) +{ + unsigned long cntrl0Reg; + + /* + * Setup UART1 handshaking: use CTS instead of DSR + */ + cntrl0Reg = mfdcr(cntrl0); + mtdcr(cntrl0, cntrl0Reg | 0x00001000); + + return (0); +} + + /* * Check Board Identity: */ diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index cb458eb..d1b6807 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -77,10 +77,10 @@ int board_revision(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ /* * Restore GPIO settings @@ -88,18 +88,18 @@ int board_revision(void) mtdcr(cntrl0, cntrl0Reg); switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version 1.0 and 1.1 */ + case 0x00100200: + /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */ return 1; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 1.2 */ + case 0x00000200: + /* CS2==0 && IRQ5==1 -> version 1.2 */ return 2; + case 0x00000000: + /* CS2==0 && IRQ5==0 -> version 1.3 */ + return 3; #if 0 /* not yet manufactured ! */ case 0x00100000: - /* CS2==1 && CS3==0 -> version 1.3 */ - return 3; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 1.4 */ + /* CS2==1 && IRQ5==0 -> version 1.4 */ return 4; #endif default: @@ -393,3 +393,48 @@ int testdram (void) } /* ------------------------------------------------------------------------- */ +int wpeeprom(int wp) +{ + int wp_state = wp; + volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404; + + if (wp == 1) { + *uart1_mcr &= ~0x02; + } else if (wp == 0) { + *uart1_mcr |= 0x02; + } else { + if (*uart1_mcr & 0x02) { + wp_state = 0; + } else { + wp_state = 1; + } + } + return wp_state; +} + +int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int wp = -1; + if (argc >= 2) { + if (argv[1][0] == '1') { + wp = 1; + } else if (argv[1][0] == '0') { + wp = 0; + } + } + + wp = wpeeprom(wp); + printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED"); + return 0; +} + +U_BOOT_CMD( + wpeeprom, 2, 1, do_wpeeprom, + "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", + "wpeeprom\n" + " - check I2C EEPROM write protection state\n" + "wpeeprom 1\n" + " - enable I2C EEPROM write protection\n" + "wpeeprom 0\n" + " - disable I2C EEPROM write protection\n" + ); diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c index 71fde48..fdc02e3 100644 --- a/board/esd/wuh405/fpgadata.c +++ b/board/esd/wuh405/fpgadata.c @@ -1,1725 +1,1818 @@ - 0x1f,0x8b,0x08,0x08,0x72,0xdc,0x88,0x41,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x30,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x7b,0x78,0x14,0xd7, - 0x95,0x2f,0xba,0x7a,0x57,0x21,0x4a,0xdd,0x2d,0x75,0x59,0x40,0x46,0x31,0x36,0x94, - 0x5a,0x82,0x34,0x72,0xab,0x69,0x1a,0x22,0xcb,0xb2,0xdc,0x2a,0x04,0x93,0x28,0x40, - 0x82,0xc6,0xc9,0x9c,0xcf,0x33,0xc9,0x75,0xda,0x0e,0xc9,0x61,0x7c,0x70,0x8e,0xe2, - 0xc9,0xbd,0x87,0x38,0x1e,0xa7,0xf4,0x30,0x88,0xc7,0x98,0x36,0x78,0x12,0x9c,0xf8, - 0x66,0x8a,0x47,0x62,0xec,0x90,0x9c,0x06,0xd9,0x46,0x18,0xc6,0x2e,0xb0,0xe2,0x88, - 0x87,0x41,0x71,0x3c,0x19,0x6c,0x13,0xd2,0x38,0xb2,0x2d,0x63,0x19,0xcb,0x98,0x38, - 0x92,0x85,0xd1,0x5d,0x7b,0xd7,0xa3,0xab,0xaa,0xab,0x05,0x99,0xf9,0xee,0xfd,0xe6, - 0xfb,0xee,0x68,0xfe,0x98,0x9d,0xaa,0x4d,0xb9,0xf6,0xea,0x5d,0x6b,0xfd,0xf6,0x6f, - 0xfd,0xf6,0xda,0x50,0x1c,0x1a,0xd6,0xff,0x0f,0xc0,0x77,0x07,0x88,0xff,0xeb,0xff, - 0x5c,0xb9,0x20,0xfe,0xe9,0xaf,0xce,0xfb,0x6a,0x3c,0x1e,0xfb,0xe6,0xd7,0x56,0xc0, - 0x9d,0x10,0x48,0xfc,0xfd,0xa7,0xe3,0x5f,0xff,0xf6,0xb7,0xe6,0x2d,0x58,0x00,0x5f, - 0xc3,0xff,0x15,0x8f,0x2f,0x98,0x3b,0x6f,0xde,0xdc,0xf8,0x7c,0x58,0x01,0xc5,0xf3, - 0x16,0xd4,0x27,0x6a,0xeb,0xe7,0xc5,0xe1,0xeb,0xe0,0x9b,0xbf,0x73,0x1c,0xff,0x9e, - 0x78,0xe4,0xaf,0xbf,0x11,0x07,0xc5,0x07,0x00,0x93,0xe3,0xbe,0x14,0xfd,0xff,0x81, - 0xb8,0x4f,0xf2,0x81,0xd2,0x58,0x13,0x07,0x8d,0xfe,0x6f,0x30,0xee,0x17,0xc7,0x41, - 0xb2,0xff,0x6f,0x5f,0x1c,0x64,0x68,0x01,0x79,0x23,0x94,0xc5,0xe1,0xca,0x7f,0x32, - 0xaf,0x98,0xcd,0x3f,0xb3,0xff,0xf8,0x51,0xa5,0x60,0xaf,0xdc,0x5f,0xe3,0x05,0xd5, - 0x6c,0x92,0xab,0x78,0xbe,0x4f,0x06,0xeb,0xf9,0xaf,0x5e,0xd5,0xf3,0x3f,0x34,0x9f, - 0xff,0xe7,0xf6,0x87,0xb2,0xab,0xe8,0x0e,0xc0,0x5b,0xef,0x43,0xfb,0x13,0xc0,0xf7, - 0x8b,0x80,0x1f,0x88,0x02,0xaa,0x57,0xa3,0xb1,0xd7,0xfc,0x87,0xda,0x03,0x97,0x61, - 0x5c,0x49,0x0e,0x87,0x56,0x72,0xe7,0xe1,0x0f,0xd0,0xd8,0x55,0xaa,0x71,0xf1,0x78, - 0x2f,0x24,0x5a,0x42,0x23,0xdc,0x05,0x72,0x5c,0xf9,0x74,0x3c,0x78,0x8a,0x8b,0x43, - 0xab,0xd9,0xbf,0xfc,0x9b,0x70,0x40,0x89,0xf5,0x05,0x76,0x71,0x31,0x78,0x8f,0x24, - 0xd4,0x60,0x4f,0x59,0x0c,0xc6,0x7a,0xab,0xb7,0x06,0x32,0xed,0xaf,0xf3,0xeb,0x94, - 0xb0,0x22,0x6c,0x26,0x12,0x6f,0x5a,0xb1,0x6f,0xd2,0x46,0xa1,0x1b,0x56,0x69,0x01, - 0x95,0x1c,0x87,0x6e,0x2e,0xd2,0x1b,0xf0,0x11,0x7c,0xdb,0xbf,0xac,0x6a,0x09,0x24, - 0xc8,0x20,0x74,0xc1,0x6c,0x41,0x48,0xb7,0x13,0x90,0xcc,0xe7,0xf3,0xbb,0xe1,0x00, - 0x94,0x1e,0x0a,0xec,0x6a,0x5f,0x85,0x8d,0xb0,0x56,0x9e,0xf9,0x4c,0x14,0x1b,0x31, - 0x25,0x90,0xc1,0xfe,0xeb,0x00,0x9f,0x9f,0x26,0x71,0xde,0x7c,0x9f,0xbf,0x9a,0x36, - 0x04,0x63,0x90,0xd4,0x96,0x47,0x38,0x6c,0xf0,0x37,0x2b,0x21,0x7c,0x7f,0x08,0xc2, - 0x5f,0xc8,0x9b,0x32,0x8b,0x34,0x38,0xac,0xd4,0xca,0x41,0x89,0x13,0x17,0x9b,0xfd, - 0x55,0xdf,0x41,0x18,0x87,0xc6,0x43,0x81,0x2c,0x77,0x10,0xde,0x83,0xef,0x2a,0xcb, - 0x87,0x2b,0x87,0x84,0x71,0xc0,0x7f,0x38,0xcc,0x8d,0xc0,0x65,0xb5,0x51,0x0b,0x65, - 0x03,0x83,0x90,0x32,0xfa,0xf7,0x8b,0xbb,0xd9,0xf3,0x43,0x3b,0x3b,0xa2,0x53,0xc7, - 0xa0,0xfe,0x78,0xa9,0xc2,0x29,0xd0,0x27,0x24,0x52,0xbb,0x33,0xdc,0x80,0x82,0xb7, - 0xe4,0xa0,0xca,0xc5,0x79,0xc9,0x1a,0x6f,0x94,0xc7,0xb7,0xd5,0x02,0x4f,0x90,0x98, - 0xfc,0x9c,0x24,0x0d,0x0b,0xf5,0x24,0x0a,0xbf,0xc9,0xd6,0xb6,0x95,0x64,0xc8,0x10, - 0x1c,0x90,0xa2,0x9a,0xa0,0x92,0xbd,0x38,0xfb,0xcd,0xf1,0x2e,0x83,0x6e,0x88,0x6a, - 0x01,0xc1,0xff,0x20,0x7f,0xa0,0x4a,0xda,0x13,0x10,0x88,0x06,0xea,0x42,0x49,0x16, - 0xe2,0xe4,0x97,0x90,0x51,0xa2,0xbe,0x88,0x48,0xea,0xf0,0x5b,0xd1,0xff,0x86,0xc5, - 0xdb,0x61,0x9f,0x52,0x93,0x0d,0xf4,0x91,0x19,0xb0,0x2f,0x2d,0xa9,0xc5,0x75,0xe4, - 0xab,0xca,0xbe,0x9d,0x1b,0x7b,0x8a,0x57,0x93,0xdf,0xc2,0x53,0xca,0x5c,0x55,0xb8, - 0x8d,0x6c,0xb5,0x9e,0xdf,0x2c,0x2c,0x93,0x3f,0x80,0x86,0x6c,0x20,0x4c,0x1e,0xac, - 0xea,0x56,0x33,0xd9,0x4d,0x50,0x79,0x18,0xb2,0x6a,0x3c,0x15,0x8c,0x73,0xc7,0x95, - 0x0b,0xd0,0x00,0xc1,0x34,0x57,0x46,0xcc,0xf9,0x20,0x4f,0x3b,0x28,0xa2,0x7d,0x7a, - 0x43,0x59,0x6e,0x48,0x1e,0x27,0x37,0x6a,0xc1,0xe1,0x29,0x07,0xe1,0x35,0xb1,0x56, - 0x45,0xfb,0x5c,0x82,0x71,0xb1,0xb1,0x73,0xf9,0x2b,0x5c,0x7f,0x91,0x69,0x1f,0x81, - 0x37,0xec,0xa3,0xa2,0xfd,0x9f,0x97,0x6a,0x95,0x50,0x17,0x27,0x91,0x3e,0x65,0xaf, - 0xbc,0x31,0xc3,0x65,0x61,0xc4,0x97,0x5c,0x88,0xb7,0xfc,0xd6,0xef,0xdb,0x57,0xfe, - 0x28,0xec,0x83,0x1a,0x2d,0xd0,0x1a,0x3e,0xcd,0xbf,0x75,0x6b,0x85,0xb2,0x34,0xce, - 0x7d,0x05,0xd6,0x42,0x85,0xe2,0x6f,0x25,0xa7,0xd4,0x27,0x23,0x78,0x2b,0x4b,0x12, - 0x96,0x3d,0x25,0xf8,0xb1,0x3e,0xde,0x95,0xe4,0x0c,0xfc,0x85,0x3a,0x2b,0xfb,0xa3, - 0x66,0x42,0x04,0x05,0x2a,0x52,0xc2,0x6a,0xf2,0x6f,0xda,0xbe,0x4c,0x4d,0x0a,0x6f, - 0x81,0xf5,0xfc,0x41,0x7e,0x23,0xda,0x13,0xed,0x5f,0x15,0xc6,0xf9,0x06,0x92,0x36, - 0x3d,0x4e,0x96,0x89,0x1d,0x20,0x29,0xfe,0x38,0x9d,0x81,0x29,0x34,0x75,0x15,0x29, - 0xb3,0x9e,0x9f,0x9d,0x36,0x08,0x1f,0x41,0x52,0x09,0xad,0xdc,0x32,0x08,0x2f,0x41, - 0xad,0xb2,0x49,0xe5,0x22,0x70,0x14,0xee,0x51,0x82,0xea,0x94,0x77,0x44,0x76,0x6b, - 0x47,0xa0,0x8e,0x37,0xc7,0xdb,0xec,0x53,0x61,0x04,0x92,0x10,0x52,0x2a,0xb3,0xc2, - 0x20,0x6d,0x68,0xdc,0xfb,0x70,0x09,0xbe,0x27,0x86,0x14,0xee,0xac,0x82,0xe3,0x95, - 0xf0,0xca,0x4b,0x60,0xce,0x7f,0x41,0xdc,0xe9,0x1b,0xa5,0x93,0xe4,0x87,0x1d,0x2b, - 0x84,0x51,0x48,0xa4,0x36,0xfd,0xd0,0xf7,0x4b,0x38,0x0b,0x89,0x85,0x68,0xf6,0x4f, - 0xf1,0xa3,0x15,0x49,0x79,0x79,0x9a,0x23,0xd6,0xf7,0xa2,0xf0,0x2b,0x60,0xbf,0x2f, - 0x26,0x0b,0xe9,0xea,0x9d,0xca,0xfe,0xa6,0xea,0x54,0x69,0x9a,0xbc,0x05,0xeb,0xe4, - 0x54,0xab,0x20,0x92,0xb9,0xf4,0xd3,0x93,0x03,0x69,0x2e,0x05,0xa2,0xd1,0xbf,0x6e, - 0x52,0x15,0xec,0x87,0x98,0x1c,0x49,0x17,0x61,0x23,0x45,0x9a,0x03,0xfd,0xe4,0x8f, - 0xc2,0xcf,0xa1,0xb2,0x39,0x92,0x26,0x51,0xdf,0x7e,0xf9,0x9b,0xf2,0xd2,0x96,0xa6, - 0x22,0x6b,0x3e,0x44,0x78,0x1e,0xf6,0x40,0x14,0x9f,0x5f,0xd4,0x09,0x7b,0xaa,0x23, - 0x4b,0xfe,0xf6,0xd6,0xf6,0x97,0xd5,0xb5,0x91,0x8a,0x25,0x42,0xda,0x1f,0xc4,0x5b, - 0x77,0xcb,0x81,0x16,0xd2,0xe4,0x33,0xe7,0xc3,0xea,0x92,0x94,0xd0,0x83,0xc3,0x0c, - 0x2a,0x9c,0x24,0x8c,0x48,0x09,0x61,0x79,0xfb,0xa2,0xac,0x32,0x28,0x55,0x76,0x09, - 0x78,0x85,0xfe,0xbe,0x3e,0x1c,0xef,0x0c,0xce,0x7c,0x9f,0xad,0xd7,0x0f,0x00,0x8e, - 0x77,0xe9,0xf2,0xfe,0x29,0xd8,0x88,0x26,0xe5,0xd2,0x34,0x47,0xaf,0x34,0x2c,0x09, - 0xbd,0xd4,0xc1,0x6e,0x2d,0x09,0x6d,0xee,0x78,0x73,0xb2,0x69,0xcf,0xf2,0x49,0xec, - 0x62,0x4b,0xa8,0x9f,0xab,0x82,0x7f,0x10,0xe6,0x37,0x85,0x5e,0xba,0x66,0x41,0xfa, - 0x45,0x29,0xd1,0x12,0x7c,0x18,0xff,0x21,0xfb,0xbe,0xd2,0x5c,0x91,0xcf,0xfc,0x7e, - 0xeb,0xca,0xb3,0xd0,0x03,0x31,0x69,0x83,0x4a,0x24,0x6c,0xd4,0x2a,0x81,0x07,0x48, - 0x85,0xdc,0xd5,0x12,0x16,0x85,0xf6,0x30,0xbb,0x25,0x08,0x4a,0xd9,0x83,0xd6,0xef, - 0xdb,0x0c,0x9d,0x6c,0xbc,0x81,0x34,0xe1,0xa1,0x5b,0x90,0xe4,0x80,0x48,0x16,0x93, - 0x36,0x9f,0x7a,0x5b,0xb9,0x18,0xee,0x85,0x3d,0x4a,0xb4,0xa9,0x59,0x3c,0x5c,0xe6, - 0x33,0xed,0xbf,0x95,0xdf,0xc9,0xec,0x19,0x48,0x17,0x45,0xf9,0xfd,0x30,0x9b,0xfe, - 0xc3,0x15,0xe8,0x76,0x24,0x79,0x65,0xba,0xe9,0x4d,0x71,0x3f,0x35,0x9d,0x48,0x7e, - 0x6a,0xcd,0x07,0x75,0x1a,0x7b,0x7f,0x39,0x34,0x75,0x51,0x15,0x3f,0x4a,0xdd,0x66, - 0x9a,0x5b,0x01,0x47,0x20,0x41,0x5f,0xfb,0x8d,0xf8,0xa8,0x92,0x94,0xa3,0x69,0x2e, - 0x62,0xf9,0xab,0x3e,0xdf,0x4e,0xbd,0xff,0xa3,0x81,0x21,0x78,0x5f,0x48,0xca,0x9b, - 0x44,0x8e,0x5d,0xd1,0xf0,0x1f,0x0e,0xf0,0xa3,0x12,0xde,0x4a,0x73,0x1f,0x59,0xfe, - 0x47,0x10,0xcd,0xf9,0x46,0xad,0x0d,0x89,0xf2,0xa8,0xc2,0x41,0xd7,0x30,0xd4,0x03, - 0x3a,0xa2,0xb3,0xcd,0x23,0xfa,0x4f,0xe3,0xb7,0xc6,0x1b,0x99,0x14,0x81,0x67,0xa8, - 0xb7,0x1c,0x24,0xbb,0xe0,0x59,0x72,0x43,0x46,0x78,0x02,0xbd,0xc7,0xb3,0x72,0xb8, - 0x07,0xdd,0xce,0xdb,0xf0,0x8c,0x1c,0x53,0x04,0x95,0x5b,0x62,0x9b,0x0f,0x86,0xff, - 0xa9,0x23,0xc1,0xdb,0xf6,0x34,0xa9,0x9d,0xb7,0xd5,0xf9,0x27,0xb5,0xec,0x69,0x8e, - 0x9c,0x0a,0xc4,0xc9,0x49,0xa9,0x3b,0xb5,0x4a,0x6b,0x8e,0x37,0xf9,0xad,0xf9,0xa6, - 0x88,0x5f,0x31,0xbe,0xdf,0xf6,0x53,0xf0,0x24,0xcc,0x51,0xf1,0x33,0x9c,0x0a,0xcf, - 0x41,0x65,0x5f,0x71,0x2b,0x39,0xed,0x7b,0x0a,0x6a,0xfa,0x84,0xbf,0x0f,0xaf,0x14, - 0xcd,0xfe,0x5d,0x5d,0xb7,0x8b,0x7f,0x52,0x6e,0xc9,0x86,0x6e,0xfb,0xd4,0x0c,0xb8, - 0xd8,0x16,0x97,0x96,0xc5,0xa7,0x7c,0x02,0x3e,0x56,0x6e,0x78,0x3d,0x70,0x7f,0xc7, - 0x19,0xf8,0x93,0xd2,0x78,0x31,0x3a,0xc2,0x55,0x87,0xcd,0xfe,0xc2,0x24,0xea,0x4f, - 0x1a,0xb3,0x21,0xf1,0xb3,0xbb,0xd4,0x8b,0xf4,0xeb,0xa3,0x6e,0x04,0xa7,0x41,0x79, - 0xe9,0x93,0xdc,0xdb,0xea,0x81,0x48,0xb2,0x3f,0xf4,0x64,0xc7,0xe1,0x76,0xd3,0x3e, - 0xc0,0x3f,0x4b,0xe3,0xd7,0x40,0xe8,0x93,0xdc,0xd3,0xf2,0xe1,0xf4,0xdf,0x63,0x3c, - 0x22,0xa5,0xf0,0x62,0xfa,0xc6,0x70,0x70,0x84,0x4b,0xe0,0x2d,0x7c,0xd4,0x08,0xa7, - 0xa9,0xa6,0xfd,0x77,0x95,0x5f,0x27,0xe3,0xfb,0x67,0x03,0xb7,0x73,0xb7,0xf6,0x5f, - 0x54,0xa4,0xb3,0x25,0xf7,0x56,0x2e,0x87,0x97,0x32,0x73,0xb3,0x42,0x2b,0x0e,0xf2, - 0x29,0x19,0x87,0xf6,0x2d,0x72,0x6e,0xaa,0xf5,0x7c,0x85,0xf9,0xab,0xbe,0xc0,0xaf, - 0xc9,0xc3,0x87,0x3a,0xa5,0x88,0x22,0xdc,0x43,0xbe,0x04,0x0f,0x48,0x35,0x3e,0xa1, - 0x95,0x5c,0x07,0x4f,0xd3,0xfe,0xad,0xe8,0xb1,0xcd,0x3f,0x89,0xdf,0x28,0x32,0x7b, - 0x8a,0x7e,0x10,0x54,0xd8,0xa5,0x15,0xdf,0x42,0x64,0xd8,0x02,0xd1,0xd9,0x91,0xcc, - 0xad,0x02,0xec,0x85,0x68,0x36,0x50,0x4f,0xfa,0xac,0xef,0x7d,0xd7,0xb4,0x21,0x11, - 0xc7,0xab,0x85,0x24,0xb2,0x5b,0x58,0x07,0xd7,0x2a,0xc1,0x27,0xb9,0x6f,0x6e,0x3d, - 0xa2,0x52,0xc7,0xcb,0x45,0xd1,0x35,0x35,0x1e,0x0e,0x7d,0xc8,0x9d,0xb3,0xe6,0x8f, - 0xe2,0x33,0xfc,0x6d,0xba,0xe3,0x0d,0x18,0x86,0xda,0x74,0x68,0x2f,0xf7,0xae,0x84, - 0x13,0x49,0x43,0x43,0x9d,0x87,0x11,0x99,0x35,0xb2,0xd6,0xfc,0xa9,0x10,0x69,0xbc, - 0x9b,0xab,0x2d,0xd7,0xb8,0x9b,0xc5,0x4b,0xed,0xf3,0x15,0x98,0xc7,0x35,0xc0,0xc7, - 0x30,0x8f,0x3e,0xbf,0x16,0xfe,0x41,0x6a,0xd4,0x36,0x0d,0x73,0xda,0x62,0x73,0xfe, - 0x6c,0xe3,0x69,0xd8,0x9d,0xad,0x05,0x1e,0x25,0x3b,0xa0,0x47,0x8c,0xa8,0x42,0x0f, - 0xa9,0x86,0xfd,0xca,0x27,0x00,0xe3,0x97,0x84,0x0d,0x74,0xad,0x19,0x92,0x95,0xad, - 0xf9,0x30,0x89,0x45,0x67,0x2d,0xd0,0xe5,0x8f,0xa2,0xa3,0x08,0x6f,0xf7,0x67,0x58, - 0xff,0x30,0x08,0x19,0xa2,0xb6,0xe0,0x54,0xd4,0x96,0x66,0x9a,0xb2,0xd6,0x7c,0x13, - 0xa6,0x06,0x71,0xbe,0x55,0x1d,0xdf,0x90,0x6e,0xef,0x54,0xc4,0x78,0x24,0x5d,0x9d, - 0xf0,0x0b,0x5d,0x19,0xa8,0xea,0x9b,0x13,0x47,0x37,0x9e,0xa1,0xa6,0x8b,0x93,0xc3, - 0x96,0xff,0x81,0x92,0x55,0x74,0xbc,0x47,0x43,0xed,0x89,0x39,0xd9,0x9e,0xbb,0x12, - 0x5b,0x1f,0xdc,0xcb,0xcd,0xe9,0x1b,0xbd,0x33,0x71,0xdd,0xb2,0xd6,0xca,0x2a,0xfc, - 0x22,0x1a,0x0f,0x61,0x60,0xd2,0x38,0x33,0x3e,0x6e,0x9b,0x84,0x41,0xca,0x37,0xf3, - 0x48,0xa8,0x7f,0x91,0xd6,0x79,0x09,0x92,0x9d,0x25,0xbf,0xe6,0x46,0xb4,0xd1,0xba, - 0x64,0x10,0xbb,0x0d,0xa3,0xa3,0x46,0x53,0x0f,0x73,0x83,0xc4,0xc2,0x33,0x93,0x2e, - 0x9b,0x93,0x64,0x48,0xfe,0xfd,0x82,0x84,0x54,0x3a,0xcc,0xc5,0x5f,0x38,0xe6,0x4b, - 0xfc,0xba,0x64,0xc4,0x77,0x01,0x7e,0x0f,0xf3,0xf9,0xe0,0xa9,0xca,0x1c,0xfe,0x51, - 0x44,0x8a,0x7f,0xea,0xb3,0x81,0x1e,0x72,0x49,0xd9,0x94,0xaa,0x55,0x85,0x8b,0xa4, - 0x42,0xd9,0xb4,0x6a,0x9b,0x86,0x86,0x7a,0x13,0x36,0xf5,0x6e,0xef,0x45,0x7c,0xa2, - 0x5a,0xbf,0xaf,0x00,0xc7,0x85,0x6e,0x7d,0x50,0xc7,0xb5,0xee,0xbf,0xfc,0x85,0xec, - 0x5f,0x40,0x9a,0xe5,0x1d,0xa9,0x95,0xc7,0x8b,0xe3,0x24,0x0b,0x5b,0xc4,0x88,0x2c, - 0x94,0x1d,0x25,0x96,0x7f,0xd3,0xa6,0xed,0xd6,0xed,0x99,0xc1,0x68,0xf5,0x33,0x12, - 0x4b,0xfb,0x33,0x65,0x5f,0x80,0x9f,0x41,0xb5,0x26,0x64,0x9a,0x06,0xe4,0x0d,0xd8, - 0x68,0x4e,0x93,0x8c,0xe5,0x7f,0xe0,0x61,0x63,0x3e,0x64,0xb8,0x21,0x61,0x8c,0xdc, - 0x07,0x0f,0x66,0xb8,0xff,0x01,0xef,0x60,0xb7,0x92,0x0c,0x77,0x0c,0x5e,0x83,0x3a, - 0x65,0x59,0x3a,0x00,0x96,0x7f,0x38,0x0b,0x74,0x3e,0xdc,0x8c,0x46,0xa8,0xbc,0x84, - 0x61,0xf1,0xef,0x45,0xec,0x86,0xf1,0x9d,0xbf,0x91,0x9a,0xe5,0x32,0xfc,0x09,0x6a, - 0x69,0x63,0x44,0x36,0xfb,0x6b,0x62,0xee,0xf9,0x38,0x51,0x13,0x2d,0x45,0x99,0x8e, - 0x48,0xf1,0x31,0x8e,0x5d,0x79,0x1b,0xc6,0x94,0xa4,0x16,0x4c,0x07,0x6c,0xf8,0x87, - 0xc7,0xf9,0x20,0xb1,0xf7,0xbf,0x04,0x9b,0x7c,0x61,0x28,0xba,0xb4,0x3e,0xca,0x6f, - 0xe2,0x6f,0x3c,0x14,0xa4,0xf8,0xe7,0x39,0x88,0xfd,0xba,0x26,0xc3,0xdd,0x63,0xfd, - 0xbc,0xd9,0x49,0x86,0xff,0x41,0xfb,0xf0,0x3b,0x30,0x1e,0x5c,0xfb,0x64,0x51,0x33, - 0x6c,0xe0,0xab,0x0f,0x61,0xbc,0xd6,0x7c,0x5b,0x20,0x58,0x86,0xf6,0xcc,0xe1,0x9f, - 0x94,0x6f,0x06,0xc3,0x03,0xd3,0xef,0x25,0x67,0xd2,0x93,0x95,0x6d,0x83,0xd7,0x7e, - 0x97,0xdc,0x0b,0x6b,0x95,0x8a,0x41,0x74,0x44,0x2f,0xc1,0x8d,0x9d,0x35,0x83,0xc5, - 0xb7,0x91,0xdb,0x6c,0xf8,0x27,0x28,0x77,0x23,0xfe,0x09,0xd5,0x93,0xf3,0x50,0xa9, - 0xc4,0x57,0x96,0xde,0xcc,0x7d,0x01,0x3a,0x3a,0x23,0x83,0xa5,0x71,0xee,0x88,0xf8, - 0x1b,0x68,0x90,0xd1,0x3e,0x36,0xfc,0x53,0xc2,0xf0,0x61,0x2f,0x45,0x3b,0xf2,0x7b, - 0xab,0x10,0x58,0xfe,0x91,0xdb,0x28,0x8f,0xcb,0x37,0xf6,0x2f,0xa7,0xf8,0x70,0xbc, - 0xb8,0xb1,0x0f,0x43,0x55,0x0e,0xff,0xec,0x9a,0x34,0x64,0xd9,0xa7,0xfd,0xd8,0xc2, - 0xc4,0xd6,0xd0,0xbe,0xa5,0x51,0x38,0x96,0x4d,0xf4,0x07,0x19,0x3e,0xd4,0x12,0x0a, - 0xfa,0xff,0x6a,0xc8,0xf9,0x7f,0x13,0xff,0x34,0xfd,0x4e,0x5b,0x0b,0x73,0x5e,0xde, - 0xc0,0xf0,0x8f,0xb4,0xa3,0x0f,0xfd,0xc9,0xbf,0x4a,0xfb,0x84,0x88,0x56,0xdd,0x4a, - 0xf6,0x5a,0xbf,0xaf,0x26,0x1a,0xf8,0x67,0x75,0xf8,0x04,0x0e,0x73,0x0e,0x0e,0xbc, - 0xec,0xab,0xc0,0xa5,0xbf,0x3e,0xe0,0x5f,0x5d,0x74,0x06,0x6f,0xdd,0xf1,0x7a,0xf9, - 0x6d,0xb8,0x66,0x31,0xed,0xdf,0x3c,0x35,0x67,0x4f,0xd8,0x00,0x91,0x6c,0x20,0x53, - 0x56,0xe2,0x43,0xfc,0xa3,0x09,0xf1,0xa2,0x17,0x95,0x6e,0x5f,0x75,0xd6,0x1f,0xf7, - 0x6f,0xb6,0xe6,0xe7,0xe0,0xb4,0x5d,0x70,0x81,0xba,0x59,0x95,0x1b,0x84,0xa3,0x7c, - 0x7d,0x7b,0x40,0x85,0xbf,0x25,0xeb,0x31,0xb0,0xc6,0x54,0xee,0x9c,0xf4,0x11,0xcc, - 0x57,0x97,0x3d,0xc1,0xd5,0xe7,0xf0,0x0f,0x64,0xcd,0x78,0xa4,0x61,0xa3,0x94,0xc2, - 0x1e,0x7a,0xa5,0x81,0x5e,0x39,0x2b,0x8e,0xc0,0xd3,0xf4,0x4a,0x0e,0xff,0x74,0x89, - 0x34,0x3e,0x26,0x28,0x68,0x19,0xf0,0xd1,0xb0,0x18,0x4a,0x4f,0xa9,0x92,0x8e,0xf8, - 0x58,0x58,0x1f,0x90,0x31,0xf0,0x2d,0x8c,0x3d,0xe4,0xc6,0x3f,0xb0,0x1d,0xfb,0x87, - 0x07,0x28,0xda,0x7f,0x29,0xf0,0xfd,0xb2,0x2a,0x6c,0xc4,0xe4,0x92,0x34,0x79,0x0f, - 0x1e,0x81,0xd2,0xdb,0x22,0x69,0xbf,0x64,0xc5,0xa3,0x72,0x9e,0xe2,0x9f,0x6a,0x1a, - 0xa6,0x07,0xe0,0x71,0xd8,0xde,0x1c,0x78,0x08,0xf1,0xf6,0xe3,0x40,0x11,0x14,0x59, - 0x21,0xed,0x5f,0x18,0x93,0xab,0x45,0x52,0x64,0xcd,0x37,0x81,0xa7,0x78,0x20,0x42, - 0x61,0x40,0xef,0x4e,0x5f,0x44,0x92,0x8f,0x95,0xb5,0x57,0xa9,0x6d,0x91,0xe8,0x92, - 0x62,0xbc,0x02,0x0f,0x61,0x03,0xf1,0xb6,0x35,0x1d,0x10,0x50,0xa4,0x70,0x74,0xf5, - 0x74,0x74,0xd9,0x76,0x55,0x4a,0x40,0xa8,0xbd,0x12,0xda,0x07,0xa5,0xa4,0x80,0x61, - 0x17,0x6f,0x61,0xa3,0x14,0xb8,0x52,0x62,0xe1,0x9f,0x69,0x34,0x9a,0xd7,0xca,0x93, - 0x71,0x74,0x4f,0x8e,0xce,0xc1,0x68,0xbe,0x79,0xdd,0x45,0x75,0x34,0x92,0x5c,0x32, - 0x39,0xed,0x1b,0x80,0xbf,0x82,0x46,0x0a,0x84,0xde,0x2c,0x32,0xe7,0xc3,0x56,0xc4, - 0x3f,0x1f,0x53,0x3c,0x90,0xfe,0xef,0x03,0xd2,0x68,0xbc,0x56,0xa6,0x40,0xa8,0xe5, - 0xc8,0x9d,0x89,0xbf,0x0d,0xd2,0xfe,0x1f,0x43,0xe3,0xb2,0x68,0x0b,0x57,0x64,0xcd, - 0x9f,0x3a,0x31,0x8b,0x6e,0x36,0x06,0x01,0x85,0x9c,0x6d,0xeb,0x89,0x87,0xb1,0xd1, - 0x2e,0xc9,0x5d,0x77,0xdc,0x8f,0xb0,0x87,0x30,0xfc,0x33,0xd5,0xdf,0xde,0x5e,0x9a, - 0xf3,0x3f,0x93,0x7a,0x75,0xfc,0x23,0x92,0xce,0x5d,0x7b,0x24,0xc4,0x3f,0xf3,0xca, - 0x78,0x32,0x4f,0x96,0xe4,0x08,0x1d,0xef,0x9e,0xa9,0xd1,0x94,0xbf,0xcc,0x9f,0xf3, - 0x3f,0xe5,0xd7,0x54,0xf9,0x74,0xfc,0x83,0xf6,0xdc,0x03,0x3f,0xa5,0x40,0xa8,0x4a, - 0xd9,0x4f,0xee,0xa2,0x88,0x71,0x80,0xa7,0xb7,0xfc,0x68,0x4f,0x6b,0x3e,0x6c,0x9f, - 0x6a,0xe0,0x99,0x34,0x47,0x81,0x53,0xed,0xe7,0x7e,0x94,0x0e,0xcc,0x4a,0x8f,0x92, - 0x3b,0xe5,0x8d,0x69,0xee,0x4d,0x76,0x0b,0x11,0x60,0xa4,0xd3,0x8a,0xbf,0x60,0xf5, - 0x1f,0x10,0x46,0x49,0xbd,0x1c,0x12,0xb9,0x5e,0xc4,0x4b,0x0d,0xf4,0xca,0x9b,0xca, - 0xa8,0xde,0x38,0xa7,0x98,0xcf,0x8f,0x20,0xfe,0x19,0x14,0xd9,0x7c,0xa3,0xd3,0x2c, - 0x21,0x32,0x20,0xd4,0x0f,0xb5,0x80,0x40,0x28,0x2b,0x8d,0xc0,0xde,0x20,0xc5,0x3f, - 0x9d,0xe6,0xfc,0x97,0x78,0x03,0xff,0xa8,0xe1,0x41,0x38,0x07,0xe1,0xae,0xa5,0x03, - 0x5f,0x5c,0x29,0x3c,0x03,0x09,0x84,0x3d,0xe4,0x1c,0x3c,0xab,0x54,0xaa,0x4b,0x54, - 0x22,0xe4,0xf0,0x0f,0xfa,0x9f,0x6d,0xc6,0xf7,0xe2,0xc3,0xf5,0x42,0x56,0x48,0x90, - 0x65,0x30,0x1f,0x52,0x08,0x7b,0x60,0x19,0xec,0x38,0x2b,0x0d,0x43,0x9c,0xf8,0x2d, - 0xff,0x53,0xe1,0xbb,0x0e,0x9e,0x62,0xdf,0x6f,0xd1,0x69,0xed,0x31,0xc9,0x47,0xa3, - 0x3f,0x45,0x44,0x2b,0x7a,0xf1,0xfb,0x3d,0x2d,0x3d,0xa5,0x49,0x9a,0x7f,0xb8,0x5d, - 0x90,0xad,0xe7,0x0b,0x33,0xe0,0x0d,0xfc,0x7e,0x43,0xab,0xc9,0x19,0xf5,0x83,0x43, - 0x7b,0xee,0x2c,0xa9,0x0b,0xdc,0xae,0x8c,0xef,0xda,0x33,0x18,0x5c,0xcd,0xfd,0x2d, - 0xe2,0x9f,0x6f,0x65,0xa3,0xab,0x03,0x7e,0x6b,0x95,0x2f,0x94,0xec,0xd6,0xd1,0x20, - 0xfa,0x13,0x65,0xac,0x39,0x59,0xbe,0x29,0xc3,0xed,0x96,0xc7,0xc4,0x9b,0x5f,0x0a, - 0x65,0xc8,0xdb,0xea,0xfb,0xf4,0xd6,0x93,0x81,0xc3,0x96,0xff,0x91,0x27,0x5d,0x96, - 0x3f,0xa6,0xf8,0x67,0x84,0x3b,0xbf,0xf0,0x98,0x32,0x9f,0x36,0xc6,0xe5,0x93,0x4a, - 0x22,0x1b,0x1c,0x21,0x97,0x65,0x1a,0xda,0xa2,0x5f,0x41,0x74,0x6e,0xd9,0xff,0x1a, - 0xea,0x7f,0xa2,0x83,0x38,0xde,0x33,0xf0,0xbc,0x32,0x67,0x10,0x97,0xe1,0x27,0x94, - 0xb5,0x7b,0x2b,0xb2,0xf4,0xfd,0xc5,0x7d,0x7c,0x8d,0x26,0xb4,0x90,0x6a,0xeb,0xf7, - 0xdd,0x0c,0x8f,0xfa,0xf4,0xf1,0x92,0xd3,0xca,0x16,0xa8,0x68,0x42,0xc7,0x75,0x1a, - 0xfd,0x95,0xa4,0x95,0xb7,0x92,0x97,0xe1,0x69,0xa8,0xe9,0x17,0x5a,0x11,0x8d,0x99, - 0xf6,0x4f,0x4d,0x3d,0x6e,0xf8,0x9f,0x26,0xe6,0x7f,0xc2,0xf8,0x1f,0x7a,0x17,0x0c, - 0xff,0xd3,0x1b,0x41,0xfc,0xa3,0x09,0x75,0xe1,0xdb,0xac,0xf9,0x29,0xe1,0xfa,0x9d, - 0x0e,0x2a,0x90,0x99,0x7c,0x89,0xfb,0x67,0x08,0x67,0x66,0x62,0xe0,0x90,0x4f,0x42, - 0xb7,0xd6,0x9c,0x59,0x34,0x80,0xa1,0x30,0x99,0x09,0xf6,0x04,0x96,0x58,0xef,0xd3, - 0x09,0x39,0xfb,0xf8,0xde,0xd1,0xf1,0x21,0x7a,0x60,0xd2,0x48,0xaf,0xbc,0x81,0x8f, - 0x6a,0xc8,0x60,0x43,0xb5,0xfc,0x4f,0x9b,0x78,0x09,0x3f,0xa2,0xf9,0x18,0xd4,0xa6, - 0x5c,0xf2,0x8d,0x93,0xf9,0xe8,0xd8,0x17,0x0d,0xc1,0x49,0xbc,0x82,0xf8,0xe7,0x82, - 0xfc,0x1e,0x4e,0x0c,0x6c,0xc0,0x62,0xb3,0xff,0x21,0xc4,0x3f,0xe8,0x4f,0x68,0xfc, - 0xc2,0xd5,0x3a,0x54,0xf7,0x04,0x0e,0x72,0xbb,0xe1,0x67,0xbe,0x30,0xc6,0x53,0xf2, - 0x7a,0x64,0x7f,0x3a,0xbc,0x57,0xc8,0xf8,0xe3,0x0e,0xfc,0xf3,0x38,0x84,0xb1,0x7f, - 0x11,0xed,0x8f,0xdf,0x63,0xcf,0xe6,0x21,0x36,0xde,0x66,0xca,0x57,0xec,0x87,0xb0, - 0x24,0x88,0x45,0x52,0x0e,0xff,0xf0,0x14,0xff,0x44,0xe8,0xb2,0xf4,0xf8,0x8a,0x6e, - 0x21,0x22,0xd2,0x89,0x57,0xba,0xa3,0x59,0x3d,0x8c,0x78,0xa0,0x0f,0xbf,0x38,0x09, - 0xa8,0xff,0xb1,0xf0,0x8f,0x12,0x8c,0x0a,0x6f,0x43,0xb8,0x37,0xb4,0x87,0x3b,0x0d, - 0xcf,0x89,0x89,0xdb,0x70,0x3e,0x5c,0x92,0x7f,0x75,0xc7,0xfc,0xd3,0xd7,0x65,0xf4, - 0x2f,0x02,0xe8,0xfb,0x5b,0xf8,0x47,0xbd,0x1e,0xf1,0x0f,0xdf,0x78,0x7c,0xf2,0x05, - 0xee,0x52,0xdb,0x38,0x20,0xec,0xd1,0xd6,0xee,0xd6,0xc6,0x74,0xd8,0xc3,0xf0,0x8f, - 0x4c,0xf1,0x4f,0x91,0x1d,0xff,0x5c,0x0e,0xd7,0x66,0x4b,0xb6,0x72,0xb7,0xc3,0xdb, - 0x6d,0xf3,0xa5,0x92,0xe6,0x29,0x31,0x71,0x5c,0x99,0x9f,0x0d,0xf5,0x71,0xf7,0xc3, - 0x49,0x01,0x1b,0x38,0x59,0x72,0xfc,0x8f,0x78,0x1e,0x9e,0x49,0xd7,0x22,0xfe,0x69, - 0xfa,0x85,0xb8,0x4e,0x09,0x57,0x08,0x5d,0x24,0x86,0x88,0x28,0x7c,0x36,0xb0,0x8b, - 0x44,0x95,0xb5,0x72,0x38,0x1b,0xd8,0xee,0xe0,0x7f,0x8e,0xe3,0xf7,0x58,0xa5,0x15, - 0x67,0xf0,0xb3,0xda,0x86,0x30,0x01,0xdd,0xec,0x46,0xb6,0x30,0x47,0x0f,0xb3,0x4c, - 0xea,0x88,0x44,0xb4,0x80,0x6a,0xe7,0x7f,0x10,0xff,0x3c,0x23,0x20,0xfe,0xdc,0xd3, - 0xbe,0x1b,0x1e,0x57,0xaa,0xe3,0x42,0x57,0xd3,0x6e,0xb8,0x99,0x5a,0x58,0x25,0x41, - 0x9c,0x51,0xd5,0x87,0xb0,0x91,0xe3,0x7f,0xe4,0x69,0x43,0xfc,0x47,0x5f,0xaa,0xd5, - 0x4a,0xae,0xe3,0x96,0x41,0x56,0x4b,0xc4,0x4b,0xba,0x38,0x8a,0xa0,0x12,0x5a,0x00, - 0xb8,0x55,0x70,0x0c,0xea,0x11,0x5a,0xbb,0xf8,0x9f,0x8f,0x14,0x0a,0x1a,0x3b,0x2e, - 0x21,0xba,0xdb,0x07,0x9b,0xb4,0xc0,0x7d,0x18,0xf1,0x9f,0xd3,0xd0,0xf1,0x5e,0x22, - 0xe3,0x80,0x40,0x28,0xcb,0xd9,0xf9,0x1f,0x04,0xe1,0x32,0x82,0xa2,0x83,0x5f,0x1b, - 0x12,0xdf,0x6e,0xdd,0x0b,0xe8,0xcd,0x0c,0x44,0xd4,0x83,0x13,0xef,0x18,0xfe,0x87, - 0x30,0x74,0x0e,0xdb,0xf9,0x1f,0x04,0xf9,0x61,0x8d,0xdb,0xd5,0x14,0xeb,0x0a,0xc8, - 0x92,0x24,0x00,0xc6,0xa3,0x6e,0x1e,0x11,0xd1,0x53,0x38,0xa3,0x36,0x01,0xa1,0x03, - 0xb9,0x60,0xcd,0x87,0x41,0xf4,0x3f,0x7b,0x41,0xd5,0x02,0x0b,0xc8,0x83,0xb0,0x6d, - 0x61,0x70,0x56,0x35,0xf8,0x8d,0x2f,0x08,0x68,0x04,0x27,0x68,0x28,0x89,0x8c,0xe4, - 0xf8,0x1f,0xc4,0x3f,0x4f,0x2b,0x15,0xd9,0xc0,0xbd,0x4d,0x33,0x94,0x07,0x94,0x12, - 0x49,0x18,0x2c,0x3b,0xa3,0xdc,0xa8,0xd4,0x0c,0x72,0x2b,0xe1,0x0c,0x05,0x42,0x94, - 0x2a,0x39,0x65,0xc7,0x3f,0xb8,0x4c,0x88,0x0f,0x85,0xea,0xb9,0x07,0x95,0xb3,0x4a, - 0x43,0x73,0xa9,0xc8,0x9d,0x80,0x0f,0x94,0x86,0x41,0x74,0xbc,0x43,0xca,0xf3,0x10, - 0xa7,0xf6,0x79,0x29,0x87,0x7f,0xae,0x3f,0x08,0xff,0x20,0xa2,0xd1,0x5a,0x71,0x98, - 0xef,0x8b,0x7b,0x64,0x5c,0xdd,0x37,0x50,0x44,0x84,0x66,0x41,0x8b,0x8d,0xcb,0xb4, - 0xe1,0xc2,0x3f,0x23,0xd4,0x1a,0x71,0xee,0x17,0xfc,0x11,0xdf,0x02,0x05,0xbd,0xb1, - 0x81,0x88,0xd6,0xe0,0x7a,0xe4,0x58,0x6b,0x92,0x3e,0xdf,0xc6,0xff,0xa0,0xff,0x19, - 0x60,0xfe,0x84,0xbb,0x0f,0xfe,0x15,0x5d,0x6f,0x44,0x26,0xa7,0x75,0x44,0x74,0x6b, - 0xfb,0x69,0x71,0x2d,0xdc,0xa2,0x05,0x52,0xfe,0x1c,0xff,0xa3,0xc0,0x8f,0xe1,0xc9, - 0x2e,0x8a,0x7f,0xc8,0x65,0xf8,0xbf,0xdb,0x6b,0x52,0xc2,0x6d,0xe4,0x8c,0x81,0x88, - 0xb0,0xb1,0x56,0xc5,0xc6,0xa0,0x8d,0xff,0x69,0x46,0xff,0xc3,0xfc,0xf9,0x82,0xa6, - 0x65,0xf0,0x50,0x6b,0x24,0x25,0xf8,0xc8,0xf1,0x49,0x16,0x22,0xda,0x02,0x74,0xbe, - 0xd9,0xf8,0x1f,0x8a,0x7f,0x2e,0x53,0x37,0x92,0xc2,0x1f,0xfd,0x8c,0xd2,0xa8,0x44, - 0x07,0x39,0x83,0x11,0xda,0xdd,0x31,0x48,0x8e,0x62,0x28,0xc1,0xf1,0xd6,0x39,0xf0, - 0x0f,0xa3,0x7d,0xd6,0x70,0x67,0x61,0x84,0xd4,0xf2,0x46,0x60,0xa2,0x11,0xaa,0x83, - 0xde,0x9a,0x01,0x0e,0xfc,0x23,0x88,0x03,0x66,0xbc,0xab,0x82,0x51,0x35,0x21,0x17, - 0xe9,0x7c,0x88,0x1e,0x01,0xcd,0x86,0x03,0xff,0x08,0x7a,0xfc,0x6d,0xfa,0x09,0xf5, - 0x06,0x08,0x93,0x30,0x10,0xef,0x87,0x6f,0xca,0xe8,0x91,0x06,0x0c,0x6a,0x82,0xcb, - 0xf1,0x3f,0xe5,0x93,0x4c,0xfc,0x53,0x34,0xcb,0x77,0x80,0x0f,0x37,0xfb,0x29,0x70, - 0x7a,0x84,0x76,0xdb,0x6a,0xf5,0x27,0x45,0x36,0xff,0xc3,0xc3,0x9e,0x08,0xc5,0x03, - 0x45,0x9d,0xc5,0xe8,0x9d,0x68,0x34,0xb7,0x10,0x42,0xaf,0x71,0xcb,0xc6,0xff,0xd4, - 0x95,0xa4,0xa0,0x47,0x42,0xfc,0xa3,0x52,0xfe,0x87,0xec,0xa5,0xb4,0x03,0x1d,0x6f, - 0xcc,0x40,0x80,0x12,0x0b,0xcd,0x33,0x2c,0xff,0xb3,0xf5,0xfa,0x01,0x9e,0xe2,0x99, - 0xe5,0xfd,0x38,0xba,0x3f,0xfa,0x1a,0xe5,0x60,0x3f,0xa5,0x35,0xd8,0x30,0x2b,0x07, - 0x32,0x08,0x84,0x64,0x07,0xfe,0xd1,0xf9,0x1f,0x84,0x85,0xfd,0xf8,0x05,0xfc,0x0e, - 0xe6,0xcb,0xc1,0x16,0x6e,0x85,0xf0,0x31,0x31,0xec,0x73,0xa4,0x9c,0x35,0x1c,0xf8, - 0x07,0x41,0x0e,0x85,0x3d,0xb8,0x1a,0xed,0x82,0x6a,0x7c,0x1f,0x46,0x04,0xc5,0x60, - 0x29,0xc5,0x3f,0xbb,0xe4,0x18,0x7e,0x33,0xe4,0x41,0xcb,0x9e,0xcd,0x14,0xff,0xc8, - 0x2a,0x0e,0xaa,0x8c,0xa7,0x78,0x72,0x21,0xc2,0xc2,0xc5,0xd6,0x78,0xd5,0x36,0x89, - 0x36,0xda,0xcb,0x72,0xf8,0x67,0x1a,0x85,0x31,0x61,0x6a,0x34,0x0a,0x3b,0xab,0x9b, - 0x97,0x7c,0x9f,0x50,0x0b,0xcf,0x96,0x97,0xf6,0x30,0x84,0x19,0x5b,0x18,0xc8,0xe3, - 0x7f,0x4e,0x51,0x58,0xdb,0x51,0x05,0x47,0x24,0xe9,0xd6,0xa0,0xc8,0xad,0x30,0x7e, - 0xd6,0xe7,0x07,0xc4,0x23,0xfa,0xef,0x9b,0xe3,0x7f,0x06,0x7d,0x3b,0xe1,0x7d,0x05, - 0x2f,0xfe,0x70,0xd1,0x80,0x81,0x8e,0xbe,0x38,0x20,0xd2,0xc6,0xf2,0xdc,0x7c,0x80, - 0x1c,0xff,0x43,0xf1,0xcf,0x88,0x8c,0xb0,0xb3,0x73,0x11,0x9a,0x5d,0xde,0x3b,0x35, - 0xd8,0xe9,0x93,0xf4,0x19,0xd8,0x5e,0x99,0xe5,0x07,0xf9,0x04,0x2c,0x57,0x02,0x6e, - 0xfe,0x27,0xac,0x2c,0xbd,0x3b,0x5c,0x2e,0x3d,0xbb,0x38,0xac,0x04,0x55,0x74,0x0c, - 0x0c,0x11,0xed,0xc4,0x78,0xb4,0x1e,0x6f,0xe1,0xfc,0xf7,0x3b,0xf0,0x0f,0xf3,0xc6, - 0x10,0x5e,0xac,0x3c,0xd3,0x27,0x69,0xb8,0x0c,0x0f,0xc2,0x0e,0xf6,0xbd,0x14,0x0d, - 0x91,0x0e,0xea,0x9a,0x28,0xfe,0x31,0xe7,0x9b,0x8a,0xf8,0xa7,0x11,0x2a,0xb4,0x40, - 0xff,0x9a,0xa9,0xf0,0x9c,0x5c,0xa1,0xad,0x1f,0x0e,0x7f,0x45,0xd8,0x47,0x6a,0xb4, - 0x0d,0x29,0x72,0xba,0x0b,0xfd,0x8f,0xb6,0xb4,0x35,0x1c,0xb1,0xfa,0xef,0x12,0xe8, - 0x7a,0x6d,0x5b,0x36,0x74,0x5b,0xe0,0xbf,0x05,0x3f,0x5c,0x33,0x2f,0x5b,0xb2,0x9a, - 0x9b,0x01,0x6f,0x51,0x46,0xe8,0x6f,0xb8,0x71,0xf2,0xfc,0xae,0x79,0xd9,0xd0,0x77, - 0xbe,0x66,0xe3,0x7f,0x10,0xff,0x7c,0x40,0xd0,0x69,0x88,0x68,0xed,0x0f,0xa0,0x41, - 0x9b,0x94,0xc9,0xf9,0x93,0x21,0x69,0xac,0x05,0x1b,0x4f,0x71,0x39,0xfc,0x03,0x7f, - 0x7d,0x99,0x1f,0x57,0x2a,0xb3,0xa1,0x53,0xdc,0xed,0x4d,0x27,0x95,0x05,0x03,0xc1, - 0x91,0x29,0xf7,0xf3,0x8d,0xe9,0x9b,0xcf,0x86,0x46,0x7c,0x97,0xe1,0x64,0xdb,0xfc, - 0xec,0xe4,0x11,0x4e,0x56,0x9d,0xf8,0xa7,0x62,0xa8,0xa3,0x85,0xfb,0x8c,0xb2,0x56, - 0xad,0x18,0xf4,0x53,0x1a,0x67,0x0b,0x1d,0x2f,0xbe,0x3f,0x3c,0x86,0x43,0x2b,0x7e, - 0x9f,0x54,0xe7,0xf8,0x1f,0x78,0x14,0x17,0xad,0x15,0xbd,0x81,0x7e,0xec,0xb6,0xa9, - 0xf5,0x53,0x7d,0xc5,0xc3,0x14,0xef,0x91,0x39,0xbd,0x81,0xbf,0xc2,0xfe,0x6b,0x61, - 0x1b,0x85,0x46,0xb2,0xe5,0x7f,0x24,0xfe,0x38,0xcf,0xec,0x29,0xae,0x59,0x0c,0x3b, - 0x94,0xaa,0x6c,0x71,0x03,0x06,0x3e,0xf6,0x7c,0x08,0x1f,0x47,0xc3,0x4a,0x34,0x14, - 0x0a,0x39,0xfe,0x67,0x12,0x46,0x2b,0x19,0x83,0xc8,0x56,0x8e,0x27,0xc7,0x96,0xd5, - 0x66,0x8b,0x33,0x1d,0x94,0x81,0xa9,0xa7,0x78,0xe6,0x92,0x70,0x92,0xc6,0x97,0x61, - 0xee,0xae,0x1c,0xff,0x03,0x68,0x0d,0x81,0x45,0x9f,0x37,0x84,0x2f,0x93,0xfa,0x5f, - 0x96,0x66,0x3a,0x76,0xe3,0x32,0x3f,0xa9,0xcd,0xfc,0xb1,0x61,0xa8,0x12,0x3b,0xff, - 0xe3,0xc3,0x90,0xcf,0xbc,0x77,0xff,0x94,0x8b,0x18,0xdd,0xf6,0x61,0xe0,0x23,0x07, - 0x31,0xf0,0xe1,0x95,0x4b,0xdc,0x25,0x7e,0x8c,0xa7,0xc0,0xc0,0x07,0x16,0xff,0xa3, - 0x30,0xfe,0x07,0xa3,0xd5,0xc1,0xb2,0x37,0x94,0xb6,0x3e,0x29,0x1b,0x8a,0x13,0x83, - 0xe1,0x79,0x94,0x21,0x22,0xb6,0xb4,0x97,0x72,0xf8,0x67,0x9a,0x7e,0xd7,0xff,0x28, - 0x51,0x97,0x1c,0x68,0x9b,0xbd,0x78,0x7a,0x86,0xec,0xf6,0xb1,0x6e,0x6a,0xae,0xbf, - 0xea,0xc2,0x3f,0x94,0x1f,0x23,0x72,0x78,0x43,0x3c,0xdc,0x77,0x53,0x86,0xe1,0x81, - 0x55,0x68,0x9f,0x26,0x13,0x3a,0x92,0x76,0x07,0xff,0x83,0x20,0xf0,0xf8,0x17,0xd2, - 0x95,0x3b,0x7b,0xc7,0x52,0xb5,0x7d,0x68,0x96,0x9f,0xc3,0x6b,0x5c,0xf2,0x65,0xf4, - 0x48,0xa7,0x71,0x68,0xb8,0x42,0x1f,0x0e,0x28,0x0e,0xfc,0xf3,0x27,0x3e,0x79,0x7c, - 0xf9,0xad,0x0f,0x0d,0xf0,0x1f,0x24,0x66,0xf6,0x7f,0xb5,0x75,0xd1,0x7d,0xd2,0x78, - 0xa4,0xb1,0x6f,0xb9,0xe6,0x33,0x4c,0x31,0xcc,0xad,0x74,0xe0,0x1f,0xc6,0xff,0x8c, - 0x72,0xff,0xa0,0xbc,0x17,0xaf,0x95,0x42,0xc3,0x95,0x27,0xe0,0x35,0x6d,0x3e,0x65, - 0x84,0x5e,0x82,0x4b,0x4a,0xe3,0xe1,0xe0,0x08,0x02,0xa7,0x1c,0xff,0x73,0x1e,0xd1, - 0xce,0xb5,0xd9,0x50,0x62,0xd1,0xa5,0xe6,0x4d,0xf1,0x6a,0x49,0xf8,0x38,0xfc,0x4d, - 0x1e,0x61,0x09,0x65,0x84,0xde,0x84,0x67,0xda,0x63,0xc3,0x42,0x0f,0xc9,0xda,0xd6, - 0x5f,0xd6,0xa0,0x96,0x29,0x3b,0xd0,0x71,0x2d,0x61,0x61,0x48,0xaa,0xa2,0x57,0x28, - 0xde,0x8b,0x6a,0x11,0xca,0x77,0x39,0xf9,0x9f,0x6a,0x6d,0x09,0x9a,0x11,0x61,0x64, - 0xb5,0x4f,0xc8,0x90,0x55,0xd7,0x74,0x30,0x33,0x16,0xbd,0x01,0x3d,0x62,0x4c,0xc3, - 0x2b,0xc3,0x96,0xff,0x91,0x8d,0xfc,0x17,0x1a,0x79,0x15,0xbc,0x03,0x0b,0xde,0xff, - 0x42,0x86,0x3b,0x2e,0xbc,0xc6,0xd7,0xd2,0xf9,0x43,0xd7,0xe3,0x0d,0x5a,0x30,0xc3, - 0xf5,0x5b,0xf3,0x27,0xab,0xe7,0xbf,0x18,0xff,0x43,0x5e,0x83,0xc6,0xe1,0x20,0x25, - 0x6a,0xbe,0xc7,0x18,0x21,0x9a,0xdf,0xa1,0xff,0x21,0x4a,0x74,0x98,0xcf,0xcf,0xf1, - 0x3f,0x53,0x86,0xc8,0x49,0xa8,0x3f,0x15,0xca,0x04,0xa2,0xca,0x18,0x4e,0x4b,0x9c, - 0x66,0x2b,0xe5,0xb7,0xf1,0x56,0x34,0xe3,0xc2,0x3f,0xc6,0x8f,0xde,0x00,0x21,0x12, - 0x1e,0x0e,0x8c,0xb6,0xcf,0x45,0xd8,0x16,0xd6,0x4a,0x33,0xb8,0x7e,0x5f,0x07,0x73, - 0xfb,0xf0,0xfd,0x73,0xf8,0xc7,0xc6,0xff,0xec,0x06,0x0e,0x22,0x10,0x88,0xcf,0xde, - 0x88,0x9f,0x49,0x84,0x5e,0x39,0x24,0xa9,0x78,0xab,0x2b,0x6e,0xc3,0x3f,0x06,0xff, - 0x33,0x88,0xd1,0xbf,0x14,0xd6,0xa6,0x2b,0x54,0x6c,0xfc,0xb8,0x73,0xad,0x5a,0x9c, - 0xf5,0xaf,0x26,0x17,0xa6,0xae,0x41,0x60,0x20,0xac,0x76,0xe1,0x1f,0x9a,0xff,0x42, - 0x7c,0xf2,0x20,0x74,0x64,0xea,0xbe,0x11,0x9a,0xcf,0x3d,0x38,0xe7,0x1d,0xb5,0x6e, - 0xa8,0x24,0xfe,0x17,0xcd,0xda,0xd7,0xc4,0x06,0xed,0xba,0xb8,0x0b,0xff,0xd0,0x49, - 0x35,0x39,0xc3,0xfd,0x4b,0x13,0xc2,0xe6,0x7f,0x0d,0xec,0xf9,0xec,0x2a,0x78,0x4f, - 0xdc,0xa7,0x85,0xde,0xe7,0x86,0x5b,0x2e,0x0b,0x8c,0x1a,0xf2,0xe2,0x7f,0x02,0x35, - 0x30,0xee,0x4b,0x94,0x23,0x50,0x1f,0x82,0x77,0x8a,0x92,0x1a,0x02,0xf5,0x9d,0x1a, - 0xe5,0x63,0x37,0x66,0xb8,0x73,0x39,0xfe,0x87,0xf9,0x9f,0x9b,0xd0,0xc8,0xe4,0xfa, - 0xb6,0xb5,0x2d,0x15,0xe9,0x07,0xbf,0x45,0x97,0x5d,0xc6,0x0a,0x4b,0xdd,0x17,0xac, - 0x19,0xc4,0x85,0xd8,0x85,0x1c,0xff,0x63,0xe6,0xbf,0x56,0x93,0x19,0xfc,0x63,0xea, - 0xdf,0xa5,0x02,0xf7,0x22,0xec,0x79,0xcc,0xc0,0x3f,0xbe,0x7d,0x4a,0x74,0x00,0xc7, - 0x3b,0xec,0xc0,0x3f,0xdd,0xba,0xf5,0x28,0x5a,0x4e,0x8d,0xe8,0x69,0x2f,0xdd,0xc2, - 0x27,0xb4,0x6e,0x8e,0xcd,0xb7,0x97,0x1c,0xfc,0xcf,0x47,0x3a,0xff,0x13,0xc1,0xc6, - 0x3d,0x19,0x46,0x04,0x9d,0xd3,0xaf,0xe0,0x2d,0x3e,0x89,0x11,0xa4,0xf2,0x23,0x17, - 0xff,0x53,0x6f,0xae,0xc7,0x9f,0xe5,0x4b,0x3b,0x2d,0xfc,0x33,0x99,0x46,0xa8,0x64, - 0x61,0xfc,0xc3,0x1f,0x21,0xb5,0x72,0xe8,0x51,0xee,0x2d,0x0c,0xa3,0x8c,0x08,0xc2, - 0x5b,0xcd,0x0d,0x94,0x28,0x38,0xec,0xe2,0x7f,0x62,0xf2,0x06,0x3d,0xfe,0x12,0x6d, - 0xc3,0x56,0xf2,0x02,0x0d,0xdc,0x34,0x22,0xbf,0xbb,0xf8,0x80,0x5c,0xda,0x12,0x49, - 0x63,0xa0,0x77,0xe2,0x9f,0x98,0x15,0xdf,0xe9,0xb2,0x62,0xc0,0xb7,0x4d,0xef,0x8f, - 0xf8,0x47,0x8e,0x35,0x61,0xff,0x17,0x9c,0xf8,0x47,0x8f,0xfe,0xfc,0xf6,0xb6,0x88, - 0x24,0x6f,0x28,0x6b,0xef,0x45,0xc4,0x48,0x11,0x02,0x1a,0x0a,0x6f,0x2d,0x11,0x44, - 0x1b,0xff,0x5c,0x17,0x4c,0x19,0xa3,0x0b,0x80,0xa2,0x51,0xfe,0x67,0x3b,0x8e,0x77, - 0x90,0x24,0x0c,0x0b,0xf8,0x92,0x42,0x54,0xe1,0x4e,0xd8,0xf0,0x8f,0xc1,0x6f,0x6c, - 0xde,0x31,0xa0,0x8e,0x56,0x3f,0x2b,0x6f,0xa2,0x61,0xfd,0x15,0x84,0x3d,0xac,0x31, - 0xea,0x63,0xa6,0xb0,0xe1,0x1f,0x9f,0x61,0x9f,0x87,0xb9,0x37,0xd2,0xa3,0x02,0xe3, - 0x7f,0xa6,0xc2,0x91,0x26,0x0b,0x1f,0x36,0x52,0xa2,0xec,0x05,0x17,0xfe,0x89,0x41, - 0xa0,0x9d,0x9c,0x55,0x7a,0x52,0xd5,0x3a,0x10,0x3a,0xc5,0x18,0xa1,0x26,0x9d,0xff, - 0x11,0x14,0x72,0xc2,0x8b,0xff,0xf9,0xa5,0x6f,0x8f,0x50,0x25,0x07,0x16,0x14,0xf1, - 0xd0,0xe6,0x33,0xf1,0x1e,0x8f,0xf3,0x41,0xb4,0xf9,0x1f,0x1d,0xff,0x18,0xfc,0xcf, - 0x7e,0xb8,0xab,0x85,0x01,0xa1,0x47,0x8c,0x2b,0xe2,0x7e,0x9d,0x58,0x7b,0x21,0x3f, - 0xff,0xa5,0xbf,0x6d,0xed,0xc2,0x50,0x3a,0x80,0x40,0xc8,0xba,0xa2,0xb2,0xfc,0xd7, - 0xa0,0xe5,0x7f,0x76,0xf9,0x76,0xe6,0xa1,0xdf,0x01,0x9f,0xd1,0x78,0x03,0x46,0xfb, - 0x74,0xfe,0xc7,0x89,0x7f,0xd0,0xfe,0x08,0x3b,0x55,0xd0,0x7c,0xb5,0xb8,0x82,0xe2, - 0x28,0xfe,0x49,0x40,0x89,0xce,0xff,0x30,0x22,0xee,0x68,0x7e,0xfe,0x8b,0xca,0x1d, - 0xd6,0xfb,0x6a,0x77,0x2e,0x1d,0x20,0xe5,0x40,0xf9,0x4c,0x8c,0x47,0xe7,0x94,0x7a, - 0x75,0x2e,0x25,0x82,0x8e,0xba,0xf0,0x0f,0xfb,0x3a,0x36,0x62,0x98,0x96,0x7a,0xa7, - 0xd7,0x92,0x65,0x02,0x0d,0xd3,0xf4,0x7b,0x81,0xf9,0x4a,0xb4,0x5f,0x88,0x63,0x7f, - 0x2b,0xbe,0x20,0xfe,0xa1,0x5f,0xeb,0x74,0xf4,0x3f,0xda,0x0f,0xe0,0xeb,0xf8,0xd9, - 0x56,0xb7,0xe0,0x32,0x64,0x16,0xfb,0x7e,0xe9,0x2d,0x19,0xbf,0xdf,0x41,0xeb,0xf9, - 0x14,0xff,0xd0,0xfc,0x57,0xe9,0x47,0xe4,0xc7,0xea,0xef,0xb3,0x88,0x76,0x56,0xe3, - 0x42,0xfb,0xbd,0x27,0x18,0x10,0x7a,0x55,0xa2,0xb7,0x82,0xab,0xb9,0x73,0x96,0xff, - 0x11,0xae,0xd7,0xfd,0xed,0xe4,0xa7,0xb8,0x4b,0x9d,0xef,0x08,0xc9,0x3e,0x74,0x5c, - 0xaa,0x30,0x76,0x0d,0xf3,0xc0,0x67,0x95,0x31,0xa9,0x41,0x9e,0x9b,0xb1,0xe3,0x1f, - 0x3d,0x7e,0x0d,0x84,0x3e,0xe6,0xce,0xcb,0x27,0xd3,0x89,0x05,0x18,0xc8,0x66,0xc0, - 0xff,0x50,0x92,0x34,0x7e,0x7d,0x28,0x5f,0xd2,0xe6,0xab,0xc1,0x51,0x04,0xea,0x39, - 0xfc,0x73,0x9d,0xce,0xff,0xdc,0x8b,0xa3,0xfb,0x8d,0x5a,0x91,0x0d,0xdd,0x47,0xca, - 0x70,0xd9,0x18,0xcd,0xe2,0xfb,0x9f,0x82,0x27,0xe5,0x8a,0x2e,0x44,0x44,0xe7,0x72, - 0xf9,0x05,0x30,0xf2,0x5f,0x74,0x74,0x3f,0x80,0x3b,0x84,0x40,0x82,0x3c,0xea,0x33, - 0xfc,0xd5,0xcb,0x70,0x50,0xa8,0xd0,0x9a,0x5b,0x8b,0xb4,0x1c,0xfe,0xb1,0xf8,0x1f, - 0x72,0x5c,0x44,0x33,0x66,0x71,0x7d,0xa1,0x98,0x8c,0xd0,0xf3,0x90,0x29,0x96,0x34, - 0xf4,0x48,0xf6,0xfc,0x97,0x11,0x5f,0x68,0xf4,0xf9,0x67,0xdf,0xf6,0xd7,0x37,0xa4, - 0xa7,0x77,0x31,0x0f,0x1c,0xca,0x4c,0x3e,0x0f,0x63,0x93,0x12,0x32,0xc6,0xaf,0xdc, - 0xfb,0x30,0xfc,0xc3,0xee,0xb2,0xf8,0x85,0x1f,0x26,0x5d,0x0d,0x2d,0xf5,0x25,0x0f, - 0x51,0x22,0x48,0xa6,0xf9,0x62,0x96,0xff,0x32,0x9f,0xef,0x13,0x2f,0xb1,0xfc,0x17, - 0x3e,0x7f,0x88,0x1f,0xc3,0x30,0xb7,0xbc,0x05,0xe7,0xfa,0x49,0xb8,0xf1,0x50,0x09, - 0x86,0x39,0x09,0xe3,0xfb,0xca,0x8d,0x34,0xff,0x65,0xf1,0x45,0x66,0xfe,0x4b,0xe7, - 0x7f,0xea,0xeb,0xbe,0xbc,0x91,0x93,0xc4,0x9f,0xf9,0x58,0x44,0xc3,0xa5,0xd0,0xe1, - 0xa8,0xec,0x77,0xe7,0xbf,0x7e,0xa6,0xc7,0xbb,0xa1,0x49,0x37,0x43,0x6c,0x92,0x7f, - 0x2b,0x79,0x42,0xdc,0x00,0xdf,0xd4,0xd8,0x7a,0xed,0x66,0x31,0xa6,0x60,0xbc,0xcb, - 0xba,0xf0,0x4f,0xd5,0xd1,0x62,0xb4,0x4f,0xe7,0x96,0xb8,0x54,0x5e,0x2c,0xb6,0xb7, - 0x1f,0xda,0x21,0xaf,0x3a,0x35,0x3d,0x4e,0x9a,0xa9,0xa1,0xa8,0x50,0xc1,0x99,0xff, - 0x7a,0x07,0x62,0x7d,0xd4,0x3e,0xc2,0xf8,0x1d,0xf5,0x62,0x68,0x73,0xa5,0xaa,0x9c, - 0x94,0x6b,0x5f,0x7d,0x20,0xc3,0x0d,0x94,0x8f,0xe8,0xf1,0x37,0x97,0xff,0x52,0x8b, - 0xe9,0x78,0x93,0x47,0x37,0xed,0xe1,0x3e,0x56,0xc7,0xe4,0x9b,0xcb,0xf1,0x7b,0x94, - 0x5a,0xc6,0x17,0x32,0x98,0x37,0x0c,0x17,0x71,0x7d,0x9d,0xc7,0xff,0xfc,0x91,0xb2, - 0x3d,0xf7,0x70,0x0d,0xca,0xaf,0x20,0xd1,0x57,0x72,0x81,0xbb,0x4f,0x39,0x59,0x35, - 0xbf,0xaf,0xe4,0x75,0x2e,0x89,0x86,0x6a,0x3c,0x1c,0x75,0xe3,0x9f,0xfd,0x4a,0x38, - 0xbb,0xe1,0x51,0xee,0x7f,0xfa,0x5e,0x3d,0x1c,0x6e,0x15,0x0e,0x92,0x1a,0xd8,0x90, - 0xae,0x8e,0x0b,0x55,0x87,0xa3,0xea,0xa6,0xf4,0xdc,0x7c,0xfc,0xb3,0x87,0x7e,0x4d, - 0xf3,0xfc,0x7f,0x09,0xdd,0xa2,0xda,0x5b,0x5c,0x41,0x96,0xc9,0x0f,0x41,0x55,0x6f, - 0xf1,0x14,0x8c,0x50,0x1d,0x94,0x0f,0x74,0xe3,0x9f,0xfd,0xca,0x9d,0xda,0xd2,0x3d, - 0xe1,0x15,0x74,0x21,0x23,0x17,0x67,0xca,0xa2,0xe8,0x7f,0xaa,0x09,0xba,0x1d,0x1a, - 0xd1,0xbe,0xe9,0xc4,0x3f,0x80,0xf8,0x07,0xd7,0x8f,0x87,0x66,0xee,0xfe,0xec,0x2a, - 0xb2,0x7f,0x71,0xfc,0xd7,0x25,0xfb,0x71,0xbd,0xf3,0x9a,0x92,0xe8,0x2f,0xd9,0xc5, - 0x45,0xc9,0x31,0xb4,0x0f,0xce,0x1f,0x2d,0x97,0xff,0x42,0xfc,0xf3,0xb1,0xf0,0x9c, - 0x16,0x1a,0xe4,0x1e,0x85,0x33,0xc5,0x8d,0x08,0x4b,0xb8,0x63,0xe4,0x9d,0x34,0xc6, - 0xbb,0xb7,0x71,0x06,0x8e,0x21,0x5e,0xca,0xcb,0x7f,0x8d,0x2a,0xf5,0x5a,0x69,0x15, - 0x86,0xf5,0xb3,0x72,0xfd,0xdb,0x21,0x89,0x8b,0x8a,0x67,0xe5,0xba,0x7e,0x74,0xcb, - 0x51,0xec,0x5f,0x4f,0x9f,0xef,0xc4,0x3f,0x7b,0x30,0x0c,0xa1,0x93,0x89,0x91,0x27, - 0x20,0xdc,0xff,0xf9,0x0c,0xe2,0x67,0x43,0xb6,0x14,0xa5,0x89,0x72,0x4a,0x24,0x5e, - 0xb0,0x7e,0x5e,0x13,0xff,0xf8,0xe3,0x45,0x7d,0xd2,0x0e,0x2d,0x9a,0xbe,0x09,0x03, - 0x13,0x6c,0xc7,0x08,0x2e,0x50,0xbe,0xab,0x5b,0xb7,0x8f,0x13,0xff,0x3c,0xa7,0x7c, - 0x6a,0x50,0x18,0x2d,0xba,0x36,0xbb,0x76,0xd7,0xac,0x95,0x9f,0xbc,0x8d,0x7c,0x02, - 0xd6,0x28,0x77,0xa4,0x84,0x95,0x4d,0x14,0x1a,0xcd,0xca,0x16,0xbb,0xf1,0x4f,0x37, - 0x24,0x69,0xb6,0xeb,0x05,0xed,0x0f,0x6a,0x43,0xa6,0x04,0x02,0x74,0x7d,0x57,0xa7, - 0x45,0xe3,0x1c,0x83,0x46,0x5a,0xd0,0x8d,0x7f,0x3e,0x86,0xfa,0xde,0x99,0x99,0xc0, - 0xcb,0xf2,0x98,0x78,0x13,0x8d,0x47,0x43,0x54,0xf6,0xb3,0x18,0x1d,0x0b,0xd5,0xff, - 0xdc,0xfc,0x52,0x01,0xfc,0xc3,0x09,0xfc,0x2b,0x90,0x51,0x4a,0x32,0x01,0x09,0x8e, - 0x2a,0x09,0x2d,0x88,0xf6,0x87,0xef,0xa6,0x6a,0xfb,0x4b,0xf2,0xf1,0x0f,0x7a,0x8f, - 0xf8,0x94,0xdb,0xf0,0xd7,0xff,0xb4,0x86,0xde,0x32,0x0e,0xbf,0xa5,0xfc,0x70,0x0a, - 0x57,0x58,0xdd,0x82,0xd4,0xe7,0x81,0x7f,0xee,0x66,0xf8,0x07,0x1e,0x50,0x2a,0xd4, - 0xe2,0x08,0xb9,0x1d,0xb6,0x28,0x15,0x59,0xa1,0x8e,0x29,0xa0,0x6a,0x06,0x8b,0xf3, - 0xf1,0x8f,0x8e,0xb7,0x17,0x6f,0x51,0xaa,0x06,0x84,0x9b,0xd8,0xfa,0x0b,0x1b,0x71, - 0x44,0xc8,0x14,0x1a,0x09,0x4e,0xfc,0x33,0x08,0x1f,0x49,0x94,0xed,0x99,0x5c,0x4d, - 0x8e,0xb6,0xc5,0xb7,0xd5,0xd0,0xf5,0xf2,0xab,0xb0,0x57,0x89,0xaa,0x01,0x8a,0x88, - 0x9e,0x55,0x4a,0x54,0xce,0x8e,0x7f,0x54,0x1d,0xe4,0xac,0xa3,0x30,0x80,0x26,0x26, - 0x60,0x91,0xa2,0x30,0x44,0xa4,0x71,0x34,0x54,0x2d,0xf0,0xc0,0x3f,0xba,0xa8,0x63, - 0x36,0x1c,0x51,0xea,0x75,0x22,0x88,0xe6,0x3b,0x98,0x30,0xe6,0x10,0xec,0xa5,0xf1, - 0xdd,0x85,0x7f,0x04,0xc4,0x3f,0x22,0x99,0x24,0xb7,0xb5,0x84,0x5b,0x4b,0x68,0x7f, - 0x3d,0xff,0x55,0xc6,0x32,0x62,0x34,0x11,0x96,0x75,0xe5,0xbf,0x30,0x3a,0x67,0xfc, - 0x0d,0x95,0x9b,0x8a,0x6f,0x58,0x82,0x0b,0xd5,0x05,0x18,0x24,0xe7,0xca,0xfe,0x7e, - 0xa2,0xf7,0xa7,0xf1,0xda,0x9a,0x6f,0x02,0x18,0xf8,0x67,0xf3,0x9a,0xa9,0xea,0x03, - 0x73,0x2a,0x96,0x14,0xdf,0xfa,0xe0,0xd4,0xed,0x0f,0x44,0x6a,0xb0,0x81,0x40,0x08, - 0x11,0x11,0x4d,0x84,0xd9,0xf0,0x8f,0x90,0x62,0x78,0x23,0xd4,0x3e,0x45,0x6a,0xeb, - 0x92,0xea,0x85,0x4d,0xed,0x9c,0xa4,0x74,0xd1,0xb4,0xd7,0x61,0x2e,0x4b,0xfa,0xa4, - 0x04,0x8d,0xbf,0x27,0xac,0xf9,0x43,0xf5,0x3f,0x2c,0x9f,0xd5,0x1f,0x18,0x20,0x06, - 0xda,0xd9,0xa9,0xea,0x88,0xa8,0x63,0x60,0xa7,0x11,0xe8,0xed,0xfc,0xcf,0x4e,0x1f, - 0xeb,0x5f,0xc6,0x3d,0xa9,0x7e,0x2c,0xcd,0x93,0x63,0xd8,0x5f,0x7e,0x45,0x48,0x34, - 0x05,0xbf,0xcf,0xcd,0x82,0xd1,0x48,0x62,0x49,0xc8,0x13,0xff,0x28,0x24,0x02,0x5d, - 0x62,0xad,0x58,0xf2,0x00,0xae,0x46,0xbb,0xe4,0xb0,0x28,0x74,0xe2,0x32,0xb3,0x07, - 0x1b,0xc5,0x0e,0xfc,0xc3,0x1b,0xf8,0xe7,0x21,0xd2,0x5b,0xbe,0x8d,0x97,0x16,0xfb, - 0xc5,0x26,0x1c,0x26,0xa4,0x64,0xe1,0x13,0x84,0x57,0x28,0xc3,0x16,0x70,0xe1,0x1f, - 0xde,0xc0,0x9f,0x2b,0xda,0xd7,0xc1,0x6c,0xb9,0x38,0x4d,0xbe,0x0e,0xeb,0x70,0xb5, - 0x0a,0xe9,0x76,0x46,0x0d,0x2d,0x2c,0x4e,0x37,0xd9,0xf0,0xcf,0x54,0x7a,0x11,0xdf, - 0xbf,0x9c,0xfb,0x25,0x23,0xb2,0x8a,0x36,0xc3,0x9b,0x70,0x44,0x0a,0xcb,0xc1,0x87, - 0x11,0x38,0x8d,0xe2,0xef,0x1b,0xb2,0xe3,0x9f,0x27,0x00,0x2f,0x8a,0x0c,0xef,0xed, - 0x84,0xb3,0x70,0x69,0xe1,0x4c,0x91,0xeb,0x6c,0x3f,0xab,0x1c,0x94,0xe7,0x5e,0x63, - 0x20,0xa2,0x12,0x77,0xfe,0x4b,0xc7,0x9f,0x53,0x2a,0xf0,0xb3,0x4e,0x90,0x12,0x9a, - 0xff,0x1a,0x6c,0xaa,0x85,0x8d,0x9d,0x38,0xdf,0x86,0x11,0x08,0x21,0x34,0x3a,0xea, - 0xc8,0x7f,0x5d,0x9e,0x4a,0xf1,0x0f,0xa9,0x83,0x5f,0xec,0xad,0x4c,0x47,0xd4,0xa2, - 0x08,0xbf,0x1e,0x2a,0x29,0xec,0xa1,0xd0,0xa8,0x96,0x36,0xfa,0x72,0xf8,0xe7,0x81, - 0x65,0xb0,0x43,0x66,0x6c,0x4f,0x49,0x55,0x1b,0x54,0xa5,0x96,0xc4,0xfd,0x1b,0xa1, - 0x83,0x8f,0x28,0xd5,0x71,0xb6,0x30,0xaf,0xa2,0xf1,0xfa,0xa8,0x94,0x97,0xff,0x1a, - 0xf6,0x97,0x8b,0x15,0x30,0x8b,0x20,0x5a,0xd8,0x08,0x6b,0xa1,0x58,0xf1,0x27,0x08, - 0x85,0x16,0x55,0x67,0xf1,0xfb,0xed,0x73,0xe4,0xbf,0x98,0xfe,0x67,0x35,0x57,0x0a, - 0xbf,0x54,0x9e,0x4a,0x85,0xea,0x10,0x08,0x3d,0xaf,0x6c,0x55,0x4b,0x57,0x77,0xfc, - 0x58,0xf9,0x40,0xf9,0xf4,0xd9,0xd2,0xd5,0xdc,0xd1,0x1c,0xfe,0xf9,0xe4,0x6e,0x78, - 0xdb,0xc8,0xef,0x60,0xa3,0x5e,0x46,0xef,0x71,0x37,0x5d,0x6f,0x2a,0x9f,0xdf,0xe7, - 0x63,0xf1,0x9d,0xde,0x72,0xe4,0xbf,0x18,0xfe,0xd9,0x34,0xca,0xc5,0xe0,0x45,0x65, - 0x4a,0xb6,0x64,0x84,0x4b,0xa6,0x36,0xec,0x49,0x6e,0xfb,0xfc,0x48,0x65,0x23,0xb0, - 0x44,0xc6,0x08,0xd7,0xef,0xc8,0x7f,0x3d,0xa5,0xe3,0x9f,0xd2,0xde,0xb6,0x27,0xe6, - 0x21,0x5a,0xe3,0x6e,0x97,0xff,0x4d,0xad,0xd9,0x29,0xdc,0xc3,0xde,0x7f,0x4e,0x6f, - 0xc0,0x8e,0x7f,0x14,0xc4,0x3f,0x4f,0x33,0x7f,0x85,0x77,0xdb,0xe2,0x73,0xe4,0x62, - 0xca,0x17,0xad,0xf5,0x45,0x95,0xe2,0x56,0x3f,0xed,0x5f,0x41,0x81,0x50,0xd6,0x91, - 0xff,0xda,0x63,0xe8,0xa9,0x84,0x36,0x59,0x6d,0x11,0x16,0xe8,0xfc,0x4f,0xa7,0xd0, - 0x40,0x82,0xe6,0xd2,0xec,0x94,0x35,0x3f,0x23,0x6c,0xbd,0x4f,0x07,0xb5,0x21,0x4a, - 0x9e,0x57,0xea,0x53,0xff,0xf8,0x24,0xd7,0x20,0x6c,0x80,0x64,0xa6,0xe4,0x02,0xae, - 0xa0,0xe9,0x42,0x1b,0xc7,0x7b,0xd4,0xc1,0xff,0x8c,0x2a,0x8c,0x6f,0xef,0x15,0x46, - 0xe5,0xe8,0x67,0x42,0x7b,0xb9,0xe3,0xe8,0xc6,0x93,0xed,0xa1,0xbd,0x95,0x43,0x7a, - 0xfc,0xa2,0xf8,0xc7,0x7c,0x1f,0x1f,0xcb,0x7f,0x31,0xd2,0x23,0x0a,0x2f,0x96,0xcf, - 0xa7,0x68,0xea,0x12,0x86,0xf5,0x6e,0x65,0x23,0x6d,0x7c,0x00,0xf3,0xb5,0xa8,0x1d, - 0xff,0xb0,0xfc,0x17,0x13,0xf9,0xf8,0xe7,0x52,0xef,0xf1,0x99,0x6a,0x0a,0x84,0x5e, - 0x03,0x89,0xc2,0x98,0x21,0x91,0x2a,0x72,0x69,0xfc,0x5d,0x68,0xe1,0x1f,0xaa,0xf7, - 0xd0,0x45,0x41,0xd8,0x5f,0x46,0x6f,0x43,0xfb,0xe3,0x7a,0x5f,0x89,0xe8,0x08,0x8a, - 0xf6,0x2f,0x72,0xe2,0x9f,0x3d,0x4a,0xf4,0x38,0xc2,0x48,0x7e,0xb1,0x92,0x92,0x64, - 0x9c,0x66,0xc7,0xab,0xb6,0x54,0x4a,0xed,0x82,0xbe,0x50,0x95,0x74,0x3c,0x60,0xce, - 0x07,0x10,0xa2,0xf4,0xa3,0xe8,0x0b,0xec,0xe5,0x6a,0x94,0x23,0x77,0x27,0x5a,0x96, - 0x65,0xa6,0x9c,0x6e,0x3b,0x16,0x49,0x74,0x05,0x29,0x62,0x3c,0x00,0x7b,0x59,0x7c, - 0x77,0xf0,0x3f,0xe8,0x4f,0x8e,0x07,0x10,0xff,0xc0,0x68,0xc5,0x2d,0x4b,0x28,0xf0, - 0xa3,0x8c,0x87,0x32,0x59,0xe7,0x37,0x1a,0xf3,0xf1,0xcf,0x38,0x45,0xcb,0x3d,0xdc, - 0x65,0x18,0xa3,0x44,0x50,0xf7,0xa2,0x18,0x5e,0xb9,0x51,0x09,0x8e,0x70,0x1f,0xc1, - 0x49,0x5d,0x1a,0x34,0x6c,0xd9,0x5f,0x63,0xfc,0x4f,0x2c,0xfb,0xe5,0x1e,0xc2,0x1a, - 0x67,0x4b,0x3f,0xe0,0xbe,0x09,0xdd,0x52,0xb8,0x02,0x61,0x0f,0x0e,0x1c,0x6f,0x05, - 0xec,0xf8,0xa7,0x6f,0x92,0xb5,0x1e,0x67,0x81,0xe9,0xd0,0xd2,0x44,0xd3,0x46,0x5f, - 0x37,0x2e,0x1a,0x05,0xca,0xff,0x74,0x50,0xe2,0x0b,0xc7,0x6b,0xcb,0x7f,0x59,0xfc, - 0x09,0xb5,0x76,0x4c,0xf3,0xeb,0x8d,0xea,0x30,0x1a,0xf6,0x3c,0x1a,0x96,0xdd,0xca, - 0xbd,0x4f,0xaf,0xc5,0xff,0x70,0x56,0x20,0xd6,0x15,0x74,0xc1,0xcc,0x94,0x73,0xe4, - 0x18,0x61,0x57,0xfa,0x65,0x97,0xfe,0xd9,0x64,0x7b,0xb0,0x11,0x9f,0x72,0x1f,0x3f, - 0x0e,0x37,0xca,0x73,0xed,0xf6,0xb1,0xe6,0x7f,0xbf,0x4d,0xff,0x63,0x36,0x18,0xec, - 0xa1,0xfa,0x96,0x41,0x38,0xa6,0x5f,0xf1,0xe4,0x7f,0xf0,0xd7,0x27,0x94,0x4d,0x42, - 0xfc,0x76,0x80,0x87,0x2c,0xbe,0xff,0x7b,0x92,0xf1,0xfe,0x9e,0xfc,0xcf,0xf1,0xa9, - 0x46,0x23,0x88,0x4f,0x88,0x0c,0x44,0xa8,0x3e,0xaa,0x43,0xbf,0xe2,0xcc,0x7f,0x99, - 0xd9,0x1f,0x65,0x9f,0x5a,0x82,0x1f,0x72,0x78,0x46,0xd7,0x3e,0xa5,0x62,0xa5,0xb0, - 0x9a,0xfc,0x06,0x17,0x32,0xec,0x56,0x0e,0xff,0x7c,0x4e,0x08,0xf2,0x1f,0xf8,0x1a, - 0x86,0x66,0xd6,0x71,0x27,0x94,0x0f,0xd4,0x86,0xa1,0xd0,0x4d,0x5c,0xa9,0xf2,0x41, - 0xa6,0x6e,0x30,0x18,0x9f,0xf2,0x2e,0xae,0x48,0x1a,0xe8,0xa7,0x94,0xcf,0xff,0xd0, - 0x69,0x23,0xb3,0xb4,0xe9,0x1f,0x69,0xda,0x4b,0x87,0x85,0x17,0x45,0xc3,0x3e,0xde, - 0xfa,0x1f,0xf8,0x00,0x61,0xcf,0xcc,0x27,0xd9,0x42,0x63,0xa6,0x66,0x0a,0x17,0xd9, - 0xf7,0x9b,0xcb,0x7f,0x3d,0x64,0xea,0x7f,0xb8,0x47,0x85,0x7d,0xb0,0x4d,0x2b,0x35, - 0x97,0x8d,0x74,0xfd,0xc5,0x1b,0x0b,0xab,0x0b,0xf6,0xfc,0x97,0x68,0x65,0xbb,0xf6, - 0xb1,0xc4,0x5f,0xd8,0x96,0xff,0x32,0x1a,0x9a,0x17,0xfe,0xa1,0xc2,0x7b,0xb6,0xda, - 0x62,0x57,0xfa,0x97,0xd2,0xf5,0xac,0x71,0xeb,0x25,0x9b,0xfe,0xd9,0xe2,0x7f,0x68, - 0xda,0x2b,0x61,0x36,0x6e,0x79,0x38,0xa4,0x2e,0x1a,0x31,0x6f,0x8d,0x78,0xe9,0x7f, - 0x54,0xca,0x7e,0xb0,0x7c,0x10,0x6f,0x44,0xa8,0xac,0x4c,0x1b,0xcb,0x0b,0xf0,0x3f, - 0xae,0x46,0xd0,0x76,0x25,0x9f,0xff,0x31,0xf8,0x87,0x5c,0x63,0x85,0x90,0x2e,0x7b, - 0x53,0xa2,0x57,0x38,0x4f,0xfe,0xc7,0xdd,0x5f,0x8e,0xa4,0xc9,0x9b,0xe6,0x15,0x4f, - 0xfe,0xc7,0x00,0x06,0x94,0xff,0x31,0x68,0x1f,0x8b,0x2a,0x39,0xec,0xc8,0x7f,0x19, - 0xe3,0x35,0x06,0xde,0xae,0x37,0x28,0xec,0xc9,0x0a,0xc6,0xad,0x33,0x96,0xff,0x39, - 0xa5,0xeb,0x9f,0x0d,0xb6,0xc7,0x80,0x3d,0x08,0x63,0x1a,0xe9,0x30,0x2f,0xaa,0x1e, - 0xf8,0xc7,0x0a,0xfa,0x06,0x70,0xda,0xdc,0x41,0x61,0x43,0x63,0x1f,0xda,0xe7,0xa2, - 0x6c,0xf4,0x7f,0xc1,0xd2,0x2b,0xae,0x36,0xf0,0x8f,0x40,0xed,0xcf,0x80,0xd0,0x1a, - 0xc2,0x1a,0x62,0x89,0xa1,0xff,0xa1,0xd0,0xe8,0x44,0xce,0xfe,0x8c,0xff,0x89,0xc9, - 0x54,0xdd,0x24,0xec,0xe1,0xa3,0x0b,0x03,0xe2,0x61,0x5e,0xdc,0x13,0x89,0xb6,0xd0, - 0xc4,0x9f,0x62,0x8c,0xf7,0xa5,0x3c,0xfe,0x07,0x41,0xe3,0x4e,0xd1,0x48,0x44,0xee, - 0x74,0x1a,0x76,0x29,0x1a,0x36,0x8f,0xff,0x29,0xb1,0xfd,0x9a,0xf4,0xfd,0x93,0x29, - 0xc4,0xb7,0x6f,0x48,0xc6,0x95,0x41,0x47,0xfe,0xcb,0x6b,0x3e,0x34,0x2c,0xa6,0x4f, - 0x48,0x19,0x57,0x3e,0xca,0xe3,0x7f,0x72,0xf6,0xa7,0xfc,0xcf,0x08,0x9f,0x80,0x20, - 0xce,0x37,0xd2,0xc7,0xb3,0x89,0xe7,0xc5,0xff,0x90,0x41,0xf8,0x21,0xc4,0xda,0xb0, - 0xb1,0x0b,0xaf,0x6c,0xa7,0xb0,0x67,0x4c,0x59,0xaf,0xdf,0x3a,0x2a,0xca,0x56,0xff, - 0x65,0xfa,0x7e,0x01,0x1b,0x4d,0x4a,0xc3,0xb4,0x94,0x42,0xff,0xfc,0xa2,0xe9,0x7f, - 0x8e,0x3a,0xf2,0x5f,0x26,0x5b,0x0b,0x3f,0x80,0x9a,0x43,0x81,0x7b,0x08,0x7e,0xd1, - 0xaa,0xd4,0x82,0xb0,0xe7,0x0c,0xbf,0x56,0xbf,0x35,0x98,0xcb,0x7f,0x75,0x59,0xf8, - 0xe7,0x8c,0xde,0x48,0x76,0xcc,0xc0,0xf8,0x32,0x2f,0x15,0x5d,0x8d,0x11,0xe7,0x57, - 0xfa,0xad,0x73,0x92,0x95,0xff,0xba,0xde,0xe6,0x6f,0x69,0x5a,0x27,0xf4,0x34,0xfa, - 0x93,0x71,0x9a,0x46,0xcf,0x2c,0xb2,0x5c,0xcd,0xe1,0x4e,0xd3,0x3e,0xf0,0xc0,0x65, - 0x91,0xf1,0x3f,0x23,0xdc,0x65,0x79,0x3c,0x5d,0x4b,0x1b,0xb1,0x85,0x63,0x2f,0xcf, - 0x5b,0x51,0x8a,0x57,0x2c,0xfd,0xb3,0xe2,0xe4,0x7f,0x6a,0x28,0xdb,0x73,0x02,0x5f, - 0x1b,0x81,0x50,0x2b,0x99,0xa1,0x74,0x2b,0xd2,0x4a,0x81,0xf2,0x3f,0xc6,0xd0,0xce, - 0x2d,0xb6,0x9e,0x6f,0xe3,0x7f,0x94,0x7d,0x52,0x0d,0x45,0x47,0xf8,0x84,0x8a,0x8a, - 0xe6,0xf5,0xad,0x66,0xe2,0xbe,0x95,0x78,0xf3,0x3f,0x7a,0x23,0x93,0xb3,0xe7,0xf3, - 0x8a,0x71,0xcb,0x83,0xff,0xc1,0xf1,0x06,0xc7,0xa0,0x56,0xdb,0x34,0x1c,0x88,0xa2, - 0xbf,0xcd,0x0c,0xe2,0xc2,0xfc,0xbc,0x62,0xdc,0x3a,0xe7,0xcc,0x7f,0xe9,0xfc,0x8f, - 0xcd,0xf1,0xea,0x7c,0x91,0x6f,0x80,0x37,0xae,0xd8,0xf2,0x5f,0xe2,0x25,0x57,0xbc, - 0x1b,0xe6,0x1a,0xa0,0x11,0xe3,0x63,0x89,0x7e,0x65,0x26,0xbd,0xa2,0x39,0xf3,0x5f, - 0xc4,0x8c,0x5f,0x50,0x8a,0x8d,0x5b,0x77,0xd3,0x1d,0x3d,0x2b,0x30,0x7e,0xfd,0x41, - 0x34,0x42,0x9b,0x87,0xfe,0x19,0xfb,0x0b,0x07,0xa0,0x88,0x36,0xf4,0x2b,0xc5,0x99, - 0xa6,0xf3,0xd2,0x01,0x9d,0x08,0x72,0xf3,0x3f,0xcc,0x08,0x2f,0x2a,0xf3,0x9b,0x11, - 0x08,0x2d,0x20,0x1b,0x15,0x63,0x99,0x6f,0x99,0x2e,0x4f,0xff,0x7c,0x7a,0xf9,0x53, - 0xdc,0xbb,0xd2,0x58,0x0a,0x47,0xf7,0x6d,0xae,0x46,0xfe,0xd3,0xbc,0xe4,0xf1,0x12, - 0x5b,0x44,0xb6,0xe1,0x9f,0x12,0xc6,0xff,0x1c,0x0f,0x5d,0x60,0x77,0x1b,0x4f,0xe1, - 0xe8,0x3e,0x56,0xc6,0xe3,0x78,0x65,0x78,0xca,0xb0,0x37,0xfe,0xb9,0x0c,0x37,0x42, - 0x49,0x96,0x0b,0xc3,0x25,0x1d,0x2d,0x53,0x20,0x44,0xf9,0xc3,0x40,0xd2,0x9c,0x3f, - 0xc3,0x96,0x7f,0xa0,0xfc,0x4f,0x8f,0x52,0x09,0xc2,0xae,0xca,0x30,0x64,0x20,0x4c, - 0xd1,0x8e,0x8e,0x88,0xb0,0x11,0x33,0x1b,0x4e,0xfe,0xe7,0x19,0x98,0xad,0x04,0x24, - 0xbf,0x06,0x99,0x39,0x6c,0x3f,0x8e,0x39,0x4c,0xd9,0x32,0xc5,0x61,0xeb,0x7b,0x61, - 0xfa,0x1f,0x04,0x8d,0xeb,0x77,0x51,0xfd,0xb9,0x12,0x36,0x7f,0x88,0x58,0xce,0xb0, - 0x01,0x77,0xfe,0xeb,0x23,0xb9,0x56,0x0a,0x3d,0xc1,0xbd,0xc9,0x8f,0x28,0x7b,0xf5, - 0xfe,0x36,0xa0,0xa2,0xe3,0x1f,0x47,0xfe,0x6b,0x04,0x1a,0x57,0x94,0xa4,0xa6,0x7c, - 0x1b,0x2e,0xf9,0x9c,0x13,0xc3,0x6a,0x38,0xf3,0x5f,0x1f,0xc9,0x09,0x88,0xaa,0x53, - 0xde,0xc2,0x30,0xb7,0xd7,0x01,0x84,0xac,0x86,0x5b,0xff,0x23,0xfd,0x37,0xf4,0x36, - 0xd4,0x5b,0xb2,0xb4,0x97,0xf1,0xfe,0xf1,0xdc,0x40,0x9c,0xf8,0x07,0xfb,0x83,0x10, - 0xe7,0x8f,0xa3,0xf7,0xae,0x72,0x38,0x22,0xab,0xe1,0xe4,0x7f,0x9e,0x54,0x2a,0x24, - 0xe1,0x5e,0xf2,0x92,0xf2,0xa4,0x3a,0x8b,0xa6,0xbd,0x1c,0x78,0xe0,0x6e,0x27,0xfe, - 0xa1,0xfc,0xcf,0x5e,0x48,0xec,0x0a,0xd6,0x4f,0x3e,0x2a,0x0f,0xab,0x0b,0x28,0xda, - 0x61,0xfa,0x9f,0x6c,0x20,0xce,0x16,0x0e,0x1e,0xf8,0xe7,0x32,0x46,0x9f,0xd0,0xfb, - 0x93,0x87,0xf1,0xd3,0x61,0x42,0xf1,0x21,0xd9,0x6d,0x9f,0x7e,0x62,0xda,0x87,0xe2, - 0x1f,0x84,0x0d,0x62,0x50,0x21,0x74,0xb7,0x82,0x0d,0x08,0xd9,0xed,0xe3,0xe4,0x7f, - 0x9e,0x82,0x8a,0xc5,0x25,0xf2,0xa2,0xdb,0xf4,0x85,0x55,0x6b,0xd9,0x69,0x73,0x19, - 0x65,0xf9,0x13,0x27,0xff,0x83,0xde,0x49,0x15,0x22,0x4d,0xb7,0x07,0x9f,0x6e,0xd7, - 0x87,0xc9,0xef,0x53,0xe6,0x60,0xa3,0xe5,0x8c,0x09,0x8d,0x1c,0xfc,0x8f,0xd0,0x2d, - 0x87,0xfb,0x1e,0x2f,0x22,0xcb,0x94,0xbd,0x92,0x65,0xc6,0x88,0xc3,0x9e,0x2f,0xf1, - 0xe6,0x7c,0xd3,0xf5,0x3f,0xf3,0x7b,0xa2,0x6f,0x92,0x2f,0x57,0x51,0x21,0x50,0x40, - 0xc7,0x3f,0xcf,0x98,0x40,0x88,0xe1,0x1f,0x57,0xfe,0x4b,0x78,0xd6,0x90,0x3d,0xfb, - 0x66,0x98,0x81,0x69,0xb6,0x2d,0x42,0xb9,0xf0,0x8f,0xef,0x7d,0xba,0x1b,0x48,0x5c, - 0x54,0x45,0x17,0xb6,0x1e,0x40,0xc8,0x03,0xff,0x84,0x53,0x91,0xb4,0x5f,0xa7,0x7d, - 0x42,0x79,0xc0,0x26,0xe0,0xc6,0x3f,0xb8,0xc8,0x6a,0x16,0xd2,0x45,0xdf,0xa0,0xfb, - 0x05,0x3c,0x80,0x50,0x71,0x1e,0xfe,0x89,0x48,0x47,0x85,0xb2,0x17,0x78,0xb1,0x0d, - 0xa3,0xff,0x74,0xa7,0xfe,0xc7,0x0b,0xff,0xf4,0x48,0x09,0x61,0x59,0x3b,0x97,0xd2, - 0x65,0x27,0xb6,0x61,0xea,0x8d,0x12,0x67,0xfe,0x6b,0x80,0xaa,0xe9,0x96,0x6c,0xea, - 0xe7,0x2e,0xc2,0xc7,0x11,0x6b,0xff,0x97,0x6d,0xbc,0x93,0xf3,0xf0,0x4f,0xa4,0xb1, - 0x29,0xb8,0x79,0xf2,0xb7,0xe9,0x6a,0x97,0xc1,0x24,0x0c,0xbc,0x49,0x79,0x66,0x7f, - 0xee,0x1f,0xe6,0xf0,0x0f,0xe3,0x7f,0xe4,0x18,0x74,0x75,0x72,0x29,0xf1,0x99,0x8a, - 0x5a,0xaa,0xff,0xc9,0x42,0x17,0xd3,0x23,0x15,0xc6,0x3f,0xd1,0x26,0x61,0x2a,0xe9, - 0x84,0xfd,0xc5,0xd2,0x42,0x36,0xcc,0xb6,0xbc,0xf1,0xba,0xf0,0xcf,0xf3,0xc2,0x43, - 0x45,0x68,0x3d,0x32,0x5b,0xf6,0xa3,0x19,0x05,0xfa,0x43,0xf8,0x99,0x3d,0x7d,0x14, - 0xff,0x94,0xb9,0xf2,0x5f,0x2d,0xc9,0x96,0xe0,0x56,0xf2,0x93,0xaa,0xf7,0xf9,0x84, - 0x21,0x5b,0xc2,0xd7,0x0e,0xd8,0x06,0xee,0xca,0x7f,0x29,0x0d,0x2b,0xe6,0x96,0x2f, - 0x5a,0xc1,0x8f,0x1a,0x32,0x27,0x46,0x94,0xd9,0xf4,0x3f,0xf8,0xbd,0x98,0xbf,0x97, - 0xa1,0xff,0xc1,0xef,0xab,0x52,0xe5,0x47,0x78,0x8a,0xae,0x17,0xb1,0xb4,0x23,0x85, - 0xd9,0xba,0xfd,0x97,0xe7,0xe1,0x1f,0xdf,0x0d,0xca,0x20,0xe2,0x9f,0xc8,0x33,0x3c, - 0x43,0x3b,0x7d,0x60,0x34,0x06,0x4d,0x68,0xe4,0xc6,0x3f,0x52,0x56,0x88,0xc3,0x09, - 0x98,0x8f,0x5f,0xc7,0x74,0x2f,0xff,0xe3,0xcc,0x7f,0x3d,0xa7,0xcc,0x69,0xef,0x62, - 0x5f,0x6b,0xbc,0x46,0xfb,0xb2,0xed,0xb3,0xb5,0x1a,0xee,0xfc,0x57,0x5c,0x0d,0x32, - 0xfc,0xb3,0xed,0x96,0xb3,0x33,0x2d,0x20,0x64,0x6b,0x9c,0x33,0xa7,0x1b,0xc3,0x3f, - 0x1f,0xe0,0x6a,0x5d,0xf7,0x1e,0x72,0x32,0xcf,0xdf,0xce,0xa0,0x89,0x9e,0xc3,0x39, - 0xfe,0x9f,0xad,0xdf,0xc9,0x40,0x68,0xd4,0x77,0x5e,0x1e,0xd3,0xe6,0x9f,0x65,0xf1, - 0xeb,0x3d,0x3d,0x6c,0xe5,0xf0,0x8f,0x4b,0xff,0x2c,0x45,0x03,0xf1,0x5b,0xcf,0x28, - 0x1d,0x99,0x4f,0x0f,0x51,0x20,0xa4,0xb9,0xdf,0xdf,0x9d,0xff,0xaa,0x10,0x02,0xad, - 0x4d,0x97,0xd4,0xff,0x0d,0x15,0x7a,0x22,0xec,0x31,0x57,0x7f,0x17,0xfe,0x51,0x24, - 0x2a,0xeb,0x3d,0x29,0x74,0x34,0x15,0xf0,0xe7,0x2e,0xfc,0x23,0x27,0xd2,0xcb,0x7b, - 0xb8,0x77,0xe1,0x3d,0xd9,0x70,0x9b,0xef,0x4c,0xd2,0xf3,0x59,0x96,0xff,0x74,0xe6, - 0xbf,0xca,0x0f,0xa6,0x43,0x7b,0x16,0x0e,0x75,0x8e,0x15,0x27,0xb5,0xe5,0x19,0xb6, - 0xde,0x9c,0xe1,0x30,0x94,0x33,0xff,0x85,0x30,0x80,0x30,0xb6,0x64,0x9c,0x14,0x88, - 0x77,0xee,0xfc,0x57,0x2c,0x1e,0xc9,0x94,0x9d,0x97,0xbb,0x21,0x7c,0x68,0x29,0x15, - 0x96,0x38,0x18,0x09,0x2f,0xfc,0xa3,0x0a,0xb6,0x30,0x9d,0xdf,0x70,0xe1,0x1f,0x3e, - 0x5a,0x42,0xd1,0x4e,0xff,0x01,0x81,0xa5,0x59,0x71,0x06,0xca,0xd1,0xde,0xc0,0x44, - 0xf8,0x47,0xd8,0x48,0xd1,0xef,0xb8,0x94,0xec,0xdb,0x94,0xa9,0x7c,0xb7,0xd9,0x1d, - 0x7f,0x9d,0xfc,0x0f,0x0e,0xaa,0x24,0x34,0xfc,0xfc,0xcb,0xda,0x9f,0x84,0x24,0x55, - 0x6b,0x0c,0x69,0xe3,0x52,0x63,0x5f,0x68,0x62,0xfe,0x67,0x84,0x3b,0x0f,0xaf,0x29, - 0x37,0x9e,0xdd,0xf4,0x21,0x77,0x0f,0xbb,0x82,0x16,0xbb,0x0f,0x7e,0x6f,0xe0,0x1f, - 0x97,0xfe,0x27,0xa6,0xc3,0x9e,0x77,0x94,0xd8,0xe1,0xc0,0x87,0x24,0x0c,0xdd,0x42, - 0x2c,0xbb,0x64,0x84,0x24,0xf3,0xf9,0x1f,0x9b,0xfe,0x87,0x35,0xfa,0xfc,0x0b,0xe8, - 0x46,0x54,0x69,0x15,0x5d,0x98,0x2f,0xcb,0x8d,0xd7,0xa9,0xff,0x31,0xac,0xcd,0x12, - 0x8b,0x71,0xff,0xdf,0x99,0x44,0x50,0x34,0xc7,0xff,0x98,0xf3,0x01,0xf1,0x4f,0xf0, - 0x80,0xb5,0x5e,0xf0,0xd5,0xe2,0xb4,0xf1,0xdd,0xd9,0xfc,0x5d,0xbc,0x82,0xf8,0x79, - 0x95,0x37,0xfe,0xd1,0xf3,0xa1,0x3e,0x23,0x31,0x9a,0xe1,0x32,0xcc,0x2c,0xcb,0x75, - 0x20,0xed,0x81,0x7f,0x9c,0xeb,0x91,0x0c,0x37,0x8b,0xf2,0x3f,0xd9,0xd2,0x3a,0x2e, - 0x28,0x79,0xe2,0x1f,0xeb,0xd7,0xff,0x11,0x53,0x13,0x91,0x08,0x5e,0x59,0xa0,0x09, - 0xc3,0xe4,0x5f,0x48,0x41,0xfe,0xa7,0xd8,0xb4,0x06,0x36,0xba,0x68,0xbe,0x46,0xcf, - 0xc8,0x57,0x7a,0xe1,0x1f,0x43,0xff,0x73,0x46,0xa1,0x8d,0xe9,0xab,0x97,0x7c,0x9f, - 0xa6,0xbd,0x86,0x8b,0x57,0x93,0x1f,0xe7,0xf3,0x3f,0x86,0xfe,0x67,0x30,0x44,0xd9, - 0x0f,0x26,0x7b,0x4e,0x70,0x0f,0x66,0xb1,0x31,0x84,0xb0,0x27,0xa8,0xfd,0xc1,0x9b, - 0xff,0x61,0x22,0x9f,0x21,0xf8,0xbd,0x48,0xe7,0xcf,0x8e,0xfb,0xc4,0x31,0xf1,0xba, - 0x43,0xa5,0xc3,0x81,0x8f,0xe5,0xf7,0xc4,0x89,0xf8,0x1f,0x5c,0xbf,0x64,0x6b,0x7a, - 0x48,0xa4,0x6f,0x4c,0x29,0xd3,0x42,0x7b,0xb9,0x68,0x9f,0x27,0xfe,0x71,0x78,0x9b, - 0xf2,0xbf,0x27,0x0f,0x4b,0x94,0x08,0x5a,0x1a,0x6f,0xbf,0xce,0x1b,0xff,0xe8,0x20, - 0xa7,0x89,0xc1,0xbc,0xb3,0xe5,0xab,0x13,0x33,0x94,0x7d,0xed,0x5f,0xcf,0x06,0xbe, - 0x4b,0x2c,0x69,0x90,0x67,0xfe,0xeb,0xb8,0x99,0x3d,0x64,0x34,0xfe,0xa1,0x40,0x7c, - 0xc9,0xc6,0x1c,0xfe,0xb1,0xeb,0x7f,0x9e,0xc9,0xf1,0x3f,0xb5,0xca,0xf5,0x6a,0x25, - 0x4d,0x7b,0x2d,0x60,0xfa,0x9f,0x4f,0x7e,0xe4,0xf3,0xc2,0x3f,0xf6,0xe8,0xff,0x3d, - 0x85,0x3b,0x0b,0x75,0x34,0xff,0xc5,0x93,0x3b,0x7c,0xf4,0xca,0x64,0x37,0xff,0xe3, - 0x82,0x3d,0x5f,0x1b,0x10,0x47,0x79,0x06,0x0c,0x66,0xb7,0x5c,0x99,0xff,0xe1,0xd2, - 0x4d,0xef,0x2a,0x6f,0x43,0x6c,0xa1,0x90,0xf6,0xcf,0x92,0x3c,0xf1,0x4f,0xae,0x3f, - 0xe2,0x1f,0x62,0xea,0xa5,0xfd,0x5b,0xdb,0xab,0xae,0xc8,0xff,0xac,0xd2,0xf9,0x9f, - 0x6d,0xd8,0x10,0xca,0xda,0xf9,0x5d,0x7b,0x88,0x07,0xfe,0xa1,0xb0,0x27,0xc0,0xc6, - 0xcb,0x35,0xf8,0x4a,0xc9,0x94,0x2c,0x0c,0x53,0x45,0x4a,0x3b,0x27,0x75,0x19,0xa6, - 0x70,0xe2,0x1f,0x0b,0xed,0x7c,0x87,0xed,0x76,0xdf,0x81,0x16,0x88,0xea,0x57,0xca, - 0x0b,0xf2,0x3f,0x14,0xf6,0x88,0xa3,0x88,0x2e,0x74,0xfe,0x47,0x9c,0xbf,0x30,0xb4, - 0x59,0x27,0x52,0xe4,0xbc,0xfc,0xd7,0xa0,0x0e,0x72,0x18,0xda,0xf1,0x6f,0xa0,0xc0, - 0xac,0x07,0x6a,0x21,0xd0,0xc9,0xb5,0xc2,0x56,0x03,0xff,0x38,0xf4,0x3f,0x0f,0x19, - 0xe3,0xe5,0x71,0xbc,0xcd,0x3f,0x12,0xdb,0x79,0x61,0x4f,0xf8,0x0e,0x39,0xf0,0x25, - 0xf2,0x4f,0xde,0xf8,0xe7,0x71,0xbb,0x3d,0x7f,0x94,0x6e,0xfa,0xba,0xbc,0x1f,0xbe, - 0x21,0x6f,0xe8,0x27,0x17,0xa9,0x10,0x68,0x61,0xc0,0xad,0xff,0x79,0xc5,0xf9,0xfb, - 0x92,0xd9,0x02,0x53,0x74,0xa7,0x2b,0x77,0x16,0xc0,0x3f,0x8e,0xfe,0xa2,0x6e,0x96, - 0x26,0xec,0xbf,0xc2,0x7c,0x54,0xbe,0xfe,0x47,0xe7,0x1b,0xb1,0x11,0x55,0x16,0x55, - 0x28,0xec,0x0a,0x59,0x24,0x99,0xb7,0x0a,0xf0,0x3f,0xb4,0x81,0x0b,0xb1,0x1b,0xa4, - 0x7a,0x88,0x6d,0x0b,0xa9,0xc2,0x2e,0x0b,0xff,0x78,0xeb,0x7f,0x68,0x03,0xe2,0xa4, - 0x54,0x98,0x8e,0xff,0x99,0x00,0x00,0x2f,0x78,0xe2,0x1f,0xfb,0xf7,0x3b,0x58,0xfc, - 0x2d,0x32,0x15,0xf6,0x49,0x77,0xf7,0xe3,0x0a,0x37,0x5d,0x08,0xff,0x30,0x90,0x43, - 0xbf,0xd6,0xc6,0x0b,0xfc,0x08,0x37,0x63,0xf1,0x9f,0xd4,0x5b,0xd4,0x10,0x15,0x42, - 0x9b,0xf8,0xc7,0xae,0xff,0xb9,0xc6,0x11,0xdd,0x4a,0x33,0x1d,0x6f,0xc0,0x98,0x38, - 0x03,0x1b,0x39,0xc6,0xc3,0xad,0xff,0xc1,0xf8,0xb5,0x9f,0x3b,0x43,0x8e,0x29,0x8d, - 0x03,0x33,0xf7,0x4f,0xa9,0x16,0xde,0xeb,0xbf,0x39,0x15,0x3a,0xc5,0xd5,0xca,0x27, - 0xbd,0xf0,0xcf,0x5b,0x94,0xff,0xb9,0x17,0xfd,0xe7,0xda,0xed,0x51,0xea,0x48,0x89, - 0xf2,0xbc,0x5a,0xf3,0x6e,0xa0,0x95,0x6b,0x21,0x6b,0xbd,0xf0,0x0f,0x45,0x3b,0xd3, - 0x29,0xff,0xf3,0x03,0x69,0x4e,0x5f,0x20,0x1e,0xae,0x53,0x1e,0xab,0x9c,0x23,0x23, - 0x50,0x0c,0xfa,0xd6,0x7a,0xe1,0x9f,0x1d,0xa6,0xff,0x31,0x64,0xab,0x80,0x61,0x2b, - 0x7a,0x88,0x05,0xfa,0x0e,0x2f,0xfc,0xf3,0x8e,0x31,0x5e,0xf2,0x1a,0x47,0xbd,0xeb, - 0xf4,0xe8,0xca,0xf7,0xa0,0x5e,0xc1,0x9f,0x35,0x2a,0x1c,0xf3,0xc2,0x3f,0xef,0xb8, - 0xa2,0xff,0xbb,0x78,0xa5,0x41,0x63,0x1e,0x6c,0x8c,0x78,0xe0,0x1f,0x07,0xda,0x09, - 0x0e,0x4f,0xa9,0xa7,0x3b,0xa0,0x95,0x60,0x2b,0x79,0x54,0x17,0x42,0x7b,0xe0,0x9f, - 0x1c,0x7a,0x41,0x60,0x13,0x49,0x19,0x69,0xaf,0xdd,0xdc,0x06,0x7e,0x02,0xfe,0x87, - 0x35,0xe6,0x64,0x48,0x95,0x70,0x00,0xaa,0x65,0xf4,0x57,0xbb,0x65,0x8c,0x77,0x87, - 0x0a,0xf0,0x3f,0xed,0x2f,0x42,0xb7,0x18,0x7d,0x01,0xfd,0xf3,0x24,0x05,0x81,0x56, - 0xaf,0x40,0x03,0x5f,0x47,0x01,0xfc,0x73,0x9c,0x0e,0xb3,0x6b,0x0c,0x61,0x4c,0xf0, - 0x02,0x57,0x01,0xe3,0x95,0xf5,0xcd,0x41,0x9a,0xe8,0x39,0x56,0x00,0xff,0xf4,0xb3, - 0xfc,0xc5,0xf8,0x9d,0xc9,0xbe,0xe5,0x17,0x03,0xfd,0xf2,0x58,0x39,0xe5,0x7f,0x0a, - 0xe3,0x9f,0xfb,0xa4,0x50,0x3f,0x87,0xff,0xa3,0xf3,0xc6,0x6c,0x48,0x87,0x3d,0xf3, - 0x4d,0xfc,0x3c,0x9f,0x66,0x54,0xf3,0xf0,0x8f,0x84,0x9f,0x79,0x84,0x3f,0xd5,0x59, - 0x9b,0x2d,0x1d,0x61,0xb0,0xc4,0x20,0x82,0xba,0xa5,0xea,0xa3,0x5e,0xfa,0x67,0x40, - 0x27,0x43,0x6b,0x0f,0xd1,0x30,0x44,0x64,0x61,0x8b,0xae,0xaf,0xdb,0x48,0xf5,0x1e, - 0x34,0xe2,0xe7,0xe1,0x1f,0xc9,0xff,0x90,0x7f,0x0e,0x6c,0xed,0xfc,0x29,0x85,0x3d, - 0x12,0xd3,0x0f,0x33,0x0b,0x33,0xfd,0x46,0xbe,0xfe,0x39,0x16,0x0f,0xd4,0xb5,0x57, - 0xca,0x7d,0x5d,0xb5,0x14,0xc6,0xac,0x42,0xa0,0x42,0x89,0x9a,0xc9,0xbb,0xc1,0x10, - 0x2a,0xe7,0xe9,0x9f,0x49,0x68,0x78,0x4a,0x3f,0xe3,0x7f,0x4a,0x87,0x73,0xb0,0xa7, - 0x00,0xff,0x83,0xf6,0x17,0x4b,0xff,0x09,0x61,0xcf,0xa0,0x84,0xd6,0xde,0xc3,0x35, - 0xdb,0x67,0x60,0x3d,0x05,0x5a,0x2e,0xfc,0xc3,0xc7,0xc4,0xe6,0xa7,0x96,0xcc,0x16, - 0x14,0xb9,0x5a,0x0b,0xac,0x2e,0x1b,0x34,0x61,0x9b,0x9e,0x0f,0x2d,0xf1,0xc0,0x3f, - 0x92,0x9f,0x47,0xb3,0xa8,0xfa,0x67,0x72,0x1c,0x7e,0x06,0x36,0xe2,0xc2,0x9f,0x8f, - 0x7f,0xe6,0x4a,0xc2,0xdf,0x5c,0x7b,0x2d,0x6c,0x54,0x1f,0xa7,0x1b,0xc3,0xcf,0xf8, - 0xd6,0xda,0x33,0x44,0x79,0xfa,0x9f,0x0f,0x7c,0xf7,0x6d,0x2f,0x55,0xb8,0x26,0xe9, - 0x75,0xe5,0x20,0x15,0x42,0xff,0x4a,0xdb,0xa1,0xc3,0x1e,0xca,0xff,0xe0,0xfb,0x7b, - 0xe0,0x9f,0x4e,0x9c,0x0f,0x83,0x3a,0xed,0xf3,0x3e,0x2e,0xe4,0x2d,0x85,0x5e,0xa1, - 0xfc,0x17,0x84,0x32,0xa1,0x26,0xaa,0x7e,0xc9,0x06,0xf7,0x74,0xe4,0x7f,0xa1,0x79, - 0xf8,0x07,0x4a,0x5b,0x49,0x39,0xbc,0xac,0xeb,0x7f,0xf2,0xd7,0x8f,0x79,0xf8,0x47, - 0x0d,0xdc,0x47,0x12,0xd1,0x67,0xdb,0x2b,0xb2,0xc2,0xbd,0x24,0x3f,0xff,0x95,0x87, - 0x7f,0x0e,0xfb,0xeb,0xfc,0x01,0x69,0x73,0xaa,0x8a,0xe2,0x9f,0xf3,0x39,0x44,0x74, - 0xc0,0x0b,0xff,0x7c,0x04,0x73,0xd3,0xa1,0x55,0x5c,0x3d,0x5c,0x86,0x84,0x12,0x41, - 0xb4,0xa3,0xd8,0x32,0x62,0xde,0xf8,0x47,0x0c,0xb5,0x07,0xb6,0x31,0x21,0xd0,0x4c, - 0x70,0xf3,0x21,0x5e,0xfa,0x67,0x9a,0xdd,0x98,0xad,0x8c,0xaa,0xf5,0x72,0x68,0xeb, - 0x42,0xbb,0x3e,0x16,0xea,0xbd,0xf0,0x0f,0xad,0xcf,0x43,0x7e,0x0a,0x7b,0xf8,0x5a, - 0x39,0xb0,0xb5,0x68,0x27,0x23,0x82,0x0c,0x44,0x54,0x9b,0x8f,0x7f,0x1e,0xa7,0x6c, - 0x73,0x9a,0xe8,0x1b,0xc1,0x96,0x6e,0x26,0x8e,0xfe,0xd5,0xde,0xf8,0x47,0xd8,0xbc, - 0xbe,0x53,0xdd,0x0f,0x2b,0xe8,0xfe,0xf7,0x4e,0x95,0xf2,0x21,0x9c,0x8e,0x88,0xaa, - 0x3c,0xf1,0x8f,0x52,0x42,0xb8,0x08,0x9a,0x05,0x61,0x5e,0x3b,0x51,0xdb,0xfb,0x72, - 0xe3,0xad,0x77,0xe1,0x9f,0x4f,0x32,0xd1,0xf2,0xc2,0xd0,0x4b,0x1d,0x17,0xd5,0x3f, - 0x1a,0xc0,0x46,0x65,0xdb,0xbe,0xd8,0x78,0x23,0xc9,0x25,0x1e,0xf8,0xe7,0x16,0x39, - 0xf8,0x5b,0x6e,0x81,0xf2,0x22,0x34,0xca,0xfe,0x7e,0x8c,0x77,0xa3,0xb2,0x33,0x51, - 0xf8,0x82,0x7b,0xff,0xbb,0x4f,0x58,0xe3,0xaf,0x58,0xbc,0x9e,0xa2,0x9d,0x4e,0xf2, - 0xb6,0xd6,0x23,0x99,0x88,0x48,0x8a,0x09,0xfe,0x7c,0xfd,0x73,0x4c,0x8e,0x4c,0xbd, - 0x76,0xb1,0xda,0xc6,0x47,0xe5,0x6b,0xc5,0xb2,0xde,0xf4,0x1e,0x5f,0x54,0x5e,0xca, - 0xc6,0x2b,0x44,0x9b,0x98,0xde,0xdb,0x7c,0x7f,0x83,0xff,0x69,0x8d,0x94,0x85,0x57, - 0x14,0xad,0x6b,0x33,0xcc,0xf8,0x48,0xce,0x9e,0xd1,0x85,0xfe,0x3c,0xfd,0x33,0xdf, - 0xd0,0x1a,0x4c,0x57,0x2e,0x56,0x8e,0xe8,0xbb,0xdd,0xdf,0xd0,0x15,0x41,0xb6,0xf7, - 0xf7,0xc2,0x3f,0x8b,0x76,0xf2,0x14,0x06,0x53,0x6b,0x2c,0x74,0xf3,0x81,0x79,0xf8, - 0xa7,0xac,0xa4,0x1d,0xd1,0x4e,0x1f,0x49,0xc0,0x49,0x85,0xab,0x20,0x7d,0xb0,0xd7, - 0x31,0xdf,0xdc,0xf8,0x67,0x6e,0x46,0xc8,0x92,0xba,0xf0,0x83,0x62,0x58,0xd9,0xf0, - 0x04,0xa1,0x42,0xe8,0xb0,0xb2,0xd4,0xce,0xff,0xb8,0xf1,0xcf,0xb7,0x8b,0x3f,0x5d, - 0xe6,0x4f,0xb7,0xcb,0xaa,0x9e,0xff,0xea,0xd0,0xfd,0x73,0x01,0xfe,0x67,0x1f,0xcc, - 0x85,0x95,0xc3,0x61,0x11,0xd6,0x74,0xde,0x41,0x85,0x2e,0x33,0x14,0xba,0xed,0x4b, - 0xff,0x7e,0x25,0x96,0x2a,0xca,0xc3,0x3f,0x15,0x9f,0xff,0x0e,0x97,0x80,0x5e,0x85, - 0xe9,0x9f,0x93,0x70,0x52,0x9d,0x67,0xf0,0x3f,0xed,0xf9,0xf8,0x87,0x3a,0x0d,0xdf, - 0xf2,0xf8,0x72,0x84,0xd9,0x18,0x6d,0x75,0x37,0x22,0x9a,0xfe,0xa4,0x3c,0xf9,0xc2, - 0x64,0x0f,0xfc,0xa3,0x96,0x9c,0xf2,0xdf,0xaf,0xbd,0x80,0xcf,0xe7,0xf7,0x73,0xe7, - 0x53,0xe3,0xca,0x8d,0x13,0xf0,0x3f,0x88,0x7f,0x1a,0x9a,0x6f,0xf5,0x7f,0x02,0x7e, - 0x2b,0x46,0xb4,0x9a,0xd5,0xdc,0x46,0x85,0xb9,0x91,0x09,0xf8,0x9f,0xb9,0xc2,0x9c, - 0x16,0x52,0x7e,0xf4,0x61,0x98,0xc5,0xfc,0x95,0xb2,0x8f,0xaf,0x39,0x54,0x98,0xff, - 0xd9,0xe1,0x0b,0x96,0x0b,0x0f,0x1f,0xa6,0x60,0x65,0xb7,0xbe,0xfe,0x32,0xdc,0x8e, - 0x55,0x0a,0xa6,0xcf,0xe2,0x9f,0xf5,0xfc,0xd7,0x0c,0xb1,0xe4,0x19,0xce,0xaf,0x3c, - 0xe4,0x7b,0x1a,0xa3,0x1b,0x73,0xb3,0xb5,0x66,0x62,0xab,0xd1,0x83,0xff,0xf1,0xa1, - 0xff,0xa1,0xf5,0xc7,0x46,0x9a,0xeb,0x0d,0xb3,0x90,0x9c,0xbf,0x3d,0xe4,0x81,0x7f, - 0x6e,0x96,0x30,0x08,0xd6,0xf3,0x97,0xe0,0x46,0xd3,0x8d,0xcf,0xd7,0x1b,0x33,0xf3, - 0xf0,0x0f,0xd0,0xfc,0x57,0xd4,0xe7,0xef,0xaa,0xdc,0x0e,0xbb,0xfa,0xaa,0xb5,0xa5, - 0xfb,0x8d,0xb0,0xe5,0xe0,0x73,0xdc,0xf8,0x87,0x2f,0xde,0x4a,0xa2,0x1d,0x3d,0x8a, - 0x2e,0x9c,0xf6,0x59,0xfd,0x19,0x03,0x90,0x09,0x3b,0xf0,0x8f,0xaf,0x9b,0x16,0xfd, - 0x2b,0x27,0x3f,0x69,0x53,0x40,0xd5,0xd6,0xc5,0xdb,0x8f,0x2b,0xdd,0x92,0x63,0xbe, - 0x81,0x1b,0xff,0xd4,0x87,0x4a,0xfa,0x27,0xcf,0x09,0x8f,0x40,0x6d,0x3f,0x2e,0xab, - 0x87,0x94,0x31,0x69,0xef,0xd1,0x4d,0x74,0xbc,0xbf,0xd7,0xed,0xe3,0xc6,0x3f,0xb7, - 0x08,0x81,0xfe,0x29,0x0a,0x5c,0x8a,0x34,0x1e,0xc5,0x40,0x46,0x85,0xd0,0x66,0xfc, - 0xe2,0x1b,0xe9,0xfe,0x26,0x37,0xfe,0x31,0xd8,0xc2,0xdf,0x2b,0xc9,0xe3,0xab,0x2e, - 0x70,0xb7,0xe0,0x1b,0x35,0xf6,0x6d,0xbc,0x40,0x85,0x52,0x91,0xf9,0xeb,0xbd,0xf8, - 0x9f,0xb3,0x81,0x9e,0x32,0xda,0x98,0x7b,0x4a,0x78,0x7f,0x7d,0x83,0xd6,0xa7,0xc4, - 0xaa,0x4a,0xd6,0x85,0xff,0x20,0x77,0x69,0xe1,0x56,0x0f,0xfe,0x27,0x62,0xad,0x2f, - 0x4e,0xf9,0x13,0x65,0x41,0xba,0x43,0x19,0xfc,0x12,0xa1,0x0b,0x4f,0x49,0x09,0xc4, - 0x9b,0xbc,0xf9,0x1f,0x36,0x6d,0x84,0x0c,0x44,0x85,0x47,0x28,0xec,0x4c,0x93,0x41, - 0xe1,0x09,0xba,0xb1,0xc5,0x6b,0xff,0x17,0xcb,0x87,0x52,0x7e,0x66,0x59,0x66,0x51, - 0x14,0x06,0xc9,0x4c,0x0a,0x6c,0x2e,0xd1,0xd0,0xa7,0x78,0xf0,0x3f,0xf4,0x47,0x27, - 0x97,0xf4,0x42,0x88,0xad,0x8b,0x8e,0xc3,0x7b,0x52,0x03,0xfc,0x63,0x6f,0x87,0x86, - 0xeb,0xaf,0xc6,0x96,0x99,0x5e,0xfc,0xcf,0x4c,0x13,0xed,0xe0,0x44,0xba,0x0f,0x4e, - 0xcd,0xc3,0x85,0x98,0xca,0x55,0xc9,0x9a,0x2f,0xa1,0x14,0xda,0xff,0x45,0xdf,0x7f, - 0xee,0xa1,0x2e,0xfa,0x1f,0x3a,0xa6,0x20,0x90,0x4e,0x57,0x57,0x53,0x20,0x27,0x17, - 0xd8,0xff,0x25,0xdb,0x88,0xa0,0x32,0x19,0x07,0x3e,0x95,0x04,0xd2,0x1c,0xb0,0x42, - 0x88,0x79,0xfc,0x8f,0x15,0xfd,0xcf,0x0a,0xab,0x13,0x67,0xfe,0x7a,0xcd,0xb6,0xbb, - 0x67,0x09,0x73,0xc8,0x27,0xe4,0x4e,0x9a,0x2a,0xf2,0xe0,0x7f,0x34,0x23,0xdb,0x55, - 0x3f,0x58,0x52,0xcf,0x7d,0xa1,0xf7,0x37,0xb4,0xec,0xa1,0x8f,0x03,0x72,0x08,0x32, - 0xb2,0x53,0xff,0x5c,0xe2,0xd0,0x47,0xcd,0x78,0x21,0xf4,0x47,0x2a,0x04,0x92,0x1a, - 0x0f,0x21,0x10,0xba,0x44,0x53,0x63,0xca,0x44,0xfc,0x4f,0xb2,0x3f,0x98,0x59,0xd4, - 0x20,0x9d,0x7a,0xb5,0x5e,0x8b,0xa6,0x03,0xb4,0x90,0x60,0xa2,0x39,0x3a,0x01,0xff, - 0x13,0x3d,0x2a,0x7c,0xd8,0xd4,0xa0,0x3c,0x46,0x33,0x80,0x12,0xe1,0x71,0x3e,0x2c, - 0x68,0x2f,0xb4,0xff,0xeb,0x4c,0xf1,0x3e,0x7d,0x77,0xdb,0xed,0xda,0x6e,0xad,0x46, - 0x12,0x9a,0xc9,0xad,0xd0,0xa9,0xcc,0x4a,0x79,0xec,0xff,0x72,0xf0,0x3f,0x65,0xcb, - 0x60,0x87,0x56,0x45,0xb7,0x7d,0x51,0xa9,0x67,0x95,0x22,0x14,0xd8,0xff,0xa5,0xa3, - 0x9d,0xa0,0xba,0x68,0x25,0x9c,0xd3,0x1a,0x68,0xfd,0xc3,0x95,0xf8,0xfe,0xb5,0x74, - 0x07,0x71,0x41,0xfe,0xa7,0x41,0x5f,0x98,0x77,0xa5,0x6e,0x16,0x67,0x6a,0x5c,0x1a, - 0x2e,0x4a,0x8d,0xde,0xfb,0xbf,0x2c,0x7d,0x48,0x89,0x48,0x37,0x82,0x61,0x7c,0x2f, - 0x99,0xca,0x84,0xcd,0x71,0x0f,0xfd,0xb3,0x9d,0xff,0x41,0x20,0x54,0xc5,0x6f,0x90, - 0xa8,0x9e,0xa7,0x72,0x85,0x90,0xaf,0x7f,0xb6,0xf3,0x3f,0x8f,0xeb,0x7c,0x11,0xdd, - 0x08,0x16,0x6b,0x9a,0xd3,0x5f,0xd6,0x00,0x3f,0x87,0xaf,0x69,0xc2,0x44,0xfa,0x9f, - 0x25,0x42,0xd9,0x7a,0x7e,0x57,0x1b,0xdc,0xbd,0x44,0xb8,0x75,0xcd,0x97,0xd4,0x9f, - 0x54,0xdf,0xe1,0xd2,0x3f,0xdb,0xf5,0x3f,0x83,0x10,0x13,0x42,0x4c,0xff,0x4c,0x92, - 0x42,0x09,0x36,0xda,0x07,0xa5,0x6e,0xa6,0x7f,0xf6,0xe6,0x7f,0xf4,0x6a,0x87,0x5b, - 0x06,0x7e,0xfa,0x3e,0x24,0x17,0xbe,0xc7,0x36,0x82,0xe5,0xf1,0x3f,0xd6,0xfe,0xa9, - 0x2f,0xb2,0xc6,0x6d,0xc1,0x2d,0x1d,0xb3,0x94,0x57,0xf8,0xc6,0xe6,0xe8,0x66,0xae, - 0x4a,0x3a,0x22,0x24,0x96,0x78,0xef,0xff,0xd2,0xf9,0x9f,0xba,0xa9,0xfe,0x35,0x04, - 0xdf,0x07,0x70,0xc5,0xa1,0x90,0x79,0xd0,0xb5,0x38,0x2c,0x16,0xda,0xff,0xc5,0x80, - 0x50,0x33,0xa2,0x9d,0x49,0xca,0x1e,0xa8,0x59,0xe1,0xff,0x12,0x99,0x8a,0xee,0x1e, - 0xbf,0x2f,0x07,0xff,0x33,0xc9,0xae,0xf6,0xe1,0x59,0xb5,0x1f,0x44,0x98,0x8b,0x63, - 0x29,0xff,0x45,0xb2,0x40,0x31,0xf5,0xe4,0x39,0xfc,0x33,0xc9,0x3e,0x5e,0x8e,0xa2, - 0x9d,0xe9,0xb4,0x10,0x62,0xb2,0xf5,0x41,0x5d,0xe8,0x9e,0x28,0x84,0x7f,0x68,0xff, - 0x49,0xf5,0x7a,0xe3,0x15,0x36,0x31,0x02,0xbd,0xe4,0x7d,0xed,0xa0,0x3c,0xd7,0x81, - 0x7f,0x40,0x85,0x53,0x76,0x74,0x8d,0xd6,0xc6,0xaf,0x08,0x1a,0x84,0xdd,0x0a,0x27, - 0x55,0xe9,0x42,0x20,0xef,0xfd,0x5f,0x16,0xff,0xb3,0x0b,0xfc,0x10,0xcb,0x60,0x63, - 0x0e,0xdb,0x1a,0xef,0xdc,0xff,0x35,0x6d,0x99,0xfd,0x7b,0x89,0x69,0x5d,0xf1,0x6b, - 0x83,0x62,0xc7,0xa4,0x68,0x05,0x08,0xc4,0x87,0x57,0x54,0xcd,0x73,0xff,0x97,0x19, - 0xfd,0x8f,0x47,0xee,0x21,0x8f,0xca,0x6b,0x61,0x2e,0x41,0x7f,0x45,0x6f,0x49,0x9a, - 0xe7,0xfe,0x2f,0x33,0xdb,0xf5,0xfa,0xb2,0x7a,0x34,0xd2,0xaf,0x94,0x86,0x54,0x70, - 0x65,0xa0,0x0c,0x3e,0x68,0x9b,0x97,0x8d,0x7a,0xed,0xff,0xb2,0xa2,0xf9,0xf2,0xa7, - 0x3b,0x86,0xda,0x47,0x7c,0x6c,0x5b,0x53,0x41,0xfe,0x27,0x97,0xed,0x1a,0x28,0x1d, - 0xe9,0x48,0xca,0x27,0xb5,0x64,0x2a,0x38,0xc8,0xd5,0x22,0x5a,0x9c,0x9f,0x0d,0x7a, - 0xe0,0x1f,0xe3,0xfd,0xf9,0xbb,0x07,0x43,0x09,0xf2,0xa0,0xfc,0x2b,0xf5,0xeb,0x2b, - 0x84,0x6f,0xb5,0x5f,0x57,0xf5,0x98,0x30,0xe7,0x05,0xc1,0x63,0xff,0x57,0x6e,0x75, - 0xe6,0x6f,0x85,0x47,0x95,0x1f,0x88,0x35,0xb2,0x3f,0x45,0xbe,0x24,0xaf,0x15,0x2b, - 0xe8,0x78,0x0b,0xf0,0x3f,0xdd,0xf0,0x4d,0xba,0xdb,0x7d,0x23,0x28,0xe9,0xaa,0x55, - 0xd5,0x09,0xf2,0x79,0xf4,0x3f,0x91,0x3e,0xa1,0x90,0xfe,0x07,0xc6,0xb8,0xc6,0x43, - 0x18,0xb6,0x1a,0xca,0x4e,0xc9,0xc9,0x74,0xec,0x51,0xee,0x2e,0x38,0xa6,0x25,0x86, - 0xa3,0x5e,0xfc,0xcf,0xf2,0x9c,0x35,0xa6,0x1c,0x87,0xd1,0xe6,0x19,0x0a,0xfa,0x93, - 0x8d,0x91,0x31,0xa9,0x61,0x42,0xfe,0x27,0x49,0xf9,0x9f,0x06,0x38,0xa1,0xd1,0xc0, - 0xca,0xdd,0x00,0xcf,0xfb,0x12,0x78,0xc5,0x8d,0x7f,0x58,0xfc,0xe2,0x56,0xc1,0xcd, - 0xd8,0x20,0x18,0x7f,0x61,0x97,0x12,0xcb,0x0a,0xf4,0xca,0x06,0x7d,0xfd,0xee,0xc0, - 0x3f,0x3e,0x2b,0xde,0xd1,0xfe,0x3e,0xec,0xcf,0x77,0x09,0xb1,0xc5,0x46,0xbe,0x86, - 0x11,0x47,0x9e,0xfa,0x1f,0x36,0xf1,0xfa,0x71,0x75,0x1f,0xec,0xda,0x36,0x69,0x55, - 0x53,0x35,0x5e,0x61,0xf5,0x16,0x8a,0x3d,0xf8,0x1f,0x73,0x3e,0xcc,0x3d,0x15,0xfc, - 0x36,0x77,0xfd,0x8a,0xf5,0x55,0xc9,0xe6,0x52,0xaa,0x6f,0x39,0x86,0xef,0x1f,0xf5, - 0xe0,0x7f,0x74,0x99,0xd3,0xf7,0x20,0x79,0x2a,0x70,0x61,0xc3,0x90,0x32,0x22,0x36, - 0x2e,0x2c,0x61,0x3b,0xc8,0xf2,0xf9,0x9f,0x67,0xcd,0xfc,0xd7,0x05,0x38,0xde,0xf6, - 0xbf,0x72,0xb0,0x19,0xa7,0xcd,0xe5,0xa9,0xe3,0xe9,0x1b,0x75,0xfd,0x4f,0xce,0xfe, - 0x14,0xf6,0x94,0x22,0xfe,0x21,0xaf,0x83,0xa0,0xdc,0x99,0xd3,0xff,0xf8,0x0d,0xfe, - 0xe7,0xac,0x03,0xff,0x44,0x78,0x23,0xe9,0x50,0x37,0xbb,0x0f,0xb6,0xda,0x97,0x15, - 0xba,0xde,0x49,0x07,0x7e,0x87,0x7d,0xe6,0xfc,0xd1,0xa6,0x19,0x20,0xb3,0x87,0x9c, - 0x83,0xad,0xc5,0x61,0x7d,0x63,0xbb,0x29,0x84,0xc6,0x7f,0x58,0xed,0xd4,0x3f,0x03, - 0xab,0x3f,0x8c,0xcb,0x84,0x9e,0x45,0xaf,0xc3,0x29,0xf9,0xce,0x1c,0xed,0x10,0xd4, - 0x1b,0x34,0xa3,0x3a,0x45,0xfb,0x92,0xf9,0xfc,0x6d,0xa2,0xb5,0xff,0x7d,0xb8,0x6c, - 0xe8,0xa1,0xef,0x7a,0xe7,0x43,0x07,0xbd,0xea,0x1f,0x46,0x60,0x50,0x76,0xca,0x5a, - 0xcc,0xe7,0xdb,0xf1,0x0f,0x6f,0xe0,0x9f,0x47,0x48,0xa9,0xa8,0xfe,0x55,0x75,0x0e, - 0xc8,0x19,0x8d,0x5a,0x3d,0xff,0x65,0xfe,0x69,0xb9,0xf9,0xd0,0x24,0xa7,0x5d,0xcb, - 0x2e,0x5d,0x0f,0xef,0xcc,0x7f,0x01,0xc5,0x3f,0x77,0x0f,0x4e,0x6f,0x25,0xf7,0xf0, - 0x4f,0x32,0x19,0x8c,0x41,0x83,0x4c,0xd7,0x1b,0xb3,0x5c,0xf9,0x2f,0x30,0xf6,0xbf, - 0xcf,0xeb,0x58,0x02,0x2f,0xd1,0x6a,0x3f,0x09,0x7c,0xac,0x4d,0xff,0x13,0xef,0x73, - 0xe6,0xbf,0xae,0x33,0xf4,0xcf,0xad,0x5c,0x97,0x9c,0x15,0x73,0x66,0xe9,0xcd,0xd9, - 0xe7,0x7d,0x7b,0xfd,0xe7,0x49,0x3a,0x2c,0x0c,0xf5,0x30,0xb7,0x5c,0x40,0xff,0x93, - 0xd3,0x3f,0x0f,0x5a,0xf5,0x0f,0xcb,0x44,0xbe,0x33,0xe7,0x58,0xdc,0xfa,0x1f,0xb3, - 0x3f,0x30,0xfc,0x83,0xc3,0x1c,0x21,0xf5,0xf0,0x40,0x6e,0xbc,0x15,0x56,0x46,0xac, - 0x80,0xfe,0x39,0x42,0x26,0x83,0xa2,0x39,0xcd,0x68,0xe3,0x7f,0xac,0xf7,0xe1,0x29, - 0xfe,0xa9,0x57,0x42,0xd9,0x8e,0x4f,0xde,0x73,0x42,0xc6,0x06,0x5d,0x26,0x7f,0x04, - 0x7b,0x1d,0xfc,0x8f,0x4d,0xff,0x6c,0xe4,0x23,0x96,0x6f,0xa4,0xf1,0x48,0xf4,0xd2, - 0xc3,0xb8,0xf0,0xcf,0x4e,0x73,0x7f,0xf7,0x5b,0x70,0x44,0x60,0x0b,0x7f,0x07,0x42, - 0xa8,0x97,0x97,0xa7,0xa7,0x1c,0x9e,0x9a,0xc3,0x3f,0x06,0x9e,0x79,0x98,0xbc,0xc9, - 0xbf,0xd2,0x9b,0xaf,0xe7,0x09,0xbb,0xf8,0x1f,0x30,0xf1,0x4f,0xd9,0x80,0xb8,0x4e, - 0xcb,0xef,0x6f,0xf0,0x3f,0xe6,0x9f,0xb5,0xff,0x2b,0x1e,0xce,0x25,0x86,0xd8,0x15, - 0x9d,0x0f,0x31,0xf6,0x43,0x59,0xfd,0xeb,0xca,0x6d,0xf8,0xa7,0x0f,0xee,0xcf,0x1b, - 0x2f,0xe3,0x7f,0xce,0x58,0xf5,0x0f,0x7b,0x4c,0xfc,0xd3,0xc2,0x5d,0x64,0x85,0x80, - 0x36,0xd9,0x68,0x0d,0xc6,0xff,0x38,0xf1,0x4f,0xdd,0x24,0x63,0x93,0x7b,0x0b,0x37, - 0x15,0x5e,0x84,0x5a,0xbd,0xdb,0xc7,0x78,0x65,0x95,0xb1,0xa3,0xdc,0x99,0xff,0x2a, - 0x17,0xb3,0xbc,0xae,0x7f,0xfe,0x62,0xca,0xe7,0xd7,0x0b,0x01,0xe9,0x88,0xc8,0x8f, - 0x0d,0xa1,0x47,0x0a,0x3b,0xf3,0x5f,0x66,0xfd,0xe7,0x75,0x22,0x59,0x81,0xce,0xbd, - 0x2a,0x37,0x5e,0x5d,0xef,0x2d,0x54,0xb9,0xf4,0xcf,0x53,0x75,0xfc,0x53,0xfc,0xd0, - 0xf6,0x15,0xca,0x23,0xe2,0x6c,0x79,0xba,0x69,0x4f,0xbf,0xcd,0xfe,0x39,0xfd,0xf3, - 0x76,0xde,0x80,0xb5,0x0f,0x73,0x2b,0x22,0x47,0xb4,0x5a,0xf3,0xf7,0x8d,0x19,0xfa, - 0x76,0x9e,0xbd,0xff,0xa0,0x55,0xff,0x70,0xd0,0x98,0x0f,0xb1,0xad,0xdc,0x9b,0xe4, - 0x6d,0xa5,0xde,0x02,0x8a,0x0b,0xed,0xfc,0xcf,0x47,0xf9,0xfb,0xbf,0x1e,0xe0,0xc2, - 0x8b,0x4f,0xc9,0xb5,0x79,0xf6,0x67,0x85,0x08,0x72,0xfb,0xbf,0x80,0xd5,0x3f,0x8c, - 0x2a,0x81,0x95,0xe4,0x87,0xb0,0xe6,0x4b,0xd5,0x66,0x22,0x2c,0x6a,0x36,0x6a,0x75, - 0x45,0x90,0xe9,0x1f,0x04,0x73,0xfd,0x35,0x9b,0x00,0x69,0x97,0xdd,0xfe,0xe7,0x80, - 0xfe,0xe1,0x1c,0xb5,0xe6,0x43,0xc5,0x35,0x06,0xfe,0xd1,0xca,0x7a,0x60,0x2d,0xcc, - 0x71,0x7c,0xb6,0xb4,0xc1,0x36,0xc2,0xf7,0x99,0x8f,0xcf,0xed,0xff,0x5a,0xc9,0x5d, - 0x6b,0xf0,0x3f,0xc4,0xa6,0xff,0x19,0x1f,0x66,0x57,0x8e,0x86,0xad,0xf9,0x69,0xe0, - 0x81,0xe5,0xf8,0xf5,0x21,0xd4,0x35,0xf9,0x0d,0x93,0x0f,0x19,0x93,0x74,0xfc,0xb3, - 0xd6,0x1c,0x6f,0x8a,0x7f,0x96,0x15,0x39,0x0c,0x8d,0x71,0x3f,0x96,0x5f,0x48,0xb3, - 0xb4,0xc5,0x2f,0x64,0x3b,0x22,0x62,0xfb,0xbf,0x72,0xfa,0x67,0x78,0x94,0xd6,0x7f, - 0x1e,0x0a,0x7c,0xbd,0xbd,0x54,0x59,0xa3,0x7e,0x9a,0xee,0xbf,0x38,0xa3,0xcb,0x92, - 0x73,0x03,0xe1,0x9e,0xb0,0xf4,0xd5,0x8a,0xa8,0xef,0x76,0xf7,0x7f,0x83,0xfc,0x4e, - 0xee,0x94,0x66,0xe5,0x8d,0xb7,0xc6,0xb9,0xff,0x4b,0x9e,0x4a,0xe3,0x5d,0xf0,0x10, - 0xfa,0x9f,0x65,0xa0,0x64,0xab,0xac,0xfd,0x17,0x0e,0xc3,0xda,0xf6,0x7f,0x19,0xeb, - 0xc7,0xd2,0xc8,0xe4,0x73,0x53,0x95,0xae,0x5a,0x73,0xa1,0xed,0x10,0x36,0xdb,0xf0, - 0xad,0x6a,0xc6,0xa3,0xce,0xc9,0xbb,0xe4,0x11,0xf9,0x7e,0xd6,0xcd,0x37,0xe6,0x73, - 0xf2,0xed,0xaa,0xf5,0x7b,0x99,0xf8,0xa7,0x34,0xcb,0xad,0x2e,0xac,0x77,0xcd,0xe9, - 0x9f,0x0f,0x19,0xf9,0xaf,0xa5,0x3b,0xc9,0x0d,0x91,0x1e,0x6d,0xaf,0xb7,0x9e,0x67, - 0xd8,0xfa,0x7d,0xe9,0xfe,0x2f,0x26,0x53,0x51,0x8b,0xee,0x82,0x9e,0xae,0x7c,0xfd, - 0x8f,0x5b,0xff,0x0c,0x41,0x9e,0xc2,0x9e,0x80,0xda,0x24,0xc8,0x19,0x9c,0x5d,0x4b, - 0xd1,0x2c,0xaa,0xdb,0x3e,0x39,0xff,0x03,0x40,0xf7,0xbf,0x27,0x4f,0x85,0x70,0x35, - 0xaa,0x8c,0x48,0x66,0x61,0x4c,0x48,0xf6,0x06,0x6c,0xf6,0xd1,0xac,0xfa,0xf3,0xea, - 0x35,0x0c,0xe6,0xfd,0x3a,0x94,0xe2,0xde,0x4e,0x8f,0xc8,0x66,0x59,0x1b,0xc1,0x1a, - 0x2f,0x2b,0x05,0x30,0x38,0x39,0x8f,0xff,0xb9,0x30,0xe5,0x92,0x82,0xff,0xb0,0x6f, - 0xd3,0x05,0xc6,0x2f,0xdd,0xa8,0x6d,0x1c,0xe1,0x3e,0xf4,0xd0,0xff,0x80,0xa1,0xff, - 0xd9,0x1f,0x3e,0x2f,0x1f,0xe8,0x8f,0x0d,0x07,0xfe,0x85,0xbc,0x27,0xbf,0xd3,0x3f, - 0x17,0x7d,0x0f,0xdd,0x9f,0x95,0xa7,0xff,0x01,0xfa,0x7d,0xb1,0x4d,0x5e,0xbd,0xb0, - 0x8d,0x44,0xfa,0x37,0xe8,0xc3,0x64,0x89,0x89,0x01,0xbd,0x30,0x94,0x73,0xff,0xd7, - 0x6e,0x97,0xb5,0x9f,0x26,0xef,0x52,0x61,0x27,0x85,0x91,0x03,0xf9,0xfb,0xbf,0xc0, - 0xe4,0x1f,0x14,0x16,0xad,0xee,0x7f,0x21,0x94,0xa9,0x1c,0x40,0xb7,0x50,0x4b,0xf1, - 0xcf,0x0b,0xa6,0x62,0x27,0xf7,0xfb,0xaa,0xd7,0xe8,0xf8,0x67,0x53,0x96,0x9e,0x76, - 0x41,0xd8,0xe8,0x2e,0xc1,0xf9,0x22,0x66,0x9f,0xf1,0x09,0xf0,0xcf,0x66,0x8e,0x6d, - 0x64,0x7e,0x29,0xf4,0x24,0x2d,0xd3,0x21,0x25,0x7b,0x69,0x7d,0x63,0xf3,0xf9,0x0e, - 0xfe,0x87,0x37,0xf0,0x1b,0xda,0x67,0x21,0x5a,0x63,0x5f,0xd9,0xbb,0xda,0x01,0xb9, - 0x26,0x1b,0xa1,0xef,0x6f,0xe9,0x9f,0xcd,0x3f,0x0b,0xff,0x2c,0x20,0xcb,0xe4,0x6e, - 0x59,0x12,0x8b,0xa1,0xec,0x73,0xbe,0x6e,0x91,0xe1,0xc3,0x5e,0xd3,0x3e,0x6e,0xfc, - 0xa3,0xf3,0x21,0xe2,0xbe,0xad,0x25,0x3b,0x03,0x7f,0x17,0x7e,0x55,0xd9,0xd7,0x19, - 0x1d,0x11,0x6c,0xf9,0x20,0x1b,0xfe,0x29,0x0f,0x1a,0x22,0xe7,0x8e,0x5e,0x5a,0x1d, - 0xf4,0xae,0x90,0x48,0x37,0x82,0x29,0x0d,0x43,0xf4,0xfc,0x0b,0xf8,0x4d,0x9e,0xfe, - 0x27,0x68,0xe7,0x7f,0x7c,0x8c,0x5d,0x1c,0x92,0xc7,0x3f,0xdd,0xf8,0xba,0x77,0xfe, - 0x4b,0x30,0xed,0xdf,0xc5,0x55,0xc3,0xab,0xca,0xff,0x25,0x05,0xbb,0xb8,0x30,0xf4, - 0x29,0x09,0x5a,0xa8,0x6a,0xc0,0x63,0xff,0x97,0x89,0x7f,0x52,0xa4,0x1c,0xd6,0x40, - 0x45,0x9b,0xc0,0x1a,0xbe,0x8a,0x21,0x6f,0xfc,0x63,0x9d,0x7f,0x51,0x4e,0x8a,0xa0, - 0x4d,0x91,0x52,0x42,0x39,0x02,0x9b,0x87,0x10,0xff,0x2c,0xf5,0xdc,0xff,0xb5,0xd2, - 0xe2,0x7f,0xfc,0x41,0xd2,0xd1,0xac,0x6a,0x11,0xda,0xd8,0xa2,0xa8,0x8e,0xef,0xcb, - 0x8d,0x7f,0x10,0xe4,0xbc,0xdb,0x71,0x13,0x9c,0x59,0x78,0x63,0x5b,0x30,0xcb,0xd5, - 0xc3,0x99,0xe6,0xc4,0x15,0xf0,0x4f,0xc8,0xa8,0xbe,0x62,0x10,0x23,0xd2,0x15,0xf1, - 0x8f,0x2d,0xdb,0xc5,0xf6,0xfb,0xc8,0xc1,0xcd,0xde,0xfa,0x67,0x0b,0xff,0xbc,0x41, - 0xab,0xf7,0xb4,0x2c,0x65,0x8d,0x26,0x46,0x04,0x15,0xd0,0x3f,0xeb,0x17,0xdb,0x07, - 0xa4,0xfd,0x42,0xac,0x89,0x36,0x2a,0x1e,0x11,0x9c,0xfd,0x6d,0xf8,0xc7,0xe4,0x7f, - 0xca,0xda,0x7b,0xd5,0x3d,0x73,0xa2,0x4b,0xf4,0x46,0x24,0x7a,0x97,0x60,0x29,0x82, - 0x1c,0xfc,0xcf,0xf5,0x29,0x6b,0xdb,0x17,0xf5,0x3f,0xc5,0x66,0x43,0x88,0xd8,0xc6, - 0xeb,0x81,0x7f,0x98,0xfe,0x99,0x26,0xc2,0xb0,0x21,0x7c,0xac,0xc3,0x98,0x8b,0xe6, - 0x78,0x73,0xe7,0x5f,0xd4,0x59,0xfc,0x4f,0xc7,0x4e,0x69,0x54,0xd0,0x0d,0xa5,0xe0, - 0x95,0xe6,0x90,0x5d,0xff,0x6c,0x7d,0xef,0xe5,0x82,0xc1,0xff,0x74,0x92,0x0a,0x26, - 0x84,0xa6,0x65,0x7f,0x82,0x3d,0x0b,0xe7,0xea,0xf5,0x0f,0x4d,0xfd,0x73,0x91,0x1b, - 0xff,0x04,0x4e,0xb1,0xd3,0x61,0x6a,0xbe,0x15,0xf8,0x4a,0xd9,0xbf,0xc1,0x53,0x2f, - 0xd4,0xb4,0xd8,0xf5,0xcf,0x36,0xfc,0x63,0x9e,0x7f,0xd1,0x42,0xbe,0x0d,0xff,0xc2, - 0xcf,0x95,0x03,0x54,0xf6,0xf3,0x2f,0x30,0xd7,0x01,0x2c,0xdf,0xb4,0xf8,0x19,0x75, - 0xaa,0x0d,0xdf,0x8e,0x6a,0xf7,0xb7,0x84,0x1e,0xae,0x44,0xff,0xb0,0xd0,0x99,0xcf, - 0x1a,0xb4,0xfc,0xe7,0x60,0xae,0xfe,0xf3,0x4e,0x65,0xb4,0xe2,0x7e,0xb3,0x5b,0x2d, - 0x63,0x08,0xcd,0xfd,0x6e,0x1f,0x59,0xf1,0xd7,0xc2,0x3f,0xda,0x17,0xe9,0x0e,0x89, - 0xf9,0x10,0xa4,0xe7,0xfb,0x0c,0x61,0xc3,0x91,0xff,0xb2,0xf0,0x8f,0x60,0xd5,0x7f, - 0xa6,0x69,0x2f,0x08,0x2b,0x5d,0x6a,0x13,0x6b,0x6c,0xb7,0xeb,0x9f,0xfb,0x24,0xd3, - 0x3f,0x08,0x39,0xfd,0xcf,0x83,0xb0,0x43,0x91,0xb2,0xfe,0x3a,0x5a,0xff,0x50,0xa1, - 0x15,0xfc,0xec,0xf9,0x2f,0xf3,0x4f,0x32,0xf9,0x1f,0x99,0x4c,0x81,0xce,0xde,0x8a, - 0xb8,0x7f,0x19,0x49,0x88,0x9d,0x5a,0x05,0xa0,0xc5,0xac,0xef,0xd7,0x86,0x7f,0xca, - 0x0d,0xfc,0x23,0x71,0xeb,0xc9,0xeb,0x4a,0x46,0x8d,0x45,0x02,0xf5,0xf0,0xba,0xb2, - 0x47,0x0d,0xdd,0x96,0xd3,0x3f,0xdb,0xf0,0x4f,0x89,0x79,0xbe,0x43,0xae,0x1a,0x80, - 0x65,0xc6,0x1c,0xff,0xb3,0xc6,0x1c,0x6f,0x6a,0xea,0xb3,0x26,0xc8,0xa9,0x85,0x17, - 0x95,0xe4,0x8a,0xd0,0x2b,0xdc,0x65,0xf9,0xe3,0xb6,0xc6,0xd4,0xf2,0xdb,0x38,0x6b, - 0xff,0x4e,0xff,0x4e,0x1b,0xfe,0x31,0xde,0x9f,0xbb,0x0d,0x7e,0x7b,0x4d,0x8d,0x1a, - 0xb8,0x8b,0xbc,0x04,0x4f,0x43,0xb4,0x13,0xdf,0xff,0xd1,0x42,0xf9,0x2f,0xe6,0xaf, - 0x44,0x9c,0x4a,0x35,0x82,0xbf,0x89,0x9c,0xd2,0x9e,0x14,0x6b,0x24,0xec,0x7f,0x5d, - 0x21,0xfc,0xc3,0xea,0xfb,0x2d,0x33,0xbd,0x77,0xaf,0x71,0x22,0x06,0x5a,0x38,0x1f, - 0xff,0x98,0xfc,0xcf,0x56,0x2e,0x06,0xc7,0xf4,0x8d,0xd8,0x6f,0xb2,0x63,0x05,0x70, - 0xbc,0x51,0x29,0xcf,0x7f,0xaa,0x30,0xa4,0x6f,0xf2,0x8a,0x70,0x87,0x85,0x11,0x25, - 0x29,0xa1,0xe3,0x3d,0x0a,0x23,0x0a,0x2e,0x4c,0x72,0xf6,0x99,0x92,0xb5,0xfc,0x9b, - 0xc5,0xff,0xb4,0xe1,0xfa,0xfd,0x04,0x65,0xef,0xb3,0xdc,0xb0,0x7c,0x82,0x6b,0x6c, - 0x63,0x81,0x2f,0x0f,0xff,0xd8,0xf4,0x3f,0x34,0xb1,0xce,0xce,0x7f,0x19,0xd2,0xf3, - 0xe9,0x3d,0x9e,0xf8,0x67,0x92,0xd1,0x9f,0x1d,0x13,0x43,0x62,0x0b,0xbf,0x9c,0xbe, - 0x73,0x00,0xd6,0x15,0x61,0xff,0xcd,0x9e,0xfa,0x67,0x30,0xe2,0x9d,0xe4,0x17,0x60, - 0x3b,0x89,0xb6,0x4f,0x0f,0x93,0x23,0xa4,0x5d,0x44,0xfb,0xdb,0xe6,0x9b,0x8d,0xff, - 0x29,0x5f,0x65,0xc6,0x77,0x89,0xae,0xaf,0x83,0xb4,0xcc,0x7e,0x17,0xcb,0xbf,0x4f, - 0xa4,0x7f,0x36,0xd1,0xce,0x8d,0x7d,0x18,0xaf,0x31,0x7e,0x49,0x8d,0x47,0xbc,0xf5, - 0x3f,0x00,0xa4,0x93,0x55,0xe1,0xf5,0x8b,0x13,0x34,0xc0,0xfe,0xc7,0x03,0xbe,0x9d, - 0x8c,0x1e,0x78,0x82,0x86,0xfd,0xaf,0x13,0x2a,0x40,0x90,0xd9,0xf4,0x29,0xd8,0xf8, - 0x8f,0x3c,0x5f,0xa1,0xc9,0x13,0xfd,0xcc,0xb3,0x82,0x0d,0xdb,0xdf,0xc4,0x1d,0xf5, - 0xc6,0x7f,0xe4,0xf9,0x7f,0xee,0xdf,0x7f,0x32,0xfb,0x8b,0xf4,0x2c,0xbf,0xe3,0xf0, - 0xf7,0x70,0x9d,0x36,0x41,0x83,0xff,0x77,0x3f,0xff,0xff,0x65,0xfb,0xf3,0xa2,0x72, - 0x15,0x36,0xf7,0xd9,0xf8,0xa5,0x3f,0xef,0xaf,0xa1,0xe1,0x6a,0x7a,0x85,0x42,0xff, - 0xce,0xc7,0xff,0x7f,0xf0,0xd7,0x38,0x3e,0x3e,0xae,0x5d,0xa1,0xf1,0xff,0xe7,0xfe, - 0xff,0xc9,0xbe,0xc7,0xff,0xf2,0x87,0xff,0xe5,0x0f,0xff,0x03,0xf6,0xff,0x2f,0x7f, - 0x78,0xa5,0xbf,0xff,0x6c,0xfe,0xe7,0x3f,0x57,0x7f,0x6d,0x1a,0xe5,0xc7,0x6e,0xa1, - 0xc7,0x22,0x5c,0x2e,0x37,0x76,0x13,0x9c,0x07,0x37,0xbf,0xea,0xd2,0x47,0x75,0xce, - 0x1d,0x16,0x54,0xca,0x0e,0xb5,0x25,0xad,0x8d,0x72,0xd8,0xe0,0x7e,0x61,0xd5,0x07, - 0xb0,0xf0,0xbc,0x00,0xec,0xbc,0xce,0xc5,0x82,0x44,0x86,0x4c,0xf5,0x7b,0x3e,0x5f, - 0x9a,0x97,0x1f,0x94,0x05,0x75,0xcd,0x4f,0xe9,0x69,0x20,0x0e,0xbe,0xd1,0xa2,0xce, - 0x72,0xfc,0x98,0x4f,0x3f,0x9f,0x74,0xd7,0xc6,0x9d,0xe4,0xfc,0xc3,0xba,0x7a,0x9f, - 0x1b,0x02,0x6b,0xc7,0xdc,0x98,0x9b,0x1f,0x33,0xf2,0x83,0x03,0x21,0x0d,0x57,0xeb, - 0x16,0x90,0x7e,0x4f,0x6f,0x1c,0x2c,0xc8,0x8f,0x2d,0x2e,0x55,0x11,0x66,0x1f,0x33, - 0x1f,0xeb,0xd6,0x3f,0xbb,0xf3,0x83,0xd1,0x6f,0x0b,0x9d,0x84,0x67,0x6c,0x5e,0xa9, - 0x17,0xbf,0x9a,0x57,0x1f,0x12,0xfc,0x61,0xff,0x83,0x85,0xed,0x93,0xa7,0x8f,0x4a, - 0x09,0xdf,0x29,0x9a,0xa9,0xac,0xd5,0xab,0x41,0x9e,0x51,0xdc,0x7a,0xe9,0x53,0xbc, - 0x6c,0xf4,0xd7,0xeb,0x43,0x36,0x28,0xa5,0xea,0x94,0x5f,0x28,0xcf,0xef,0x61,0x6c, - 0xd8,0x09,0xe5,0x83,0x9c,0x3e,0x5c,0xe7,0xc7,0xac,0x03,0xb4,0x8c,0xfa,0x48,0x03, - 0x38,0xa8,0x83,0xac,0x3e,0x52,0x29,0x3d,0x8f,0x26,0xaf,0x3e,0x80,0xb5,0x7e,0x8c, - 0xe8,0xf6,0x2f,0x0f,0xaa,0x34,0x5b,0xed,0x32,0x8b,0x2d,0x3f,0x68,0xae,0x07,0xfb, - 0x44,0xb6,0xde,0x6c,0x6a,0xc6,0xd5,0x25,0xf9,0x37,0x9d,0x8d,0xd7,0x97,0xd5,0x21, - 0x1b,0x3f,0x76,0x8f,0x2b,0x3f,0x18,0x55,0xfd,0x83,0x45,0xd6,0xee,0xbf,0x89,0xeb, - 0x23,0xe9,0xeb,0xd3,0x72,0x91,0x14,0x9b,0xf6,0xdc,0x98,0x67,0xcf,0x97,0x26,0x99, - 0xef,0xa3,0xd7,0x47,0x6a,0x54,0xa2,0xaf,0x73,0x75,0xf2,0x7a,0x98,0x61,0xe6,0x07, - 0x93,0x85,0xf8,0x31,0x4b,0x1f,0x15,0x70,0xa5,0x05,0xf5,0x83,0x33,0x58,0xbd,0x1a, - 0xee,0x56,0x97,0x3e,0xaa,0x41,0x0e,0x3e,0xcc,0xcd,0x86,0x57,0xe0,0x13,0xe6,0xb6, - 0xf1,0xda,0x09,0xeb,0x03,0xc4,0x64,0x49,0x24,0x6b,0xec,0x32,0x6f,0x5b,0x63,0xba, - 0x57,0x7d,0x48,0x2a,0xa3,0x4a,0x3d,0xa2,0xaf,0x67,0xf3,0xeb,0x09,0xe4,0xf1,0x63, - 0x4b,0xb0,0x7f,0xa7,0x33,0x5f,0xe6,0xd8,0x2f,0x6f,0xf5,0x5f,0x2d,0x48,0x66,0x35, - 0x24,0xe0,0x4f,0x91,0xfc,0xfc,0x14,0xdb,0x3a,0x97,0xe3,0xc7,0x74,0x7d,0x54,0xa3, - 0x1c,0xba,0xb5,0xc3,0xaa,0x86,0x94,0x5f,0x0f,0xc1,0xa9,0x8f,0x7a,0x05,0x1a,0x53, - 0xc1,0x7e,0xee,0xdb,0xf0,0x62,0xae,0x5b,0xa3,0x6c,0xaf,0x1f,0x65,0xd3,0x47,0x95, - 0xb3,0xfc,0xa0,0x88,0x51,0x90,0xca,0xa2,0xbe,0x91,0xa3,0xc5,0xe8,0xf9,0x68,0x41, - 0x93,0x1f,0x73,0x9e,0x0f,0x02,0xd1,0x7e,0xa1,0x6c,0x0d,0x2f,0xb5,0xc1,0xaa,0x5c, - 0x3d,0x04,0x7b,0x3d,0xa8,0x1c,0x3f,0xb6,0x55,0xd7,0x47,0xb5,0x08,0x71,0xff,0x62, - 0xa7,0xfd,0xed,0x7c,0xe3,0x9b,0x0e,0x7d,0x14,0x55,0x37,0x45,0xd3,0xbe,0x15,0xe1, - 0x23,0xac,0x9e,0x43,0x4e,0x16,0x4e,0xf3,0x83,0xee,0xfa,0x48,0xd7,0xec,0x84,0xef, - 0x50,0x9a,0x3a,0xcd,0xed,0xe4,0xed,0xd3,0x60,0xe1,0xdc,0x89,0xf2,0x83,0x62,0xb4, - 0xed,0xf9,0x14,0xf1,0xae,0xcf,0xe0,0xe0,0xc7,0x24,0x5d,0x1f,0x9e,0x8e,0x0c,0x90, - 0x03,0xfc,0x7a,0x5f,0x0c,0x3f,0x7c,0x23,0x3f,0x58,0xea,0xc9,0x8f,0x45,0x3a,0x8d, - 0x22,0xb4,0x75,0x45,0x25,0x8a,0x71,0x2c,0x88,0x57,0x7d,0x00,0xf3,0xaf,0x02,0xae, - 0x33,0x8a,0x60,0x17,0x95,0x4b,0x6b,0x61,0x96,0x46,0x72,0xc2,0x21,0x4f,0x7e,0xac, - 0x6b,0x86,0xb8,0x4f,0x69,0xc8,0x46,0x57,0x4f,0xae,0xe5,0x1f,0xeb,0xbc,0xe5,0x6c, - 0xc8,0xab,0x3e,0x80,0x8d,0x1f,0xbb,0x8e,0xf9,0x13,0x79,0x72,0x26,0xf4,0x93,0xb4, - 0xe9,0x46,0xae,0x71,0xfb,0x93,0x1c,0x3f,0x66,0xd4,0x87,0xa4,0x6a,0x96,0xff,0x0e, - 0xbf,0x52,0xf6,0x99,0x61,0x2b,0xe9,0xcc,0x0f,0xda,0xcf,0x07,0x91,0xf7,0xc1,0x4d, - 0x2d,0xc2,0x77,0x3b,0x4e,0x68,0xbf,0xc9,0x54,0xf4,0x86,0x0c,0xff,0xc3,0xf8,0x79, - 0x39,0x8f,0x1f,0x53,0xd8,0xf9,0xb0,0x51,0xad,0xf8,0x1e,0x72,0x11,0xd6,0x4a,0xce, - 0xb4,0xa0,0x47,0x7e,0x50,0x3f,0x1f,0x2d,0xd2,0xf4,0xb9,0x05,0xe4,0x31,0x79,0x8b, - 0xbe,0xbb,0x67,0x23,0xdd,0x11,0x5f,0x28,0x3f,0x38,0x95,0x8e,0xb7,0xa1,0xbf,0xa6, - 0x01,0xde,0xc5,0x78,0x31,0xc3,0x08,0x13,0xfc,0xfd,0x4e,0xff,0x69,0xab,0x17,0xc7, - 0xec,0x93,0x2e,0xdd,0x49,0xcf,0x03,0x35,0xd2,0xa6,0x82,0xdb,0x3e,0xf6,0xfa,0x90, - 0x7a,0x50,0x0b,0x5e,0xea,0xb8,0x28,0x9d,0x34,0xdd,0xf8,0xff,0x9e,0x20,0x3f,0xa8, - 0x9f,0xc6,0x1e,0xd9,0x4d,0x66,0x49,0xef,0x40,0xbd,0x29,0xf3,0x2e,0x2d,0x94,0x1f, - 0xf4,0xb1,0xfe,0x59,0x3d,0x7b,0xc5,0x5b,0x85,0x01,0x67,0x3b,0xfa,0x3b,0xf4,0x51, - 0x34,0x3f,0x28,0x0b,0x7b,0x49,0xf0,0xf0,0x96,0x54,0x44,0xfb,0x32,0x95,0xcd,0x6f, - 0x81,0xe0,0xe1,0x09,0xeb,0x03,0x68,0xc1,0xcd,0xdc,0x1f,0xc3,0xc7,0x8c,0x7a,0x11, - 0xf2,0x04,0xf5,0x01,0x3e,0xc9,0x06,0x25,0x07,0x1e,0xe6,0x5e,0x56,0xde,0x31,0xf2, - 0x83,0x4a,0x9e,0xfe,0x27,0xa7,0x8f,0xfa,0x27,0x6b,0x92,0xdc,0x1f,0x1c,0x6f,0xc7, - 0x78,0xb7,0x77,0x4b,0x0c,0x9e,0x83,0x1b,0xb5,0x12,0x4f,0xfc,0xa3,0xd9,0xeb,0x03, - 0x1c,0x50,0xe6,0xfe,0x4e,0xb8,0xd8,0x8e,0xfd,0xbf,0x91,0x7c,0x55,0xb0,0x15,0x4a, - 0x1a,0xce,0xd5,0x87,0x04,0xe3,0xbc,0x60,0xa6,0xce,0x85,0xe8,0xe1,0x6b,0x13,0xd7, - 0xe2,0x17,0xd7,0x1c,0xe9,0x65,0x89,0x63,0xca,0xa0,0x2e,0x8d,0x97,0x5d,0xc8,0xe9, - 0xc3,0xa7,0xda,0xf3,0x83,0x24,0x46,0x0f,0x0a,0xd1,0x15,0x47,0xcd,0x39,0x7b,0x42, - 0x4e,0x1f,0xbe,0xd0,0xd2,0x87,0x73,0xab,0x04,0x0a,0x4b,0x8a,0xa8,0x3e,0x7c,0x0c, - 0xea,0x3b,0x1d,0xf3,0xc1,0xf2,0x3f,0x8e,0xfa,0x90,0xcf,0x61,0xe3,0x7a,0x63,0x3f, - 0x82,0x6a,0xd4,0x87,0xfc,0x1e,0xb3,0x8f,0xc5,0xff,0xbf,0x2c,0xee,0x76,0xa0,0x9d, - 0x43,0xc1,0x61,0x6e,0x15,0x7c,0xe0,0x8b,0x2d,0x2c,0xb5,0xd5,0x2b,0xf3,0xd2,0x87, - 0x03,0xd3,0x87,0x6b,0x7e,0x5a,0x98,0xf4,0x39,0x3e,0xa6,0x17,0x0e,0x7d,0x47,0x1f, - 0xda,0x87,0xd6,0x7c,0xd0,0xf8,0x65,0xfc,0x0e,0x5f,0x54,0xe3,0x4c,0x7d,0x66,0x80, - 0x1e,0x24,0xd7,0xed,0x8b,0x69,0x2b,0xe3,0x60,0xcd,0x87,0x8f,0x72,0xf5,0x21,0xc5, - 0xdb,0xf3,0xa2,0xff,0x0c,0x61,0xdf,0xf6,0x92,0x2c,0xcb,0x0f,0x1a,0x07,0x67,0x8c, - 0xd8,0xf4,0xe1,0xcb,0xe0,0x0f,0xf8,0x10,0x8a,0x76,0xe4,0x0f,0xc4,0xe4,0x60,0xa0, - 0x8e,0xfb,0x02,0x7c,0x20,0x5e,0x47,0xb7,0xc5,0x1d,0x2f,0xce,0xaf,0x8f,0x34,0x2d, - 0x67,0x9f,0x6b,0xb0,0xf1,0xf2,0xfa,0xf7,0xdb,0x10,0xff,0xb4,0x26,0x7b,0x99,0x3e, - 0x3c,0x3f,0x3f,0xc8,0x5b,0xfa,0x31,0x3a,0x51,0x63,0xa7,0xaf,0xbb,0x40,0xcb,0x52, - 0x55,0xec,0x85,0xa8,0xf7,0xfe,0xb8,0x72,0xa7,0x3e,0x5c,0xfb,0x3f,0xbe,0xc5,0x7d, - 0x05,0xde,0x92,0x70,0xdd,0x68,0xcf,0x0f,0x56,0x99,0xcf,0x97,0x6c,0xfa,0x70,0x91, - 0x1e,0x03,0xd7,0x75,0x2f,0x2b,0x8b,0xed,0x2c,0x0c,0x95,0xb5,0xf0,0xea,0x20,0xef, - 0x42,0x3b,0x9f,0x8c,0xfb,0xd1,0xc2,0xf0,0xd3,0x0b,0xf6,0xfa,0x63,0x39,0x7d,0x78, - 0x76,0x9a,0x0b,0xed,0x6c,0xd4,0x0f,0x0a,0xb9,0x31,0x53,0xea,0x8d,0x7f,0x7c,0xae, - 0x7a,0x7d,0xa5,0xc0,0xd1,0x63,0xaa,0xea,0xf9,0xc0,0xd5,0xe4,0x07,0x1b,0xe4,0x12, - 0xba,0x6d,0xfc,0x7d,0x5f,0x42,0x5e,0x76,0x15,0xf5,0x21,0x89,0x5e,0xa8,0x10,0x1b, - 0xd5,0x05,0xf2,0x83,0x75,0xfa,0xfe,0xb8,0xdc,0x36,0x2e,0x3f,0xeb,0x5f,0x74,0xe7, - 0x42,0x67,0x7e,0xd0,0x9c,0x0f,0x91,0xa9,0xa6,0x3e,0xbc,0x08,0xa3,0xbf,0x2f,0xba, - 0xc4,0x5f,0xd6,0xde,0x09,0x7b,0xe6,0x08,0x05,0xea,0x43,0xae,0x2e,0x71,0x96,0x45, - 0x12,0xe6,0x12,0x5a,0x96,0x59,0x12,0xe9,0xb1,0x20,0xd6,0x78,0xcf,0xe7,0xf4,0xe1, - 0xce,0xf3,0x32,0x92,0x4b,0x3e,0xbf,0x79,0xcf,0x0a,0x7e,0x74,0x4e,0xe3,0x12,0x3b, - 0xfe,0xf9,0xd0,0xa5,0x0f,0x67,0xd9,0x31,0xb6,0x3b,0xfe,0x33,0x25,0xdf,0xa7,0x69, - 0xc4,0xf2,0x7b,0x9b,0x1c,0x78,0xc9,0xa6,0x0f,0x57,0x73,0xfa,0xf0,0x11,0x12,0x2b, - 0x2f,0x59,0x4b,0xb2,0xbe,0x1e,0xf9,0x69,0xd1,0x9e,0x1f,0x3c,0x93,0xc3,0x3f,0x7c, - 0xa7,0x1d,0xdd,0x45,0x58,0xa1,0x48,0x71,0x8f,0x24,0xdd,0xe5,0x5d,0x1f,0x69,0x2b, - 0xbf,0xd3,0xae,0xb7,0x8f,0xca,0xc5,0x69,0x5a,0x28,0xc9,0xe7,0x04,0x96,0x4e,0x7d, - 0xb8,0xbe,0x1b,0x8e,0xdd,0x9d,0xc1,0xf2,0x59,0xe2,0x7e,0xa8,0x4e,0x39,0xf2,0x83, - 0x96,0x3e,0xaa,0xcf,0xa1,0x0f,0x27,0x49,0xfc,0xbd,0xf4,0xc4,0x71,0xb3,0xb7,0x3e, - 0x4a,0x00,0xd5,0xb4,0xbf,0xca,0xd4,0x68,0x9b,0x58,0xa2,0xc4,0xc7,0x64,0xe1,0x1e, - 0xf8,0xc7,0x55,0x1f,0x60,0x36,0x36,0x96,0x44,0x04,0x9a,0x28,0x8c,0x18,0x15,0x23, - 0x9d,0xfa,0xa8,0x88,0xfd,0x3c,0xe5,0x6e,0x73,0x7f,0xee,0x06,0xbd,0x4c,0xb1,0xc7, - 0xfe,0x38,0x45,0xfc,0x0a,0x2d,0x0b,0x99,0x53,0x43,0x6d,0xb8,0x17,0xce,0xf8,0xd6, - 0x4a,0x15,0x67,0x9b,0x8d,0x8a,0x91,0xac,0x3e,0x80,0x6c,0x3e,0xbf,0xab,0xeb,0x76, - 0x07,0xda,0x19,0x58,0xfe,0x11,0x77,0x66,0xea,0xa2,0x4c,0x7c,0x88,0xb7,0xd7,0x47, - 0xca,0xd3,0x47,0x19,0xfe,0xf6,0x7b,0xfd,0xa1,0xa7,0x3b,0x82,0x30,0x26,0x3e,0xeb, - 0xc2,0x3f,0xa6,0x7d,0xc0,0xd4,0x47,0xe9,0xfb,0x9b,0xee,0x7f,0x3d,0x38,0xb2,0x25, - 0xb6,0x78,0x4c,0x99,0xff,0xfa,0x46,0x7b,0xfc,0xb2,0xf4,0x51,0x4f,0x18,0xfe,0x87, - 0xad,0xb6,0xde,0x22,0x75,0xd9,0x48,0x6b,0x60,0x86,0xbc,0x4f,0xa9,0x1c,0x2a,0xa1, - 0x57,0xfe,0x64,0xe0,0x9f,0x5c,0xfd,0x49,0xb0,0x4e,0x03,0xd1,0xbd,0x93,0xc0,0xce, - 0xc3,0x95,0x6a,0xfa,0xec,0xfe,0x2a,0xa7,0x6f,0x91,0xec,0xfe,0x67,0x87,0x2f,0x72, - 0x48,0x88,0x87,0xd9,0x89,0x18,0x54,0xf6,0xec,0x59,0x1f,0xc9,0xb6,0x5a,0x3c,0x80, - 0xde,0xf5,0x3a,0x1a,0x5f,0x18,0x62,0xb1,0x8d,0xf7,0x55,0x9b,0x3e,0x7c,0x37,0xaf, - 0x97,0x4d,0x60,0x77,0x6f,0xd6,0xbe,0x1a,0x5f,0x64,0x6d,0xd3,0x36,0x17,0xe6,0x53, - 0x06,0x2c,0xff,0x53,0x61,0xd7,0x87,0xb3,0x65,0x7e,0x46,0xa6,0x65,0xb7,0x6f,0xd1, - 0x82,0x36,0x3c,0x90,0x8b,0xd7,0xdb,0xdc,0xf5,0x01,0x98,0x50,0xdc,0x28,0x14,0x60, - 0xc3,0x33,0xf6,0xfd,0x71,0x3f,0xb3,0xf7,0xf7,0xeb,0x34,0xc5,0x37,0x5d,0xfd,0xcd, - 0xf9,0x20,0x4c,0x0d,0x3a,0xe6,0x1b,0xad,0x0f,0xf9,0xa2,0xd2,0x2d,0xad,0xea,0x93, - 0x73,0xf6,0x49,0x38,0xf0,0x8f,0x40,0x83,0xa6,0xf1,0xeb,0xdf,0xd2,0x1f,0xba,0xc8, - 0xfd,0x5c,0x1a,0xa7,0xf5,0x63,0xed,0xf1,0xdd,0xf2,0x3f,0xdb,0xa7,0x39,0xd5,0x5f, - 0xbd,0x93,0x2f,0x70,0xf7,0xc1,0xb8,0x9c,0xec,0xf5,0xc6,0x3f,0x87,0x72,0xf8,0x99, - 0xd2,0x3e,0x33,0x1d,0xb0,0xd9,0x0b,0xff,0x08,0x94,0xe4,0x49,0xf6,0xd9,0xd1,0x4e, - 0x7e,0xc3,0x56,0x1f,0x5b,0x9f,0x0f,0x87,0x71,0x1a,0x1c,0x2f,0x36,0x84,0x52,0x1e, - 0xfc,0x4f,0x4e,0x1f,0xc5,0x53,0xeb,0x45,0x0c,0xeb,0x91,0x7c,0xbd,0x99,0x8b,0xff, - 0xd1,0xf1,0x4f,0xcc,0x31,0x5b,0xf2,0x1b,0xfd,0x8b,0x3d,0xf1,0x4f,0xc1,0x46,0x0e, - 0xff,0xf4,0x8a,0xbb,0x45,0x9b,0xda,0xbc,0xc0,0xf3,0x73,0xf8,0x47,0xd3,0xf1,0xcf, - 0x69,0x41,0xaf,0x17,0x5a,0xe0,0xfd,0x6d,0xfb,0xe3,0x78,0x6b,0x5b,0x5c,0xbe,0x59, - 0x3c,0xf8,0x9f,0x61,0x60,0xf8,0x67,0xf0,0x73,0xf7,0xb2,0xfa,0xd8,0xa6,0x50,0xca, - 0xcd,0xff,0x58,0xcf,0x5f,0x59,0xbe,0x8c,0x56,0x8f,0x1f,0x2c,0xb9,0x89,0x3b,0xd1, - 0xf7,0xc1,0xd3,0x88,0x76,0xea,0x72,0xb4,0x4f,0x81,0xfa,0x90,0x74,0xda,0xd0,0xdd, - 0x85,0xf2,0xf8,0x35,0x4c,0x1f,0xc5,0x2a,0x8c,0x15,0xa8,0x0f,0x60,0xe2,0x9f,0x60, - 0x66,0xa1,0xdd,0x2c,0xc4,0x69,0x1f,0x9b,0x3e,0xca,0xf0,0x3f,0xcd,0x5e,0xcb,0xa8, - 0x09,0xf4,0x51,0xc2,0xea,0xb2,0x33,0xfc,0xbe,0xf6,0xbb,0xb3,0x4b,0x57,0x4f,0x58, - 0x1f,0x5b,0x9f,0x6f,0x31,0xad,0xce,0x86,0x1e,0x87,0xf2,0xf9,0x1f,0x5b,0x7d,0xec, - 0x41,0x56,0x1f,0x29,0x28,0xc1,0xa0,0xbd,0x50,0x92,0xd5,0x88,0x5d,0x01,0xff,0x5c, - 0xa5,0x3e,0x3c,0x98,0xb6,0xaa,0xfd,0x4c,0xce,0xab,0x98,0x94,0x8f,0x7f,0x5a,0x22, - 0xe9,0x30,0xad,0x27,0x69,0x04,0x62,0x1b,0x11,0x51,0xef,0xc2,0x3f,0x3e,0xc6,0xff, - 0x34,0x09,0x66,0x7d,0x00,0x6b,0xa3,0x5c,0x60,0x42,0xfc,0x23,0xd0,0x63,0x68,0x8c, - 0xe8,0x3f,0xe0,0xcb,0xaf,0x97,0x68,0xce,0x87,0xd5,0x6c,0x7f,0x5c,0x03,0x8d,0xb6, - 0x92,0xa0,0xab,0xc1,0x49,0x36,0xaf,0x50,0xe4,0x19,0x37,0xfe,0x41,0xb4,0x13,0xd2, - 0x87,0xb9,0xdc,0xc5,0xff,0xd4,0x7b,0xd5,0x47,0x6a,0x5c,0x1c,0xec,0xf7,0xa0,0x89, - 0xbc,0xf9,0x1f,0x0a,0x72,0x22,0x02,0x43,0x3b,0x24,0xe6,0x90,0x45,0x79,0xd4,0x87, - 0x34,0xf5,0x51,0x16,0xba,0x5b,0xea,0xc5,0x77,0xbd,0xe4,0xc2,0x3f,0xb4,0x3e,0x43, - 0x51,0x3e,0x8d,0xe6,0xc5,0xff,0x18,0x78,0x2f,0x4a,0x61,0xcf,0xa8,0xab,0x2c,0xa4, - 0x47,0x7d,0x48,0x27,0xfe,0xc9,0xeb,0xff,0x1d,0x77,0x7d,0x6c,0xc1,0xd0,0x47,0x05, - 0x27,0x9c,0x6f,0x4b,0xdc,0xf5,0x01,0xe8,0x26,0x38,0x9c,0xcf,0xbe,0x98,0xa3,0x2c, - 0xa4,0x57,0x7d,0x00,0x9e,0x7d,0x14,0x59,0x61,0x42,0xff,0x93,0xab,0x8f,0x4d,0xf1, - 0x0f,0x7e,0xa4,0x2d,0xd6,0x69,0xf2,0x9e,0xdf,0x6f,0xae,0x3e,0x36,0xe2,0x1f,0xf1, - 0x4f,0x18,0x44,0xa2,0x14,0xed,0xfc,0x2f,0x17,0xed,0x63,0x35,0xee,0x9a,0x6d,0xf6, - 0x37,0xf0,0x4f,0x8b,0xa7,0x9b,0xf5,0xda,0x1f,0xc7,0xb3,0xfd,0x4d,0xdf,0x0e,0xae, - 0xe6,0x62,0x30,0x96,0x6e,0xcc,0x2e,0x1f,0xa9,0xbc,0x2c,0xe7,0xd5,0x07,0xc8,0xf1, - 0x3f,0xe5,0x94,0xff,0xa1,0xe3,0xf5,0xcf,0xd0,0xba,0x55,0x76,0xf0,0x07,0x3a,0x52, - 0xe3,0xfd,0xf3,0xf9,0x1f,0x60,0xfc,0xcf,0x2c,0x5a,0x3d,0xfb,0x3a,0xd8,0x27,0xb2, - 0xfa,0xd8,0xa7,0x15,0x43,0x06,0xef,0x55,0x1f,0x80,0xe5,0x3b,0xa2,0x08,0x7b,0x88, - 0x3d,0xd0,0xbb,0xf8,0x1f,0x37,0xfe,0xa9,0xd5,0xa2,0x74,0x99,0x6f,0x2f,0x34,0xe7, - 0x18,0xaf,0xad,0x3e,0xb6,0x8f,0xd9,0x07,0x26,0xb6,0x4f,0xae,0x3e,0x76,0x85,0xc9, - 0xff,0x50,0xef,0xfd,0x3d,0x5a,0x06,0x70,0x78,0xd1,0x44,0xfa,0x70,0x1d,0xff,0x34, - 0x2c,0xb4,0xa1,0x17,0xce,0xad,0x58,0xf6,0xa8,0x0f,0x20,0x5f,0x6d,0x7d,0x48,0xbf, - 0x8e,0x7f,0x76,0xd1,0xea,0xeb,0x4a,0x77,0x2a,0xaa,0x2d,0x5d,0x40,0x36,0xf2,0xdd, - 0x3e,0x77,0x3e,0xc8,0x34,0x3f,0xfc,0xe3,0xaa,0xe0,0x98,0xaf,0xe6,0x33,0xd1,0x3d, - 0xdc,0xbb,0x2a,0xdb,0x1d,0xf0,0xa4,0xae,0x0f,0x2f,0xc4,0xff,0x4c,0x62,0xf5,0x10, - 0x0c,0xda,0x27,0xc5,0x46,0xf7,0xf3,0xfc,0xf8,0xee,0x55,0x1f,0x20,0x09,0xe3,0xe9, - 0x1b,0x07,0x4a,0x46,0xb9,0x67,0x17,0x8f,0xc7,0x6b,0x27,0xca,0x7f,0x21,0xc8,0x29, - 0x65,0xd9,0x2e,0x49,0xea,0x6b,0xce,0x90,0xa0,0xf2,0x5c,0x3c,0x5c,0x00,0xff,0xd8, - 0xcf,0x87,0x85,0x6e,0x09,0x03,0x7d,0xa2,0x5a,0xc7,0xc3,0x81,0x2b,0xd6,0x87,0xc4, - 0xbb,0x61,0xba,0x0c,0x89,0xe6,0xd5,0x67,0x70,0x9e,0x8f,0x66,0xe3,0x1f,0x6a,0xe9, - 0x79,0xca,0xd1,0xbc,0xf9,0xa3,0xe5,0xd5,0x07,0xc0,0xf8,0x7e,0x90,0xed,0x16,0x5c, - 0x4e,0xeb,0x41,0x8d,0xe9,0xfa,0xf9,0xfb,0xae,0x50,0x1f,0x92,0x01,0xef,0xbd,0x38, - 0x1f,0x7e,0x95,0xdb,0xb8,0xc1,0xce,0x23,0x2e,0x58,0x1f,0x20,0xf6,0xba,0x70,0x50, - 0x89,0xa5,0x36,0x09,0xe1,0x42,0xf8,0xc7,0x76,0x3e,0x08,0x0d,0xdc,0x7d,0x94,0x2f, - 0x25,0x3b,0x94,0x48,0x0e,0x11,0x15,0x4f,0x54,0x1f,0x60,0xd0,0xff,0x1d,0x32,0x03, - 0x1e,0x7b,0xa0,0xa2,0x00,0xfe,0x31,0xeb,0x03,0xe8,0xfc,0x0f,0x34,0x0c,0x96,0xee, - 0xe1,0x1e,0x84,0x3f,0xec,0x2c,0xcf,0x5a,0xf8,0xa7,0xc4,0x03,0xff,0x98,0xb3,0xe5, - 0xfe,0xde,0x92,0xf7,0x11,0x08,0xfd,0xf3,0x6d,0x85,0xf0,0x8f,0xb3,0x3e,0x80,0xbe, - 0x2d,0x6e,0x95,0xef,0xf7,0x12,0x6d,0x4c,0xb6,0x4c,0x57,0xb0,0x3e,0x00,0xdb,0x16, - 0xd7,0x00,0xb8,0x7e,0x74,0xe1,0x1f,0xcb,0xfe,0x36,0xfe,0xc7,0xd8,0x16,0x47,0x6e, - 0xe7,0xb7,0xb4,0xd1,0x46,0x59,0xae,0x3e,0x92,0xc5,0xff,0xb8,0xea,0x03,0x6c,0xd7, - 0xcb,0xaa,0xff,0xc8,0xb5,0xf1,0xb0,0x60,0x7d,0x00,0x26,0x0b,0xa7,0xe7,0xa3,0x25, - 0x8c,0xf3,0x61,0x0b,0xd4,0x47,0x72,0x64,0x7f,0xf2,0xf1,0x40,0xc1,0xf3,0x41,0xea, - 0x11,0x08,0x55,0xd2,0x6d,0xe3,0xf5,0x13,0xe3,0x1f,0xeb,0x74,0x57,0x99,0x16,0xca, - 0x26,0xc6,0xf9,0xb0,0x13,0xea,0xc3,0xe9,0x5d,0x5d,0x16,0xce,0x0e,0x76,0x2f,0x80, - 0x7f,0xf2,0xce,0x07,0x61,0x40,0x88,0x1e,0x14,0x5b,0xb8,0x3e,0xb6,0x35,0xde,0x61, - 0xc4,0x3f,0x41,0x7a,0x3e,0x45,0x9f,0x54,0xef,0x18,0xef,0xf9,0x02,0xf5,0x01,0x68, - 0x35,0xa4,0xcd,0x1d,0xf4,0xa0,0xd8,0x82,0xf9,0xaf,0x49,0x2e,0xb4,0x10,0x64,0x44, - 0x90,0x94,0x90,0x0b,0xf1,0x3f,0x2e,0xb4,0x83,0x40,0x48,0x12,0x3a,0x53,0x61,0x27, - 0xfe,0x29,0x50,0x1f,0xe0,0x06,0x76,0x0c,0xdc,0x97,0xd4,0x7f,0x6a,0xde,0x29,0x7b, - 0xf3,0x3f,0xae,0xf3,0x61,0x6b,0xe4,0xe2,0x7e,0x32,0x95,0xff,0x47,0x28,0xc8,0xff, - 0x4c,0x75,0xe1,0x99,0x1a,0x9d,0xc8,0x72,0xe6,0x37,0x73,0xfc,0xcf,0x2e,0x70,0xf5, - 0x2f,0x75,0x6d,0x1c,0xd0,0xeb,0x23,0x79,0x9c,0x8f,0xc6,0xea,0xb1,0x37,0xc2,0x09, - 0x6d,0x0a,0x3d,0xe6,0xf2,0xda,0x42,0xf5,0x91,0xf8,0xfc,0xfa,0x90,0x83,0x4c,0x28, - 0xee,0xd0,0x87,0x7b,0xd5,0x87,0xd4,0xbf,0x0e,0x5c,0xbf,0x1f,0x67,0xe7,0x33,0x7a, - 0xd7,0x47,0xb2,0xf4,0xe1,0xc6,0xd7,0x4a,0xe5,0x3e,0xfd,0xf0,0x80,0x6b,0x7f,0x6b, - 0x8e,0xff,0x89,0xd8,0xeb,0x03,0x7c,0x88,0xd1,0xa4,0x94,0x1e,0x0b,0xf2,0x26,0xdc, - 0xe4,0xac,0x8f,0xed,0x5d,0x1f,0xe0,0x23,0x36,0xba,0xca,0x2c,0x02,0x69,0x17,0xff, - 0x93,0x3b,0x1f,0x6d,0x9a,0x6b,0xb5,0x1e,0xec,0x41,0x20,0x74,0x22,0x57,0xdf,0xcf, - 0x15,0xbf,0x76,0x7d,0xd2,0xe6,0x7f,0xde,0x82,0x64,0xa4,0x64,0x09,0x69,0xd7,0x1e, - 0xd7,0x8f,0xb9,0x2f,0x58,0x1f,0xc9,0xe8,0xff,0x34,0xd4,0xf4,0x15,0xdf,0x43,0xae, - 0x13,0xd7,0x28,0x15,0x05,0xf0,0x4f,0x8a,0xb7,0xf9,0x9f,0xed,0x7c,0x14,0x8a,0x15, - 0xa2,0xe2,0x7a,0xc4,0x55,0x6f,0x2a,0x5f,0x1f,0xae,0x8f,0xee,0x7e,0x1a,0x4d,0xa2, - 0xb4,0xac,0x8a,0x63,0xbc,0x67,0xec,0xf5,0x01,0x78,0x5b,0xff,0x7b,0xd9,0xb1,0x44, - 0xb4,0x30,0x85,0xbd,0x7f,0x65,0x81,0xfa,0x00,0x97,0x61,0xbe,0xb6,0x91,0x6e,0x9c, - 0x3f,0x61,0xd6,0x47,0xca,0xe3,0x7f,0x4c,0x7d,0x78,0x31,0x8d,0x56,0x3f,0x86,0x1b, - 0xc0,0xaf,0x71,0xad,0xf0,0x3b,0x7d,0x5b,0xb7,0x27,0xfe,0x59,0x65,0x8f,0xd7,0x12, - 0x25,0x2e,0xa2,0xf0,0x43,0x8c,0xd7,0xc5,0xde,0xfc,0x0f,0xd8,0x60,0xe1,0x16,0x88, - 0x94,0xfb,0x81,0xc8,0xda,0x43,0x0c,0x0f,0x14,0x79,0xe1,0x1f,0x81,0xa5,0x15,0xf4, - 0xe7,0xa3,0x7f,0x7e,0x35,0x18,0xe7,0x4a,0xd4,0xa3,0x62,0xa2,0xd7,0x81,0xf7,0xf2, - 0xf4,0xe1,0xb4,0x1a,0x00,0x9c,0xa1,0xf3,0xe7,0x10,0xfe,0xfa,0x1f,0x5f,0x01,0xff, - 0x24,0xb3,0xd1,0x11,0xee,0xbc,0x70,0x40,0x09,0x9b,0x44,0xd0,0x84,0xfa,0x1f,0x5a, - 0xed,0x87,0xa2,0x9d,0x31,0x08,0xa7,0xfc,0x9e,0xfc,0x0f,0x38,0xf1,0x4f,0x4c,0x67, - 0x53,0x0f,0xe8,0x78,0x06,0xaf,0x10,0x37,0xde,0x73,0xe3,0x1f,0x66,0xbd,0x9f,0xa1, - 0xdb,0xf7,0x7b,0xf3,0x3f,0xd6,0xfc,0x64,0xf8,0xa7,0x41,0x0b,0xea,0xf6,0x8f,0x67, - 0x3d,0x89,0x9a,0xdc,0xf9,0xb0,0x26,0xfe,0x89,0xe9,0xd5,0x12,0x9e,0x6b,0xf5,0x3e, - 0x1f,0x24,0x6f,0x7f,0x5c,0xd0,0x0b,0x96,0x4f,0x90,0xff,0x32,0xf0,0x70,0x58,0x9e, - 0x8e,0x0d,0xde,0x7a,0xff,0x31,0x0f,0xfd,0x8f,0x98,0xab,0x96,0x40,0xf5,0x18,0x57, - 0xa5,0xff,0x61,0xd9,0x2e,0xed,0x07,0x4a,0x45,0x8a,0x02,0x83,0xb6,0x89,0xf5,0x3f, - 0x1f,0x40,0x32,0x1b,0x8c,0xff,0xc5,0x89,0xf4,0x98,0xb2,0x20,0x15,0x60,0x07,0xa5, - 0x65,0x26,0xd6,0xff,0xd0,0x6a,0x00,0xbe,0x21,0x71,0xfc,0x1a,0xf4,0xc6,0xc3,0x7a, - 0xbe,0xb5,0xd7,0x2e,0x94,0xca,0xe9,0x7f,0x4c,0xfc,0x83,0xf6,0x39,0x01,0xc7,0x14, - 0x0c,0x5b,0x5e,0xf6,0x71,0xe3,0x9f,0xb9,0x5a,0xa4,0x95,0x3b,0x4d,0xd6,0x92,0x4f, - 0xcb,0x86,0x1b,0xb9,0xbb,0x00,0xfe,0x39,0x64,0xf1,0x3f,0x38,0xba,0xb5,0xc6,0x78, - 0xf3,0xf8,0x1f,0x77,0x7d,0x24,0x36,0xdf,0x36,0xf2,0x1d,0x74,0xb7,0xbb,0x97,0x3d, - 0xf3,0xf1,0x4f,0x90,0x46,0x87,0xa3,0xb0,0x5d,0x07,0x42,0x6e,0x22,0x68,0x02,0xfc, - 0x63,0x34,0xee,0x9f,0x18,0xff,0x34,0x47,0xd3,0xdc,0x4e,0xe3,0x74,0xf8,0x4a,0x3d, - 0xcc,0x6d,0xf2,0xc4,0x3f,0xed,0x3a,0xfe,0x49,0xd1,0xec,0x15,0xbf,0x9f,0x9d,0xf7, - 0x11,0xbe,0xd2,0xf9,0x20,0x6e,0x75,0xca,0x55,0xe8,0x7f,0x1c,0xea,0x97,0x89,0xf4, - 0x3f,0x3d,0x06,0xfe,0x09,0xd2,0xfc,0xcb,0x30,0x49,0xd2,0xfc,0x4b,0xd6,0xe7,0xb6, - 0xc0,0x09,0xb7,0xfe,0x47,0xcf,0x76,0x7d,0xac,0x1f,0x8b,0x36,0x91,0xfe,0x67,0xab, - 0x51,0x1f,0x20,0x4a,0x77,0xcf,0xbd,0xc2,0x0f,0x1b,0xdd,0x7c,0xce,0x7f,0x98,0x57, - 0x1f,0x49,0x60,0xfc,0x4f,0x97,0x54,0xeb,0x38,0x16,0xa4,0x20,0xfe,0x89,0x35,0x09, - 0x62,0xd3,0x00,0x3c,0x22,0x48,0x05,0xc6,0xeb,0x71,0x3e,0x5a,0xd1,0x80,0xf0,0x08, - 0xf5,0x3f,0x9e,0xf6,0xcc,0xe1,0x9f,0x7f,0x32,0xf4,0x5d,0xf8,0xb6,0xc2,0xaf,0x19, - 0x4c,0x9d,0x90,0xff,0x31,0xeb,0x23,0x31,0xb5,0x8f,0x49,0x03,0x8a,0x79,0xf5,0x21, - 0xdd,0xf8,0x87,0x37,0xf0,0x4f,0x01,0x22,0xc8,0xa1,0xff,0xf1,0x21,0xc8,0x51,0x2d, - 0xb4,0x53,0xe2,0xc5,0xff,0xe4,0xe1,0x9f,0x6c,0x80,0x6e,0xba,0xb3,0x39,0x22,0x17, - 0xff,0x63,0x9d,0x0f,0xeb,0x3a,0x1f,0x6d,0x6e,0xb6,0xd8,0x8b,0xff,0xc9,0x9d,0x0f, - 0x4b,0xeb,0x23,0xed,0xb3,0xd8,0x9e,0xcc,0x2d,0xd9,0xa0,0xa7,0xfe,0xc7,0x13,0xff, - 0x88,0xf9,0xfc,0xc6,0x6b,0xba,0x07,0xce,0xe1,0x1f,0x33,0x7e,0x21,0xec,0xb9,0x2c, - 0x8f,0x75,0x21,0xbe,0x1a,0xe1,0x9e,0x95,0xdf,0x4b,0xdf,0xc2,0xea,0xdb,0x58,0xfa, - 0x1f,0xd7,0xf9,0x20,0x73,0x87,0x04,0x26,0x9b,0xcc,0x60,0xe3,0x99,0x29,0xf7,0x43, - 0x87,0xca,0x12,0x5b,0x05,0xf0,0xcf,0x63,0x08,0x83,0xe7,0xb4,0x16,0x51,0xda,0x67, - 0xae,0xe6,0xbf,0x40,0x0e,0x2a,0x46,0x22,0xcc,0x43,0xff,0x23,0xe9,0xf9,0x44,0xd9, - 0x5c,0xbd,0xf6,0x32,0x22,0x68,0x8b,0xcb,0xb0,0x39,0xfd,0xcf,0x4a,0xa3,0x3e,0x76, - 0x89,0xbe,0xdb,0x9d,0xe9,0x45,0x31,0x02,0xf2,0xf4,0xd8,0xf7,0xcf,0xda,0xf4,0x3f, - 0xe6,0xfb,0x98,0xe7,0xa3,0x95,0x3a,0xcc,0xe2,0xd6,0xa3,0xe6,0xe2,0xaf,0xe6,0x71, - 0x3e,0xda,0x55,0x9c,0x0f,0x62,0x46,0xdb,0xfa,0x42,0xf5,0x01,0x5c,0xfc,0x8f,0x79, - 0xb7,0xfa,0x4a,0xfc,0x8f,0x51,0x1f,0xe9,0xf8,0xf4,0x04,0xa1,0x65,0x21,0x85,0xbe, - 0x23,0xf1,0xf6,0xe3,0x6d,0xdd,0xc5,0x51,0x6d,0x83,0x69,0x1f,0xce,0x8e,0x7f,0x14, - 0x5d,0xff,0xb3,0x84,0x8e,0x4e,0x1a,0xaf,0xab,0x7f,0x39,0xf4,0x34,0xf7,0xae,0xec, - 0x3e,0x38,0x26,0x4f,0xff,0xd3,0x1c,0xba,0x48,0xfb,0x43,0x7d,0x6f,0x68,0x6f,0xc7, - 0xd0,0xc2,0xb1,0x48,0x41,0xfc,0xf3,0x80,0x03,0x3f,0x53,0xd9,0xd8,0xa2,0x09,0xf3, - 0x5f,0xe5,0x26,0xff,0x63,0xa0,0x9d,0xe9,0xac,0x50,0xa4,0xe4,0xe4,0x7f,0x6c,0xfa, - 0x9f,0x49,0x54,0xff,0xe3,0x5c,0x4d,0x60,0x43,0x70,0x5e,0xb1,0xe9,0x7f,0xf8,0xdd, - 0xb9,0x6a,0x48,0xb6,0xfc,0x57,0x21,0xfe,0x67,0xe1,0x34,0x57,0xb4,0x0d,0x78,0xe3, - 0x13,0x77,0xfe,0xab,0xd4,0xb4,0xc6,0x26,0xaf,0xf9,0x30,0x54,0x90,0xff,0x39,0xb4, - 0xdc,0x26,0xfb,0x29,0x9c,0xff,0xf2,0x9e,0x06,0x56,0x23,0xa7,0xff,0xe9,0xe3,0x97, - 0xe5,0x79,0x1b,0xab,0x8c,0x8f,0x57,0xfe,0x2b,0x4f,0xff,0xe3,0x55,0x2f,0xda,0xa9, - 0xff,0xc9,0x65,0xbb,0xc4,0x86,0x6c,0xa8,0x5e,0x87,0x3d,0x7d,0x36,0xfc,0xe3,0xf3, - 0xd6,0xff,0xe8,0xd5,0x27,0xde,0xa7,0xc3,0x14,0xaf,0x94,0xff,0x72,0xc1,0x1e,0xc5, - 0xc5,0xdf,0x16,0xd2,0xff,0x14,0xaa,0x8f,0xe4,0xa9,0xff,0xb1,0x37,0x66,0x31,0xfe, - 0xc7,0x4c,0xfc,0xe5,0xfc,0x8f,0x53,0xff,0xe3,0xb3,0xf2,0xad,0x85,0xf8,0x9f,0xec, - 0x35,0xf9,0x6a,0x67,0xbd,0x8c,0x4c,0x01,0xfd,0xf3,0xbf,0x33,0xff,0xe5,0x2a,0x83, - 0x33,0xe9,0x0a,0xf9,0x2f,0x53,0x4f,0x52,0x00,0xcf,0x38,0xf5,0x3f,0x05,0xbb,0x4d, - 0xa8,0xff,0x99,0x10,0xff,0xb8,0xf2,0x5f,0xee,0x61,0x0e,0xbb,0xf1,0x4f,0x9e,0xfe, - 0xa7,0xd4,0x09,0x03,0x5c,0xfc,0xcf,0x87,0x85,0xf9,0x1f,0xbd,0x21,0x3b,0xf9,0x1f, - 0xdb,0xf9,0x68,0xe5,0xf9,0x68,0x27,0xcb,0x67,0xa4,0x6a,0xc7,0x95,0x33,0x79,0xf9, - 0x2f,0xe7,0x30,0xf7,0x83,0x9b,0xef,0xf2,0xd4,0xff,0xb8,0xcb,0x4c,0x79,0xe1,0x9f, - 0x69,0x9e,0xef,0x0f,0x89,0x02,0xf8,0x27,0x2f,0xff,0x45,0x1b,0x82,0xfb,0x4a,0x7e, - 0xfe,0x0b,0x8d,0xec,0xf8,0x21,0x12,0x13,0xd6,0xc7,0xce,0x4f,0x7b,0x85,0x0b,0xe6, - 0xbf,0xbc,0xfd,0x4f,0xa1,0xfa,0xd8,0x46,0xfe,0xeb,0x0a,0xdf,0x6f,0xae,0x3e,0xa4, - 0x9e,0xff,0xca,0x4b,0x7b,0xa5,0xe7,0x39,0xf9,0x1f,0xf3,0xf5,0xdd,0xfa,0x1f,0xb3, - 0x21,0xb9,0xf8,0x9f,0x9c,0x3e,0x27,0x57,0x1f,0xc0,0x1e,0xb6,0xba,0x12,0xd9,0x4d, - 0xde,0xe7,0xc3,0x8a,0x8f,0xca,0xce,0xf7,0x8f,0x93,0xd3,0xf2,0x73,0x4a,0xc5,0xa0, - 0x83,0xff,0xc9,0x9d,0x0f,0xab,0x78,0xfa,0x2b,0xc9,0x38,0x28,0x2d,0x3f,0xff,0x25, - 0xe6,0xef,0xb6,0xc8,0xf7,0x3f,0x05,0xf4,0x3f,0xb4,0xb1,0x94,0x16,0x3a,0x1e,0x77, - 0xf1,0x3f,0x36,0x3d,0xb6,0x6f,0x37,0xef,0x61,0x1f,0x52,0x08,0xff,0x54,0x88,0x07, - 0xff,0x2c,0xfc,0xa3,0xe7,0xbf,0x92,0xee,0xb0,0xc5,0xbb,0xf1,0x4c,0x01,0xfc,0x53, - 0x7a,0x25,0xfc,0xe3,0x77,0xe9,0x7f,0x8c,0x86,0x34,0x41,0xfe,0xcb,0x61,0x9f,0x97, - 0x43,0x4f,0x51,0xa0,0x18,0x29,0x88,0x7f,0xa6,0xe5,0xf2,0x5f,0xb9,0x61,0x8e,0x39, - 0xea,0xfb,0x79,0xe6,0xbf,0xf6,0x72,0x97,0x94,0x63,0x52,0xa3,0x14,0x9c,0x58,0xff, - 0x63,0x9d,0x8f,0xf6,0x08,0x79,0x4b,0xde,0xd0,0x1f,0x93,0x22,0x08,0x7b,0xf8,0xc2, - 0xfa,0x1f,0x2b,0xff,0x25,0x91,0xe3,0x64,0x0b,0x7a,0xa7,0x62,0xaf,0xfd,0x05,0x1e, - 0xf9,0x2f,0xea,0x6d,0x7e,0x14,0x89,0x91,0xe2,0x89,0xf9,0x9f,0x5c,0x7d,0x6c,0xfc, - 0xe8,0x5e,0x93,0x1b,0xc4,0x12,0x4f,0xfd,0x4f,0x5e,0xfe,0xeb,0x24,0x15,0xf9,0xbc, - 0xa7,0x34,0x8a,0xa5,0x5e,0xf3,0xc1,0x23,0xff,0xa5,0x72,0xc7,0xa5,0x63,0x72,0xb2, - 0xc5,0x93,0x5f,0xf2,0xcc,0x7f,0xbd,0x47,0x4f,0x43,0x6b,0x5e,0x79,0x05,0xfd,0x8f, - 0xc9,0x3f,0xcf,0x23,0x27,0x20,0x0d,0x51,0xf0,0x5c,0x7f,0x79,0xe4,0xbf,0xfe,0x86, - 0xfc,0xb6,0xf9,0x61,0x75,0xae,0x24,0x78,0xf1,0x21,0x1e,0xf9,0xaf,0x1b,0xb8,0xe3, - 0xa9,0x5f,0xab,0x0d,0x7c,0x90,0xe9,0x7f,0x94,0x86,0xec,0x84,0xfa,0x1f,0x8d,0x96, - 0xb5,0x91,0xdf,0x85,0x06,0xde,0xa3,0x3e,0xa4,0x67,0xfe,0xab,0x87,0xdb,0x05,0x47, - 0xa1,0x0c,0xae,0x8a,0xff,0x61,0x6e,0xa7,0x5c,0x58,0x03,0x15,0x50,0x40,0xff,0x63, - 0xd9,0xdf,0xc4,0x3f,0x2b,0xc9,0x17,0xc4,0x1d,0x4a,0x4d,0xe6,0xaa,0xf8,0x1f,0x6a, - 0x34,0xff,0x8b,0xed,0x3b,0x60,0xb7,0xb2,0xc1,0xcb,0x9e,0xf9,0xfc,0x4f,0x60,0xb0, - 0xfd,0xbb,0xd2,0xf9,0x75,0x8d,0x79,0xfa,0x9f,0xc2,0xfc,0x8f,0x84,0x3f,0x4a,0x58, - 0x08,0x79,0xf1,0x21,0xce,0xf3,0x61,0x19,0x1e,0x78,0x08,0xc3,0xdc,0x11,0x48,0x34, - 0x3f,0xef,0xc5,0x0f,0x78,0xe4,0xbf,0xb6,0x86,0x7f,0x09,0xeb,0x60,0x7b,0xea,0x0b, - 0x57,0x3e,0x1f,0xd6,0xb8,0xf8,0x06,0x59,0xe7,0x0b,0x5f,0x09,0xff,0x38,0xea,0x23, - 0xd1,0xb4,0x97,0x9f,0xc1,0x00,0x5f,0x70,0x82,0xfc,0x57,0x0f,0x3b,0x0d,0xad,0x32, - 0xab,0xf4,0x49,0x34,0xec,0xce,0xcf,0x0a,0x79,0xfc,0x4f,0x5e,0xfe,0x6b,0x53,0x7f, - 0xe5,0x45,0x3f,0x2d,0xf3,0x58,0xea,0x35,0x5e,0x5b,0xfe,0xcb,0x67,0x14,0xcd,0xee, - 0x87,0x27,0xd5,0x23,0xc2,0x14,0x39,0xe8,0xd5,0xdf,0x75,0x3e,0x2c,0x03,0x39,0xfe, - 0x39,0xf0,0x2a,0x4d,0xd4,0x4c,0xac,0xff,0xb1,0xce,0x47,0x9b,0x4a,0x16,0x9b,0xd5, - 0xb0,0xaf,0xc0,0xff,0xf8,0x8c,0xfa,0x54,0xab,0xe0,0x11,0xb8,0xf3,0x36,0x4f,0x62, - 0xcd,0x75,0x3e,0x9a,0x0f,0x61,0xed,0xc3,0x64,0x05,0x1c,0x81,0x70,0x4a,0xf0,0x12, - 0xf6,0xe4,0xf3,0x3f,0x9b,0x44,0x6e,0x27,0xbc,0x6f,0x0d,0x93,0x2f,0x7c,0x3e,0x08, - 0xdd,0x7f,0x47,0x4f,0xbf,0x9d,0x9f,0x62,0xa7,0xd1,0x6d,0xf2,0xe4,0x7f,0xbc,0xf0, - 0x4f,0xb9,0xf0,0x0c,0xd4,0x39,0xb6,0x7d,0x15,0x3e,0x1f,0x44,0x0b,0xd4,0x15,0x29, - 0x32,0x36,0x16,0x06,0x6c,0xc2,0x39,0x0f,0xfc,0x63,0xf2,0x3f,0xd3,0x17,0x10,0x76, - 0x1a,0x9a,0x4c,0xbc,0xbe,0x5f,0x67,0x7d,0x6c,0xc6,0xff,0xdc,0x16,0xd8,0x8c,0x68, - 0xe7,0x7a,0x06,0x7b,0x84,0x3f,0x75,0x5e,0x3f,0xc1,0xf9,0xb0,0x86,0xd3,0x90,0xb0, - 0x51,0x2f,0x3b,0x0f,0x82,0x37,0xf1,0x8f,0xeb,0x7c,0xd8,0xc6,0xec,0xcc,0xd5,0x5c, - 0x82,0x9e,0x86,0x96,0xda,0xa4,0x9f,0x6f,0xde,0xe8,0xc4,0x3f,0x2e,0xfe,0xa7,0x66, - 0x30,0x70,0x0f,0x29,0x87,0xb5,0x50,0xb3,0x92,0xea,0x7f,0xa0,0x3b,0x13,0x9d,0x38, - 0xff,0xd5,0x47,0xeb,0xd9,0x62,0xff,0x59,0x7d,0x9e,0xfe,0x4a,0x73,0xf3,0x3f,0x68, - 0xb4,0xf5,0x02,0xdd,0x7f,0x4a,0xf9,0xe7,0x21,0xc1,0x6d,0x4f,0x8f,0xfa,0xd8,0x3d, - 0x5c,0x58,0x39,0x46,0x17,0x3e,0x19,0x9f,0x87,0xff,0xcc,0xe3,0x7f,0x36,0xcd,0xe3, - 0x7a,0xc9,0x07,0xe0,0x2c,0x1b,0xee,0x81,0x7f,0xac,0xfc,0xd7,0xfb,0xdc,0x02,0x38, - 0x09,0xf3,0x65,0xe6,0xc6,0xff,0xf9,0x2a,0xf8,0x1f,0xff,0x6c,0x8c,0x5f,0xdb,0x57, - 0xb0,0xb0,0xb5,0xc1,0x8d,0x67,0xbc,0xf8,0x9f,0xd9,0xec,0xf4,0x87,0xab,0xe3,0x7f, - 0xfa,0xd0,0x08,0x3c,0x74,0xc8,0x52,0x33,0x06,0xbe,0xa1,0x8d,0x3b,0x8a,0xa3,0xb9, - 0xfc,0xd7,0x52,0xcf,0xfa,0xd8,0x7b,0xb8,0x2a,0x38,0xb6,0x30,0xd1,0x44,0x87,0xa9, - 0x8e,0xc9,0x08,0x84,0xbc,0xf1,0x0f,0xcb,0x7f,0xb1,0x6c,0xc5,0xcb,0xb4,0x21,0x87, - 0x2e,0x60,0xb7,0xdf,0x17,0xe6,0x7f,0x26,0xe5,0x9f,0x26,0xac,0xcf,0x9f,0xc2,0xf8, - 0xe7,0x1d,0x27,0xda,0x09,0x9f,0x17,0x27,0xc6,0x3f,0xb6,0x7a,0xe9,0xc6,0xfe,0x82, - 0x89,0xf1,0xcf,0xcf,0x3c,0x69,0x93,0xe9,0x05,0xf1,0x8f,0x9b,0xfd,0x33,0x33,0xa4, - 0x8b,0x86,0x7c,0x05,0xf1,0x4f,0xc8,0xd4,0x83,0x4d,0xd6,0x1b,0x73,0xcd,0xc6,0x15, - 0xf5,0x3f,0x57,0x8d,0x7f,0x26,0xd0,0x6f,0x17,0xd4,0xff,0x58,0x0d,0xa7,0x50,0x7c, - 0x82,0xf3,0x41,0x36,0x5c,0x25,0xfe,0x31,0xd1,0x4e,0x69,0xfc,0xea,0xf0,0x8f,0x35, - 0x5b,0xa8,0xfe,0xf9,0xf7,0x22,0xc5,0x3f,0x93,0xaf,0xa8,0xff,0x29,0xd4,0x70,0xe2, - 0x9f,0xb7,0x3c,0xd6,0x8f,0x13,0xe1,0x1f,0xba,0xa9,0xad,0xd8,0x63,0x98,0x4d,0x05, - 0xf0,0xcf,0x0e,0x87,0x3d,0x33,0x57,0xc4,0x3f,0xe7,0xe8,0xf9,0x5f,0x79,0xb0,0x27, - 0x50,0x10,0xff,0x14,0xdc,0x86,0x7c,0x65,0xfd,0x0f,0x6b,0x54,0x5d,0x0d,0xfe,0xd1, - 0xa3,0x2d,0x95,0x9d,0x70,0x2b,0xae,0x0e,0xff,0x58,0x77,0xf3,0xaf,0x14,0xd4,0xff, - 0x54,0xd1,0xbb,0x8b,0x27,0xe0,0x7f,0x74,0xfd,0x4f,0xcc,0x31,0x3a,0x29,0x6f,0xbc, - 0x85,0xcf,0x07,0xc9,0x35,0x66,0x4e,0xa0,0xff,0xa9,0x77,0xf5,0x7f,0xdb,0xd5,0xdf, - 0x91,0xff,0xf2,0xb9,0xd0,0x0e,0xa7,0xba,0xaf,0x14,0xd4,0xff,0xf8,0x56,0xe9,0xfa, - 0xe7,0x6d,0xec,0x4a,0xd9,0x95,0xf5,0x3f,0xac,0x81,0x57,0x7c,0xec,0x58,0xd8,0x02, - 0xf8,0x67,0x7f,0xde,0x78,0xdf,0xbe,0x22,0xfe,0x71,0xf6,0xff,0x0e,0x6f,0x08,0xe3, - 0x3d,0xf0,0x8f,0x83,0x6f,0xac,0x37,0xca,0x2c,0xd0,0x0a,0xed,0x57,0xc7,0xff,0x2c, - 0xcd,0x6b,0x14,0x3a,0x1f,0x96,0x6d,0xdc,0xd6,0x9c,0xf5,0x9c,0x8d,0x1d,0xf1,0x85, - 0xcf,0x07,0x61,0x0d,0x9f,0xeb,0x4a,0x59,0xc1,0xf3,0x41,0x6e,0xa2,0xfa,0x9f,0xfc, - 0xfc,0x57,0xe1,0xf3,0x41,0xbc,0xf9,0x8d,0x82,0xe7,0x83,0x24,0x07,0x8c,0xc6,0xf7, - 0x06,0x42,0x13,0xe1,0x1f,0xf3,0xb5,0xef,0xa6,0xc7,0x4c,0x53,0xd9,0xf3,0x15,0xf0, - 0x8f,0x75,0xf7,0xca,0xf8,0x67,0x02,0x19,0xf9,0x44,0xf8,0x67,0xc2,0xfc,0x45,0x3e, - 0xfe,0xb9,0x92,0xfe,0xd9,0x53,0xff,0xf3,0xe7,0xe7,0xbf,0x1c,0x0d,0x98,0x18,0xff, - 0x5c,0x95,0xfe,0xd9,0x76,0x3e,0x88,0x61,0x8d,0x84,0x27,0x1e,0xb0,0xcc,0xef,0x3c, - 0x1f,0x24,0xd9,0x47,0xcf,0x47,0x03,0xa6,0xc7,0x98,0x00,0xff,0xe4,0x46,0xd7,0x3f, - 0x73,0x0f,0xe7,0xa8,0x8f,0xed,0x81,0x7f,0x4e,0x2a,0xf3,0x68,0xb6,0xf4,0x7e,0xf8, - 0xa5,0x32,0xff,0xc8,0x4c,0x5a,0x16,0xfb,0x45,0x98,0x4f,0xcf,0x97,0x99,0xa1,0x9f, - 0x2f,0x33,0xe8,0xc0,0x3f,0x43,0x10,0x80,0xb0,0x56,0x9e,0x29,0x8b,0xf2,0x1b,0x7c, - 0xe1,0x97,0x3f,0xa7,0xe3,0xc3,0x84,0x2c,0xa8,0xfa,0x79,0x28,0x54,0x71,0xe7,0xc4, - 0x3f,0x1d,0x20,0xe9,0x7a,0x78,0xda,0xc0,0xd1,0xf5,0x62,0x63,0xb6,0x2c,0x48,0xc6, - 0x41,0x84,0xd8,0x70,0xd4,0xc7,0x46,0xd8,0x59,0xd5,0x2b,0x64,0x48,0x50,0xee,0xd0, - 0x58,0x3e,0xf1,0x04,0x6c,0x10,0x71,0x61,0xa5,0xe2,0x15,0xb6,0x31,0x53,0xb5,0xed, - 0xff,0x92,0xaf,0x19,0x2a,0x3f,0x96,0x4e,0x68,0x42,0x26,0x10,0x23,0x1b,0x94,0xed, - 0x80,0xf3,0xe7,0x3c,0x7e,0xdf,0x4f,0x66,0xa3,0x6a,0x80,0x56,0xa4,0xd9,0xdb,0x13, - 0x54,0x6d,0xfb,0xbf,0x74,0xfc,0x73,0x40,0xfb,0x9f,0xc3,0xdc,0xb3,0xfc,0xb8,0xef, - 0x46,0xb9,0x44,0x17,0x86,0xa1,0x59,0xb2,0xdc,0x25,0x82,0xf6,0x49,0xcf,0xcd,0xda, - 0xf6,0x7f,0x99,0xf8,0x87,0xca,0xd2,0xc8,0x31,0x48,0x74,0x85,0xf6,0x56,0x46,0x15, - 0x76,0x2c,0x8b,0x8a,0xf6,0x3f,0x46,0x4f,0x04,0xdb,0xce,0xc5,0x6d,0xf8,0xa7,0x46, - 0x3e,0x70,0x6b,0xec,0x65,0xe1,0xa9,0xc9,0xab,0xc4,0x0d,0x24,0xdc,0x1f,0x38,0x48, - 0xcd,0x22,0xd4,0xf6,0x09,0x3b,0xc9,0x79,0xe5,0xb5,0x6c,0xec,0x4b,0xc2,0xae,0xf6, - 0x84,0x0d,0xff,0xac,0xf2,0xd1,0x6c,0x17,0x9a,0x11,0xad,0x21,0xa5,0xfa,0x97,0x36, - 0x90,0x12,0xd8,0xa0,0xa4,0x34,0xe1,0xa7,0xe4,0xb8,0xb2,0x01,0x87,0x81,0xf6,0xa9, - 0x73,0x9f,0x0f,0x8b,0x4b,0xf0,0xb2,0xdb,0x95,0x4d,0xca,0xb6,0xc1,0xc0,0xea,0xf6, - 0xa4,0xd4,0xa1,0x7c,0x2a,0x2b,0xac,0x24,0x97,0xe1,0x07,0x4a,0x8d,0x2a,0x0c,0xe2, - 0xd2,0xc6,0x7c,0xbe,0x81,0x7f,0x06,0x4a,0xf6,0xe0,0x6b,0x3c,0x0f,0x71,0x6d,0x69, - 0x26,0x50,0x22,0x62,0xa3,0x3f,0x2a,0x21,0xfe,0x79,0x1e,0x92,0x87,0xb1,0x51,0xe6, - 0xc4,0x3f,0x22,0x3d,0x44,0x6f,0xd1,0xa5,0x34,0x5a,0xe3,0x08,0x2e,0x1c,0x4e,0x93, - 0x71,0xf1,0x96,0x5e,0x34,0x8b,0x31,0x7f,0xee,0x08,0xb8,0xf1,0x0f,0x63,0x6b,0xcf, - 0xa3,0x35,0xea,0x81,0xf1,0x63,0xe7,0x2a,0xe2,0x5a,0xa9,0x3a,0x85,0xd9,0x87,0x9e, - 0x2f,0xe6,0xcf,0xed,0xcf,0x62,0xfe,0xc7,0x60,0xcb,0xd7,0x42,0x85,0xcc,0xd2,0xe8, - 0x6b,0x84,0x0a,0x4d,0x48,0x91,0x97,0x69,0xaa,0x5d,0xf1,0x67,0x49,0x22,0x97,0x4f, - 0x64,0xfc,0x0f,0x93,0x3d,0x3f,0x8b,0x6b,0xdf,0x39,0x19,0x61,0x35,0x0e,0xf3,0x53, - 0x4a,0x65,0xd6,0xbf,0x92,0xdc,0x0f,0x6b,0xa9,0x29,0x56,0x12,0x70,0xe0,0x9f,0x3d, - 0xa2,0x94,0x0a,0xc4,0x9b,0x7a,0xe5,0x76,0x25,0x3c,0x8c,0x13,0x6f,0x50,0xe8,0x50, - 0xb6,0xf7,0x08,0x52,0xf8,0x3c,0xf5,0xe7,0x97,0xfc,0x12,0x29,0xcb,0xd5,0xc7,0x66, - 0xfc,0x4f,0x62,0x17,0xa2,0x9d,0x27,0xe0,0xc1,0xec,0x0d,0xca,0x2a,0xd5,0x37,0xaa, - 0x9c,0xcb,0xce,0xcf,0xc4,0xb2,0xdc,0x39,0xe5,0x28,0xce,0x87,0x60,0x36,0x50,0x67, - 0xc3,0x3f,0x67,0x61,0x44,0x7e,0x56,0xa4,0xf1,0xa8,0x68,0xa4,0x38,0x29,0x50,0xfd, - 0xa1,0x34,0xac,0x24,0xf9,0xb9,0x9d,0x9c,0x71,0x74,0xac,0x13,0xff,0xbc,0x05,0x47, - 0x0e,0x25,0x5a,0xe9,0xfe,0x2f,0x71,0x54,0x49,0xe8,0xfc,0xc6,0x9c,0x6b,0x68,0x03, - 0x81,0xca,0x11,0x65,0xc6,0x4a,0x48,0x73,0xc4,0x8e,0x7f,0xc8,0x3a,0xd8,0x2e,0x47, - 0xd2,0xd5,0xb3,0x60,0x0f,0x1f,0x6e,0x11,0x1e,0x26,0x6f,0xf1,0xeb,0xe4,0xb0,0x2c, - 0x7c,0x9f,0x0a,0x9b,0xff,0x2a,0xd6,0x1c,0x11,0xfd,0x92,0x0d,0xff,0xf0,0x26,0xad, - 0x31,0x0b,0xf6,0x4b,0xdb,0x5b,0xb0,0xdb,0x9b,0xb0,0x4e,0x08,0xd3,0x2b,0x3b,0x57, - 0xac,0x93,0xa3,0xf2,0xfa,0x34,0x29,0x72,0xf8,0x1f,0xf6,0xd1,0x51,0xd9,0xf3,0x7e, - 0x90,0xe8,0xb6,0xf7,0x17,0x48,0x5b,0x44,0xc5,0xfe,0x7e,0x5a,0x11,0x28,0x2a,0x93, - 0x34,0x21,0x0e,0xfc,0xa3,0x01,0xdb,0x6d,0x2d,0x89,0x23,0x10,0xd7,0xb7,0xbd,0xf7, - 0x4a,0x09,0x88,0x2a,0x3e,0x2a,0x24,0x49,0x42,0x91,0xc2,0xcd,0xb0,0xe3,0x9f,0x9d, - 0x1f,0x47,0x1a,0x97,0x84,0x36,0xef,0x78,0x79,0xdb,0x9f,0xa2,0x8d,0x4b,0x4e,0x6e, - 0xee,0x78,0x59,0xfd,0x5d,0x64,0x2e,0x15,0x42,0x7f,0x49,0x1d,0x8d,0xdc,0x72,0xb4, - 0xe4,0xa5,0x0e,0x27,0xfe,0x79,0x1b,0xea,0x17,0x53,0xd9,0xb3,0x78,0x44,0x4c,0x50, - 0xa2,0xac,0x4a,0x3e,0x52,0x65,0x18,0xca,0x38,0x5f,0xcc,0x81,0x7f,0xa4,0x2e,0x21, - 0x0c,0x42,0xfb,0x66,0xa9,0xbd,0xab,0x22,0x5c,0x16,0x01,0xb4,0x46,0x97,0x5e,0x17, - 0x2f,0xab,0x28,0xb0,0x1d,0x84,0xc3,0x0e,0xfc,0x73,0x51,0xf9,0x39,0xcc,0x91,0x85, - 0x5b,0xc9,0x54,0xf5,0x81,0x70,0xc5,0x32,0xe1,0xd6,0xa6,0xa9,0xf0,0x40,0x5d,0x45, - 0x93,0xd0,0xd2,0xfe,0xb2,0xf4,0x93,0x48,0x25,0x6d,0xd8,0xea,0x63,0x4f,0x7b,0x18, - 0xfe,0x11,0x2a,0x65,0xa1,0x65,0xc9,0x54,0x2a,0xeb,0x4d,0xf9,0x5b,0xc9,0xf5,0xf0, - 0x80,0xdc,0x21,0x0b,0xfd,0xe4,0x65,0xe1,0x27,0x78,0x2b,0xd2,0xef,0xda,0xff,0x75, - 0x56,0xa9,0x4f,0xb1,0xfd,0x7d,0x9f,0x93,0xf7,0x52,0xbe,0x0b,0x7f,0xd6,0xf6,0x04, - 0x55,0x7c,0xbd,0x49,0xde,0x06,0xf6,0xd3,0xbb,0xf0,0x8f,0x94,0x6c,0x7e,0x2f,0x5d, - 0xf9,0x66,0x0b,0x36,0xe4,0xeb,0x71,0x98,0x64,0x34,0x9d,0x6c,0x0a,0xa5,0x3b,0x06, - 0xd4,0x57,0x84,0x64,0xb3,0x23,0xff,0x45,0xf1,0x4f,0x1f,0xb3,0x7f,0x07,0x4b,0x7b, - 0x91,0x12,0xa5,0x83,0x1d,0x14,0x2b,0x46,0x75,0x20,0x9a,0x10,0x42,0x1a,0xe7,0x77, - 0xe0,0x9f,0xa3,0xba,0x13,0x3e,0x27,0x3e,0x03,0xe1,0xcd,0xc2,0xce,0xc3,0x11,0x6d, - 0x3d,0x84,0xd3,0x02,0xad,0x98,0xfd,0x0c,0x3d,0x8f,0x52,0x25,0x7e,0x1b,0xfe,0xf9, - 0x02,0x74,0x28,0xe1,0xb3,0xc2,0x4d,0xe4,0x78,0x73,0xb7,0x22,0x0d,0x47,0x1a,0x48, - 0x29,0x5e,0xa9,0xd6,0x84,0x05,0x65,0x21,0x98,0xaf,0x49,0xc3,0x81,0xf8,0x76,0xbf, - 0x35,0xdf,0x54,0xdf,0x27,0x85,0x35,0x72,0x45,0x5a,0x48,0x15,0x9d,0x86,0xa7,0xe5, - 0x8a,0x43,0x42,0xab,0x7f,0x2a,0xac,0x95,0xd1,0xc2,0xab,0x89,0x28,0xed,0x13,0x2a, - 0xd2,0xf8,0xa9,0x46,0xac,0xfe,0xbb,0x84,0x24,0x39,0xa9,0x74,0xd3,0xfd,0x5f,0xaf, - 0x8a,0xe3,0x4a,0xb7,0x5a,0xb2,0x92,0x4b,0xc2,0x09,0x65,0x3f,0xbd,0x32,0x03,0x3e, - 0xa4,0x27,0x86,0x8c,0x04,0xaa,0xc3,0x66,0x7f,0xe1,0x93,0xe8,0x6f,0x79,0xca,0xb7, - 0x7f,0xd1,0x5a,0x7d,0x0c,0x90,0x8f,0xa8,0x9e,0x3c,0x13,0xc8,0xe2,0x95,0x67,0x15, - 0x17,0xfe,0xc1,0x68,0xd5,0xd9,0xb8,0x2a,0x34,0x8a,0xfe,0xe7,0x63,0x95,0x9e,0x66, - 0x5e,0xf9,0xac,0xfc,0x76,0xba,0x6e,0x67,0xe9,0x4a,0xa3,0x3e,0x36,0xc6,0x2f,0x5b, - 0xfe,0xeb,0x9a,0x34,0x74,0x86,0xa3,0xd5,0x4b,0xbf,0x23,0x9d,0xd1,0x0e,0x6a,0x73, - 0xfa,0x85,0x61,0x32,0x55,0x7b,0x40,0x99,0x23,0xf9,0x69,0x05,0xec,0x7d,0xd4,0xff, - 0xa4,0x48,0x4e,0x7f,0x45,0xf1,0xcf,0x5a,0x5f,0x8d,0xb6,0xf4,0x1e,0x38,0xb5,0xf3, - 0x39,0xb1,0xe2,0x61,0x21,0x4b,0x2e,0xf1,0x51,0xe9,0x86,0x2e,0x74,0x53,0xd7,0xc1, - 0xd3,0xb8,0x70,0x46,0xff,0xe3,0xc4,0x3f,0x1d,0x4a,0x54,0xe3,0x32,0xe4,0x1c,0x7a, - 0x43,0x41,0x01,0x95,0xfc,0x25,0xa2,0x16,0xfc,0x68,0x55,0xbf,0x24,0x3f,0x43,0x62, - 0x0f,0xa3,0xff,0x71,0xe2,0x9f,0x0d,0x5d,0xc9,0x6c,0x28,0xbd,0xf0,0x4d,0xf1,0x40, - 0x7b,0x82,0x96,0xad,0x18,0x54,0xde,0x51,0xea,0xfa,0x4b,0xd3,0x53,0x62,0x14,0x0f, - 0xaf,0xc0,0xf9,0x63,0xdb,0xff,0x05,0x83,0x84,0x99,0x45,0x99,0x32,0x00,0x63,0x2d, - 0x0d,0x2d,0x38,0xdf,0xb6,0x91,0x31,0x31,0x46,0x2b,0xb4,0x9f,0x85,0x51,0x19,0xfd, - 0x4f,0xda,0xb6,0xff,0x0b,0xf1,0x8f,0x8f,0x39,0xed,0x5f,0x7f,0x76,0x81,0x7c,0x52, - 0x48,0x88,0x1b,0x0f,0x55,0xd6,0x4b,0x2f,0x68,0x37,0x1f,0xde,0xf8,0x6b,0x68,0x20, - 0xc7,0x45,0x6e,0x71,0xf0,0x94,0x57,0x7d,0x6c,0xa5,0xa9,0x4a,0xdc,0xb0,0x38,0x2c, - 0x06,0x3b,0x9b,0xb8,0x96,0xf5,0x68,0x7f,0x21,0x5d,0x16,0xd6,0xba,0x20,0x5c,0x86, - 0x6f,0x68,0xc7,0x3f,0xc6,0x6a,0x2b,0x43,0x6a,0xe0,0x11,0x0a,0x0c,0xd2,0xf8,0xeb, - 0xaf,0x83,0x6a,0xa5,0x5a,0x69,0xdf,0x0d,0x8f,0x0b,0xd5,0xb2,0xd0,0xee,0xc0,0x3f, - 0x80,0xbe,0x31,0x4a,0x02,0xf1,0xf5,0xc1,0xea,0xb6,0xb0,0xa4,0x15,0x8b,0xa5,0x12, - 0x69,0x93,0x66,0x83,0x1f,0xae,0x55,0x70,0x61,0xd2,0x05,0x2b,0xc1,0x71,0x3e,0xec, - 0x32,0xbd,0x9a,0xdf,0x5e,0x12,0x55,0x5e,0x83,0xbd,0x4a,0x50,0x99,0x12,0x41,0xfb, - 0xd5,0xaf,0xc3,0x85,0xc0,0x6e,0x5c,0x8a,0xd6,0xcb,0xe8,0x9a,0xb4,0xc9,0x36,0xfc, - 0x83,0xe3,0x4d,0x1e,0x66,0xcb,0xf6,0x31,0xb9,0x51,0xc3,0xb5,0xf1,0x69,0xf8,0x50, - 0xbc,0x99,0x2f,0xe9,0xa7,0x07,0xdf,0xc3,0xa7,0x35,0xfc,0x5e,0x6c,0xf8,0xc7,0xd2, - 0xcf,0x4f,0xbe,0x5f,0x6f,0xf4,0x4c,0xa1,0x57,0x1c,0xfb,0x07,0x2b,0x3d,0xf2,0x5f, - 0x66,0xda,0x6b,0x69,0x5e,0x23,0xd0,0x53,0xe6,0xca,0x7f,0xe9,0x6a,0xe7,0x8d,0x76, - 0x5a,0xa3,0xaa,0x10,0xff,0x33,0x49,0xcf,0x7f,0x2d,0xcd,0x7c,0x42,0x47,0x8f,0x53, - 0x72,0x30,0xb2,0x69,0x48,0xcc,0xe3,0x7f,0xa4,0x1c,0xff,0xb0,0x4a,0x34,0x69,0x1f, - 0xb7,0x50,0x79,0x72,0xfe,0xfe,0x2f,0x1b,0x1a,0xb4,0xf6,0x03,0x4e,0xb1,0x1a,0x36, - 0xfe,0x07,0x4c,0x7c,0x3e,0x85,0x3e,0xcd,0xda,0xf6,0x55,0xaf,0x15,0xe4,0x7f,0x2c, - 0xb5,0x33,0x6b,0x70,0x79,0xf9,0x53,0xce,0xce,0xff,0x68,0xd3,0x5c,0xeb,0x2f,0x83, - 0x7f,0x8e,0x68,0x8b,0xe2,0x4d,0x57,0xc1,0xff,0x0c,0x52,0xfd,0x8f,0x6f,0x9f,0x52, - 0x62,0x27,0x46,0xc0,0xb6,0xff,0x9d,0xe2,0x9f,0x69,0x0d,0xda,0xf2,0xf8,0x67,0x29, - 0xdb,0x53,0xc7,0xf4,0x3f,0x0a,0x36,0xb4,0xd0,0xbc,0x82,0xfc,0x0f,0xff,0xbd,0x9c, - 0x35,0x96,0x33,0x43,0x89,0x94,0x51,0x5c,0xf4,0xe7,0xf0,0x3f,0x0e,0x21,0x7a,0xc1, - 0xfd,0x5f,0xd6,0x31,0xd3,0x73,0x1d,0xf5,0xd3,0x0a,0xec,0xff,0xba,0x91,0x35,0x8a, - 0xce,0xe8,0x08,0xd0,0x9e,0xff,0xb2,0xef,0xff,0xca,0xdb,0x4d,0x69,0x6c,0x6c,0x89, - 0x7f,0xe2,0xca,0xfb,0xbf,0x1c,0x07,0xc5,0x5e,0xb5,0xfe,0x59,0x74,0x33,0x24,0x13, - 0xf3,0x3f,0x03,0xa2,0x2e,0x84,0x9e,0x88,0xff,0xe1,0xae,0x52,0xff,0xe3,0xc1,0xff, - 0x34,0x0d,0xc0,0xe3,0x4c,0x38,0x5d,0x74,0x65,0xfe,0xe7,0x8a,0xfa,0x9f,0x3a,0x4f, - 0xfd,0x8f,0x9b,0x01,0x2b,0xb4,0xff,0x0b,0x74,0xbd,0x37,0x3f,0x41,0xfe,0x2b,0x5f, - 0xff,0x13,0xf6,0xc8,0x97,0x15,0xde,0xff,0xc5,0xf4,0x3f,0x57,0xcb,0xff,0x18,0x8d, - 0x6b,0xae,0xac,0x7f,0xb6,0xd9,0xd3,0x63,0x23,0xfc,0x04,0xfb,0xbf,0x3c,0xf5,0xcc, - 0x36,0xfc,0x03,0x3b,0xcd,0x4d,0xee,0x13,0xf4,0x2f,0xb4,0xff,0xab,0x60,0xfd,0xc3, - 0xc2,0xfb,0xbf,0x68,0x43,0xbc,0xcb,0xad,0x7f,0xce,0xd5,0x3f,0x74,0xf3,0xcf,0xb4, - 0x10,0x19,0xdf,0x0d,0xc1,0x02,0xf9,0x2f,0xd7,0xfe,0x2f,0x63,0xdb,0xc2,0x63,0x4e, - 0x3e,0x24,0x9c,0xbf,0xff,0x2b,0xe0,0x45,0xfb,0x5c,0x2d,0xff,0xe3,0x73,0x5f,0xb1, - 0xed,0xff,0x9a,0x94,0xa7,0xd6,0x20,0x97,0xe5,0x31,0xa5,0x71,0xa0,0xc0,0xfe,0xaf, - 0x6b,0x72,0xfa,0x1f,0x7e,0xdf,0x24,0x4a,0xfb,0x34,0x9d,0x6e,0x61,0x8e,0xf4,0xaa, - 0xf8,0x1f,0xe3,0x1f,0xba,0x88,0x20,0xdb,0xfe,0xaf,0x3f,0x93,0xff,0x89,0x78,0xeb, - 0x9d,0x5c,0x8d,0x57,0x27,0xe6,0x7f,0x78,0x9d,0x38,0x9a,0x62,0x5d,0x19,0x70,0xf1, - 0x3f,0x6e,0x3d,0x8c,0x19,0xef,0xcc,0xf3,0x52,0xf3,0xf7,0x7f,0x4d,0xcc,0xe7,0x9c, - 0xf5,0xde,0xff,0x75,0x35,0xfc,0x8f,0x6d,0xff,0xd7,0x24,0xaa,0x0f,0x0f,0xcc,0xd3, - 0xcd,0xd2,0x57,0x80,0xff,0x61,0xfb,0xbf,0xea,0xdd,0x66,0x09,0x27,0x8f,0x4e,0xbc, - 0xff,0xcb,0x1c,0x66,0x5f,0xe8,0x82,0x1e,0xbf,0x0a,0xf1,0x3f,0x25,0x97,0xf5,0x8b, - 0x17,0x16,0xd5,0x0a,0x9b,0x94,0x44,0x2a,0x38,0x8c,0xd1,0xaa,0x4f,0x49,0x48,0x08, - 0x0b,0x93,0x42,0xbe,0xfe,0x59,0x39,0x0f,0xcf,0x68,0xec,0x58,0xb4,0xd9,0xb0,0xae, - 0xbd,0x3a,0xeb,0xdf,0x85,0x8b,0xc0,0x75,0x80,0x2b,0x32,0x91,0xc4,0x3c,0xea,0xff, - 0xc0,0x46,0x61,0x9e,0x1c,0x6d,0x09,0x48,0x64,0x71,0xf9,0x16,0xa8,0x3a,0xd4,0x35, - 0x0f,0x3f,0x43,0xb6,0x5e,0x13,0x73,0x15,0x12,0x72,0xfc,0x4f,0x96,0xdf,0x4d,0x41, - 0x4e,0x3f,0x3e,0x64,0x85,0xef,0x47,0x55,0xb1,0xac,0x9f,0x0a,0x7b,0xd6,0xf9,0xf0, - 0xf9,0x69,0x12,0xcd,0xe5,0xbf,0xcc,0xf7,0xf1,0xf1,0x7a,0x7d,0x9e,0x50,0xc3,0xd7, - 0x16,0xc3,0x6f,0xf8,0x05,0x5a,0xb0,0x87,0x1b,0xc4,0xef,0x75,0x6f,0x2a,0xda,0x16, - 0x88,0x5a,0xfc,0x58,0xae,0xbe,0x01,0x1c,0xe4,0x2f,0xd3,0xfc,0x69,0x26,0xf0,0x24, - 0x5d,0x98,0x68,0xc5,0x6f,0x73,0xff,0x0f,0x6d,0xd7,0x1f,0x1d,0xc5,0x71,0xdf,0xbf, - 0xb3,0x37,0x77,0xda,0xfb,0x21,0xb4,0x27,0xee,0x60,0x71,0x55,0xbc,0x27,0x09,0x38, - 0x3b,0x82,0x9c,0x30,0xd8,0xd4,0x96,0xd1,0xe8,0x4e,0x12,0x02,0x14,0xfb,0x00,0x01, - 0xaa,0x9f,0xfe,0x58,0xa8,0xfe,0x20,0xef,0xb9,0xad,0x84,0x9b,0xda,0xf9,0xa3,0x66, - 0xee,0x74,0x80,0x08,0xb8,0xbe,0x60,0x1a,0xe4,0x96,0xbe,0x9e,0x5a,0x9c,0xb8,0xad, - 0xdb,0xa7,0xd8,0x71,0x4d,0x5d,0x37,0xac,0x28,0x22,0x18,0x53,0x87,0xc4,0x34,0x4f, - 0x49,0x69,0x50,0x5e,0x95,0xbe,0xb8,0x89,0x1f,0x38,0x75,0xdf,0x33,0x76,0x30,0xfd, - 0xce,0xee,0xde,0xed,0x9e,0x74,0x92,0x9c,0x97,0x74,0xe1,0x8f,0xcf,0x9b,0x9d,0x1b, - 0xcd,0xce,0xce,0x7c,0xbe,0x9f,0xf9,0xee,0xcc,0x7c,0x3f,0x14,0x2d,0xd0,0x5f,0x73, - 0x51,0xd8,0x77,0x5f,0xeb,0xf8,0xb3,0xee,0xf3,0x9f,0xa7,0x51,0xff,0x08,0x52,0x12, - 0xfe,0x1f,0xed,0x2d,0x58,0x6b,0x84,0xc6,0x82,0x71,0x76,0x09,0x1b,0xea,0x59,0xee, - 0x69,0x9a,0xad,0x7f,0x26,0x23,0xc5,0xfd,0x5f,0xbe,0x15,0x56,0x74,0xe0,0x6f,0xe2, - 0x6c,0x6b,0xc8,0xb8,0x5f,0x47,0x5a,0x6e,0x72,0xbe,0x7f,0x15,0x2f,0x33,0x3e,0x1a, - 0x69,0xe2,0x9b,0x15,0xa9,0xdd,0xf7,0x9c,0x88,0x46,0xdd,0x92,0x0d,0x00,0xd7,0xeb, - 0x79,0x70,0x2c,0x10,0x9a,0xad,0x7f,0xae,0xc0,0x72,0xf6,0x0f,0xd9,0xd5,0xa3,0xf2, - 0x63,0x81,0x5d,0x17,0x4f,0xf2,0x3d,0xb7,0xe5,0x78,0xfd,0x5d,0xfc,0x20,0x5f,0x51, - 0x10,0x07,0x21,0x56,0xf8,0xfe,0x05,0x21,0xf6,0x3e,0xb4,0x34,0x56,0x6f,0x08,0xb4, - 0x0f,0xbf,0xc3,0x13,0xd3,0xc7,0x6a,0x3d,0x01,0xb8,0x98,0x49,0x14,0x50,0xf6,0x84, - 0x2a,0xe8,0x9f,0xc8,0x4b,0xec,0x63,0x58,0x73,0xb0,0x6a,0xac,0x2a,0xc7,0xff,0x53, - 0xdc,0x45,0xf6,0x96,0xb0,0x05,0x72,0x35,0x67,0x5c,0xeb,0xa9,0x4a,0xfc,0x13,0x0f, - 0xfd,0x7d,0xe8,0x2d,0xbe,0xd6,0x78,0x54,0xf1,0xac,0x84,0xb7,0xc8,0xfd,0x3f,0x0a, - 0x9d,0x69,0x88,0xcb,0x97,0x44,0xd8,0xe5,0x82,0x93,0xdf,0x75,0xfe,0x0f,0xf2,0xc9, - 0x21,0x88,0x8d,0x07,0xd3,0x52,0x44,0x7c,0x7f,0x37,0x02,0x22,0x3e,0xda,0xb3,0x70, - 0x8f,0xf0,0xff,0x38,0xfa,0xa7,0x94,0x5f,0x9c,0xff,0x9c,0xe1,0xa3,0x7a,0xf0,0xa9, - 0xc0,0x46,0x38,0x89,0xb2,0xc7,0xaf,0x4a,0x77,0x49,0x87,0x78,0x4c,0xb8,0x7d,0xe6, - 0x38,0xff,0x67,0x08,0xb4,0xc9,0xe0,0xba,0x43,0x3e,0x78,0x2e,0x87,0x7a,0x5b,0x49, - 0xca,0xf2,0x51,0x1e,0x17,0x6e,0x46,0x97,0xfe,0x29,0xe6,0x37,0xe8,0x8b,0xf0,0x36, - 0x34,0x7f,0xb9,0x46,0xf7,0xc4,0xeb,0x7f,0x20,0xdf,0x2f,0x84,0xe4,0x06,0xb8,0x54, - 0x58,0x9b,0x6f,0x3a,0x5d,0xf9,0xfc,0xe7,0x82,0x54,0xb4,0x3e,0xb2,0x90,0x01,0x8b, - 0x72,0xab,0xa6,0x44,0x8a,0x54,0x63,0x0c,0x55,0xd2,0x3f,0x70,0xda,0xb4,0x6e,0xa1, - 0x91,0x9a,0x95,0x70,0x8b,0x5b,0xdb,0xbe,0xe8,0x11,0xe1,0xd6,0x18,0xa9,0xa8,0x7f, - 0xec,0xf8,0xa4,0xf2,0x97,0xa5,0x46,0xf6,0x8f,0x8a,0xb0,0xb6,0x9e,0x0b,0x70,0xe4, - 0xd0,0xba,0xb4,0xfc,0x27,0x15,0xf5,0x8f,0x7d,0xfe,0x33,0x0e,0x93,0x46,0x2a,0x36, - 0x8e,0x6d,0xcd,0x67,0xa7,0xd9,0x5f,0x9f,0x6f,0x68,0x97,0xaf,0x54,0xdc,0xff,0x05, - 0xa8,0x7f,0xee,0x6d,0xda,0x12,0x38,0x9e,0x2d,0x2d,0x04,0x9a,0x96,0x5e,0x20,0xab, - 0xf4,0x78,0xaf,0x74,0x9e,0x16,0xf5,0x40,0x29,0xde,0x41,0x2f,0xce,0x04,0x3e,0x8c, - 0xad,0x91,0x17,0x65,0x03,0xc2,0xdb,0xb0,0x5c,0x04,0x4a,0x33,0x50,0xff,0x24,0xd0, - 0x42,0x2e,0x2e,0x2d,0x04,0xfa,0xa1,0xaf,0x58,0x9f,0x91,0xe8,0x55,0x33,0xba,0xeb, - 0xea,0x9b,0xd2,0x55,0xf9,0x36,0x79,0x98,0x79,0xae,0x78,0xbe,0x51,0xf8,0xbe,0xbd, - 0x11,0xbe,0xa4,0x67,0x9c,0x78,0x67,0xa8,0x4f,0x6e,0x69,0x6b,0x93,0xa1,0xe3,0x7f, - 0x7b,0x1a,0x06,0x45,0x6f,0xc9,0x07,0xd7,0x0b,0xff,0x73,0xba,0xe6,0xaa,0xe7,0x03, - 0xd9,0x5a,0x0a,0x5e,0x1e,0x1f,0x16,0x45,0x4e,0x3d,0xe0,0x24,0x5e,0xb7,0xd4,0xce, - 0x84,0xa4,0xf1,0x17,0xb5,0xb9,0xf6,0xbf,0xef,0x83,0x1c,0xbc,0x6a,0xc4,0xc4,0x36, - 0xf6,0xab,0xf0,0x2a,0xfc,0x2e,0x0b,0xf6,0x4a,0x8d,0xb3,0x36,0x82,0x39,0xfe,0x9f, - 0x33,0xd8,0xfe,0x67,0xa1,0xc1,0xf0,0xff,0x5c,0xfa,0x03,0x04,0x9f,0x65,0x7f,0x76, - 0xc5,0xfc,0x9e,0xb8,0xb7,0x4c,0x61,0xba,0xfc,0x3f,0xf4,0xb4,0xb9,0x5a,0xbb,0xfa, - 0x84,0x64,0xbe,0xe8,0xf6,0xa5,0x27,0x1a,0x1a,0xe1,0x3b,0xf0,0xb2,0xb9,0xd0,0x5d, - 0x9d,0xb5,0xff,0xfd,0x12,0x9c,0xa6,0xef,0xe7,0xdf,0xe8,0x5f,0x93,0xf7,0x7c,0x0d, - 0x6e,0x19,0x1b,0xf7,0xd4,0xd4,0x7a,0xa6,0xb5,0x77,0xe5,0x72,0x21,0x54,0x7e,0xfe, - 0xe1,0x24,0x11,0xde,0xb6,0x2a,0x71,0xde,0x63,0x3d,0xd4,0x18,0x0d,0x1a,0xf6,0xf2, - 0x5a,0x68,0x72,0x7d,0x88,0x2c,0x8f,0x0f,0xfb,0x03,0xe1,0xff,0xd1,0x92,0x71,0xf9, - 0x75,0xa8,0xcf,0x6c,0x2d,0xd4,0x2e,0x83,0x3f,0x66,0x0f,0x70,0x79,0x4a,0x8a,0xcf, - 0xde,0xff,0x25,0xe7,0x42,0xf0,0x1c,0x17,0xa7,0x1d,0xd6,0x1f,0x8b,0xbc,0x42,0x1a, - 0x8d,0xad,0x71,0xa9,0x1a,0xf9,0xaa,0xd1,0x90,0x55,0x87,0x9f,0x9d,0xf3,0x9f,0x09, - 0xfe,0xc1,0x93,0x2c,0x66,0xc8,0x37,0x03,0x2a,0x9c,0xcd,0xae,0xe0,0x47,0xfb,0xa5, - 0x88,0x74,0x98,0xad,0xd2,0xe5,0xbe,0x52,0xbc,0xb0,0x5a,0xe7,0xfc,0x67,0x79,0x78, - 0x39,0xbc,0xc3,0xc7,0xa6,0x42,0xbd,0xd2,0x57,0xe8,0xff,0xf2,0x57,0xf5,0x9a,0x0d, - 0x41,0xe1,0xff,0x59,0x5f,0x08,0xfd,0x24,0x58,0xfa,0x34,0xe6,0x9c,0xff,0x1c,0x57, - 0x5f,0x92,0x7f,0x2a,0xa2,0x9d,0x2a,0x55,0x05,0xb8,0x45,0x1f,0x04,0xdb,0xcc,0xb5, - 0x88,0x61,0x58,0xda,0x11,0xe6,0x3a,0xff,0x99,0x7e,0x53,0xfa,0x8f,0xb1,0xfb,0x7e, - 0x82,0x85,0x58,0xde,0x9e,0xaa,0xb7,0x52,0x1b,0xe1,0x3d,0xcb,0x6c,0x89,0xef,0x17, - 0xad,0xe5,0xf1,0x61,0xff,0x46,0x39,0xc5,0x0f,0x2a,0x05,0x63,0x79,0xb3,0xa4,0xb2, - 0x57,0x60,0x35,0xf7,0x6c,0xad,0x15,0x8e,0xbe,0xd5,0x2c,0x28,0x4e,0xf8,0xb1,0x85, - 0x9c,0xa3,0x3f,0x0b,0xf0,0x86,0x92,0x89,0xc5,0x2e,0x06,0xcd,0xfe,0xa3,0xac,0xee, - 0x0c,0x3e,0xb6,0xb2,0x4e,0x7a,0x01,0x7f,0x18,0x9c,0xca,0xd6,0xc1,0x49,0x65,0x76, - 0x7c,0x34,0x29,0x03,0x9a,0x11,0x88,0x64,0x25,0xf6,0x75,0xde,0x04,0xc1,0x13,0x52, - 0x88,0x66,0xda,0x9b,0x78,0xf0,0x74,0xb6,0xd4,0x9e,0xce,0xfe,0x2f,0x19,0xf9,0xe7, - 0x92,0xb1,0x56,0xab,0x69,0x0c,0xbe,0x44,0x3f,0x92,0xd1,0x7a,0x16,0x82,0x71,0xe9, - 0x5d,0xd1,0x02,0xa7,0x82,0x4d,0xd2,0xbf,0x5b,0x4b,0x5b,0xdd,0xe7,0x3f,0xbf,0x0b, - 0xff,0x6d,0xb4,0x24,0x1e,0x31,0xd9,0x89,0x09,0x76,0x6a,0x98,0x92,0x3e,0x66,0x1b, - 0x85,0xff,0xe7,0x67,0xf0,0x53,0xe9,0x69,0x34,0x6d,0xee,0xf3,0x9f,0xe1,0x8c,0xf2, - 0x89,0xdc,0x9a,0xe8,0x36,0x3c,0xeb,0xe0,0x17,0x38,0x30,0x8f,0x8e,0x0d,0x3d,0x05, - 0xdf,0xf6,0x1f,0xc0,0x89,0x2d,0xb4,0xd8,0x33,0xdc,0x55,0xdc,0x75,0xfe,0xf3,0xe7, - 0xf9,0xeb,0x6c,0x8d,0x22,0xe7,0xea,0x35,0x2b,0xfe,0xe0,0x58,0xd2,0x9f,0x3f,0x3a, - 0xb5,0xe6,0x9d,0xad,0x63,0x25,0xfb,0x55,0xe5,0x8e,0x0f,0x1b,0xb7,0x8e,0xa1,0x28, - 0xd4,0x36,0xc1,0x83,0xa6,0xe3,0x48,0x7a,0x1c,0xfc,0x59,0xe1,0xc1,0xc8,0x16,0x5d, - 0x19,0x6e,0xfd,0xa3,0xc8,0x74,0x4c,0x2c,0x73,0x1d,0xad,0x97,0xe9,0xcb,0x22,0x2c, - 0x5d,0xb6,0x76,0x85,0x94,0x51,0xc4,0x42,0xa9,0xc0,0x31,0x62,0xb7,0x4f,0xd6,0xd1, - 0x3f,0xc3,0xfb,0xcc,0x4e,0xde,0xcd,0x83,0x8d,0xca,0x87,0x69,0x73,0x74,0x7c,0x0e, - 0xde,0x6c,0x5b,0x73,0xa5,0x66,0xac,0xa1,0x24,0x1d,0x1d,0xff,0x0f,0x8f,0x4e,0xa2, - 0xe2,0x6b,0x95,0x3e,0x7b,0x0e,0x45,0xcb,0x2f,0xbc,0xad,0xf2,0xdd,0x27,0x50,0xf6, - 0x20,0x23,0x5d,0xaa,0x19,0x70,0xce,0xb7,0xa9,0xe4,0xff,0xd9,0xf1,0x89,0xf0,0x4f, - 0x4e,0x55,0x7f,0xb8,0xe3,0xe9,0xc0,0xb7,0xed,0xf3,0xc3,0x67,0xeb,0x1f,0x2e,0xf6, - 0x7f,0x65,0xac,0x65,0x3f,0x54,0xec,0x97,0x3f,0x5a,0x0c,0x0b,0xbb,0xd5,0x59,0xff, - 0x53,0x7b,0xd3,0xed,0xff,0x89,0xbc,0xe2,0x9b,0xb1,0x0c,0x3e,0x32,0x64,0x3b,0x82, - 0x8a,0x47,0x43,0xff,0xdc,0xed,0xff,0xa1,0xff,0x24,0xfd,0xde,0xb8,0xf0,0xf6,0x38, - 0xdb,0xbe,0x8e,0xc2,0x22,0xc3,0x53,0xd1,0xff,0x03,0x11,0xab,0x11,0xf0,0xa5,0x8b, - 0xd1,0xb1,0xd6,0xa8,0x1e,0x4b,0x3d,0x6e,0x07,0x62,0xa8,0x72,0xf4,0x61,0x89,0x6f, - 0x7f,0x04,0x76,0x7c,0xd8,0x9b,0x44,0xa8,0xc1,0xbb,0x8d,0x4d,0xce,0xb1,0x3f,0xa9, - 0xe2,0xfa,0x9f,0x86,0xb2,0xef,0x5f,0xf2,0xc7,0x52,0x69,0xdb,0xd7,0x2c,0x21,0x3a, - 0xcb,0xff,0x43,0x9d,0xef,0xa1,0x8a,0x7d,0x9e,0xf3,0x65,0xbb,0xda,0x7b,0x2b,0xec, - 0xff,0xaa,0xb8,0xfe,0x87,0xcc,0x4c,0x71,0xf4,0xcf,0x9e,0x19,0xfe,0x1f,0x1b,0x14, - 0x56,0x97,0x1d,0x84,0xf8,0x51,0xf9,0xf7,0x2f,0xa5,0xa5,0xe8,0xed,0xd9,0x30,0x21, - 0x96,0xfd,0xd0,0xff,0xc9,0xb5,0x4c,0xd5,0x34,0x2f,0xbe,0x4c,0xe6,0x59,0xff,0x63, - 0xb6,0xc6,0xd3,0xe3,0xd8,0x1a,0xb3,0x1c,0x65,0x95,0xfd,0x3f,0x6f,0x13,0x3b,0xfe, - 0xc5,0xdb,0x66,0xfb,0x5b,0x0b,0xd1,0xe9,0x3c,0xfe,0x1f,0x72,0xd8,0x62,0xcb,0x6b, - 0x70,0x78,0xe6,0xfa,0x9f,0xd2,0xfe,0x2f,0xb7,0xff,0x47,0x3a,0x9c,0xb3,0x80,0xe7, - 0x6b,0xfc,0x9e,0xb2,0x16,0x98,0x72,0xfb,0x7f,0x9c,0xf6,0xf4,0x14,0x1d,0x41,0x43, - 0xd6,0xb2,0xba,0x85,0xfc,0x3f,0x97,0x4c,0x40,0x04,0x78,0x70,0x81,0xf8,0x17,0x62, - 0x19,0x2a,0xb5,0xac,0x4f,0x0a,0x81,0x19,0xf6,0x62,0x71,0x05,0xfd,0x33,0x5c,0xc9, - 0xff,0x63,0x03,0x22,0xc0,0xf2,0x79,0xd7,0xff,0x94,0x1f,0x7b,0x28,0x0e,0x22,0x9e, - 0x43,0xff,0x98,0x6e,0x1f,0x3b,0x3a,0xc6,0xb4,0x5c,0xdc,0xaf,0x44,0x7e,0x65,0xff, - 0xcf,0x19,0xb9,0x68,0x64,0xa5,0xa9,0xf2,0x85,0x28,0x45,0xff,0x03,0x59,0xc8,0xff, - 0x23,0xcc,0xba,0x54,0xbe,0xc2,0xc7,0xd9,0xff,0x35,0x12,0x2d,0xed,0x7e,0xfa,0xa0, - 0xf6,0x5f,0xe1,0x15,0x13,0xcc,0xda,0x0f,0xf5,0x5f,0x33,0xcf,0x3f,0xb4,0xd4,0xce, - 0x30,0x94,0xcb,0x9e,0x0a,0xe7,0x3f,0x97,0xf9,0x7f,0x32,0xb0,0xf0,0xfe,0x77,0xaf, - 0xa5,0x3f,0xfd,0xd6,0xb1,0x93,0xd6,0x7a,0x72,0x75,0x1e,0xff,0x0f,0x75,0xf9,0x73, - 0xde,0x9c,0xb1,0xed,0xab,0x92,0xff,0xa7,0xb4,0x1f,0x10,0xdf,0xfe,0x17,0x4d,0x37, - 0xe0,0x8e,0x69,0xfa,0xfd,0x99,0xfb,0xbf,0x16,0xf2,0xff,0xd0,0x39,0xf7,0xbf,0x97, - 0xfc,0x3f,0x38,0xd5,0x78,0x99,0x5a,0x6e,0x9f,0xc8,0xeb,0x74,0x4e,0xff,0xcf,0xc1, - 0xca,0xeb,0x0f,0xe7,0x5a,0xff,0x1c,0x2b,0xf3,0xff,0x78,0xe6,0x3a,0xff,0xd0,0xed, - 0xff,0xa9,0xb4,0xff,0x6b,0xa6,0xff,0xc7,0x39,0xff,0xb9,0xf2,0xfa,0x1f,0xd8,0x38, - 0x5e,0xe6,0xff,0x29,0x9d,0xff,0x3c,0xc3,0xff,0xf3,0xf0,0xd4,0x33,0x67,0x4c,0xf0, - 0x50,0xf9,0xfa,0xd5,0x19,0xf1,0x2f,0xac,0xda,0xb6,0xbf,0x46,0x56,0x8b,0x8d,0xf0, - 0xd7,0xf0,0x31,0xcb,0xeb,0xef,0xf8,0x7f,0x8e,0x17,0xfd,0x3f,0x83,0xf6,0xfa,0x9f, - 0xa7,0x06,0xcc,0x30,0xb2,0xf7,0xcc,0xb1,0xfe,0x67,0x86,0xff,0x67,0xcd,0x1c,0xe7, - 0x09,0x54,0xf4,0xff,0x10,0x7b,0xa1,0x05,0x5a,0x1c,0x34,0x34,0x77,0x8f,0xfd,0x4e, - 0x05,0xff,0x4f,0x7e,0x9e,0xf5,0x3f,0xa9,0x0a,0xfe,0x9f,0x8c,0x6b,0xfd,0x8f,0x7a, - 0xc3,0x3e,0x08,0x51,0x99,0xb9,0xfe,0xc7,0xb1,0xd7,0xdf,0xb1,0xfd,0x3f,0x5b,0x8b, - 0xa7,0xb5,0xc8,0x63,0xf5,0x95,0xfc,0x39,0x25,0xff,0x0f,0xcc,0x58,0xff,0x53,0xb6, - 0x5f,0x49,0x99,0xd7,0xff,0x43,0xc5,0x79,0x77,0x5d,0x89,0xed,0xd8,0x2c,0x6c,0xae, - 0xf5,0x3f,0x5c,0x7e,0x5c,0x2e,0x7e,0x7f,0xa1,0x42,0x18,0xaf,0x7e,0xb9,0x01,0x0d, - 0x7d,0xaa,0x7c,0xfd,0xf3,0x1c,0xfe,0x9f,0x1b,0x62,0x99,0xd0,0xfb,0x0d,0xb6,0x23, - 0xc8,0x79,0xde,0x86,0xf2,0xf8,0xb0,0x75,0xa3,0x20,0x27,0xa5,0x3a,0xe3,0x60,0xcb, - 0x28,0x8b,0xef,0x90,0x42,0xc9,0x1c,0x8c,0x9e,0x8f,0xdf,0x17,0x98,0x2b,0x1e,0x5f, - 0x9c,0x48,0xb4,0x4d,0x56,0xc0,0xab,0x92,0x2c,0x6c,0x5b,0x28,0x1e,0x9f,0x9c,0xab, - 0x8d,0x91,0xe1,0xe4,0x67,0x94,0xc0,0xa1,0xfa,0x18,0x1b,0xde,0x7b,0xaf,0x32,0x9c, - 0x93,0x9a,0xe5,0x61,0x56,0x8f,0x22,0x53,0x8a,0x81,0x00,0xe5,0xe5,0x2b,0x04,0xb4, - 0x24,0xd4,0x19,0x9b,0x12,0xc4,0x03,0x4f,0xc8,0x66,0xb1,0xe7,0xe7,0x89,0x87,0xa8, - 0x68,0x32,0x85,0x80,0x4c,0x86,0x94,0xc2,0x65,0x11,0x1d,0xcf,0x18,0x4a,0x98,0xcb, - 0x01,0x42,0xac,0x62,0x3c,0x44,0xa2,0x71,0x34,0x02,0x40,0x25,0xbc,0xd9,0xa5,0x49, - 0x72,0x68,0x81,0x78,0x7c,0x99,0x90,0xe6,0x8f,0x4b,0x47,0xe5,0x2c,0x5f,0xa7,0x79, - 0x65,0xf2,0x25,0x8a,0x99,0xc0,0xcc,0xcd,0x2b,0xc6,0x43,0xf4,0x58,0x37,0x69,0x3a, - 0x05,0x5c,0x4c,0x9c,0x42,0xe0,0xb1,0x7a,0x57,0x88,0x41,0x85,0xab,0xf6,0xb0,0x3a, - 0xda,0xd5,0xf4,0x84,0xa4,0x02,0xbe,0x08,0x1a,0x4f,0x06,0x94,0x73,0x0b,0xc4,0x43, - 0xa4,0xc4,0x07,0x8c,0x45,0xc2,0x5e,0x8d,0x7c,0x09,0x92,0x4c,0xe1,0x0b,0xc4,0x8b, - 0xd4,0x62,0x5b,0x64,0x51,0xc8,0x21,0x25,0xd6,0x2e,0xa7,0xa4,0x88,0x91,0xc3,0x6c, - 0x73,0xc6,0x43,0x54,0xa8,0x46,0x8e,0xc1,0x13,0x24,0x72,0xc5,0x1b,0x27,0x14,0x4b, - 0x8b,0xb0,0xaa,0x04,0x16,0xfb,0x84,0x13,0x2a,0x51,0xfc,0x21,0xe7,0x3a,0xbc,0x2e, - 0x06,0x4d,0x6d,0x56,0x69,0x97,0xe5,0x1d,0x08,0x0e,0x27,0xe6,0x89,0x87,0xb8,0xd6, - 0xab,0xf0,0x2a,0x6c,0x9f,0xba,0xfd,0xd8,0xb4,0x1e,0x2d,0xdd,0x25,0x4b,0x74,0xde, - 0xf6,0x3f,0xd8,0xa8,0xc9,0xb2,0x27,0xab,0x24,0x79,0x63,0x4c,0x96,0x07,0x92,0x94, - 0xe7,0x70,0x78,0xcf,0x1d,0x0f,0xd1,0x23,0x8b,0xb4,0x23,0x2a,0x92,0x0b,0x5c,0x86, - 0xc5,0x1c,0xb8,0x27,0x51,0x5e,0x62,0x59,0x3c,0x44,0xc5,0xfc,0xcf,0x91,0x5a,0x14, - 0x50,0x98,0x96,0xe7,0xe6,0xeb,0x9d,0xeb,0x6a,0x69,0x49,0x14,0x78,0x01,0xd0,0x1e, - 0x2b,0x37,0x0b,0xf8,0xfe,0xf1,0xb7,0x8a,0x31,0x2b,0x97,0x3b,0x1e,0xa2,0x67,0xd2, - 0x33,0x02,0x2d,0xcb,0xde,0x50,0xa5,0xec,0x78,0x1b,0x5f,0xf6,0xcf,0x7c,0xc5,0x7c, - 0xe5,0x83,0x59,0x15,0x88,0xec,0x8c,0x44,0x11,0x49,0x10,0xc1,0x7f,0x0b,0x5f,0xf7, - 0x11,0x2a,0xb5,0x9b,0x40,0xca,0xb4,0x67,0xd9,0xbc,0x79,0x5d,0xd1,0x00,0xcf,0xfe, - 0xff,0xc6,0x1f,0x3c,0x7b,0xc3,0x06,0xd7,0xef,0x5c,0xff,0x54,0xe5,0xb7,0x9e,0xb5, - 0xc1,0x81,0x4f,0x55,0x7e,0xeb,0x8d,0xb9,0x1e,0xa4,0x72,0xfe,0x03,0xbf,0xff,0xcb, - 0xc5,0x87,0x3d,0xdf,0x18,0x3b,0xa2,0x25,0x03,0x11,0xe9,0x5b,0x14,0xf9,0x50,0x6c, - 0x21,0x9b,0x3f,0x3e,0xa9,0x57,0x21,0x13,0x90,0x02,0x15,0xaa,0x14,0x24,0x2e,0x06, - 0x2a,0x9b,0x3f,0x3e,0xe9,0xa1,0x35,0xcd,0x17,0x87,0x93,0x0d,0x11,0xf9,0xf0,0x9a, - 0x66,0xf9,0x14,0x93,0x22,0x7c,0x81,0xf8,0xb0,0x5a,0xc6,0x8f,0xe5,0x9b,0xc3,0x7c, - 0x42,0x0c,0x4c,0x3e,0x6f,0x7c,0xd8,0xe4,0xb9,0x84,0x16,0x08,0x09,0x9a,0x42,0xf3, - 0xcc,0x65,0xac,0x52,0x85,0xf1,0xe2,0x8a,0x4f,0xca,0x3d,0x48,0x8c,0x1a,0x8e,0x1e, - 0x2c,0x30,0xc7,0x90,0x18,0x21,0x59,0x71,0x3c,0x16,0x0b,0x61,0x99,0x75,0x63,0x01, - 0xd9,0x33,0x04,0x05,0xae,0xe1,0x00,0x23,0x73,0xf1,0x61,0xe9,0x22,0x1a,0xde,0xc2, - 0x9b,0x59,0x4b,0x2d,0xb0,0xca,0x03,0xcd,0x69,0xff,0xc3,0xda,0xa8,0x2c,0xb7,0x05, - 0x90,0x2e,0x12,0xa3,0x55,0xf1,0xf4,0x9c,0x7c,0x68,0x37,0x82,0x56,0xd5,0x42,0x42, - 0xb0,0x5d,0x8e,0x48,0x08,0xfc,0xb0,0x17,0x5f,0xc4,0xfc,0xed,0x3f,0xb4,0xa1,0x39, - 0x14,0xd7,0x3d,0x0a,0x3f,0xdc,0x18,0x03,0xd8,0xe6,0x89,0x54,0xe4,0x43,0x87,0xf4, - 0xaa,0x42,0xe4,0x32,0xdd,0xce,0xd4,0xb5,0x55,0x75,0xe4,0x22,0xec,0x67,0xea,0xfc, - 0xf1,0x61,0x95,0x83,0x6a,0xac,0x03,0x92,0x01,0x55,0xca,0x69,0x31,0x22,0xb3,0x64, - 0x65,0x3e,0x74,0x91,0x9e,0xc6,0x17,0x35,0x12,0xd6,0xcd,0x99,0xc6,0xa5,0x85,0xe3, - 0xc3,0x2a,0x19,0x25,0xd1,0x1d,0x97,0x52,0xd4,0xe0,0x09,0xcd,0x1f,0x42,0x50,0x99, - 0x0f,0x8b,0xb0,0x9e,0x28,0x80,0x3d,0x92,0x87,0xfe,0x12,0x89,0x11,0x73,0x31,0xa7, - 0xd2,0x15,0xe3,0xc3,0x2a,0x26,0x1f,0x72,0x86,0xc4,0x88,0xaf,0x4a,0xa9,0xfc,0xbe, - 0x5c,0xf1,0x61,0x13,0x45,0x3e,0xbc,0xc9,0x67,0x12,0x63,0xc5,0xf8,0xb0,0xd2,0x8f, - 0xc9,0x24,0x6f,0x51,0xd7,0x3f,0x93,0x4d,0xfd,0x29,0xe1,0x1b,0x7b,0x1f,0x1e,0xa9, - 0x90,0xc9,0x9d,0x1f,0xe9,0x90,0x13,0x42,0xbc,0x66,0x2f,0x22,0x64,0xfe,0xdc,0xd6, - 0x75,0x1f,0x25,0x44,0xb2,0x01,0xed,0x62,0x95,0xb2,0x54,0xa0,0xb5,0x03,0x9f,0x8a, - 0xdf,0x1e,0x28,0x81,0xb3,0x07,0x3e,0xe1,0x0b,0xe7,0x77,0xc0,0x8d,0x1b,0x37,0x3e, - 0x45,0xf9,0x2e,0x70,0xfd,0x97,0xe2,0xe7,0x8d,0xbf,0x4e,0x3e,0x3f,0x48,0x3c,0x03, - 0xec,0x9a,0xf2,0x00,0x6c,0x1b,0xf7,0x0d,0xb0,0x53,0xca,0x93,0x91,0xea,0x09,0x18, - 0x6c,0xeb,0x43,0xe0,0x9f,0xa8,0x1a,0x64,0x7d,0xe9,0xa5,0xb4,0xda,0x68,0x2e,0xe5, - 0xef,0x68,0xf7,0x0e,0x92,0x3e,0xb6,0x5b,0x61,0x39,0x1b,0x44,0x72,0x64,0x00,0x41, - 0x4a,0x89,0x9e,0x27,0x56,0x4a,0xd4,0x68,0x4e,0x97,0xca,0x17,0x7a,0xac,0x4b,0xab, - 0x95,0x69,0xb6,0x1c,0x2c,0x55,0x11,0xc4,0x78,0x97,0x8e,0x29,0x5c,0x2b,0x95,0xcf, - 0x81,0xe8,0x38,0xb2,0x97,0xc0,0x55,0xee,0xd5,0xa1,0x17,0x96,0x28,0xde,0x1c,0xa6, - 0xf4,0x4a,0xbb,0xc0,0x9b,0xf3,0xea,0x99,0x5e,0x0d,0x81,0x2b,0xff,0x44,0xef,0x8a, - 0xfb,0xc9,0xe7,0xf8,0x8e,0x36,0x3a,0x0c,0xfb,0x49,0x5f,0x7e,0xa9,0x16,0xbd,0xe8, - 0x45,0xc0,0x97,0xc6,0xa3,0x97,0x4c,0xb0,0x5b,0x73,0xd7,0x67,0x82,0x31,0x4d,0x91, - 0xa9,0x44,0xf0,0x2f,0x89,0x3f,0xe4,0x93,0x51,0xe4,0xee,0x11,0x00,0x48,0xce,0x4a, - 0x01,0xc2,0x9d,0xe7,0x9d,0x00,0xba,0x97,0xa8,0xbc,0x53,0x83,0x67,0x70,0x84,0x89, - 0xd3,0x78,0x95,0x61,0x1a,0xcb,0x20,0x58,0xa7,0xe4,0x50,0x4a,0x21,0x8b,0x6a,0x8a, - 0x3b,0xff,0x16,0xef,0xf6,0x4c,0x4f,0x61,0x67,0xdc,0x1b,0x08,0x27,0x33,0xe9,0xb1, - 0x9e,0x78,0x34,0xe0,0x65,0x99,0x74,0x21,0x12,0x8f,0x4a,0x84,0xf1,0xb4,0x16,0x69, - 0x89,0x82,0x53,0x9f,0x5c,0x1d,0xa9,0x62,0x3b,0x8d,0x68,0x0f,0xad,0x23,0xbb,0x61, - 0x27,0x0f,0x0f,0x78,0xfb,0xc8,0x0e,0x88,0x18,0xd1,0x04,0x02,0x0f,0xf4,0x18,0xd1, - 0x0d,0xb4,0xe4,0xfe,0xc1,0xf6,0x89,0x43,0x17,0xd4,0x02,0xe5,0x8a,0xd0,0x6e,0x0a, - 0x23,0xd0,0x06,0x96,0xd1,0x50,0xda,0xa8,0x60,0x0d,0x4e,0x15,0x68,0x73,0xb5,0xcf, - 0x3e,0x49,0x66,0xc8,0xc8,0x39,0x10,0x8c,0x9f,0x85,0x18,0x97,0x05,0x87,0x64,0x85, - 0xc9,0xd0,0x7c,0x36,0x68,0x73,0xb5,0x4f,0x9a,0xf4,0x93,0xdf,0x86,0x5d,0x8c,0xe6, - 0x4d,0xb0,0x84,0x45,0xf3,0x55,0x3a,0x99,0x84,0x5d,0x10,0xcd,0xa3,0x22,0x9d,0x84, - 0x3f,0x84,0xa8,0xfb,0x79,0x59,0x50,0x87,0x49,0xb8,0x1f,0x5f,0x8a,0xc7,0x02,0xd5, - 0xdc,0xb3,0x17,0x5f,0xdc,0x93,0x08,0xaa,0xf6,0x92,0x5e,0xbe,0x04,0x81,0xab,0xff, - 0x24,0x69,0x02,0x15,0x77,0x4a,0x96,0xb3,0x54,0xc9,0x50,0x04,0xca,0x39,0x91,0x12, - 0xeb,0x44,0x20,0x59,0xb7,0x14,0xd7,0xfb,0x02,0xb1,0x9e,0x30,0x04,0xa6,0x71,0xb3, - 0x81,0x61,0x02,0x49,0x7c,0x6c,0x2c,0xa6,0xb8,0xda,0x47,0x22,0x09,0xde,0xad,0x2d, - 0x16,0xdd,0xcc,0x06,0xe7,0x48,0x62,0xdc,0x04,0x6f,0x91,0x84,0xd1,0x9d,0xd8,0x21, - 0x53,0x57,0xfe,0x89,0x64,0xb1,0x53,0x65,0x2d,0x20,0x47,0x11,0x8c,0xf7,0x6a,0x4b, - 0xe4,0xe8,0x90,0x57,0x1b,0xef,0x4d,0x60,0x0a,0x77,0xb5,0x4f,0xd2,0x6c,0x39,0xa9, - 0xd8,0x84,0x36,0x08,0x69,0xc9,0x22,0x40,0x0b,0xeb,0x7a,0x5e,0xef,0x76,0xaa,0x67, - 0x54,0xad,0xb3,0x0b,0x8e,0x23,0x58,0xa6,0x75,0xca,0xe1,0x2c,0xed,0xc7,0xc7,0xec, - 0xec,0x0a,0x1f,0x47,0x8b,0x8f,0xcf,0xdb,0x15,0xe6,0xcd,0x25,0x93,0x71,0x5e,0xf7, - 0xf6,0x92,0x5d,0xd8,0x11,0x40,0x80,0x25,0x08,0xa2,0x08,0xa8,0xcf,0x04,0xa4,0x97, - 0x74,0x42,0x98,0x47,0x99,0x53,0x9f,0x8c,0x8f,0x6c,0xe3,0x3d,0x7a,0x74,0x84,0x1e, - 0x22,0x6d,0x3c,0xad,0x47,0x54,0xaf,0x6f,0x16,0x00,0xad,0x54,0x7e,0xae,0xd6,0xb4, - 0x30,0x52,0x17,0xad,0xc5,0x21,0xd0,0x66,0x8d,0x05,0x8a,0x26,0x49,0xb1,0x52,0x4c, - 0xe0,0xfa,0x3c,0x3b,0xd1,0x29,0x85,0x79,0x4e,0x8f,0xa9,0x6a,0xa7,0x67,0x1b,0xbf, - 0xaa,0x27,0xd4,0x6a,0x01,0xce,0xeb,0xeb,0x11,0x54,0x89,0x14,0x04,0xae,0xfa,0x4c, - 0xf8,0xbc,0x83,0x99,0x3e,0x7d,0xb7,0x52,0x77,0x01,0x04,0x58,0xaa,0x92,0x0b,0x98, - 0x72,0x99,0x6d,0x52,0xa3,0x02,0x5c,0xd3,0x9f,0x54,0xa3,0x6e,0x3e,0xe9,0x24,0x83, - 0xfc,0x9a,0xfe,0x80,0x5a,0x7d,0xc1,0x33,0xc8,0x27,0xf7,0x2c,0xb5,0x40,0x9f,0x95, - 0xd2,0x8c,0x60,0xb7,0x5a,0x6d,0x84,0x5d,0xf9,0x69,0xb3,0x28,0xbf,0x77,0xb3,0x28, - 0xad,0x5b,0x5f,0xac,0x46,0x3b,0xbd,0xb1,0x83,0x21,0xcc,0x16,0xbd,0x00,0xcd,0x99, - 0x90,0x9e,0x52,0x77,0x1a,0x61,0xa7,0xff,0x48,0x64,0xc0,0x4d,0x3b,0x3d,0x16,0xe8, - 0xb3,0x52,0x00,0xc1,0x52,0xe4,0x1f,0x57,0x6f,0xf3,0x91,0x3d,0xbc,0x57,0x5f,0xa2, - 0x62,0x7b,0x5a,0xc0,0x8b,0x20,0x63,0x81,0x70,0xcc,0x02,0xae,0xfc,0x1d,0x6c,0x7d, - 0x82,0x74,0xc3,0x0e,0xa0,0xdc,0x3b,0x40,0xea,0x60,0x13,0x44,0x0d,0x13,0xec,0x46, - 0x40,0x12,0xa4,0xcf,0x04,0x4e,0x7d,0x3a,0x52,0x5c,0x2b,0xc8,0x71,0x29,0x80,0xbd, - 0x45,0xe7,0xaa,0x66,0xf2,0x4f,0x11,0x50,0xcd,0x02,0xdc,0xf5,0xbc,0x5b,0x72,0xfa, - 0x28,0xf6,0x1f,0xcc,0x8f,0xbd,0x45,0xc6,0x6e,0xa6,0xb8,0x80,0x6e,0x01,0x77,0x7e, - 0xe6,0x4d,0xb7,0xf5,0xd4,0x76,0x20,0xf1,0x52,0xa4,0x1d,0x7c,0xde,0xa8,0xe4,0x65, - 0x7c,0x9b,0x00,0x9e,0x68,0x9a,0x9b,0x29,0xe0,0x6a,0x9f,0x20,0x49,0x5f,0xec,0x49, - 0x44,0x65,0x9a,0x22,0x69,0xa3,0x47,0x8b,0x86,0xbc,0x26,0x48,0x20,0x48,0x5a,0x40, - 0xf6,0x32,0xe7,0x79,0x91,0x75,0x74,0x9c,0x43,0x52,0xc2,0x84,0x7e,0x14,0x23,0x18, - 0x4c,0x80,0xd2,0x12,0x2d,0xb6,0x05,0xda,0x5c,0xcd,0xd9,0x96,0x92,0x24,0xce,0x0b, - 0x5a,0xd7,0x88,0x24,0x04,0x24,0xe6,0x96,0x05,0xc8,0xc4,0x71,0xd2,0x27,0xf9,0x44, - 0x0a,0x02,0x57,0x7d,0x3a,0x00,0xd9,0xa6,0x17,0x76,0x79,0x22,0xc8,0xff,0x02,0xa0, - 0x0c,0x26,0xc8,0x3f,0x14,0xf9,0x87,0xfb,0x75,0x9b,0x7f,0x9c,0xe7,0x3d,0xc8,0x84, - 0x75,0x00,0x9f,0xe7,0xcf,0x31,0x9b,0x77,0x12,0x04,0xdb,0x78,0x74,0xe8,0xa3,0x26, - 0x11,0x69,0xd0,0x07,0x4b,0xe1,0x37,0xdd,0xef,0x57,0xcc,0xed,0x90,0x34,0x28,0x6a, - 0x98,0x04,0x09,0x21,0xc3,0xa6,0x0d,0x9a,0xf0,0xaa,0x52,0x4a,0xe8,0x19,0x8d,0xa8, - 0xd0,0x59,0x3e,0xe3,0x13,0x83,0x01,0xf3,0x33,0x14,0x77,0xcd,0x3c,0xc4,0x52,0x69, - 0xb8,0x0a,0xeb,0x50,0x77,0x62,0xca,0x55,0x68,0x04,0xbf,0x20,0x22,0x77,0x7e,0x1f, - 0x69,0x66,0xdd,0xe9,0xc5,0x27,0x4e,0x7c,0x8b,0x34,0xb7,0x75,0xb3,0xc5,0x11,0x2a, - 0xc0,0x23,0x69,0x04,0xe7,0x49,0xac,0xad,0x3b,0xbd,0x43,0x89,0xb8,0xf3,0xaf,0xf2, - 0xee,0x1b,0x7f,0x2c,0xb1,0x6b,0xd8,0x3b,0xea,0xfd,0xbc,0xf1,0xd8,0xc0,0xae,0x63, - 0xd1,0xbf,0xc2,0x94,0xed,0x9a,0x00,0xc4,0xbc,0x75,0x2c,0x5a,0x5e,0xff,0x7a,0x90, - 0xb9,0x8f,0x15,0xc5,0x60,0x1a,0x4e,0x98,0xd5,0xc0,0xfa,0x9c,0xa0,0x76,0x7d,0xca, - 0xf2,0xf7,0xeb,0x61,0x95,0x26,0x09,0x0c,0x53,0x94,0xcc,0x46,0xa7,0x16,0x46,0x10, - 0x56,0x73,0xa9,0x58,0x98,0xb7,0x0b,0xd0,0x89,0xc0,0x9d,0xbf,0x23,0x1d,0xee,0xa1, - 0x3b,0x09,0xc5,0x8e,0xa4,0x20,0xf0,0x6e,0x63,0x1d,0x69,0xe8,0xf1,0x6e,0x83,0x68, - 0xfb,0x8f,0x45,0x4a,0x94,0xb8,0xfb,0x03,0xc8,0x31,0x61,0x60,0x14,0x2d,0x27,0x9b, - 0x7b,0x2e,0x22,0xc2,0x87,0x92,0x8c,0x5b,0x20,0xb6,0x5d,0x4d,0x1f,0x8a,0x68,0x07, - 0xdd,0xc5,0x07,0xbc,0x52,0x86,0x8d,0xb2,0x38,0x0d,0x10,0x89,0xb3,0x82,0x62,0x82, - 0x9c,0x05,0xc0,0x4e,0x71,0xe7,0x0f,0xf9,0x3c,0x84,0x1b,0x7b,0x90,0xe9,0xd1,0x2c, - 0x5e,0x45,0xb3,0x58,0xdd,0xed,0x11,0x60,0x3d,0x02,0xdf,0x62,0x0b,0xb8,0xeb,0xe3, - 0xf7,0xee,0x6f,0xab,0xcb,0xef,0xd6,0xc2,0x17,0x7d,0x68,0xfd,0x87,0x37,0x21,0xf0, - 0xee,0x87,0x6b,0x42,0x06,0x5c,0x5c,0xb1,0x9f,0x5c,0xe3,0x4f,0xd6,0x47,0xdd,0xed, - 0xff,0x1b,0x5b,0x92,0xdf,0xcb,0xbf,0x7a,0x7a,0xb5,0x3f,0x28,0xc0,0x37,0x4e,0xaf, - 0xde,0x1c,0xdc,0xbe,0xe5,0xca,0xf1,0x57,0x1b,0xff,0xce,0x1f,0x4c,0x6e,0xb9,0x2a, - 0xc0,0x3d,0xee,0xfa,0x3c,0x74,0xe0,0x91,0x3b,0xef,0x9c,0xfd,0xe0,0xbd,0x5b,0x26, - 0x78,0xed,0x83,0x1b,0xb7,0x1e,0xfa,0xe4,0xd1,0xeb,0xcf,0xdd,0x99,0xbe,0x7d,0xeb, - 0xa1,0xa7,0x1f,0xbd,0x23,0xc0,0x6d,0xf8,0x15,0xae,0x8d,0xcf,0xfb,0x57,0x26,0x37, - 0xe7,0x8f,0xf7,0xb7,0xde,0xaa,0xf9,0x6a,0xea,0x4e,0xfe,0xa3,0x3f,0xda,0xf8,0x17, - 0x9b,0x0f,0x7c,0x77,0x73,0xfe,0xe4,0xed,0xd6,0x3b,0x9b,0x57,0x7d,0x77,0xf3,0x07, - 0x27,0xa7,0xdd,0xf9,0x5b,0x9f,0x7e,0xe4,0xfa,0x73,0xaf,0x4d,0xbf,0x77,0xab,0xd5, - 0xae,0xc6,0xed,0x56,0xb3,0x62,0xd3,0x37,0x30,0xff,0x23,0xd7,0xcd,0x1a,0xba,0xf3, - 0x37,0x2c,0xef,0xba,0x7e,0xfc,0x81,0xe9,0x63,0x7b,0x1e,0x12,0x3f,0xfc,0x3a,0xfe, - 0x10,0xc1,0x0f,0x17,0xbf,0x96,0x7b,0xef,0x56,0x83,0x6a,0x82,0x9f,0x7d,0xb1,0xac, - 0x42,0xf5,0x42,0x16,0xae,0x52,0x8f,0x18,0x02,0xc0,0x2a,0xea,0x1f,0x07,0x33,0x05, - 0x81,0x34,0x60,0x08,0x40,0xdc,0xed,0x49,0x6d,0x59,0x08,0xe7,0x6d,0x10,0x15,0xa0, - 0xa7,0x08,0x2c,0x7d,0xe8,0xca,0x6f,0xeb,0x43,0x15,0xb2,0x15,0x84,0x62,0xcc,0x02, - 0xbc,0xac,0x42,0x96,0x48,0xcb,0xf0,0x92,0x5a,0xa3,0xa6,0x7e,0x53,0xc9,0x21,0x91, - 0xc2,0x7c,0x50,0xd6,0x9f,0xe5,0xf6,0xfd,0x24,0x94,0x4d,0x79,0xf8,0xe5,0xfe,0xb5, - 0xa4,0x2e,0x27,0xfa,0x03,0xdd,0x9f,0xa9,0xe3,0x08,0xde,0xa4,0xfb,0x89,0x09,0xca, - 0xea,0x0f,0xba,0xad,0x0f,0x51,0x75,0xa9,0x8a,0x28,0xbf,0xa8,0x0f,0xcd,0xbf,0xa8, - 0x99,0xc0,0xb9,0x42,0xb4,0x5e,0xe8,0xc3,0x76,0x38,0x86,0x42,0x51,0xe6,0xa8,0x06, - 0xf3,0x74,0x95,0x00,0x03,0xca,0x08,0x5d,0x49,0xfc,0x5c,0x78,0xf0,0x5c,0xf9,0x3f, - 0x43,0xb7,0x64,0x96,0x14,0x3a,0x46,0xc2,0xf7,0xd2,0xc7,0x32,0xb5,0x85,0xf6,0x17, - 0xc3,0xf5,0xb0,0xc5,0x02,0x6b,0xa8,0x09,0x46,0x5c,0x53,0x1f,0xd9,0xa8,0x86,0xc5, - 0xa8,0x06,0xbd,0x27,0x4c,0xa5,0x13,0xb9,0x02,0x96,0xb5,0xc1,0x14,0x17,0x60,0xce, - 0x0f,0x70,0xaa,0xaa,0xa0,0xb5,0xa7,0x03,0xc8,0x57,0xa6,0xe7,0x0b,0x88,0x6a,0x79, - 0x17,0xe4,0xa2,0x9b,0x61,0x1f,0x29,0xb9,0xcf,0xb1,0x7c,0x31,0x5d,0x45,0x2a,0xa1, - 0x62,0x82,0x2f,0x7c,0xad,0x82,0x53,0xa8,0x8c,0x29,0x6c,0x58,0xa9,0xa7,0x72,0xc6, - 0x9c,0xa9,0xba,0xf3,0x53,0xdd,0x22,0x49,0xc1,0xf8,0x2a,0x32,0x7e,0x98,0xfb,0xac, - 0x94,0x30,0xb7,0x6f,0x2d,0xe3,0xa5,0xfc,0x0a,0x61,0x92,0x0e,0x23,0xb0,0x52,0x43, - 0xc5,0x6c,0x02,0xf0,0x0f,0x43,0xbf,0x00,0xe2,0x1b,0x54,0x3f,0x3c,0x8f,0xb7,0xd0, - 0x02,0x16,0x2f,0x56,0xd4,0x87,0x5d,0x68,0xef,0x6c,0x35,0x88,0xfa,0xf0,0x88,0x00, - 0xf9,0x73,0x8d,0x56,0x4a,0xde,0xb1,0xa7,0xe2,0xc9,0x67,0xe9,0x43,0x36,0x0b,0x38, - 0xe5,0x23,0x3d,0x26,0x2c,0x91,0x96,0x2d,0x82,0x7f,0xa1,0x36,0x38,0x67,0xa5,0x84, - 0x5c,0xfc,0xcf,0x3a,0x98,0xa5,0xdf,0x44,0x37,0x43,0x00,0xa8,0xdf,0x86,0xc4,0x63, - 0x6a,0xd6,0xf3,0x8a,0x5b,0x34,0xcc,0x9d,0xfa,0x90,0x4a,0xfa,0x30,0x31,0x23,0xc5, - 0x29,0x3f,0x4d,0x92,0x56,0x21,0x78,0xd7,0x06,0x61,0xf1,0xe0,0x36,0xb0,0x52,0x66, - 0xd4,0x27,0x4d,0x22,0x68,0x26,0x95,0x22,0x08,0xe3,0x4b,0xb5,0x81,0x9d,0x02,0xc9, - 0x52,0x7d,0xba,0xb0,0xdf,0xb6,0xf1,0x88,0xee,0x15,0xa3,0x63,0x90,0x2b,0x3a,0x55, - 0x89,0x48,0x29,0x07,0x4e,0xf7,0xe9,0x02,0xd1,0xf3,0xcd,0x4a,0x8a,0xee,0x50,0x9a, - 0x2b,0x95,0x03,0x70,0xd5,0x67,0x17,0xaa,0x41,0xd4,0x87,0x68,0xa9,0x51,0x28,0xfe, - 0x9b,0x29,0x0b,0x3d,0xb6,0x2c,0x2c,0x01,0xe6,0xd8,0x77,0xd2,0x49,0x07,0x33,0x75, - 0xfa,0x26,0x25,0x7c,0xc1,0x02,0x6a,0xf8,0x82,0xef,0x0b,0x04,0x41,0x3a,0x7c,0x95, - 0x0e,0x92,0x3a,0xb6,0xa9,0x77,0x99,0xeb,0x79,0x49,0x67,0x74,0x90,0x9f,0xd2,0xab, - 0x50,0x0d,0xa2,0x1e,0xab,0xdb,0xb3,0x4a,0xf5,0x5f,0x40,0xc5,0x38,0xa9,0x0b,0x20, - 0x0d,0x66,0x4e,0x21,0x70,0x8d,0xdf,0x74,0x47,0xa7,0xa7,0xd9,0x94,0x9d,0x70,0x81, - 0x58,0xea,0x31,0x7a,0x81,0x7e,0x01,0x85,0xe2,0xee,0xde,0xe8,0xf7,0x2c,0x69,0xda, - 0xab,0x9c,0x73,0xf5,0x9f,0x5a,0xa2,0x0b,0x92,0xe9,0xf2,0x1e,0x47,0xda,0xd9,0x2c, - 0xd8,0x46,0xcc,0x20,0x98,0x9b,0x88,0xbc,0xee,0xfe,0xb3,0x12,0xf6,0x70,0x55,0xf7, - 0x8d,0x28,0x5f,0x45,0x70,0x97,0x2e,0x68,0x87,0x9a,0x29,0xa2,0x85,0x6d,0xc0,0x9d, - 0x06,0xea,0xd0,0xe1,0x29,0xb2,0x08,0x52,0x59,0x98,0xca,0x6d,0x20,0xcb,0x21,0xc5, - 0xc3,0x53,0xf4,0x29,0x04,0x9b,0x4c,0x00,0x26,0x70,0xf5,0x67,0xb2,0x1d,0x4c,0x7d, - 0x88,0xf3,0x05,0xae,0xf1,0x65,0x09,0x09,0x65,0x21,0xef,0x17,0xb2,0xb0,0x8b,0x1c, - 0xb7,0x84,0x62,0x97,0xab,0x7c,0x86,0x03,0x50,0x1b,0x35,0xfb,0xcf,0x97,0x72,0xa8, - 0x06,0x0b,0xd8,0x5b,0xb2,0x39,0x47,0x28,0x72,0x4b,0x1f,0xba,0xde,0x17,0x2a,0x81, - 0xb6,0x08,0xea,0x43,0x02,0x34,0x9d,0x51,0x12,0x1d,0x32,0x6a,0x29,0x76,0x50,0xd1, - 0xda,0x11,0x34,0xb2,0x8c,0x05,0x9c,0xfa,0x30,0x1c,0x2f,0x17,0x23,0x09,0xaf,0x0c, - 0x01,0x11,0xbd,0xbc,0x80,0x92,0x29,0xa5,0xa5,0x0d,0x4c,0x41,0x00,0x36,0x60,0xae, - 0xfa,0xc8,0x54,0x41,0x7d,0xd8,0x2e,0xc8,0xa6,0x1e,0xa7,0xa2,0x04,0xa7,0xc8,0x69, - 0x5b,0x1f,0xca,0xac,0x28,0x14,0x89,0xab,0x3e,0x5a,0x2d,0xea,0x43,0x5d,0x1e,0x91, - 0x56,0xe2,0x10,0xae,0x8f,0x99,0xfa,0x70,0x18,0x65,0xa1,0x7f,0x58,0xaa,0x87,0xbc, - 0xd0,0x87,0xc3,0xae,0xfa,0x10,0x96,0x33,0x49,0x86,0x84,0xf9,0x21,0x8d,0x8c,0x80, - 0x18,0x98,0x3e,0x5d,0x29,0xf2,0x8f,0xa2,0xfa,0x04,0xff,0xb8,0xfa,0x0f,0xe3,0xfd, - 0xb0,0x0c,0x56,0xb6,0x91,0x7c,0x56,0x87,0xe7,0x3d,0xc8,0x3f,0x79,0x18,0x88,0x9b, - 0x44,0x94,0x5f,0xab,0x0b,0x8e,0x06,0x97,0xfd,0x62,0x1d,0x3a,0xdb,0x00,0xe2,0x7d, - 0x19,0x05,0x7c,0x5f,0x8b,0xc0,0xc3,0x95,0x29,0xba,0xcf,0x8f,0x29,0x99,0xfc,0x94, - 0xb6,0xc1,0xbf,0x48,0x4a,0x65,0xb7,0x39,0xe3,0x3d,0x8d,0x8f,0xf2,0x5b,0xe9,0x45, - 0x69,0xcf,0x57,0xe0,0x05,0x9e,0xf8,0xbf,0x76,0xce,0xdf,0x25,0x81,0x30,0x8c,0xe3, - 0xef,0x75,0xa7,0x18,0x28,0x78,0x60,0x60,0x04,0x91,0x85,0xd0,0x78,0x82,0x4e,0x0d, - 0xbe,0xe6,0x8f,0x2c,0xb0,0x24,0x9d,0x9a,0x5a,0x13,0x02,0xc7,0xa6,0xb0,0xe8,0x0f, - 0xb0,0x6c,0xa8,0xcd,0xc1,0xb5,0xb1,0xdd,0x8a,0xa0,0x36,0x87,0x68,0x0d,0xa1,0xa5, - 0x3d,0x88,0x06,0xb3,0xe7,0x3d,0x5f,0xf5,0xd5,0x40,0xd0,0xa1,0x20,0xbe,0x9f,0xc5, - 0x2f,0xc7,0xeb,0xf9,0xaa,0xf7,0x3e,0xf7,0x79,0xee,0x50,0xee,0xf6,0xea,0x06,0xbb, - 0xa3,0xda,0x29,0x83,0xdc,0xa2,0x7e,0x5f,0x06,0x8b,0xd4,0x3d,0x45,0x3d,0x5b,0x3e, - 0x67,0x21,0xee,0xe1,0x3a,0x2d,0x58,0x23,0x94,0x76,0x67,0x29,0xdc,0x2f,0x84,0xb8, - 0x08,0xde,0x5b,0x65,0x3e,0x71,0x63,0x37,0xe6,0xb7,0x52,0x2e,0x8d,0xca,0xce,0x8d, - 0xdf,0xda,0x76,0x9b,0x15,0x3b,0xa4,0x94,0xa0,0xd6,0x1f,0x2e,0xfc,0xb0,0x6e,0xdf, - 0x9c,0x91,0x17,0x0b,0x7f,0x06,0xf5,0xf3,0x49,0x27,0x84,0x1f,0xa6,0x68,0x69,0x0b, - 0x1b,0x34,0x56,0x03,0xe6,0x85,0x21,0xb5,0xb0,0x17,0x4a,0xbd,0xfb,0x9b,0x54,0x7f, - 0x12,0x79,0x73,0xc6,0x99,0xcc,0xb1,0x7c,0x22,0x6b,0xfa,0x1c,0x49,0xcd,0xe4,0x9c, - 0xca,0x8e,0x21,0xea,0x8f,0x8f,0xb6,0x50,0xd0,0xb8,0xb2,0xbe,0x5c,0xdd,0xce,0x58, - 0x14,0x15,0xef,0xb1,0xc3,0x3e,0x36,0x99,0x38,0x36,0xb5,0x6e,0xe3,0x70,0xa4,0x5e, - 0xc1,0x15,0x7e,0xc8,0xaa,0x6c,0x99,0x75,0xfc,0x90,0x0d,0x8a,0xe2,0xb0,0x1f,0xf2, - 0x64,0x46,0xcb,0xc5,0x4e,0x1a,0x81,0xb0,0x3f,0x33,0x95,0xe3,0x4f,0x0d,0x2d,0xec, - 0xc9,0xe8,0x22,0x44,0x28,0x68,0x32,0x28,0xf3,0xa1,0xf7,0x2b,0xfc,0x70,0x6d,0x71, - 0xf6,0x31,0x28,0xcf,0xfe,0x0f,0xce,0xa2,0x0c,0xd2,0x07,0x94,0xfa,0x43,0xe7,0xeb, - 0x42,0xea,0xf9,0xf4,0xba,0xb6,0x7f,0x39,0x57,0xd8,0x10,0x7e,0x78,0xb5,0xd7,0xf1, - 0xc3,0x5a,0xdf,0x0f,0xa7,0x95,0xe1,0x2c,0xda,0xf7,0xc3,0x2d,0xe1,0x87,0xed,0x56, - 0xc7,0x0f,0xdf,0xfb,0x7e,0x38,0xe0,0x63,0xe3,0x12,0x14,0x5a,0xf8,0x56,0x6e,0xb7, - 0xa2,0x9f,0x52,0x14,0xc9,0x18,0x47,0xf8,0xa1,0xfd,0xea,0x1f,0xaf,0x34,0xfe,0xab, - 0x2b,0x8a,0x87,0xa3,0xfc,0x70,0xa5,0xeb,0x87,0x4b,0xf3,0x9b,0x2f,0x67,0x21,0x31, - 0xfe,0x60,0x68,0x7c,0x73,0xf2,0xd9,0x5b,0xd4,0x62,0xd1,0xfa,0xa6,0xc7,0xb8,0x7b, - 0xf2,0xbd,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xfe,0x3b,0x76,0xef,0x60,0xa0,0x77, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x8c,0xc6,0xee,0x1d,0x9c,0xe8,0x1d,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0xa3,0xb1,0x7b,0x07,0x97,0xdd,0x3b,0xfc,0xf5,0x54,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0xbf,0x88,0xf8,0x23,0x24,0xc6,0xd6,0x2b,0x16,0x2b, - 0x89,0xdf,0x30,0xe9,0x16,0xe3,0x63,0xdf,0x4f,0x90,0xcf,0x75,0x58,0xac,0xaa,0xf5, - 0xf7,0xd9,0xdc,0x19,0x1e,0xf7,0x0d,0xe8,0x9e,0x83,0xa0,0xf1,0x33,0x01,0x00, + 0x1f,0x8b,0x08,0x08,0xe2,0x44,0xc5,0x42,0x00,0x03,0x77,0x75,0x68,0x34,0x30,0x35, + 0x5f,0x31,0x2e,0x62,0x69,0x74,0x00,0xec,0xbd,0x0d,0x74,0x14,0xd7,0x95,0x2e,0xba, + 0xeb,0x54,0x49,0x94,0xba,0x5b,0xea,0x42,0x48,0x1e,0xd9,0x60,0x5c,0x6a,0x09,0xd2, + 0x28,0x8d,0x68,0x24,0x47,0x60,0x21,0x4b,0x45,0x8b,0x78,0x14,0x20,0x41,0xe3,0x78, + 0x12,0xee,0x7d,0x5e,0x99,0xb6,0x43,0x66,0x78,0x33,0xc4,0x97,0xc4,0xb9,0x77,0x88, + 0x27,0xd7,0x3e,0x6a,0x09,0x23,0x2c,0x6c,0xda,0x36,0x89,0x71,0xe2,0xc9,0x34,0x98, + 0x24,0xd8,0x61,0x32,0x0d,0xc2,0x46,0x80,0x63,0x97,0xb0,0xe2,0x34,0x58,0xc6,0x8a, + 0xe3,0xc9,0x60,0xcc,0xe0,0x26,0x51,0x6c,0xd9,0x96,0xb1,0x8c,0x19,0x5b,0x20,0x40, + 0xef,0xec,0x53,0x5d,0xd5,0x55,0xfd,0x23,0x27,0x77,0xd6,0xbc,0x35,0x6f,0xbd,0x61, + 0xd6,0xba,0x77,0xa7,0xba,0x52,0xa9,0x73,0x74,0x6a,0xef,0xef,0x7c,0xfb,0xdb,0xfb, + 0x40,0x91,0x77,0xcc,0xf8,0x3f,0x00,0xe1,0x36,0x28,0xfe,0xdb,0xff,0xb9,0xf6,0xfa, + 0xe0,0x67,0xfe,0x62,0x61,0xed,0x1d,0x5f,0x5d,0x03,0xb7,0x83,0xbb,0xee,0xce,0xcf, + 0x04,0xbf,0xf6,0xad,0x6f,0x2c,0xbc,0xfe,0x7a,0xf8,0x2a,0xfb,0x4f,0xc1,0xe0,0x67, + 0x16,0x04,0x17,0x2d,0x08,0x2e,0x84,0x35,0x50,0xb4,0xf0,0x33,0x8d,0x75,0x8b,0x1b, + 0x83,0xf5,0xf0,0x35,0x10,0xea,0x77,0x4d,0xb2,0x7f,0x4f,0x3e,0xfa,0xe7,0x7f,0x19, + 0x04,0x2a,0x00,0xc0,0xb4,0xa0,0x10,0xc6,0xff,0xdf,0x1d,0x14,0x54,0x01,0x68,0xcb, + 0xfc,0x20,0xe8,0xf8,0x9f,0x21,0xf5,0x7b,0x51,0x10,0x54,0xfb,0x7f,0x16,0x82,0xa0, + 0x41,0x3b,0x68,0x5b,0x84,0x52,0xf8,0x43,0xfe,0x75,0xd1,0x94,0x21,0xfd,0x61,0xf7, + 0x4b,0xe6,0xfd,0x93,0xc7,0x68,0xde,0x9b,0xd2,0xff,0x5a,0xce,0xc5,0x52,0x56,0x01, + 0x09,0x7e,0xf2,0xed,0x82,0x46,0xcd,0xa7,0x5e,0x3c,0xf9,0x07,0x3d,0xff,0x7f,0x99, + 0xcf,0xbf,0xf2,0x47,0xde,0x0f,0xca,0x1f,0x70,0x3b,0x1b,0xaf,0x69,0x5c,0x54,0x40, + 0x06,0x02,0x40,0xc1,0x0f,0x2e,0x20,0x14,0x62,0xb9,0x8c,0x96,0x65,0xe6,0xfd,0xfa, + 0xc6,0x2b,0x30,0xd1,0xd9,0x92,0x74,0x8f,0x88,0xdf,0xaa,0x98,0xa4,0x0d,0x27,0x8a, + 0xc7,0xc4,0x3a,0x66,0xb4,0x0c,0x7b,0xc7,0xc5,0x31,0x78,0x83,0xd6,0x27,0xd1,0x10, + 0xc2,0xe6,0xfd,0x15,0x3f,0x86,0xc3,0xb4,0x36,0xe9,0xde,0x4d,0xe6,0x42,0x4f,0x75, + 0x65,0x7f,0xcf,0x37,0x9e,0xf7,0xe1,0x95,0x84,0xb7,0x8f,0xbc,0x09,0x3d,0xd4,0x97, + 0x74,0xf7,0x91,0xa4,0x64,0xce,0x62,0x42,0xea,0x92,0x7b,0x21,0xa0,0xbb,0x63,0x85, + 0xc3,0xd0,0x2b,0x07,0x06,0xdd,0x41,0x02,0x78,0x25,0xc1,0x8c,0x63,0xd2,0xc3,0x92, + 0xaa,0x33,0xe3,0x88,0xa0,0x9a,0xcf,0x2f,0x18,0x86,0xc3,0x50,0xdb,0xcf,0x9e,0x1f, + 0x9b,0xde,0x09,0x35,0xfd,0x2b,0xe2,0x35,0x7e,0x38,0x4c,0x6a,0x75,0x77,0x1c,0x9f, + 0x0f,0x3e,0x34,0xc6,0xa4,0xf5,0xa9,0xfb,0x97,0x96,0x8f,0xc2,0x04,0x34,0xeb,0xde, + 0x1a,0xf1,0x26,0x8a,0x46,0x71,0x7c,0x86,0x9f,0x5d,0x99,0xad,0x5f,0x17,0x17,0xcf, + 0xc2,0xeb,0x50,0xa7,0x7b,0xe3,0xe2,0xd0,0x32,0xf3,0xfe,0xb8,0xb0,0x1f,0x26,0xa1, + 0x45,0xf7,0x26,0x3b,0xbe,0xc6,0x8c,0x45,0xfa,0xaa,0x31,0x71,0xbf,0x3a,0x49,0x5a, + 0xf4,0x92,0xb1,0x69,0x83,0xec,0xca,0x73,0xba,0x77,0x4c,0x1c,0x01,0x73,0xbc,0x43, + 0xca,0x2e,0xe3,0xf9,0x31,0x71,0x97,0x3e,0x01,0x8d,0x7a,0x71,0x50,0x9c,0x27,0x4d, + 0x48,0xcd,0xfd,0x5e,0x7c,0xfe,0xbb,0xa4,0x19,0x9f,0x3f,0x26,0x99,0xef,0x9f,0x28, + 0xa8,0xc6,0xf7,0xd7,0xdd,0xbb,0xe9,0xa7,0xd8,0xdb,0x56,0xe9,0xf2,0x18,0x99,0x4f, + 0x71,0x44,0x33,0xe3,0x64,0x14,0x3a,0x81,0x0f,0xe4,0x1c,0x5b,0xfd,0xa9,0xf1,0x4a, + 0x2b,0x81,0xcf,0x8f,0x9f,0xfc,0x52,0x7a,0x5c,0xf0,0xb3,0xd9,0x28,0xfc,0x53,0xe3, + 0x4a,0x90,0xe8,0xf0,0xb8,0x61,0x8c,0xb3,0x6f,0xc5,0xf8,0x37,0xa6,0x7c,0x49,0x3b, + 0x10,0x9b,0x9f,0x74,0x7f,0xdb,0x75,0x15,0x6c,0xa2,0x95,0x23,0xae,0x6f,0xcf,0x7e, + 0x05,0x0e,0xc4,0xbe,0x3e,0xe2,0xde,0x40,0xde,0x60,0x57,0xd8,0x4f,0x1b,0xc8,0x09, + 0xeb,0xf9,0x6d,0xf2,0x32,0xf8,0x30,0xde,0xa4,0x7b,0x55,0xb1,0x8b,0x0d,0x64,0x71, + 0xd2,0x1b,0x14,0xff,0xf4,0xc4,0x87,0xd1,0xa6,0x11,0x77,0x50,0x1c,0x84,0xdf,0x01, + 0xfb,0x29,0x28,0xbe,0x42,0xcc,0xf5,0xa0,0x15,0xec,0x57,0x26,0xcb,0xd8,0xfc,0x28, + 0xe2,0x7e,0x78,0x1f,0x1a,0x87,0x8a,0xe3,0xa2,0xdf,0x98,0xb1,0xb1,0xaa,0xd4,0x54, + 0x8f,0x89,0x43,0xc4,0x9c,0x1f,0x59,0xda,0x03,0x2f,0xe2,0x45,0x75,0xda,0xb7,0x60, + 0x82,0x36,0xbe,0xea,0x79,0xfa,0xc5,0xf9,0x2a,0xbb,0x2d,0xe9,0x89,0xb3,0x69,0xe4, + 0xf7,0xc7,0xc5,0x63,0x60,0xcd,0x4f,0xc5,0x36,0xf8,0x17,0x98,0xaf,0xbb,0xc3,0x64, + 0x16,0x3c,0x07,0x6a,0xa2,0xf8,0x9b,0xe2,0x2d,0xf4,0x80,0x34,0x5f,0x97,0xd7,0x93, + 0x53,0x70,0x00,0x7f,0x5a,0x4f,0xce,0x59,0xf3,0xa9,0xc2,0xd3,0x7c,0x50,0x3d,0x23, + 0x91,0xef,0x49,0x07,0x22,0xf3,0x46,0xe4,0x1b,0xc8,0x57,0xb4,0x03,0xec,0x4a,0xd1, + 0x06,0x72,0x1a,0x0e,0x18,0xe3,0xd5,0xad,0xe7,0x8f,0x48,0x5d,0xf0,0x30,0x9f,0xcf, + 0x23,0xf7,0xb2,0x69,0x54,0xf5,0xa2,0x60,0xe8,0x0b,0x6a,0xaf,0x18,0xd0,0xe5,0x20, + 0x39,0x4e,0x53,0x13,0xfb,0x8a,0xf5,0xfc,0x64,0xf9,0x08,0x1c,0x83,0x66,0xea,0x1d, + 0x15,0x0f,0xeb,0x17,0xa1,0x91,0x7a,0x62,0x55,0x7f,0x43,0x2f,0xb2,0x2b,0x81,0x98, + 0x38,0xce,0x0d,0xf6,0xa7,0x1f,0x97,0xcc,0xf1,0xb6,0x09,0x31,0x18,0x87,0x66,0xf0, + 0x52,0xb7,0xca,0x8d,0x05,0xb4,0x2a,0x09,0xe3,0x04,0xaf,0x88,0x67,0x52,0x3f,0x89, + 0xaf,0x80,0xb9,0xfe,0x65,0xb6,0x7e,0x8e,0x42,0xb3,0xe6,0xfd,0xbe,0xb8,0x0b,0x5e, + 0x83,0x26,0xcd,0x13,0x15,0xab,0xe1,0xa0,0xc0,0xae,0x44,0xc5,0xbf,0xa4,0x17,0x80, + 0x1b,0x47,0xac,0xef,0x85,0x4a,0xcb,0xc8,0x66,0xa8,0xd5,0xdc,0x65,0x44,0x62,0xf7, + 0xd7,0x6a,0xc5,0x51,0x12,0xf0,0x1c,0xc4,0x2b,0xd1,0xd2,0xdf,0x53,0xc3,0x20,0x49, + 0xcb,0x2d,0x2c,0x16,0xaa,0xa5,0xcd,0x42,0xad,0xb6,0x22,0x5a,0xba,0x4b,0x79,0x94, + 0xfd,0xea,0x57,0x08,0x7b,0xbe,0x71,0xdb,0xb0,0x69,0xbc,0x60,0xad,0x07,0x7f,0x59, + 0x35,0x74,0xc0,0x3a,0x76,0xf1,0xa6,0xea,0xd8,0x83,0x10,0x58,0x5e,0x54,0x7a,0x4c, + 0x82,0xbd,0x10,0xd0,0xdc,0x0a,0x19,0x88,0xa5,0x8c,0x23,0x82,0xb9,0x1e,0x36,0x14, + 0x87,0xa1,0x1b,0x07,0x15,0x13,0x63,0xf4,0x04,0x34,0xcb,0x9e,0xc8,0x0c,0x1c,0x78, + 0x13,0x0e,0x33,0x4c,0x53,0xe3,0x3d,0x2d,0x9a,0xeb,0x73,0x7b,0xc1,0xab,0xc0,0x07, + 0x35,0x24,0x9e,0x87,0x0b,0xfe,0xe6,0xe5,0x25,0x0f,0x75,0x0e,0xe3,0x95,0xe5,0x6c, + 0x98,0xe7,0x21,0x35,0xde,0x37,0x89,0xf9,0x3d,0x56,0x94,0x0f,0x1b,0x17,0xdb,0xc5, + 0x6a,0x7a,0x14,0xee,0x0a,0x05,0xb6,0x89,0xec,0x8a,0xd4,0x8c,0x13,0x75,0x5e,0xbd, + 0x6c,0xdc,0xff,0x02,0x98,0xf7,0x2f,0x56,0x92,0xd0,0x07,0xb5,0xcc,0xd1,0xb8,0x6f, + 0x63,0x2f,0xe6,0x03,0x79,0x13,0xe1,0x57,0x64,0x17,0x35,0x0c,0x70,0x53,0x72,0xdc, + 0x9a,0xff,0x36,0xe8,0x82,0xbd,0x42,0x40,0x9b,0xa9,0x7c,0x69,0x0e,0xec,0x90,0xfd, + 0x21,0xb9,0x94,0x0c,0xe0,0x78,0x43,0xb2,0x82,0x86,0x10,0x58,0xca,0xc6,0xfb,0x8a, + 0x60,0x3e,0x7f,0x7b,0xd9,0x2e,0x36,0x69,0x25,0x6c,0x7e,0x0a,0xbf,0x46,0x3a,0x40, + 0xd5,0xe4,0x68,0x68,0x98,0x4d,0x7b,0x40,0x73,0x45,0x99,0xff,0x31,0xe6,0x33,0xf4, + 0xa6,0xb5,0x1e,0x62,0x05,0x7f,0x69,0xbc,0xbf,0x22,0x4e,0xd3,0xde,0x96,0x6a,0xf0, + 0xb5,0xd9,0xfb,0x0b,0xcd,0x4b,0x67,0xb1,0x61,0xaa,0x38,0x10,0xf6,0xfe,0x23,0x96, + 0xbf,0x4a,0x4c,0xdf,0x65,0xfc,0xd1,0x1f,0xab,0x3a,0x2b,0xa7,0x66,0x63,0x18,0x32, + 0x8d,0x8b,0x96,0xff,0x91,0x15,0x73,0xbd,0x89,0x61,0x7d,0x04,0x6a,0x05,0x0f,0x15, + 0x55,0x3e,0xed,0x1e,0x63,0xbd,0x35,0xe2,0x4f,0xc7,0xac,0xf5,0xec,0x2f,0xf0,0xc3, + 0x21,0x61,0x2e,0x75,0x0f,0xbb,0xe6,0x49,0x87,0xa0,0x96,0xca,0xb1,0xba,0x79,0xd4, + 0x30,0x98,0x1b,0x39,0x04,0x3e,0xea,0x8e,0x91,0x63,0xe9,0xf5,0x60,0xfa,0x9f,0xea, + 0xc8,0x4a,0x19,0xbd,0x4d,0x5b,0x90,0x94,0xf0,0x2b,0xf8,0xbd,0x30,0x03,0x3d,0x12, + 0xbb,0xdf,0x5c,0x6f,0x54,0xb9,0x95,0x7d,0xa4,0x73,0xd8,0xf7,0xeb,0xba,0x05,0x0e, + 0xa8,0x81,0x81,0x8a,0x6f,0xbb,0xca,0xf0,0xb3,0x4d,0xb0,0xef,0xf7,0x5f,0xe1,0x39, + 0x5a,0x89,0xdf,0xef,0x88,0x75,0x7f,0x77,0xf7,0x57,0x94,0x8f,0xe9,0x8d,0x49,0xef, + 0x06,0xf1,0x2b,0xf0,0x57,0x4f,0xdc,0xf8,0xbb,0x59,0x17,0xc5,0xd9,0xf0,0x71,0x47, + 0xcb,0xc5,0xc0,0x06,0xf1,0x34,0x4c,0xd2,0x1b,0xf0,0xa7,0x77,0xe6,0x9a,0xf7,0xcb, + 0x05,0x7b,0xb8,0xf7,0x66,0x83,0xda,0x15,0x9b,0x50,0x9b,0x13,0xde,0xfd,0xc2,0x30, + 0xba,0x91,0xa3,0xcc,0x8d,0x24,0x4d,0x7f,0x72,0xe4,0x5e,0x73,0x7e,0x40,0x7a,0x96, + 0xb9,0x1d,0x16,0xbf,0xd6,0x8a,0x77,0x2c,0x7b,0xa3,0x7b,0xd1,0xb0,0xe7,0xb2,0xd8, + 0x22,0xbc,0x1b,0xad,0x39,0xe3,0x19,0x17,0x9f,0xd6,0x58,0x20,0xc3,0xf8,0xa5,0xc7, + 0xcc,0xf9,0xdf,0x5d,0xf1,0x18,0x7a,0x0f,0xdd,0xbd,0x8e,0x94,0xc2,0x5b,0xb0,0xe0, + 0x8c,0xff,0x2e,0x42,0x76,0xfd,0x3a,0x56,0x9b,0x2c,0x5e,0x4f,0x4e,0x2b,0xdc,0x9f, + 0xac,0x27,0xef,0x58,0x7f,0x5f,0xa0,0x8f,0xb1,0xd1,0x7d,0x5d,0x77,0xaf,0x89,0xdc, + 0x1a,0xdb,0x04,0xf3,0x07,0x8a,0xea,0x6e,0x6e,0xea,0x3e,0xe0,0xe3,0xfe,0xea,0x9f, + 0x29,0xfe,0x34,0x73,0xbd,0xcd,0xff,0xa8,0xd2,0x03,0xc6,0x7c,0x02,0x21,0xf2,0xe3, + 0x85,0x01,0xbd,0x28,0x7e,0x4d,0x2b,0xf7,0x48,0x45,0x41,0x9f,0x6e,0x3a,0xf6,0x84, + 0xf5,0xbd,0xef,0x2e,0x3f,0xab,0xf2,0x41,0x05,0xc4,0xe5,0xf0,0x32,0x8b,0x47,0x47, + 0xc7,0x5a,0xfd,0x45,0x13,0xe4,0xef,0x74,0xe6,0x3f,0x7f,0x4a,0x53,0xe3,0x7d,0xc7, + 0x5a,0x3f,0x54,0xd8,0x93,0x8a,0x47,0xad,0x23,0xd5,0x68,0xd4,0xc6,0xc5,0xdd,0x1d, + 0xef,0xe2,0x8c,0xc5,0xc5,0x51,0x01,0xaf,0xfc,0x29,0x4e,0x94,0xf9,0xfe,0x95,0xca, + 0x33,0xa9,0x78,0x27,0x6e,0x90,0x5e,0x26,0x4b,0x58,0x98,0x9b,0xd1,0xd8,0x75,0x0f, + 0x59,0xa4,0x17,0x8f,0xb1,0xf5,0x80,0x81,0x8f,0xf9,0x73,0x7d,0x99,0xf9,0xfe,0x3b, + 0xa4,0x75,0xa9,0xf8,0x45,0xe6,0xd1,0x1e,0x1e,0x76,0x5b,0xd7,0x4a,0x87,0x85,0x5a, + 0x7d,0x45,0x9c,0xbc,0x4b,0x0f,0x1b,0xf1,0x2b,0xa9,0x59,0xeb,0xa1,0x20,0x20,0xe3, + 0x45,0xd7,0x6e,0xb2,0x66,0xd9,0x0f,0xa0,0x04,0x7f,0x9d,0x23,0xa4,0x6e,0x7b,0x07, + 0xcc,0xfb,0xad,0xf5,0x26,0x97,0x79,0xa0,0x57,0x65,0x93,0xa0,0x46,0x54,0xb5,0x53, + 0x08,0x0c,0xad,0x08,0x7e,0x69,0xa9,0x6a,0xe0,0x01,0x18,0x84,0x5e,0x29,0x60,0xe0, + 0x01,0x73,0xfa,0xa1,0x78,0x1d,0x4c,0x28,0xb5,0x7a,0x49,0x4c,0x5c,0x03,0xec,0xfd, + 0x4f,0xcc,0x3e,0x37,0xa3,0x5a,0x99,0xf0,0x2d,0x1a,0xbc,0x3f,0x3e,0x6d,0x64,0x0b, + 0xae,0x90,0xad,0x71,0x51,0xb7,0xfc,0x4f,0xec,0x17,0x97,0x60,0x52,0xbb,0x0e,0xe3, + 0xf5,0x10,0x1b,0x78,0xf3,0x09,0xef,0xfe,0x56,0x1d,0x26,0xd7,0xb6,0x0c,0x62,0x58, + 0xd7,0x26,0x94,0xe6,0x01,0x34,0x0a,0xcd,0xf9,0xd4,0xcb,0xaf,0x00,0x5f,0x24,0x71, + 0xb1,0x59,0x7a,0xb9,0xa3,0x59,0xf4,0xee,0x23,0x01,0x78,0xff,0x86,0x4f,0x9d,0x2c, + 0x4e,0x88,0xef,0xb4,0xbd,0xae,0xd5,0x25,0x03,0x08,0x84,0xac,0xf9,0x57,0xce,0xca, + 0x1c,0xff,0x44,0x4b,0xd7,0x31,0x27,0x54,0x1b,0x77,0x7f,0x44,0xaa,0x63,0x5b,0x97, + 0x7d,0x7a,0x48,0xde,0xcd,0x96,0xfd,0x56,0xcd,0x17,0x92,0x71,0xbc,0x96,0xff,0x2f, + 0x18,0x94,0x53,0x1f,0xd1,0x4a,0x5c,0x06,0xe0,0x5e,0xb8,0x73,0xa5,0xf4,0x38,0x51, + 0x13,0x45,0x40,0xf4,0xee,0x47,0xc3,0xbe,0x84,0x8c,0xe3,0xb5,0xde,0xa7,0x60,0x8f, + 0x31,0x7b,0x51,0xb2,0x0e,0x7e,0x00,0xb5,0xc9,0xd6,0xb8,0xab,0x9a,0xc1,0x86,0x1a, + 0x5d,0xde,0x49,0x75,0xc4,0x3f,0x9a,0x8c,0xf8,0xc7,0x5a,0x9f,0x5d,0xe6,0x7a,0x70, + 0x07,0xc8,0xeb,0xd0,0xbc,0x77,0x55,0xbc,0x2a,0xcc,0x60,0x49,0x9d,0xfe,0xf9,0xa8, + 0xf8,0x36,0xfc,0x1a,0xe2,0xb8,0x90,0x74,0xcb,0x3f,0x9c,0x81,0xd4,0x7a,0x88,0x89, + 0x4d,0x2c,0xbe,0xb7,0xd0,0x7f,0x08,0x8a,0xe3,0xf0,0x77,0xd0,0xd8,0xef,0x4d,0x3e, + 0x3f,0x8e,0x3f,0xb5,0x7b,0xc7,0x3a,0xc7,0xcd,0x3f,0x17,0xe8,0xb0,0x07,0xde,0x35, + 0xf0,0xcf,0x3a,0x0c,0xf4,0x23,0x0c,0x06,0xc4,0xe0,0xfd,0x82,0x6b,0xf4,0xe2,0x6d, + 0x33,0xde,0x91,0x8e,0x76,0x1f,0xc2,0xe7,0xdb,0xf0,0x8f,0x14,0x30,0xfe,0xe8,0x31, + 0x36,0xd6,0x1e,0xa8,0x1d,0x73,0x8f,0x11,0x3f,0x6c,0x85,0x4f,0xf7,0xbb,0x62,0x64, + 0x84,0xa4,0xde,0xff,0x9c,0xf5,0xe7,0x4d,0x96,0xaf,0x34,0x40,0x4e,0xbc,0x70,0x1d, + 0x1b,0x66,0x20,0xca,0x26,0x6a,0x37,0x41,0xe0,0x57,0x24,0x91,0x04,0xbb,0xb2,0x1b, + 0x1d,0x51,0x1a,0xff,0x84,0x85,0xd9,0x46,0xd0,0x5f,0x5d,0xf7,0x15,0x0e,0x0c,0x66, + 0xfe,0x1d,0x21,0xdd,0x9b,0xa2,0x0c,0x08,0xad,0x8e,0x5c,0x3c,0xb2,0x29,0x56,0x19, + 0x96,0x9d,0xf8,0xc7,0xa3,0xfd,0x0e,0xf1,0x4f,0x93,0x78,0x07,0x79,0x1e,0x9a,0x76, + 0x6f,0xbd,0x41,0xec,0xa1,0xbf,0x8b,0x2d,0x3e,0x53,0x0c,0xe2,0x11,0x7a,0x34,0xd6, + 0x98,0x0c,0x30,0xfc,0x63,0xbd,0x8f,0x76,0x6d,0x6a,0x7e,0x7e,0x25,0x72,0x63,0x60, + 0xda,0x98,0x98,0xd4,0x26,0xb4,0xe6,0x23,0x2c,0xa2,0x0d,0x69,0x93,0xed,0xd7,0x69, + 0xde,0x0f,0xc4,0xa1,0x42,0x73,0xfe,0x77,0x17,0x8c,0x9a,0x4e,0x69,0x1d,0x37,0x3c, + 0x1f,0xe2,0x42,0x55,0x0b,0x13,0x9e,0x5e,0xc4,0x9f,0x5a,0x1d,0xce,0xcf,0x3b,0x90, + 0xf6,0xff,0x8f,0xa5,0x40,0x4e,0xe9,0x29,0xe6,0x7f,0x98,0x1b,0xb9,0x13,0x66,0x41, + 0x67,0xb8,0x72,0x70,0xf9,0x9d,0x0c,0xff,0xfc,0x13,0x7c,0x1a,0x1d,0xcb,0x39,0xeb, + 0xef,0xab,0xc3,0x0f,0x4d,0x90,0x83,0x68,0x27,0x30,0xc6,0x60,0xcf,0x4d,0xbe,0x4d, + 0x3b,0x7f,0x3f,0xd2,0xb6,0x21,0x34,0x09,0xdf,0xa5,0x95,0x49,0x36,0xde,0x31,0xcb, + 0xff,0xb4,0x95,0x0d,0x1a,0x4e,0xa6,0x8f,0x0c,0xc2,0xe3,0x02,0xbb,0x3f,0x4e,0x8a, + 0x69,0x8f,0xb4,0x46,0x77,0x2d,0x26,0x2f,0xb1,0xa9,0xae,0x4d,0xfa,0x11,0xff,0x98, + 0xeb,0x73,0xa4,0x7c,0x37,0x70,0x90,0x73,0x56,0x5c,0x2b,0x5d,0x14,0xee,0xe9,0xba, + 0x36,0x26,0x7e,0x9b,0x21,0xa2,0x06,0xea,0xd9,0x25,0x5e,0x5c,0x7a,0x12,0xf6,0xed, + 0xf6,0xc4,0xc4,0x8b,0x69,0xfc,0x03,0xc9,0x54,0x3c,0xea,0x4c,0xc2,0x08,0xdc,0x0d, + 0x25,0x74,0x06,0x5e,0x59,0x0c,0xde,0x0e,0x76,0x65,0x4c,0x6b,0x84,0xeb,0xec,0xf8, + 0xa7,0x5b,0x31,0x83,0xda,0xb4,0x6a,0x66,0x34,0xad,0x9d,0x16,0x6d,0x45,0x20,0xd4, + 0xa8,0x79,0xbe,0xcf,0x80,0xd0,0xdb,0xcc,0x58,0xb9,0xcd,0x81,0x7f,0xd6,0x98,0xa0, + 0xa5,0x5a,0x61,0x46,0xfb,0x7d,0x68,0x6c,0x86,0x06,0x4d,0x5e,0x7c,0x4d,0xb5,0x70, + 0x10,0xd7,0xcf,0x76,0x1b,0xfe,0xa9,0x90,0xaa,0xe1,0x09,0x7e,0xbf,0xc4,0x61,0xcf, + 0x90,0x1c,0x25,0x5d,0xd2,0xa3,0xc2,0xed,0x2c,0x70,0x97,0x06,0xd8,0x95,0x1a,0x66, + 0x30,0xfc,0x63,0xfe,0x93,0x21,0x85,0x76,0x4a,0x23,0xdc,0x58,0xee,0x2a,0x8d,0x74, + 0xc5,0x3a,0xe6,0x55,0x2f,0xf7,0x47,0x49,0x21,0xec,0x0d,0xb0,0x88,0x6f,0xc7,0x3f, + 0x7d,0x72,0x98,0x0d,0x93,0x8d,0x37,0xe2,0xe2,0x78,0x4f,0x2e,0x26,0x33,0x18,0x10, + 0x9a,0x1b,0x94,0x65,0x3a,0x43,0x95,0xde,0x51,0x0f,0x41,0x80,0x8a,0xc7,0x89,0x85, + 0x7f,0xae,0x4d,0x8d,0xf7,0x95,0x5f,0x0f,0xc7,0x2e,0x90,0x16,0x6d,0xeb,0x43,0x1d, + 0xdf,0x8a,0x5d,0xf0,0xd7,0x2e,0x9f,0x16,0x15,0x5f,0x8d,0x5d,0xf6,0xb7,0x2c,0xf7, + 0x3e,0xd4,0xf9,0xe6,0x34,0x0b,0x6f,0x70,0xfc,0xd3,0xa2,0x79,0x1f,0x16,0x7f,0xcf, + 0xa6,0xa5,0xa5,0xad,0xf8,0x41,0x71,0x58,0x3b,0xaa,0x34,0x2f,0x2f,0x66,0xf8,0x87, + 0xdc,0x0f,0x75,0xcb,0x3c,0x43,0xe2,0x4d,0x69,0xfc,0x53,0x91,0x94,0x0d,0x90,0x13, + 0x4a,0x52,0x66,0x6c,0x2b,0xde,0xc8,0xbc,0x71,0xf7,0x2d,0x75,0x50,0xc4,0xf0,0x8f, + 0x9a,0x90,0x19,0x22,0x8a,0x1c,0x29,0x91,0xd2,0xfe,0x87,0x81,0x1c,0xc2,0xc6,0x3b, + 0x83,0x0c,0xd0,0xbd,0x6c,0x36,0x8a,0x4a,0x43,0x03,0xd0,0x51,0xe5,0x0f,0x7d,0x4e, + 0x29,0x1d,0xee,0xe8,0x50,0xd8,0x78,0x4b,0x49,0xc8,0xf2,0x3f,0x15,0x05,0xbb,0x84, + 0x34,0x7a,0x94,0x6a,0xb5,0xa2,0x28,0xb0,0xfb,0x19,0x10,0x62,0x0b,0x69,0x18,0x36, + 0x57,0xef,0xc4,0xf9,0x29,0x4c,0xe3,0x1f,0x69,0x97,0x85,0x5e,0x14,0x86,0x76,0x96, + 0xfe,0x7d,0x74,0xfa,0x30,0x39,0x0a,0x8d,0x4b,0xd9,0xfb,0x0f,0x08,0x1d,0xb0,0x4f, + 0x0b,0x44,0xc5,0xb5,0x5d,0xe6,0xf3,0x9f,0x54,0x76,0x39,0xd1,0xce,0xec,0x68,0x2b, + 0x1a,0x8d,0x5a,0x49,0xb4,0xf3,0xcd,0x65,0x17,0x28,0x5f,0x2a,0xef,0x44,0xcd,0xe7, + 0xfb,0x19,0xfe,0x19,0x49,0xe1,0x1f,0x92,0x98,0xd6,0xac,0x14,0x30,0xfc,0x23,0x27, + 0xa0,0x41,0x08,0x51,0x31,0x29,0x21,0xa2,0x61,0x40,0xe8,0x58,0x97,0xb9,0xfe,0x55, + 0xc9,0x0f,0xef,0x48,0xb5,0x08,0x72,0xfc,0xca,0x7d,0x30,0x3f,0xca,0xdc,0x8e,0x1f, + 0xee,0x63,0xb0,0x07,0xf1,0x8f,0xf0,0x80,0xd6,0x40,0xe5,0x51,0xe6,0x58,0x4c,0xff, + 0xe0,0xdf,0x98,0xf2,0x3f,0xc1,0xc2,0x95,0xe8,0x7f,0x7e,0x23,0x07,0x4b,0x3d,0xcc, + 0xa8,0xd6,0x5d,0xc1,0x52,0xf6,0x05,0xc9,0xcc,0xf1,0x2e,0x61,0xf8,0xc7,0xfc,0xfb, + 0x56,0x0a,0xb3,0xe0,0x27,0xf8,0xfd,0xde,0x45,0x66,0x03,0xc3,0x03,0x7a,0xc5,0x37, + 0xd8,0x46,0x66,0x93,0x7a,0x5b,0x42,0x6e,0x67,0xdf,0xef,0x4f,0x60,0x4e,0x42,0x66, + 0x2f,0xaa,0x59,0xcf,0x97,0x67,0xc3,0x5b,0x88,0x7f,0x16,0x8b,0xf7,0xc0,0x2f,0x99, + 0x51,0x5c,0xf7,0x50,0x73,0xe8,0x65,0xfd,0xfa,0xe1,0xc2,0x0d,0x9d,0x2c,0xf4,0x74, + 0x2c,0x19,0x0b,0xac,0x16,0x8e,0x59,0xfb,0x2f,0xf9,0xea,0x3d,0xa6,0x3f,0x41,0xc7, + 0x72,0xbd,0xbe,0x60,0xbf,0x38,0x4a,0x27,0xd6,0xde,0xc3,0x02,0x19,0xbb,0xc2,0x3c, + 0x70,0x92,0x4d,0xc5,0x11,0x6b,0xff,0xa5,0x15,0xb0,0xfd,0x7b,0xf4,0xc6,0xa4,0x67, + 0xbc,0x33,0x15,0xc8,0xc6,0xc5,0x66,0x75,0x32,0xde,0xf2,0x5b,0xcf,0x78,0xeb,0x15, + 0xf8,0x0b,0xba,0x28,0xe9,0x49,0xb0,0x50,0x68,0xe1,0x1f,0xe6,0x7f,0x7a,0x63,0x1c, + 0xbd,0x0c,0x0a,0x6f,0xc1,0x8d,0xc7,0x7a,0xc6,0x84,0x1f,0xb2,0x2b,0x8d,0xa3,0xc5, + 0x4b,0x23,0xa7,0x60,0x93,0xc0,0xfc,0x4f,0x3b,0x0b,0xdc,0xe6,0xf3,0xb7,0x33,0xef, + 0x84,0xfe,0xaa,0x68,0x7d,0x84,0xef,0xce,0xfa,0x19,0x3a,0x9a,0x55,0x79,0x40,0x98, + 0xaf,0x0b,0x6c,0xbf,0xa6,0x3d,0x52,0xf1,0xa3,0x23,0x6c,0xbc,0x49,0xcb,0xff,0x87, + 0x15,0xc3,0xff,0x14,0x61,0x34,0xaf,0x82,0x80,0xca,0xfc,0xf9,0xf1,0xb2,0xde,0x02, + 0xbf,0x5e,0x14,0x60,0xfb,0xdf,0x1e,0xa8,0x49,0x32,0xff,0x7f,0xc2,0x5a,0x9f,0x35, + 0xe5,0xc6,0x78,0xe7,0x8f,0xcd,0xb8,0xc4,0x8c,0xbb,0xc3,0x2c,0x3a,0x37,0x31,0x58, + 0xb2,0x40,0xff,0xfc,0x13,0x33,0x46,0xe1,0x24,0x39,0x90,0xdc,0xc3,0xf6,0x8f,0xd6, + 0x7a,0x8b,0xc2,0x28,0x8b,0x56,0xcd,0x7a,0x49,0x5c,0x18,0x85,0x77,0x85,0xbb,0xfe, + 0x1b,0xdb,0xbd,0xee,0xa9,0x98,0x40,0x8f,0x8d,0x1b,0x87,0x11,0x23,0x54,0xa5,0xfd, + 0x43,0x47,0xf4,0x52,0x6a,0xf7,0x2a,0x72,0x63,0xe9,0xd6,0xb1,0x69,0x4d,0xd2,0x24, + 0xdc,0xa3,0x7b,0x8f,0x88,0xe3,0x91,0x63,0x50,0xaf,0xb3,0xef,0x8b,0x2e,0x33,0xdf, + 0xa7,0x1f,0x10,0xff,0x34,0xeb,0x3d,0x71,0x71,0x0f,0x06,0xb2,0xf5,0x0c,0xbd,0x18, + 0x11,0xad,0x68,0x5b,0xe9,0xef,0xe8,0x89,0x64,0x83,0x2e,0x53,0x12,0x4c,0xe3,0x1f, + 0x33,0xde,0xc5,0x09,0xbf,0xff,0xf6,0x1f,0xc4,0x43,0x01,0x58,0xc2,0xe2,0x35,0x8b, + 0x80,0xa3,0x70,0x1f,0xf5,0xe1,0xfd,0xb1,0x34,0xfe,0x91,0x18,0xfe,0x09,0x73,0x90, + 0xb3,0x85,0x4d,0x94,0x47,0x73,0x2f,0xf4,0x6d,0x51,0x7b,0x83,0xeb,0xf4,0xab,0x81, + 0xfc,0x82,0x0d,0xaf,0x5a,0x67,0xdf,0x17,0xb1,0xfc,0x0f,0x2d,0x62,0x61,0x25,0xcc, + 0x06,0xf5,0x94,0xf8,0x8f,0x08,0x8c,0x35,0xf7,0xd8,0x35,0x4d,0x43,0x93,0x72,0xcb, + 0x2b,0x6c,0x19,0x1c,0x25,0xc7,0x96,0xd6,0x0d,0xb1,0x8d,0x2a,0x15,0x2c,0xfc,0x53, + 0x8c,0xf8,0x67,0x89,0xee,0x3d,0x27,0x3e,0x13,0xbb,0x07,0x98,0xb7,0x39,0x57,0xb5, + 0x8e,0x4e,0xcc,0x6d,0x3e,0x56,0xac,0x8b,0x63,0x94,0xf9,0x9f,0x63,0x88,0x7f,0xca, + 0xd2,0x78,0x83,0xad,0x1f,0xb2,0x24,0x59,0xbc,0x9a,0xe1,0xcf,0xf7,0xcb,0x16,0x0d, + 0x14,0x9f,0xeb,0x3c,0x07,0x13,0xa5,0xb5,0x7a,0xf1,0xb8,0x78,0x05,0xde,0x37,0x56, + 0x54,0x1a,0xff,0xe8,0xca,0x59,0xf8,0x9b,0x21,0x5f,0xd2,0xbd,0x9d,0x3c,0x09,0x5b, + 0x6f,0xaf,0x1a,0x72,0x5d,0x0a,0xbd,0x09,0xcf,0x85,0x17,0xbc,0x22,0xf7,0x91,0xb3, + 0x06,0x35,0xe4,0xe0,0x7f,0x0a,0x06,0x8d,0x4d,0x84,0xc2,0x96,0xec,0xe3,0x5a,0xf5, + 0x6b,0xee,0x60,0x29,0x83,0xc1,0x4b,0x03,0xaf,0x15,0x05,0x59,0x84,0x7a,0x58,0x08, + 0xf4,0xb3,0x2b,0x47,0xac,0xf8,0xa5,0x97,0xef,0x51,0x0e,0x23,0xc9,0xb3,0x9d,0xec, + 0x80,0x4f,0x33,0x63,0x79,0x9c,0x9c,0x81,0xc3,0x42,0x89,0xde,0x86,0xfc,0xc9,0x61, + 0xa9,0xd6,0xc9,0xff,0x68,0xe5,0xeb,0xa4,0x09,0xe9,0x9a,0xfe,0xe2,0x6e,0x71,0x05, + 0x03,0x2a,0x0d,0x7a,0xb1,0x41,0x3b,0xcc,0x46,0x63,0xb4,0x82,0x43,0x97,0xb8,0x90, + 0xe6,0x7f,0x62,0xc2,0x33,0xca,0x5b,0x6c,0x3d,0xb8,0x87,0xc4,0x09,0x78,0x9d,0x19, + 0x05,0x63,0xe2,0x65,0xb6,0x1e,0x38,0xad,0x71,0x49,0x30,0x96,0xca,0x34,0x3b,0xff, + 0x13,0x30,0xbe,0xc7,0x4e,0x71,0x2d,0xbc,0x25,0xdd,0x80,0xd1,0xfc,0x0c,0x9b,0xb1, + 0x1b,0xd9,0x0a,0x6c,0xb5,0x42,0xbf,0x9d,0xff,0x09,0xc8,0xcf,0xe1,0x7a,0x08,0x72, + 0xd8,0x53,0xa5,0xef,0x1e,0x63,0xb3,0xf1,0x1c,0x2c,0xd0,0x65,0xfe,0xfe,0xc0,0x81, + 0x74,0x9a,0xff,0x19,0x29,0x30,0xf6,0x5f,0x45,0x65,0xa4,0x4d,0x41,0xfe,0xa7,0x88, + 0xcd,0x06,0xed,0x95,0xfc,0xfd,0x2e,0x9c,0x9f,0xde,0x2c,0xfe,0xc7,0xc4,0x3f,0x27, + 0x49,0x63,0xe4,0x53,0xb4,0x68,0xd8,0xbf,0x81,0xfc,0x26,0xb8,0x28,0x3e,0x3f,0x09, + 0x0c,0x21,0x74,0xb0,0x9f,0x46,0x32,0xf8,0x1f,0x8f,0xc1,0xff,0x54,0x88,0x5f,0xa0, + 0xbf,0x83,0xc6,0x11,0xcf,0x0d,0xe2,0x71,0xe5,0xce,0x78,0x53,0xb2,0x24,0x28,0x1e, + 0x87,0x3b,0x69,0x53,0xd2,0xc9,0xff,0x30,0xfc,0xf3,0x77,0x70,0x9d,0xbe,0x75,0x68, + 0xfa,0x25,0xed,0x0d,0x68,0x78,0xd5,0xfb,0x41,0xeb,0xa5,0x30,0x67,0x84,0x3e,0x10, + 0xad,0x4f,0xc9,0x89,0x7f,0xf8,0xec,0x81,0x28,0xc3,0xa4,0x6f,0xc9,0xab,0xb3,0xf6, + 0x77,0xbe,0x1b,0x7b,0x37,0xd8,0x32,0x1a,0xe0,0x1e,0x8c,0x64,0xf2,0x3f,0xcc,0xff, + 0xbc,0x85,0xfb,0xaf,0xf5,0xe2,0x6a,0xd8,0xa4,0x54,0x26,0xe4,0x6f,0x92,0x53,0xb4, + 0x53,0xa9,0x1a,0xcc,0xcd,0xff,0x50,0x86,0x7f,0x7e,0x82,0xe3,0x6d,0x0b,0x5d,0xa3, + 0xf6,0x46,0xfd,0x23,0xf2,0xb7,0x4b,0xaf,0x74,0x1d,0xd8,0x31,0x6f,0x24,0x37,0xff, + 0x83,0xf8,0x87,0xfb,0xf3,0xfa,0xd0,0x72,0xe6,0x6d,0x54,0xdc,0xcf,0x0e,0x6a,0x0f, + 0x33,0x43,0xe6,0xf3,0x29,0x65,0xf0,0x3f,0x23,0xe5,0x2c,0x5e,0x20,0xfe,0x49,0x8a, + 0xd7,0x30,0x20,0xd4,0xd8,0xe1,0x89,0xb5,0xbe,0xc3,0x8c,0x43,0x94,0xc1,0x9e,0x11, + 0x16,0x5d,0x32,0xf9,0x1f,0x48,0x9a,0xf1,0xe8,0xb7,0xe6,0xc6,0x1c,0xaf,0x70,0xd8, + 0x93,0xcc,0xc5,0xff,0x60,0x74,0xab,0xd5,0xbc,0x8f,0x32,0xb4,0xf3,0x1a,0x83,0x31, + 0x2c,0x2c,0xae,0x81,0x6f,0x40,0x1d,0x0b,0x73,0xc2,0xb0,0x94,0x83,0xff,0x59,0x23, + 0xf1,0xf8,0x5b,0xca,0x60,0xff,0x66,0x44,0x3b,0x51,0xb6,0x6c,0x10,0xf6,0xd8,0xf9, + 0x1c,0x1b,0xfe,0x29,0xb0,0xd8,0x9e,0xb9,0xd2,0xa3,0x20,0xb1,0x78,0x4d,0xd6,0xb0, + 0x08,0x7e,0x3b,0x32,0x42,0xc3,0xc6,0xa3,0xa2,0xbe,0x17,0x6c,0xfe,0x87,0xc1,0x1e, + 0x3f,0x27,0x79,0xaa,0xa1,0xc3,0x1f,0x5b,0x2e,0x97,0xbe,0x30,0x20,0xef,0xf5,0xab, + 0xcb,0x91,0xff,0x91,0x0c,0xfe,0x07,0xd2,0xf8,0x67,0x71,0x71,0x18,0xc6,0x55,0x3e, + 0x28,0x15,0x4e,0xf8,0x1a,0xe4,0xe2,0x88,0x88,0x57,0xf6,0xc9,0x38,0xf0,0xe9,0xd9, + 0xfc,0x8f,0x81,0x7f,0x96,0x1a,0xfc,0x4f,0x80,0xd3,0x3e,0x03,0x70,0x61,0xde,0xb3, + 0xcb,0xb7,0x46,0xab,0x2c,0x7e,0xe3,0x4d,0x6b,0xff,0xc5,0xf9,0x1f,0x0c,0xfa,0xed, + 0xee,0xeb,0xe1,0xb5,0x70,0x73,0x5b,0xc9,0x43,0xe2,0x70,0xc5,0x05,0x7f,0xe3,0x72, + 0x8f,0x8d,0x0f,0xc9,0xe6,0x7f,0xdc,0xb4,0x54,0x85,0x6e,0xa8,0x9d,0x25,0x33,0xfc, + 0x03,0xf1,0x70,0x43,0x85,0x83,0xff,0xb1,0xe6,0xb3,0x0d,0xf1,0x8f,0xe6,0x67,0x83, + 0xba,0xa9,0x1a,0x1e,0xd4,0x90,0xf6,0x29,0x65,0x57,0x64,0x7f,0xa8,0x5b,0x31,0x88, + 0x20,0xcd,0xc1,0xff,0x54,0x08,0xbb,0x8c,0xf9,0x7c,0xb0,0x10,0xe7,0x3f,0xa0,0x31, + 0x58,0x38,0x2c,0x1f,0x04,0x69,0xa9,0x0b,0xe7,0xff,0x86,0x6c,0xfe,0xc7,0x40,0x2f, + 0xc8,0xff,0x04,0x5f,0x03,0x4e,0x5b,0xbd,0xd5,0x7d,0x01,0x4c,0x22,0xc8,0x80,0xbe, + 0x69,0xfe,0x67,0x84,0x3d,0xff,0x42,0x01,0xbb,0xb8,0x7d,0xc6,0x9b,0x9a,0x39,0x1b, + 0x94,0x3f,0x21,0x27,0xff,0xe3,0x87,0x58,0x8a,0xe4,0xe9,0xbc,0x8d,0x2f,0xbc,0x12, + 0x2a,0x56,0xc1,0x38,0x69,0x40,0xd8,0x63,0xad,0xb7,0x0c,0xfe,0x07,0x18,0xfe,0x19, + 0x26,0x7e,0xf5,0x24,0x33,0x3c,0x0c,0xff,0xd0,0x43,0x50,0x43,0x8b,0xd9,0xfe,0x4b, + 0xe6,0x3f,0x39,0xf8,0x9f,0xf2,0x95,0xdc,0x3f,0xaf,0x08,0x16,0x7e,0x81,0x18,0x40, + 0x68,0x6e,0x09,0x73,0x53,0x81,0xd4,0xf7,0x62,0xf8,0x9f,0x34,0xff,0x13,0x13,0x0c, + 0x3c,0xe0,0x1e,0xbb,0xe9,0x3b,0xc2,0x23,0xc1,0xc0,0x20,0xdb,0x7d,0x94,0xc1,0x01, + 0x75,0x5e,0xa2,0xc8,0xf6,0xfd,0xa6,0xf9,0x9f,0xdd,0x32,0xfa,0xab,0x1b,0xce,0x78, + 0xd7,0x8a,0x5f,0x81,0x9f,0xc4,0x6e,0xfc,0x2d,0x03,0x42,0xb3,0xe1,0xe3,0xa1,0xa6, + 0x8b,0x1e,0xe4,0x7f,0x52,0xd4,0xd0,0x3b,0x3e,0x8b,0xff,0x29,0x36,0xf1,0xcf,0x17, + 0xb7,0xc0,0xc4,0x9a,0xe6,0x84,0x37,0xde,0xf6,0x7b,0x98,0x50,0x1b,0x12,0x29,0x44, + 0x64,0xf0,0x3f,0x16,0xfe,0x01,0x16,0xbf,0x26,0xa3,0x3c,0x48,0x9d,0x86,0xf7,0x07, + 0x96,0xa0,0xf1,0xae,0x3c,0x11,0xad,0x43,0xfe,0xc7,0x42,0x44,0x36,0xfe,0x07,0xf7, + 0x5f,0xbb,0xe6,0x0f,0xb8,0x17,0x92,0x59,0x74,0x13,0xf8,0x47,0x7e,0x10,0x24,0x2f, + 0xd0,0x03,0xb1,0xca,0xa4,0x6b,0x7d,0x6a,0xbc,0x6c,0x20,0x69,0xfc,0x03,0x90,0xda, + 0xaf,0x8d,0x91,0x6d,0x0c,0xdd,0xcd,0x4b,0xb0,0xd1,0x9d,0xa0,0x07,0xa0,0xb2,0xdf, + 0xee,0xaf,0x6c,0xfc,0x0f,0xdf,0x7f,0xad,0xd3,0xdd,0x0b,0xa9,0xc4,0x60,0xa4,0x5f, + 0x17,0x83,0x2c,0xac,0xff,0x00,0x76,0xea,0x96,0x3f,0x2f,0x72,0xf2,0x3f,0x7b,0x4c, + 0x27,0xb9,0x85,0xed,0xc7,0x59,0xe0,0x8e,0xb7,0xbe,0xc7,0x3c,0x6a,0x3d,0x06,0x1a, + 0x6b,0xbc,0x36,0xfe,0x07,0xac,0x8b,0x38,0x51,0x4d,0x68,0x8c,0xd8,0x11,0x23,0x66, + 0x40,0x6c,0xfc,0x8f,0xa0,0x18,0x4e,0x7b,0xeb,0x98,0xd8,0x0c,0x2f,0x33,0xc3,0xb3, + 0x5e,0x68,0x52,0xef,0x01,0xb6,0x2d,0x1d,0x4b,0xfb,0xf3,0x34,0xff,0x43,0xa5,0x75, + 0x9c,0xcf,0x71,0x57,0x90,0x9f,0xe1,0xfe,0x9d,0x3d,0x8d,0xec,0x06,0x8c,0xc8,0xc5, + 0x3c,0x7e,0x91,0x6c,0xfe,0x87,0xa1,0x1d,0x76,0xf1,0x69,0xb6,0x0f,0xea,0x91,0xe6, + 0xea,0xae,0x38,0x89,0x69,0x78,0xbf,0x15,0xef,0x9c,0xfc,0x0f,0xe2,0x1f,0xbe,0xa8, + 0x7c,0x5b,0x34,0xb6,0xde,0x5e,0x5a,0xb1,0xb0,0x30,0xc2,0xf0,0x80,0x7a,0xe2,0x73, + 0xe8,0xa8,0x7b,0xb5,0x1c,0xfc,0xcf,0x61,0x95,0x8d,0x6e,0xaf,0x18,0x60,0x78,0x7b, + 0xd1,0x2b,0x25,0xfb,0xeb,0x77,0x68,0x1f,0x6b,0xf5,0x43,0xc6,0xfc,0x68,0xcd,0xaf, + 0xb2,0x81,0xeb,0xd3,0x2c,0xfc,0x73,0x2d,0x83,0x91,0x15,0x2d,0xec,0x82,0x78,0x29, + 0xf2,0x06,0xc2,0x80,0xb1,0x2f,0x8e,0x0d,0x4c,0x36,0xb4,0xbc,0x86,0xf1,0x9d,0xb2, + 0xf1,0x26,0x9c,0xfc,0x0f,0xae,0x9f,0x8d,0x2d,0xc9,0xcf,0x8f,0x7f,0xf5,0x32,0xbc, + 0xa1,0x2e,0x19,0x2e,0x3e,0x27,0x7e,0x9d,0x8e,0xab,0x0d,0xfa,0xfd,0x63,0xe2,0x37, + 0xb5,0x97,0x68,0x7d,0xac,0xf8,0x03,0x31,0x68,0xe7,0x7f,0x4c,0x90,0x33,0x4a,0xb7, + 0x46,0x7d,0x09,0xf7,0x9d,0x91,0xa6,0xd5,0xae,0x0d,0x55,0x27,0xe5,0x8f,0x23,0xa0, + 0xec,0x90,0xfc,0xd4,0xf5,0x10,0x89,0xd9,0xf6,0x5f,0xd6,0x1f,0x7d,0x0b,0x3c,0xcc, + 0x3f,0xb4,0xd2,0x95,0x74,0xbb,0x20,0x0d,0xf4,0x04,0xc9,0x4a,0x29,0x32,0x4f,0xbd, + 0x4f,0x56,0x19,0xde,0x4b,0xf3,0x51,0x7b,0xcc,0x49,0x1b,0x84,0x9f,0x42,0x4d,0xff, + 0xe7,0xe2,0xc4,0x03,0xf7,0x69,0x2a,0x4e,0x6c,0x40,0x78,0x92,0x7d,0xc8,0xcc,0xd1, + 0xc5,0x2d,0xff,0xa3,0x95,0x5b,0x7f,0xf4,0x3d,0xf0,0xba,0xd0,0xa8,0x7f,0x3e,0xfe, + 0xd5,0x75,0xf2,0x85,0x68,0x03,0x5b,0x0f,0x55,0x61,0x38,0x2a,0xd4,0x51,0xcf,0x6e, + 0x51,0xb1,0xd6,0x4f,0x52,0x78,0x26,0x8d,0x87,0x5f,0x87,0x45,0xfd,0xee,0xb1,0xaa, + 0x4b,0x70,0x59,0x6a,0xc1,0x27,0x8c,0xc1,0x65,0x68,0xa1,0xde,0x01,0x71,0xdc,0x5a, + 0x3f,0xba,0xb2,0x47,0x30,0x57,0x97,0xf2,0x31,0xc3,0x57,0xd7,0x05,0xc5,0x40,0x51, + 0x42,0xab,0x4b,0x14,0xaf,0xef,0x1c,0xad,0x38,0x06,0xec,0xf9,0x7d,0x4e,0xfc,0x63, + 0xbe,0xff,0x25,0x68,0x61,0xcb,0x60,0xeb,0x98,0xab,0x99,0x76,0xc1,0xa7,0xf5,0xe5, + 0x63,0x64,0xc1,0xf6,0x93,0xc9,0x86,0x6d,0xc5,0xdb,0x6c,0xf8,0x27,0x99,0xc2,0x3f, + 0x9c,0x1f,0xe3,0x13,0xb5,0x98,0x4d,0x14,0x05,0xff,0xd0,0xf6,0x20,0x79,0x9c,0x3e, + 0x9a,0xac,0xa1,0x72,0x34,0x92,0xc1,0xff,0x60,0xfe,0x6b,0x83,0x8f,0x47,0xff,0x61, + 0x17,0xdb,0x88,0xd1,0xc2,0xd8,0xa7,0x87,0xc9,0x06,0xf2,0x90,0x5c,0x4e,0xe7,0xc4, + 0x84,0x4c,0xfc,0xd3,0x4b,0xbf,0x83,0x49,0xae,0x95,0xf0,0x21,0xc1,0xb4,0x57,0xe4, + 0x67,0x0f,0x15,0xc5,0x18,0x10,0x0a,0x8a,0x83,0xf4,0x66,0x25,0x48,0x3d,0x90,0x81, + 0x7f,0xf8,0x6e,0x62,0x8c,0xed,0x2f,0x26,0x49,0xbd,0xbe,0xf5,0x5c,0xe7,0xff,0x66, + 0x13,0xd5,0x3c,0x54,0xf2,0x6f,0x9d,0xdf,0x81,0x2b,0x5d,0x2d,0x08,0x15,0x6c,0xf8, + 0xa7,0x7c,0x34,0xfd,0xf5,0x4d,0x6a,0xec,0x0f,0x51,0xc7,0x80,0xfa,0xf3,0x75,0x3e, + 0x3d,0x70,0x9e,0x45,0xcc,0x83,0x84,0xe1,0x07,0x9a,0xc5,0xff,0xdc,0xc0,0x9c,0x06, + 0x9c,0xa2,0x07,0xd6,0x22,0xff,0x13,0xf2,0x44,0x7f,0x22,0xcf,0x3b,0xc1,0x80,0x90, + 0x02,0x4f,0xc1,0x7c,0xea,0x0e,0xe7,0xe1,0x7f,0x78,0xda,0x6b,0x33,0x1b,0xb8,0xf6, + 0x0f,0xb1,0xea,0x64,0xdb,0x5d,0xbe,0xd9,0xf0,0x74,0x64,0x7e,0xcc,0xbd,0x9a,0x8c, + 0x59,0x9f,0x4b,0x9b,0x34,0x28,0xa5,0xf8,0xc6,0x51,0x21,0x45,0xe3,0x6f,0x81,0x9f, + 0xd2,0x80,0xde,0x1d,0x24,0x1e,0x65,0x1f,0xfb,0x4a,0xd9,0x0c,0xd8,0xf8,0x9f,0x82, + 0x14,0xff,0x83,0x68,0x07,0x8d,0x6b,0xd1,0x38,0x89,0xfc,0x4f,0xcc,0xed,0x67,0x57, + 0x16,0x50,0xef,0x70,0x16,0xff,0xd3,0x68,0xc0,0x1e,0x8c,0x3e,0xd7,0xd1,0x6b,0x6e, + 0x83,0xf1,0xab,0xd9,0x15,0x69,0x46,0x12,0x2e,0x65,0xe1,0x1f,0xb0,0x65,0x37,0xfa, + 0x11,0xf6,0x54,0xb4,0x76,0xc1,0x8b,0xb1,0x46,0x0d,0x1e,0x14,0xd7,0xc8,0x3c,0x62, + 0x6e,0xcf,0xc9,0xff,0xf8,0x86,0x09,0xc7,0x3f,0x0f,0x92,0x39,0x91,0xcd,0xba,0x4f, + 0x6b,0xfb,0x1e,0x99,0x03,0x07,0xb5,0x5a,0xcd,0xef,0xe0,0x7f,0xca,0x39,0xff,0xb3, + 0x94,0xa3,0xa3,0xcd,0xa0,0x6a,0xae,0xa8,0x6f,0x17,0xd9,0xcc,0x22,0x3e,0x03,0x4e, + 0x5f,0x83,0x9f,0x87,0xd6,0x69,0xab,0x1f,0x24,0x19,0xf8,0xc7,0x08,0xfa,0xc3,0xb1, + 0x0e,0xbf,0xaa,0xc9,0x75,0x11,0x89,0x19,0xc9,0xe5,0x35,0xa5,0x91,0x32,0x36,0xff, + 0x1e,0x4d,0x2e,0x8d,0x38,0xf1,0x4f,0x0a,0xef,0x25,0xbb,0x12,0x6a,0x1c,0xbc,0x11, + 0x31,0xc6,0x8c,0x46,0x59,0x26,0x62,0x18,0x4e,0xc1,0x6c,0xf0,0x44,0xc4,0xe3,0xa2, + 0xf9,0x3e,0xdb,0x8b,0xd3,0xe3,0x8d,0x5d,0x80,0xd9,0xcb,0xbd,0x0f,0x3d,0xcc,0x0c, + 0x7f,0xf3,0xf2,0x62,0xc3,0xb8,0x67,0xb9,0xfb,0x95,0xe7,0xdf,0x9c,0x66,0xce,0x67, + 0x45,0x41,0xfa,0xfe,0xe8,0x05,0xb5,0x59,0x2b,0xfe,0x15,0x59,0xa3,0xbe,0x56,0xd6, + 0x10,0x2a,0x79,0x58,0xac,0xd6,0x8e,0x2a,0x75,0x0c,0x48,0x74,0xde,0x94,0x03,0xff, + 0x90,0x24,0xed,0x6b,0xaf,0x2d,0x72,0x6f,0x22,0x82,0x42,0xdb,0x77,0x56,0xb4,0x6d, + 0x2a,0x8d,0x95,0xde,0xa7,0xee,0x94,0xe5,0x01,0x92,0xc1,0xff,0x60,0xbe,0x4f,0x21, + 0xbf,0x50,0xd9,0xc0,0x5b,0x8b,0x14,0x72,0x4b,0xec,0xbb,0xea,0x9c,0x90,0xab,0x9d, + 0x94,0xd1,0x8d,0x50,0x15,0x92,0xdb,0xa9,0x8d,0xff,0x29,0xdf,0x65,0xcf,0x1e,0xce, + 0x5d,0xea,0x56,0x4a,0xaf,0x87,0x8d,0xe4,0xab,0x9a,0xdc,0x4e,0x1e,0x81,0x8d,0x4a, + 0xd5,0xd2,0xb6,0xa1,0x88,0x8d,0xff,0x29,0xcf,0xc8,0x5e,0x71,0x7c,0xfb,0x9a,0xda, + 0xa0,0x7d,0x21,0x5a,0x35,0xa7,0xe2,0xe8,0xb2,0xa0,0x16,0xd8,0x26,0xae,0xb5,0xfc, + 0xcf,0x6e,0x21,0x83,0xff,0xd9,0xca,0xf1,0x21,0x34,0x85,0xcc,0x2b,0xa1,0x05,0xd1, + 0xce,0x74,0xfc,0xf5,0xa7,0xf3,0x5f,0x49,0x48,0x30,0x63,0x56,0xb7,0xa8,0x76,0x8c, + 0x40,0x03,0x02,0xa1,0x1d,0x90,0x08,0x35,0x83,0x67,0x99,0xe8,0xca,0xc6,0x3f,0x0c, + 0xed,0xc0,0x7d,0xa4,0x96,0xba,0x76,0x21,0xff,0x23,0x71,0xfe,0xc7,0x0f,0x27,0x85, + 0x5a,0x06,0x84,0x5c,0xae,0x34,0xfe,0x31,0xf7,0x5f,0x18,0x9d,0x3b,0xf1,0x7b,0x59, + 0x5c,0x58,0x0c,0x8f,0x53,0xff,0x18,0xfb,0x82,0x1e,0xc0,0x2b,0x63,0xfe,0x26,0xe2, + 0xb2,0xfc,0x8f,0x85,0x7f,0xd6,0x93,0xe3,0xf4,0x11,0x98,0x3f,0xea,0x0a,0xb2,0x65, + 0xb3,0x49,0x9e,0x37,0x24,0x87,0xc9,0xb5,0xf0,0x88,0xf4,0xf5,0x48,0xd1,0xfa,0x88, + 0xdf,0x7a,0x3e,0xe2,0x1f,0x04,0x39,0xc5,0x0c,0xed,0x44,0x7e,0xc9,0xd0,0x88,0xbc, + 0x56,0x9c,0x4d,0x7e,0x4c,0x97,0x24,0x6b,0xc7,0xc5,0x43,0x0c,0x7a,0xb4,0x24,0x3d, + 0x27,0xc4,0x9a,0x34,0xff,0x73,0xad,0x81,0x7f,0xdc,0x71,0xf1,0xbd,0x18,0xdb,0xbd, + 0x9e,0xf4,0xc6,0xdc,0xc3,0x70,0x17,0xec,0xb3,0xe2,0x3b,0xc5,0xfd,0x42,0xa9,0x39, + 0x3f,0x88,0x7f,0x9e,0x43,0x90,0xd3,0x27,0x5e,0x51,0x5f,0x46,0xe3,0xa0,0xf8,0xd7, + 0xd2,0x4b,0x91,0x7a,0x75,0xeb,0xf8,0xb4,0x17,0xe0,0x45,0x1a,0x4c,0xae,0x1c,0x11, + 0x75,0x27,0xff,0xc3,0xf6,0x5f,0x25,0x77,0x95,0x5e,0xa1,0xff,0x82,0x8e,0x77,0x43, + 0x61,0xe9,0xab,0x1b,0x63,0x95,0xeb,0xae,0xb9,0x8d,0xed,0xa7,0x36,0xed,0xae,0x1c, + 0x95,0x6f,0x0f,0xd9,0xf2,0x5f,0x26,0xfe,0xc1,0x6d,0x1a,0xf2,0x5d,0xee,0x3a,0xe6, + 0xa8,0x23,0x7e,0x55,0x66,0x78,0x69,0x0c,0x1e,0x08,0x56,0xe9,0xf2,0x5a,0x9a,0x89, + 0x7f,0x02,0xc6,0xee,0xf5,0x61,0xa1,0x56,0xe7,0x1b,0x8d,0x08,0xdd,0xb9,0x94,0xc5, + 0xaf,0x41,0x09,0xf5,0x1b,0xb2,0x3f,0x13,0xff,0x00,0x57,0x53,0x5c,0x82,0x17,0xd1, + 0xf1,0x06,0xc5,0x75,0xd2,0x8b,0x50,0xd7,0xef,0x8d,0xce,0x18,0x85,0xa3,0x5a,0x9d, + 0x16,0xe8,0x13,0xd3,0xef,0x63,0xc3,0x3f,0xa3,0xf0,0xa1,0xd0,0xdc,0xbf,0x8a,0x19, + 0x84,0xc1,0x00,0xcc,0x18,0x8e,0x4a,0x13,0xb8,0x54,0x10,0xff,0x98,0xcf,0x37,0xf1, + 0x4f,0x8a,0xff,0xa9,0xd7,0x4b,0xce,0x88,0xcf,0x46,0xde,0x82,0xfa,0x64,0xc9,0x07, + 0xe2,0x62,0x18,0xac,0xa8,0x6f,0xf7,0xb4,0xdb,0xf8,0x9f,0x0e,0x33,0xff,0x65,0xa0, + 0x97,0xab,0xf4,0xb6,0xdd,0x24,0x00,0x3d,0xaa,0x6f,0x58,0xc6,0x40,0xcc,0xde,0x1f, + 0xd8,0x46,0x40,0x75,0xe0,0x1f,0xdb,0xfd,0x84,0x85,0x69,0xd7,0x6e,0xe6,0x91,0x7c, + 0x14,0x89,0x6b,0x66,0xd4,0xe8,0xae,0x58,0x26,0xff,0x73,0x3d,0xc6,0xbb,0xc8,0x20, + 0xdb,0xe6,0x57,0x33,0xb7,0x7c,0x9f,0x0c,0x1d,0x3e,0xf5,0x57,0x32,0xb8,0x02,0x6a, + 0x27,0xec,0x4e,0xb8,0x54,0x1b,0xff,0xc3,0xf3,0x5f,0xc6,0x78,0x2f,0xc5,0x26,0xa0, + 0x7e,0xa0,0x64,0x9f,0xfb,0x1f,0xf5,0x77,0xcb,0xea,0xb6,0x97,0xc4,0x45,0x95,0x32, + 0x47,0xa4,0xb3,0x8d,0x2a,0x4d,0xe7,0xbf,0xae,0x66,0xf8,0x27,0xcc,0xc7,0x8b,0x1b, + 0x73,0x44,0x3b,0xc2,0x65,0x98,0x08,0x3e,0x7b,0x82,0xcf,0xc0,0xc7,0xda,0xa2,0x21, + 0x16,0xbf,0x9c,0xf9,0xaf,0xb7,0x0c,0x91,0xcf,0xb3,0x30,0x19,0xac,0x4f,0x78,0x12, + 0xe2,0x28,0x4d,0xd0,0xd9,0xbf,0xf7,0xda,0xf0,0xb3,0x2d,0xff,0x55,0xc1,0xf0,0x8f, + 0x8a,0x22,0x9f,0xdb,0x6b,0xe1,0xb9,0x3b,0x3f,0x7d,0x4a,0xee,0x0e,0xfd,0xab,0xde, + 0x43,0x6b,0x13,0xee,0x9c,0xfc,0x0f,0xe2,0x9f,0xc7,0xe5,0xea,0x14,0xdf,0xa5,0xaa, + 0x47,0x64,0x28,0x1d,0xac,0x8e,0x11,0x1e,0xf1,0xad,0xfd,0x85,0x23,0xff,0xc5,0x40, + 0xe6,0x5c,0x9d,0xd3,0x6e,0xbd,0x92,0x5f,0xf7,0x77,0x91,0xd1,0xb2,0x9f,0xa6,0x67, + 0x38,0xc5,0xff,0x58,0xeb,0x53,0xda,0x03,0xbf,0x63,0xb0,0xc4,0x1b,0x24,0xb8,0x90, + 0x7c,0x3a,0xdb,0x76,0x8d,0x62,0x62,0x42,0xb7,0xef,0x17,0x6c,0xf9,0x2f,0x9e,0x0f, + 0x3d,0xcc,0xd7,0x83,0xcc,0x03,0xfd,0x30,0x9b,0x96,0x37,0x8e,0x19,0x2b,0x44,0x4a, + 0x2d,0x95,0x71,0xcd,0xbc,0x9f,0xe1,0x1f,0x40,0xd9,0xcf,0xd6,0x7d,0xfc,0x69,0x75, + 0xfa,0xca,0x6d,0x30,0xea,0x49,0x68,0xb3,0xfb,0xed,0xcf,0xcf,0xc8,0x7f,0xc9,0x35, + 0xba,0x7b,0x3f,0x7b,0xff,0xe7,0xa4,0x2a,0xdd,0x1f,0x0b,0x5d,0xe2,0x40,0xda,0xfe, + 0xfe,0xb6,0xfc,0x97,0x89,0x7f,0xae,0x27,0x83,0x4a,0x3d,0xa8,0xfa,0x72,0x95,0xdd, + 0x46,0xc1,0x39,0x3f,0x19,0xf8,0x27,0xca,0xf1,0x00,0x6e,0xac,0x76,0x8c,0xba,0x37, + 0x84,0x4e,0x6b,0x5d,0xdd,0x5c,0xff,0x63,0xf1,0x21,0x19,0xfc,0x4f,0x8c,0xe3,0x9f, + 0xc1,0xe8,0x87,0x50,0x97,0x2c,0xa9,0xfc,0xea,0x71,0xfd,0xf9,0x78,0xd3,0x08,0x5e, + 0x81,0x0f,0xb3,0xf4,0x3f,0x88,0x7f,0x84,0x25,0xba,0xfb,0x1b,0xb8,0x7e,0xe4,0x96, + 0x13,0x2b,0x3f,0x10,0x2f,0x1b,0xdf,0xd7,0x58,0x3e,0xfe,0x67,0x82,0xd6,0xf1,0xcf, + 0x96,0x2d,0xbc,0xba,0xa1,0x4d,0xdb,0xd4,0xf7,0x18,0xca,0x61,0x33,0x66,0xdf,0xbf, + 0x38,0xf0,0xcf,0x73,0x80,0x22,0x81,0xd2,0x59,0xd0,0xeb,0xaf,0x4c,0xc8,0xff,0xd3, + 0x37,0x48,0xbb,0x54,0xee,0x51,0x6d,0xfc,0x8f,0xf9,0x7c,0x9d,0x05,0xd8,0x9f,0xd0, + 0xca,0xe4,0x8a,0x0d,0xa5,0x3f,0x14,0x0e,0xd0,0xca,0x61,0xd7,0xea,0x9d,0xa7,0xdb, + 0x37,0x75,0x59,0x19,0x31,0x34,0x42,0x8e,0xfc,0x17,0xc3,0x3f,0x31,0xe4,0xf3,0x91, + 0x5f,0x55,0xfb,0xdb,0x1a,0xd0,0xb1,0x0b,0x1e,0xc7,0x7c,0xda,0xf3,0x5f,0x23,0xf0, + 0x0e,0x03,0xb1,0x5e,0xd5,0x8b,0x40,0xa8,0xae,0x63,0xf6,0x2e,0x11,0x15,0x41,0xd7, + 0x98,0x88,0xe8,0x6e,0x34,0xec,0xf8,0x87,0xc5,0x23,0x0d,0xe3,0x51,0x01,0xe6,0x83, + 0x2e,0x41,0x49,0x97,0xa8,0xbb,0xc6,0x6f,0x6a,0x4e,0x23,0xa2,0x2c,0xfe,0xe7,0x6d, + 0x16,0xe6,0xa6,0x7d,0x9f,0x85,0xc5,0x0f,0x18,0xfe,0x59,0xf9,0xd8,0x8c,0x35,0xd2, + 0x51,0x32,0xdb,0xce,0x0f,0x38,0xf1,0x8f,0xcc,0xe3,0xef,0xf6,0xdb,0xab,0x39,0xed, + 0xe3,0xaa,0x63,0x6e,0xe4,0xa7,0x61,0x2e,0x04,0xca,0xc5,0xff,0x48,0x16,0xff,0xb3, + 0x86,0xdf,0xef,0x8f,0xfa,0xd6,0x40,0x0f,0x0d,0x20,0xfe,0xb1,0xe9,0x7f,0xcc,0x7f, + 0x36,0xfc,0x23,0x61,0xb6,0x6b,0xb9,0x1c,0x2d,0x94,0x62,0x3b,0xd8,0x95,0x22,0x1b, + 0x1f,0x72,0xc4,0xba,0x7f,0xb1,0x1c,0x86,0x8b,0x5c,0xdd,0x54,0x15,0x96,0xfa,0xd4, + 0xb8,0xbc,0x92,0x8a,0x61,0x9a,0x30,0xf4,0x27,0x6c,0xbc,0x85,0x7c,0xbc,0xc7,0x89, + 0x85,0x7f,0xae,0xdd,0x85,0xb2,0x1f,0x6d,0x55,0x74,0xc6,0x30,0xd7,0xff,0x18,0x40, + 0x48,0x32,0x8c,0x1c,0xfc,0xcf,0xf4,0x61,0xe1,0xb2,0xa1,0x17,0xaa,0x86,0x0b,0x0b, + 0x67,0x33,0xfc,0x26,0xfc,0x5e,0xba,0x20,0x34,0x6a,0x79,0xf8,0x9f,0x0a,0xc4,0x3f, + 0x8d,0x0c,0xff,0xb8,0xc3,0xb0,0x38,0x58,0x5b,0x2a,0x53,0x72,0x46,0xef,0x43,0xb7, + 0x9c,0x93,0xff,0xe1,0xf8,0x07,0xf9,0xae,0x20,0x59,0x06,0x7b,0xd5,0x75,0x2b,0x67, + 0x2a,0xa5,0x03,0xd1,0x83,0x10,0x58,0x2e,0xdb,0xc7,0x6b,0xcf,0x7f,0xb1,0x8f,0xb4, + 0x86,0xcf,0x27,0xe6,0x1f,0xb5,0x22,0x06,0x44,0xe1,0xa0,0xef,0x0b,0x9a,0x2b,0x3d, + 0x9f,0xa5,0x2f,0x38,0xf2,0x5f,0x07,0x0d,0xfd,0x0f,0x7b,0x7f,0xd2,0xbc,0xf4,0x1f, + 0xf0,0xb5,0x3f,0xf8,0x5a,0xf3,0x52,0xfe,0xfe,0x37,0x40,0x86,0xfe,0xe7,0x49,0x65, + 0x97,0x4d,0xf6,0x43,0xac,0xfc,0x57,0x9d,0x83,0xff,0x79,0x87,0x9a,0xcf,0x37,0xf0, + 0x4f,0x9d,0xc1,0xbf,0xa1,0xd1,0xd6,0xd1,0x99,0x54,0x4e,0x68,0xcd,0x4e,0xfe,0xc7, + 0x91,0xff,0x3a,0x8b,0x22,0x9f,0xdf,0x87,0xfc,0xd2,0x21,0xa1,0x81,0xca,0x7b,0xc8, + 0x88,0x7c,0x1f,0xd4,0x76,0x20,0xff,0xe3,0x49,0x41,0xa3,0x84,0x62,0xfa,0x07,0xcc, + 0x7f,0xed,0x88,0xa9,0xfa,0x4c,0x70,0xe1,0xc6,0x7c,0x2e,0x03,0x42,0x85,0x2c,0x70, + 0x33,0x37,0xe5,0xe0,0x7f,0x54,0x7b,0xfe,0xeb,0x29,0x9d,0x7d,0xbf,0xed,0x84,0x01, + 0x21,0x5a,0x8d,0xb4,0xcf,0x69,0x0e,0x0c,0x8a,0xd6,0x17,0x5a,0xdf,0xaf,0x33,0xff, + 0x75,0x89,0xee,0x4d,0x7a,0xdb,0xc4,0xd9,0x0c,0x78,0x7c,0xe6,0xdc,0xe7,0x37,0x54, + 0x4d,0x4a,0xff,0x8c,0xb0,0xc7,0xc6,0xff,0x38,0xf3,0x5f,0x3c,0x89,0xa3,0xa0,0xf7, + 0x58,0xd3,0x3c,0xe4,0xda,0xdf,0x39,0xaa,0x5e,0x5c,0xdb,0xfc,0xcf,0x0e,0xfe,0xc7, + 0xf2,0x3f,0x5a,0xc1,0x15,0xed,0x23,0x8c,0x5f,0x4f,0x88,0x77,0x6b,0x93,0x83,0x75, + 0xc3,0x9e,0x27,0xd8,0xf8,0x5f,0xa6,0xf5,0x63,0xd3,0xc6,0xc5,0xb3,0x30,0x11,0x6d, + 0x4e,0x7a,0x2f,0x64,0xe4,0xbf,0xf6,0xa1,0x48,0xe9,0xff,0x16,0x4f,0xd3,0xe7,0x40, + 0x4d,0xba,0xfe,0x9a,0x9c,0xd6,0xb7,0xd2,0x79,0x23,0xec,0xb5,0x4f,0x1b,0x5b,0x4b, + 0x3b,0xff,0x43,0xe1,0x31,0xa9,0x01,0xfd,0x55,0x88,0xa0,0xf0,0x49,0xd5,0xe5,0x10, + 0x39,0xa5,0xfc,0xa3,0xa7,0x12,0x89,0xa0,0x53,0x0a,0x8e,0x77,0xc5,0xfa,0x50,0xd2, + 0xf2,0x3f,0x61,0x86,0x7f,0xf6,0xb1,0xdb,0xdc,0xc0,0x60,0xd2,0x61,0x08,0xeb,0xae, + 0x22,0x36,0x9f,0x3b,0xfb,0xd7,0x72,0xff,0xa3,0xa4,0xe6,0x33,0x9d,0xff,0xf2,0x33, + 0xfc,0x13,0x67,0x61,0xcb,0x0b,0xcc,0x7f,0x72,0xda,0x67,0x1b,0x73,0xb3,0x4f,0x3e, + 0x5c,0xe5,0x88,0x5f,0xc7,0x1c,0xf8,0xe7,0x22,0x5e,0xec,0x9a,0x81,0xbf,0x5e,0xd1, + 0x57,0x6d,0x7b,0x78,0x94,0xbc,0x66,0xe7,0x7f,0xae,0xcb,0xc4,0x3f,0x97,0xb4,0x7a, + 0xdd,0x3b,0x88,0x7a,0x06,0xb2,0xb0,0xdf,0x93,0x14,0x07,0xe5,0x53,0xb0,0x28,0xed, + 0xcf,0x57,0x21,0xff,0x63,0xe5,0xbf,0x18,0xfe,0x39,0x84,0xf9,0x97,0x2d,0xbe,0x00, + 0xa7,0x7d,0xe4,0x1f,0x95,0x8e,0x42,0x77,0xdb,0x1d,0xce,0xf8,0xeb,0xc8,0x7f,0x7d, + 0x1f,0xef,0xa7,0x91,0x3d,0xc6,0xfd,0xdb,0xd8,0x6d,0xdf,0x2f,0xab,0x71,0xdc,0x6f, + 0xe3,0x7f,0xc0,0x03,0xfb,0xc2,0x6c,0x7e,0x08,0xf1,0x50,0xe6,0x9f,0x07,0xe5,0x52, + 0x32,0xa8,0x76,0xc8,0x5c,0x0f,0xcc,0x10,0x91,0x6a,0xe0,0x81,0x02,0x73,0x3d,0x80, + 0xbc,0xae,0xe8,0xe4,0xda,0x3a,0x44,0x77,0x7b,0xba,0x26,0xa1,0xf7,0xd8,0x96,0x48, + 0xe7,0xa5,0xb6,0x13,0xed,0xf5,0x27,0x71,0xbc,0x74,0xc2,0x6f,0xc4,0x77,0x07,0xff, + 0x73,0x51,0x65,0x41,0x6a,0xa9,0x38,0xaa,0x4d,0x92,0x96,0xc4,0x02,0x9d,0x0d,0x73, + 0x5c,0x68,0xc6,0xb4,0xd7,0x25,0x0d,0x15,0x1d,0xc8,0xff,0x48,0x69,0xbc,0x71,0x05, + 0x26,0xba,0x38,0xc8,0x39,0x2b,0xbd,0x51,0x59,0x3f,0xc8,0x56,0xcb,0x1b,0x65,0xbf, + 0xeb,0xa8,0xfb,0x45,0xe0,0x23,0xb1,0x09,0x5e,0x4e,0xe1,0x9f,0x34,0x3e,0xb1,0xf1, + 0x3f,0xf0,0x3f,0xa2,0x9f,0x7e,0xc9,0xbd,0x8f,0x8c,0xd2,0x9e,0x6a,0x5f,0x87,0xeb, + 0x63,0xd2,0x14,0xe3,0x40,0x25,0x3b,0xff,0x95,0x8a,0xe6,0x0f,0x83,0x3f,0xd1,0x1a, + 0xf4,0xb1,0xfd,0xb8,0xac,0x76,0xcb,0x75,0xc4,0xd3,0xf5,0xb8,0x89,0x7f,0xcc,0xbf, + 0xaf,0x8d,0xff,0x19,0x55,0x7e,0x8a,0x69,0xc4,0x78,0x68,0x54,0xe9,0x81,0x18,0xca, + 0x84,0x02,0xf0,0x53,0xc8,0xc8,0x7f,0xe9,0xe5,0xa3,0x8a,0x85,0x87,0x5f,0x97,0x1a, + 0x91,0xf6,0x19,0x85,0x33,0xd1,0x73,0x9a,0x27,0x2e,0x06,0x0c,0xe9,0x0e,0xea,0x9f, + 0xd3,0xfb,0x97,0x67,0xe4,0xe7,0xd2,0x78,0x78,0x01,0xfe,0xf5,0x2f,0xc1,0x65,0xda, + 0xa2,0xda,0xe3,0xbb,0x3d,0xff,0xb5,0x47,0xb6,0xf8,0xc6,0x5f,0x33,0x58,0xb5,0x05, + 0x8d,0xa3,0x72,0x03,0x61,0xcf,0xf7,0x68,0x2f,0x42,0xf3,0x60,0x49,0x3c,0x07,0xff, + 0x53,0x14,0x67,0x0b,0x75,0x2b,0x4f,0x7b,0xb1,0xff,0x67,0xb3,0xea,0x6b,0xab,0x18, + 0xeb,0xfc,0xdf,0xf2,0x8b,0xe8,0x58,0xe2,0xb9,0xf9,0x9f,0x2d,0x5c,0x26,0x27,0x23, + 0x90,0xeb,0x80,0xea,0x76,0xb9,0x29,0xf2,0x80,0x8f,0x5d,0x19,0x72,0xd9,0xf1,0xcf, + 0x78,0x2a,0xff,0x85,0xd9,0x1f,0xfa,0x08,0x9d,0x3f,0x22,0x6f,0x28,0x7c,0x96,0x6e, + 0x8d,0xdc,0xe6,0x97,0x11,0x0f,0x6c,0x8a,0xcd,0x1f,0x81,0x0c,0xfc,0x23,0x7d,0x48, + 0xbf,0xd3,0xef,0x5d,0x22,0xfe,0x8c,0xbd,0xff,0x1d,0x49,0xf9,0xb0,0xf8,0x00,0x7d, + 0x9e,0x36,0x04,0xda,0xe3,0x78,0x85,0xf9,0x87,0x12,0x07,0xfe,0xf9,0x7b,0x83,0xff, + 0xb9,0x1f,0x67,0xe3,0x7d,0xf9,0xee,0x17,0xd8,0x6c,0x7c,0x27,0x34,0xa9,0xb4,0x2c, + 0x65,0xc6,0xdd,0x39,0xf0,0x8f,0x60,0xdb,0x8f,0x30,0x98,0xc4,0x69,0x6a,0xf1,0x45, + 0xa9,0x4e,0x5f,0xb5,0xbf,0x73,0xbe,0xce,0xa5,0xd1,0x7d,0x6e,0x57,0x3a,0xff,0xf5, + 0xa0,0xa9,0xff,0x41,0xb4,0xe3,0x9f,0x3f,0xc0,0x69,0xf3,0x8d,0xd0,0x41,0x19,0x02, + 0x9c,0xed,0xdb,0x64,0xfc,0xb4,0xcf,0x91,0xff,0x32,0x40,0x0e,0xe7,0xbb,0x02,0x23, + 0xae,0x0d,0xe4,0x0a,0x7c,0x37,0x52,0x19,0x9b,0x79,0x17,0xf9,0x21,0x45,0x05,0xd4, + 0x8a,0x0d,0x21,0xc8,0xd6,0xff,0xb0,0xf5,0x26,0xf7,0x9a,0x34,0xfe,0xa3,0x82,0x3a, + 0xe0,0x0e,0xba,0xb6,0x30,0x20,0xca,0x7f,0x7a,0xc8,0xaa,0x17,0x48,0x96,0x67,0xf0, + 0x3f,0x5e,0x83,0xff,0xe9,0xdd,0xc1,0x8c,0xdd,0x86,0x34,0x3a,0x26,0x2e,0x96,0xac, + 0xf9,0x84,0xa4,0x60,0xea,0x51,0x53,0xd1,0x67,0xc6,0x19,0x69,0xc4,0x7e,0x65,0x6b, + 0x76,0xfe,0x8b,0x27,0x41,0x0c,0x83,0x85,0x45,0x54,0x44,0xf7,0x69,0x7b,0x50,0x08, + 0x7d,0x54,0xd9,0xa7,0x95,0x64,0xe0,0x1f,0x9e,0x2f,0x4b,0xf1,0x0f,0x77,0x20,0xec, + 0xa9,0x76,0x15,0xa1,0xfe,0x27,0x3a,0x63,0x0d,0x6c,0xa6,0x3c,0x23,0xe6,0xcc,0x7f, + 0x3d,0x9a,0xc6,0x3f,0x01,0x54,0xa7,0x74,0xa9,0x9b,0x29,0x97,0xa9,0x48,0xb0,0x59, + 0x08,0x63,0xe0,0x76,0xf2,0x3f,0x3b,0x52,0x6a,0x67,0x04,0x06,0xcb,0x8b,0xf0,0xb6, + 0x0e,0x5a,0xbd,0x42,0x2e,0x3d,0xb2,0x2c,0xd6,0x09,0x19,0xfa,0x1f,0xe4,0x7f,0xb6, + 0xf3,0xd1,0xb1,0xff,0xd1,0x71,0xb5,0x56,0x66,0x61,0x37,0x06,0xba,0xd8,0x28,0xcb, + 0x11,0x11,0x22,0x6d,0x2c,0x22,0x97,0x60,0xfe,0xcb,0x7c,0x9f,0x13,0xd7,0xda,0xf9, + 0x1f,0x84,0x3d,0x0f,0x75,0xbe,0x1a,0xbb,0x5c,0xb3,0x88,0x19,0x8f,0x23,0xff,0x33, + 0x7b,0xf9,0x34,0xa5,0x35,0x37,0xff,0x03,0x47,0x3d,0x35,0xa1,0x92,0x07,0x99,0xf1, + 0x22,0xdb,0xf6,0x7a,0xbe,0x27,0xee,0xa2,0x2f,0x91,0x16,0x84,0x46,0x2f,0x94,0x9a, + 0xdf,0xfb,0x06,0x8b,0xff,0x61,0xaf,0xd1,0x0d,0xbe,0x0a,0x86,0x7f,0xf4,0x0e,0x0a, + 0x3e,0xb9,0x7b,0x93,0x6b,0x21,0xed,0x66,0x6f,0xe8,0xd0,0x3f,0x1b,0xfc,0x8f,0x31, + 0xde,0x9d,0x1d,0xe0,0x0f,0xb9,0x4a,0xc9,0xab,0xfe,0x8d,0x52,0xe5,0xcd,0x72,0x3b, + 0x29,0x47,0xc7,0x1b,0x72,0xe6,0xbf,0xd2,0xfc,0x4f,0x17,0xe7,0xd3,0xe4,0x68,0x68, + 0x80,0xdc,0xaf,0x54,0x69,0xf2,0x10,0xb9,0x9e,0x5d,0xe1,0x54,0xdb,0x9b,0xb9,0xf9, + 0x9f,0xa3,0x04,0x65,0x3c,0x22,0x12,0x71,0xfb,0xda,0x02,0xd1,0x19,0xbb,0x08,0x4a, + 0xdf,0xa7,0xd9,0xf1,0xcf,0x88,0x50,0x9d,0xbe,0xff,0x1b,0x02,0x02,0x45,0x71,0x98, + 0xf0,0x8c,0xa1,0x22,0x0e,0x4c,0x37,0x7e,0xaa,0xba,0x98,0x83,0xff,0xf9,0x22,0xa2, + 0x9d,0x06,0xb8,0x9f,0xb6,0x8e,0xc1,0x29,0xa8,0x57,0x3c,0xba,0x38,0x56,0xc1,0x80, + 0x68,0x61,0xee,0xfc,0x17,0xf2,0x3f,0x87,0xb8,0xec,0xa7,0x74,0x84,0xeb,0x7f,0x3e, + 0xbf,0x33,0x34,0xa2,0x3d,0x00,0x0b,0xe2,0xee,0xa4,0x3d,0xff,0x95,0xf6,0x3f,0xf8, + 0xe1,0x54,0xf7,0x73,0x22,0xe8,0xb0,0x54,0xf3,0x4a,0x22,0xe8,0xdb,0xcc,0x19,0xa1, + 0x99,0x6a,0xae,0xfc,0x17,0xfb,0x6c,0xe9,0x22,0x98,0x93,0x68,0xfb,0x46,0xe9,0x10, + 0xec,0x12,0xe6,0x41,0x91,0x56,0xf8,0x2a,0x2a,0x82,0xc0,0x1d,0xb6,0xe7,0xbf,0xba, + 0x67,0x9b,0x20,0xe7,0x0d,0xb5,0x97,0x2e,0x4a,0x16,0x7f,0xbb,0xea,0x24,0x9c,0xa7, + 0x4b,0x10,0xff,0x5c,0x24,0xcb,0xf0,0xa7,0xb5,0xe2,0x3b,0xaa,0x95,0xff,0xba,0xd6, + 0xd2,0xff,0xbc,0x47,0xd9,0xc6,0xf3,0xc4,0xaa,0x7d,0xe2,0xb0,0xfc,0x3a,0x3c,0x8d, + 0xdf,0xd7,0xef,0x83,0xe3,0x86,0x14,0xff,0x48,0x97,0x39,0x3f,0xb0,0xf1,0x8a,0x92, + 0xda,0xa4,0xb3,0xdd,0x7a,0x67,0xfd,0x47,0x2c,0x7e,0x9d,0x85,0x17,0x69,0xdd,0x8f, + 0x3c,0x27,0x30,0xe3,0x83,0x8e,0x7d,0xad,0x08,0xd4,0x91,0xff,0x8a,0xb1,0xf7,0x0f, + 0xc2,0x29,0xed,0x2d,0x68,0x1a,0x91,0x83,0xa5,0xbf,0x7d,0xa5,0x6b,0xd7,0xbc,0xb5, + 0x25,0x49,0x17,0xf0,0xf1,0xb2,0xf7,0xaf,0x59,0x66,0x3d,0x1f,0xf9,0x9f,0xf4,0xee, + 0x4c,0xd5,0x5d,0xeb,0xaf,0x3a,0xf1,0x50,0x97,0xfa,0x75,0xca,0x11,0x60,0x97,0x31, + 0x5e,0xc8,0xe4,0x7f,0x52,0xf3,0x29,0x05,0xfa,0x2b,0x82,0xec,0x43,0xee,0x24,0x81, + 0x76,0x97,0x5a,0xaa,0x1a,0x1b,0x5b,0x95,0xc8,0x36,0xfe,0x27,0x60,0xf1,0x1b,0xcc, + 0xb8,0x53,0x3f,0x3e,0x26,0x0e,0x17,0xbe,0x48,0x9b,0xb5,0xad,0x31,0x51,0x25,0x09, + 0x43,0xcf,0x53,0x93,0x2b,0xff,0x35,0xca,0xa2,0xdb,0x5d,0x7a,0x09,0xe6,0xbf,0x46, + 0x94,0xd5,0x11,0xef,0x36,0x71,0x54,0xe1,0x5b,0xb3,0x58,0x8e,0xfc,0x57,0x6a,0xbf, + 0x7f,0x03,0x73,0xec,0x33,0x30,0xd1,0x57,0xa5,0xed,0x49,0xce,0x58,0x0f,0xef,0xd3, + 0x5e,0x94,0x46,0x3b,0xf2,0x5f,0xa9,0xf8,0x65,0xa0,0x97,0x7e,0x16,0xad,0x9a,0x94, + 0x4d,0xf0,0x78,0x57,0xc5,0x90,0xab,0x29,0xd4,0xa3,0xf9,0x80,0x2d,0xad,0x64,0x2e, + 0xfe,0xc7,0x08,0xdc,0x6c,0xfd,0xac,0xd1,0x7a,0xa4,0xe5,0xcc,0xd3,0x90,0x6a,0x39, + 0x16,0xf6,0xc1,0xcc,0x58,0x66,0xfe,0x2b,0x68,0xf0,0x8d,0x5a,0x3d,0x04,0x8e,0xb0, + 0xf9,0x91,0x0b,0xba,0x55,0x75,0x80,0x39,0x6a,0x59,0xa3,0x08,0x1d,0x55,0xdb,0xfe, + 0x0b,0x3c,0x29,0xfd,0xcf,0x5e,0xf1,0xe7,0x6c,0xe0,0x4b,0x4e,0x15,0x9f,0x17,0x6f, + 0xeb,0xd6,0x2b,0x16,0x5f,0x23,0x53,0x71,0x19,0xbc,0xab,0xd4,0x95,0xb1,0x89,0xd2, + 0x2d,0xff,0x13,0x2b,0x66,0xf1,0x4b,0x69,0xd1,0x8b,0xcf,0xf1,0x68,0xce,0xfe,0x8b, + 0xe7,0x22,0x97,0x7e,0x6b,0xcc,0xc0,0x8c,0x71,0x83,0x11,0x4a,0x8a,0x23,0xd3,0xec, + 0xf8,0xe7,0x32,0x5b,0x96,0xde,0x0a,0xf1,0x9b,0xca,0x79,0xda,0xb0,0xcb,0x73,0x4e, + 0x5c,0x47,0x51,0xf6,0x53,0xc2,0xf1,0x33,0x6d,0xce,0xe0,0x7f,0x18,0xfe,0x79,0x9b, + 0x72,0xfd,0x8f,0x0f,0x46,0x3a,0x7c,0xdd,0xf2,0x07,0xad,0x77,0xa3,0x10,0x5a,0xcf, + 0xcf,0xff,0x1c,0x24,0x9c,0xff,0xd1,0x98,0xe3,0x0a,0x74,0xbb,0x82,0x37,0x7b,0xda, + 0x19,0xec,0x79,0x7e,0x66,0x6e,0xfe,0x87,0xe1,0x9f,0x83,0x0a,0xd7,0xff,0xdc,0x06, + 0x7d,0xb4,0x66,0xa7,0x2b,0x4e,0xd6,0x65,0xf1,0x27,0x63,0x8e,0xfc,0xd7,0x87,0xc8, + 0xff,0x6c,0x17,0xc3,0x10,0x8f,0x35,0xc7,0x6b,0x4d,0xd8,0x53,0x62,0xc3,0xcf,0x43, + 0x8e,0xfc,0x17,0x1b,0x9d,0xce,0x9c,0xea,0x5e,0xb6,0x94,0x50,0x06,0x2f,0x9e,0x72, + 0x28,0xc4,0x38,0xff,0x63,0xcf,0x7f,0xc1,0x44,0x8c,0x3f,0xe4,0x71,0x38,0x01,0x88, + 0xaf,0x66,0x04,0x94,0x17,0xed,0x78,0x3b,0x53,0xff,0x23,0xf1,0x97,0x54,0x68,0x2d, + 0xf3,0xcf,0x44,0xef,0x1c,0x23,0x4d,0x24,0x9b,0xff,0x31,0xd7,0x03,0xe2,0x9f,0x07, + 0x31,0xe9,0x39,0x2b,0x42,0x69,0x14,0x5c,0xe0,0x46,0x9a,0x91,0xbb,0x9d,0xbc,0xfc, + 0xcf,0x53,0x5c,0xff,0x1c,0x2a,0x85,0x2d,0xb4,0x32,0xd9,0xb3,0xb8,0xb0,0x64,0xe9, + 0x26,0x43,0xf6,0x73,0x9a,0xe6,0xd4,0xff,0xfc,0xca,0xd0,0xff,0x44,0x60,0x08,0x16, + 0xaf,0xf5,0x06,0x5b,0x4b,0xb4,0xe7,0x29,0xe7,0x7f,0x8e,0xd3,0x0f,0x0d,0xc3,0xc9, + 0xff,0x5c,0x36,0xf4,0xcf,0x43,0xda,0x28,0x2c,0x19,0x58,0x35,0xe6,0xfe,0x39,0x4c, + 0x2a,0xcd,0x53,0xe8,0x7f,0x78,0xfe,0x51,0x11,0x7d,0x32,0x43,0x0b,0xaa,0xa7,0xb7, + 0xf5,0xbd,0xf6,0xd7,0xd9,0x95,0xad,0x71,0xf1,0x38,0x3c,0x4f,0x83,0xc9,0xdc,0xfa, + 0xe7,0xf6,0x4f,0x2b,0xca,0xbd,0xb0,0x40,0x93,0xef,0x64,0xc3,0x44,0xd8,0x23,0xae, + 0x87,0x53,0x64,0x13,0xdb,0x6a,0xf9,0x33,0xf5,0xcf,0x4f,0xd1,0xaf,0x27,0x8b,0x4e, + 0x90,0x5e,0xd4,0x7b,0x87,0x8b,0x18,0x10,0x42,0xe0,0xc7,0xf9,0x9f,0xe9,0x9b,0x72, + 0xeb,0x9f,0xd7,0xe1,0xfe,0x2b,0xa2,0x46,0x92,0x81,0xf0,0xe7,0x38,0xb1,0x6f,0xf2, + 0x8d,0x9d,0x86,0x10,0xe8,0x15,0xc9,0xfc,0x5e,0x4c,0xfd,0x73,0xf1,0xef,0xc5,0x83, + 0xf2,0xf1,0x58,0xcb,0x43,0xc5,0x0c,0xff,0x28,0x27,0x4d,0x20,0x74,0x8c,0x6d,0x16, + 0xb9,0xfe,0xd9,0x9a,0x4f,0xcc,0x7f,0x2d,0x6d,0x66,0xf1,0x57,0x50,0xd9,0x9f,0xa5, + 0x99,0x94,0x18,0xdb,0xf0,0xbb,0x53,0x08,0x21,0xa7,0xfe,0x47,0xc5,0xfa,0xaf,0x19, + 0xc3,0x6c,0xe3,0x3f,0x1b,0x89,0x02,0x09,0xde,0x16,0x1a,0x58,0x98,0x9b,0x91,0x9b, + 0xff,0x81,0x83,0x2a,0x8b,0xbf,0x4a,0x64,0x8e,0xc9,0x36,0xec,0x82,0xcd,0x19,0xf5, + 0x5c,0x39,0xf4,0x3f,0x71,0x62,0x05,0x6e,0x53,0x11,0x9d,0xab,0xfe,0xcb,0xe2,0x7f, + 0xa2,0x6c,0x99,0xa5,0x84,0xd0,0x5d,0xb1,0x0e,0x0b,0x11,0x65,0xd6,0x7f,0x71,0xfd, + 0x8f,0x31,0xa8,0x54,0x20,0x8e,0x88,0x2a,0xc5,0xfc,0x8b,0x9d,0xef,0x3a,0xee,0xd0, + 0xff,0x70,0x3e,0x67,0x4c,0x7c,0x15,0x17,0x12,0xcf,0x7f,0x49,0x17,0x84,0xe6,0xe5, + 0xab,0x0c,0x7e,0x63,0x36,0xe2,0x01,0x1b,0xff,0x23,0x0c,0xb3,0x6d,0x69,0x09,0x03, + 0x39,0xd3,0xf6,0xc3,0x99,0x02,0xa4,0x4d,0x3a,0x39,0x42,0x68,0xe7,0xf5,0x62,0x97, + 0x51,0x1a,0x1d,0xb5,0xe1,0x1f,0xcc,0x7f,0x2d,0x36,0xf0,0x8f,0xca,0x81,0x90,0xe7, + 0xde,0x08,0x37,0x10,0xf6,0xe4,0xa8,0xff,0x62,0xf8,0x47,0x5a,0x68,0x54,0x6f,0x75, + 0xc1,0x0e,0x21,0xb0,0x7c,0xa6,0x42,0x0a,0x14,0x36,0xcc,0x36,0x77,0x6e,0xfe,0x07, + 0xf1,0x4f,0x29,0xd7,0xff,0xec,0xd2,0x0e,0x6a,0x48,0xa3,0xb9,0x72,0xd4,0xd3,0x65, + 0xe1,0x9f,0x92,0x32,0xf2,0xe3,0xae,0xb7,0xa1,0x19,0xd3,0x58,0xd5,0xce,0x0c,0x97, + 0x83,0xff,0xb1,0xf2,0x5f,0xdb,0xc5,0xb9,0xdc,0xf8,0x27,0x25,0x35,0x2d,0xb6,0xfb, + 0xab,0x1c,0xf9,0x2f,0x13,0x6f,0x9f,0x81,0x11,0xad,0x8e,0x45,0xf4,0xf4,0xb4,0xe7, + 0xd1,0xff,0x3c,0x8b,0xf8,0xe7,0x1d,0xf6,0xac,0xfb,0xe0,0x2a,0x5a,0xc2,0x81,0x90, + 0x64,0x21,0xa2,0x4c,0xfd,0x0f,0xe2,0x1f,0x63,0xd3,0x3d,0x48,0x1f,0x07,0xb5,0xbf, + 0x35,0x18,0xb2,0x47,0x70,0x53,0xff,0x63,0xcf,0x7f,0x3d,0xc5,0xf1,0x4f,0xe1,0x2b, + 0x0c,0xe9,0xcf,0x19,0x70,0x7d,0x93,0x03,0x83,0xe2,0x01,0xb7,0x43,0xff,0x63,0x3e, + 0xdf,0xd0,0xff,0xdc,0x98,0x5c,0xb5,0xa1,0xf5,0xa4,0xf2,0x16,0x5d,0x38,0xe2,0xbd, + 0x1b,0x69,0x9f,0x8e,0x6b,0x47,0xbc,0x76,0xfd,0x8f,0xb9,0xdc,0x38,0xfe,0xb9,0x90, + 0x22,0xed,0xd1,0xb1,0x0c,0x79,0x9f,0xee,0x64,0x1e,0x46,0x6a,0x3e,0xe9,0xe0,0x7f, + 0xd2,0xfc,0x3f,0xd7,0x3f,0x73,0xd9,0x4f,0x23,0x4c,0xd2,0xba,0xf3,0x25,0xe3,0xad, + 0xcd,0x58,0xf6,0xe5,0xd4,0xff,0x38,0xf8,0x9f,0x33,0x49,0xf6,0x92,0xff,0xb3,0x90, + 0xaa,0x07,0xe0,0x33,0x23,0xf2,0x7a,0xf1,0x2b,0xd0,0x1b,0x5f,0x87,0xfa,0x1f,0xeb, + 0xfd,0x9d,0xf9,0xaf,0xa7,0xe5,0x79,0xba,0x6b,0x8c,0xac,0xd6,0x9e,0x83,0xaa,0x01, + 0x76,0xdb,0xad,0x14,0x6f,0xab,0x30,0xee,0x67,0x3f,0x65,0xea,0x7f,0xf6,0xa2,0xb7, + 0x69,0xf2,0xf5,0x43,0xaf,0x16,0x48,0xb6,0x05,0xc9,0x4a,0xa1,0x17,0x2b,0xa4,0x6c, + 0xf3,0xe9,0xcc,0x7f,0x7d,0xc8,0xc2,0x4a,0x49,0xac,0xf3,0x76,0x38,0xac,0x54,0x8d, + 0x95,0x8c,0x89,0xeb,0x14,0xdc,0x81,0xca,0x6c,0xbc,0x05,0x13,0x42,0x23,0x06,0x32, + 0x67,0xfe,0xeb,0x6d,0x64,0xe3,0xf7,0xcd,0x88,0x31,0x7c,0xd8,0x30,0xc8,0xbc,0xb7, + 0x7d,0x07,0x6a,0x14,0x82,0x39,0xf9,0x9f,0xcb,0x50,0xdf,0xcf,0xbe,0xc7,0x20,0xf3, + 0xde,0x4b,0xf4,0x82,0xb1,0xaa,0x26,0xb8,0x87,0x05,0x3e,0x4b,0xff,0x53,0x6c,0xe7, + 0x7f,0x30,0xff,0xf5,0x28,0x65,0xf1,0xb7,0x89,0x3c,0xae,0xbe,0xcb,0xf5,0x3f,0x21, + 0xac,0xf0,0x9a,0x9b,0xd2,0xff,0x64,0xd5,0x7f,0x09,0x0c,0xff,0x74,0xf9,0xb0,0x5e, + 0xcc,0xc7,0x65,0x63,0xae,0xb8,0x0b,0x11,0xd1,0x1d,0x53,0xe8,0x7f,0x1e,0x54,0x63, + 0x7a,0x4f,0x3c,0x44,0x71,0x36,0x8e,0xb0,0xd9,0x28,0xde,0xd8,0x5b,0x57,0xfd,0x4a, + 0x91,0x03,0x0f,0x58,0xd3,0x5f,0xbc,0x8e,0xe1,0x01,0x5e,0xc4,0xad,0xb6,0x1d,0x86, + 0x96,0x81,0x92,0xf5,0x62,0x20,0x36,0xe1,0xf9,0xcc,0xd1,0x59,0x0c,0x21,0xe3,0x8e, + 0x1b,0x2b,0x94,0x6d,0xf5,0x5f,0xd7,0x5e,0x82,0x7f,0xc5,0xfc,0x57,0x7b,0xe7,0x58, + 0xf7,0x5b,0xe4,0x7f,0x27,0x8a,0x51,0xc8,0xc1,0x0b,0x09,0xd9,0x78,0xf7,0x4c,0xa6, + 0xf4,0xcf,0x0e,0xfd,0xcf,0x84,0xb1,0x48,0xd8,0xee,0x9e,0x36,0x25,0xff,0x71,0x4c, + 0x6c,0x8a,0x4d,0xd2,0xeb,0x38,0xa2,0xd6,0x26,0x81,0x21,0xf6,0x4c,0xfc,0x73,0x38, + 0x52,0x9b,0xec,0xe9,0x13,0x7f,0xc6,0x06,0xde,0x98,0x94,0x2f,0x91,0x16,0xdc,0x96, + 0x26,0x57,0xf4,0x91,0x61,0x7a,0x50,0xf6,0x1d,0x71,0x65,0xe2,0x1f,0x1c,0x94,0xc8, + 0x47,0x27,0x32,0x3c,0xb9,0x10,0xf5,0x18,0xc0,0x11,0xd1,0xe0,0x74,0xf6,0xe9,0x25, + 0x8a,0x32,0xf1,0x8f,0x0d,0x4f,0xd6,0xe8,0x10,0x0f,0xed,0x61,0xfe,0xbf,0xa6,0xbb, + 0x07,0xfd,0xcf,0x42,0x94,0x76,0x64,0xe2,0x9f,0x54,0xfe,0x74,0x1d,0xd7,0x83,0x79, + 0x90,0x9f,0xf9,0x9d,0x81,0x58,0x86,0xe5,0xf1,0x30,0x4a,0x83,0xa6,0x0d,0xe5,0xd0, + 0xff,0x90,0x4b,0xbc,0xfa,0xef,0x67,0x63,0xe2,0x77,0xe0,0x3d,0xbd,0x3e,0xc9,0xa6, + 0xe5,0x3c,0x5c,0x61,0x0b,0xa3,0x04,0x81,0xa2,0xf9,0x7c,0x23,0xff,0x95,0x46,0x3b, + 0x03,0xec,0xf9,0x83,0xbc,0xac,0x7e,0x15,0x7b,0x3e,0xfa,0x1f,0x3d,0x9b,0xff,0x11, + 0x6c,0x68,0x87,0x45,0xe7,0x4b,0x70,0x90,0xd6,0x50,0xf7,0x77,0xd9,0xfb,0x1f,0xca, + 0xcd,0xff,0x54,0x5b,0xde,0x26,0xe9,0xba,0x01,0x8d,0xb6,0x6a,0x84,0xc1,0x48,0xa5, + 0x06,0x74,0x57,0x56,0xfe,0x2b,0x66,0x65,0x7f,0x16,0x20,0x1f,0x72,0x1a,0x0e,0x3d, + 0x34,0x6f,0x64,0xc5,0x06,0xf2,0x2a,0xec,0xef,0xe0,0x42,0xe8,0xcc,0xfc,0x17,0x4f, + 0x72,0x0d,0xc2,0x87,0xca,0x77,0x46,0x4a,0xea,0xaa,0x18,0xec,0xd9,0x1d,0x1c,0xf5, + 0x56,0x8b,0x83,0xda,0x39,0xf6,0xfe,0x85,0x99,0xf8,0x67,0x92,0xe1,0x67,0x6f,0x7c, + 0x1a,0xc7,0xcf,0x03,0x5f,0x67,0x13,0x1b,0x66,0xd3,0xd2,0xc5,0x10,0x23,0x1b,0xaf, + 0xd2,0x9c,0x1b,0xff,0xa4,0xe6,0xa7,0x49,0x2f,0xd9,0xff,0xfc,0x71,0xfa,0x3c,0xb0, + 0xf8,0x1e,0x53,0xdf,0xc4,0xd4,0x0f,0x4e,0x54,0xae,0xfa,0xaf,0x94,0xb7,0x41,0x19, + 0xa1,0x7a,0x2f,0xf9,0x9a,0xb6,0x62,0x3d,0xe1,0xfb,0xc7,0xcc,0xfc,0x17,0xf2,0x3f, + 0x73,0x70,0xbc,0x5f,0xe1,0x44,0x90,0xeb,0xdb,0x85,0xa7,0xe9,0x26,0x3a,0x2f,0xec, + 0x5e,0x4b,0x3e,0x82,0x8d,0x0c,0x1a,0xb9,0x73,0xd6,0x7f,0xb1,0xf9,0x94,0xd0,0xe8, + 0xc6,0x89,0x8d,0x14,0x04,0x54,0x8c,0x77,0x45,0x9d,0x6a,0x6d,0x66,0xfe,0x6b,0x37, + 0xfb,0xa3,0x34,0x20,0xda,0x59,0xcb,0x81,0x50,0x09,0xc2,0x9e,0x23,0xd0,0x18,0x43, + 0xfc,0x43,0xcf,0xd2,0xe6,0xcc,0xfc,0x97,0x3d,0xfa,0x48,0xcd,0x42,0x4a,0xf6,0xbc, + 0x53,0xc2,0x2b,0x02,0x9b,0x9f,0xdc,0xf9,0x2f,0x33,0xba,0x85,0x8b,0x1e,0xab,0x1f, + 0x56,0x2e,0x40,0x5d,0xd8,0x8a,0x77,0x25,0x51,0x92,0xb3,0xfe,0x0b,0xa3,0x6d,0x20, + 0x2c,0x6f,0xf7,0x0d,0xcb,0x07,0xb5,0x9a,0xb0,0x15,0x7f,0xb3,0xf8,0x1f,0x7b,0x74, + 0x6e,0xe3,0x78,0xe9,0xa0,0xfc,0x37,0xcb,0x7e,0x30,0x94,0xba,0x3f,0x8b,0xff,0x31, + 0x82,0x7e,0x21,0x8f,0xfe,0x4b,0xfd,0xa5,0x74,0x20,0xf6,0x14,0xcc,0xd3,0xd8,0x7e, + 0x76,0x00,0x16,0xfa,0x03,0xd9,0xfc,0xcf,0x88,0x3d,0xda,0xfe,0x8f,0xc8,0xd2,0x18, + 0xc5,0xb2,0xa3,0xad,0x3a,0x5e,0x51,0xb9,0x22,0xf7,0x78,0xa6,0xfe,0xd9,0x1c,0x6f, + 0x0b,0xea,0x5b,0x18,0x22,0x12,0x3e,0xc2,0x2b,0xaf,0xee,0xba,0x6c,0x64,0xc4,0x6c, + 0xf8,0xc7,0xc6,0xff,0x78,0xf0,0x7e,0xd7,0x2b,0x9d,0xe7,0x95,0x7f,0x83,0x7d,0xec, + 0x4a,0xeb,0x30,0x1c,0xf5,0xd7,0x2d,0x2b,0xce,0xd4,0x3f,0x8f,0xa4,0xf4,0x3f,0x1c, + 0xed,0xc8,0x5d,0x21,0xac,0x08,0x63,0xdb,0x52,0x9d,0xe8,0xb1,0x11,0xd5,0x27,0xcb, + 0x59,0xf9,0x2f,0x03,0xe4,0x2c,0x93,0x50,0x08,0x74,0x8d,0x42,0x7e,0x01,0x3f,0x87, + 0x39,0x61,0xb6,0xcc,0x86,0x37,0xef,0xf5,0x07,0xda,0x8a,0x94,0xc2,0x23,0x56,0xfd, + 0x08,0xe2,0x1f,0x07,0x7a,0xac,0x88,0x86,0xd0,0xf8,0x53,0xcd,0x7d,0x82,0x5d,0xd9, + 0xc1,0x66,0x4c,0xce,0x85,0x7f,0xbc,0x28,0xfb,0x41,0xa3,0xd0,0x18,0x78,0xc3,0x52, + 0x43,0xf8,0x0d,0xcf,0x6a,0x7f,0x9f,0x13,0xff,0x98,0xf9,0xaf,0xad,0xc6,0xfd,0x8d, + 0xa9,0x0a,0x32,0x23,0x11,0x96,0x47,0xff,0x83,0x78,0x9b,0x27,0xc2,0x86,0xa0,0x51, + 0x4d,0x29,0x82,0xea,0xf2,0xe8,0x9f,0x91,0xf6,0x39,0x04,0xf3,0xa3,0xf2,0x4e,0xf0, + 0xcb,0xf7,0x19,0x65,0xef,0x23,0x50,0xc3,0x8c,0x15,0x59,0xf8,0xc7,0x8e,0x76,0x8a, + 0x82,0x3e,0x0f,0x44,0x61,0x2d,0xb8,0xa1,0x70,0x50,0xc0,0xc2,0x81,0x2c,0xfc,0x63, + 0xff,0x7e,0xb5,0x4f,0x6f,0x20,0x25,0xf2,0x56,0x98,0x0f,0x2b,0xda,0x7d,0xa7,0xa0, + 0xb7,0xb2,0x32,0x1b,0xff,0xa4,0x40,0x8e,0x81,0x76,0x8a,0x51,0xff,0xfc,0xcf,0xf4, + 0x86,0x98,0xb7,0x4d,0x3c,0x4d,0xff,0x25,0xb6,0xf7,0x1d,0xc4,0x3f,0x76,0xfd,0xcf, + 0x74,0xbb,0x3f,0x59,0x8a,0x32,0x57,0x69,0x02,0x33,0xd4,0x51,0x71,0x54,0x7b,0xb7, + 0xbd,0xf9,0x84,0xdb,0x9e,0xff,0x02,0x29,0x15,0xbf,0x2e,0x88,0x67,0x19,0xec,0xb9, + 0x31,0xe6,0xb9,0x20,0xce,0xd6,0xf4,0xe8,0x5d,0x61,0xef,0x88,0x38,0x29,0x4f,0xea, + 0xf5,0x6f,0x3a,0xf1,0x8f,0xf2,0x18,0x7b,0x8d,0x6f,0x63,0xfd,0xda,0x69,0x84,0x31, + 0xaa,0xbc,0xa1,0xb4,0xa4,0xfb,0xd7,0x3b,0x82,0x61,0xf7,0xb7,0xf0,0x4a,0x5f,0xe5, + 0x48,0x16,0xfe,0xf9,0x09,0x31,0xf4,0x3f,0x38,0x5e,0xda,0xb6,0xde,0x37,0x8b,0x6e, + 0xf4,0x7f,0x7d,0xc8,0x1d,0x26,0xa7,0xf6,0xf6,0xf2,0x54,0x7e,0x96,0xfe,0xd9,0x6f, + 0xcd,0xa7,0xe0,0x0f,0xb2,0x8d,0xc6,0xc3,0xba,0x8a,0x0a,0x87,0xb3,0x3c,0x43,0x94, + 0x85,0x7f,0xde,0x95,0xd2,0xf1,0x85,0x56,0xb0,0xfd,0xbb,0x44,0x3b,0x1a,0xf5,0x55, + 0xfb,0xbf,0x78,0xa5,0x6c,0x52,0xea,0xc5,0x8d,0xa4,0x13,0xff,0xbc,0xcb,0xb7,0xe1, + 0x22,0x87,0x85,0x8a,0x37,0xee,0x1e,0x65,0x1b,0x2b,0x76,0xff,0x33,0x9d,0xa6,0x2b, + 0x16,0x9c,0xf8,0xe7,0x7d,0x6b,0x77,0x2f,0xb5,0xc8,0xf3,0x0f,0x7e,0xf1,0x92,0x7c, + 0xb9,0x3b,0x95,0xff,0xda,0xca,0x10,0x91,0x27,0x03,0xff,0xc8,0x69,0x3d,0x0f,0x09, + 0xa8,0x72,0x1f,0x19,0x15,0x0e,0x22,0xe3,0x81,0x57,0x7e,0x6a,0x08,0xa1,0x73,0xf2, + 0x3f,0x3c,0xde,0x45,0x3f,0x17,0x2f,0x1d,0x85,0x3e,0xf5,0xa6,0x81,0x9e,0x3e,0x7e, + 0x7f,0x8d,0x2e,0xe7,0xd4,0x3f,0xd7,0x91,0x41,0x2c,0x7b,0x07,0xac,0x4f,0xe9,0xda, + 0x1b,0x8c,0x8d,0xe0,0x8c,0x75,0x3c,0xae,0xaa,0x47,0x36,0x67,0xd5,0xbf,0x23,0xff, + 0x63,0xe8,0x4f,0x9a,0x67,0x15,0xef,0x6b,0x7d,0xaf,0xeb,0x60,0x51,0xc3,0x51,0xce, + 0x98,0xbd,0x0f,0x87,0x13,0x9e,0x4c,0xfc,0x33,0xb9,0x98,0x8d,0x77,0x6f,0x2b,0x8f, + 0x5f,0x15,0x25,0x0f,0x8a,0xa3,0xc9,0xcb,0xea,0x73,0x98,0xc8,0x18,0xc5,0xfa,0x77, + 0x94,0x82,0x3b,0xf1,0xcf,0x08,0x03,0x39,0x25,0xe3,0x5f,0xbd,0x02,0x2f,0xd1,0x7a, + 0x8d,0xcd,0xc6,0x6f,0xd8,0x26,0x63,0x61,0x98,0xe1,0xe7,0xd9,0xcc,0xb8,0x31,0xe9, + 0x19,0x71,0xe8,0x9f,0x47,0xe1,0x01,0xae,0xee,0x2e,0x1d,0xe5,0xdd,0x78,0x18,0x30, + 0x1e,0x35,0xcb,0xd2,0x79,0xc5,0x37,0x0a,0xed,0x54,0x9b,0xff,0x19,0x05,0x3f,0x43, + 0x8f,0x2e,0x73,0xf7,0xcd,0xd6,0xc3,0x00,0x1a,0x1a,0x5f,0x18,0x9d,0x10,0xa0,0x19, + 0xfa,0x67,0x0f,0x96,0xbd,0xa0,0xda,0x79,0x50,0xeb,0xec,0x37,0x0c,0xda,0xc3,0x02, + 0xbf,0xfd,0xf9,0x41,0x1b,0xfe,0x39,0xab,0x8d,0x68,0xd7,0x23,0x08,0x39,0x4b,0x5e, + 0xa4,0x0f,0x45,0xf1,0x7b,0x21,0x2f,0xc2,0xbe,0x64,0x20,0xee,0xae,0x65,0x46,0x73, + 0xcc,0x13,0x73,0x3b,0xf5,0xcf,0x17,0x85,0x96,0x21,0x06,0x7a,0xaf,0xe0,0xfc,0x3c, + 0xb4,0xca,0x30,0xf8,0x0a,0x41,0xbc,0xd7,0xb2,0x6b,0x41,0x32,0x83,0xff,0x49,0x18, + 0x4d,0x84,0xf0,0xb1,0x4d,0xd1,0xaf,0xec,0x13,0x03,0xf8,0xd8,0x04,0xd7,0x9f,0xbf, + 0xa8,0x34,0x23,0x3f,0x10,0xb4,0xe1,0x9f,0xf9,0x5a,0x27,0x3c,0x89,0xeb,0xe1,0xbd, + 0x76,0xfe,0xb6,0x97,0x48,0x40,0xe8,0xe9,0xae,0x1d,0x2a,0xde,0x4f,0xde,0x54,0x5f, + 0x6f,0xaf,0xdd,0x56,0xbc,0x27,0x52,0xe7,0xc0,0x3f,0x51,0xc3,0xc9,0x18,0xfa,0x43, + 0x57,0x53,0xc8,0x43,0x7b,0xa4,0x80,0x2e,0x3f,0x4d,0x46,0x69,0x27,0xd4,0x26,0xe5, + 0x9d,0x64,0xb1,0x03,0xff,0x7c,0x2f,0x3e,0xcf,0xc0,0x3f,0x9b,0xba,0x8a,0x93,0xf2, + 0x86,0xc2,0x66,0x75,0x13,0xfd,0x1f,0xc3,0x45,0x98,0x18,0xfa,0x13,0xba,0x20,0x59, + 0xb4,0x96,0x54,0xd8,0xf0,0x4f,0x80,0xfc,0x4a,0x8f,0x23,0xfe,0xc1,0xa7,0xcd,0xd2, + 0x43,0xf1,0x9e,0x62,0xd2,0x09,0x4d,0x97,0x50,0xff,0x0c,0xcf,0x43,0xd3,0x49,0x36, + 0x3f,0xa5,0x0e,0xfc,0xf3,0x1e,0xce,0x46,0xdc,0xd8,0x1d,0x60,0xb6,0x74,0x54,0xe2, + 0x88,0x28,0x95,0x3f,0xd5,0x9d,0xfa,0xe7,0x82,0x51,0x92,0x50,0xf7,0xe9,0x01,0xa4, + 0xdd,0x50,0x28,0xe5,0xe9,0x15,0x3d,0xe4,0x75,0x08,0xb2,0xbf,0x48,0x15,0xd6,0xab, + 0xd6,0xa1,0x3e,0xcd,0x89,0x7f,0x22,0x32,0xb6,0x45,0xba,0x6a,0x96,0x74,0x00,0x2a, + 0x8f,0xc8,0x77,0xb6,0xde,0x0a,0x48,0xfb,0xc8,0x58,0x11,0xcf,0x8d,0x4c,0xfd,0xf3, + 0x46,0xba,0x03,0x49,0x9e,0xaf,0xc0,0x73,0xfa,0xbc,0xa4,0xbc,0x38,0xd4,0x0c,0x9b, + 0x22,0x55,0x49,0x17,0x5e,0xd9,0x44,0x2b,0xc3,0xf2,0x5a,0x07,0xfe,0xb9,0x49,0xeb, + 0xdc,0xa6,0x86,0xe5,0xe0,0xf2,0x65,0xda,0x3e,0xa8,0x19,0x60,0xcb,0x66,0x6d,0x5b, + 0x0f,0xec,0x8c,0xb1,0x15,0x38,0xaa,0x75,0x12,0x75,0x8c,0xad,0x37,0x27,0xfe,0x39, + 0x0e,0x3e,0x2c,0x72,0xff,0x6b,0xb8,0xa2,0x35,0x46,0xbf,0x13,0x13,0x6f,0x80,0x63, + 0x50,0xdf,0x57,0xcb,0x5e,0x9b,0x39,0xfe,0xfa,0xdd,0x81,0x64,0x6e,0xfc,0xc3,0x02, + 0x93,0xdc,0xc0,0xc3,0x90,0x8f,0x21,0x04,0x32,0xdf,0xe8,0xc7,0xf2,0x2c,0xc9,0xc2, + 0x3f,0xaf,0xb1,0xa0,0x26,0x3f,0x28,0x56,0xcb,0x47,0x19,0x2c,0xe4,0x65,0xef,0x45, + 0xd3,0x51,0xd6,0x2b,0xbe,0x49,0x8f,0xb2,0x0f,0x07,0xa2,0x22,0xb1,0xe3,0x1f,0xb2, + 0x59,0xf3,0xb5,0xcb,0xb3,0x48,0x35,0xe9,0x00,0xdf,0x7a,0xf9,0x31,0xf2,0x29,0xd8, + 0xac,0xed,0xd4,0xe4,0x6d,0xe4,0xcd,0xc8,0x66,0xd8,0xa9,0xf9,0x15,0x97,0x6a,0xc3, + 0x3f,0x12,0x74,0x68,0xbb,0x56,0x2f,0xdf,0x46,0x0a,0x84,0xcd,0xda,0x8f,0xc7,0xd8, + 0x6d,0x73,0x85,0x27,0x64,0x1f,0xde,0x3f,0xec,0xe9,0x08,0xfb,0x57,0xbb,0xb0,0xb0, + 0xdd,0x5c,0x0f,0x88,0x7f,0x50,0xf6,0xec,0x8a,0xba,0x24,0x61,0x33,0xa8,0xcb,0xe5, + 0xd2,0x48,0x21,0xd9,0x81,0xdf,0x23,0xf2,0x21,0x1d,0xe0,0x47,0xbc,0x44,0x6c,0xf8, + 0x47,0x83,0x84,0xda,0xc0,0x16,0x72,0x95,0xca,0x3e,0x84,0xcf,0xc8,0x81,0x88,0x5b, + 0x65,0x5f,0x51,0x1d,0x78,0xe8,0x74,0x9d,0xfd,0x79,0x16,0x23,0xfe,0x29,0x49,0xe3, + 0x9f,0xe2,0xf3,0xb1,0xc9,0x40,0xcb,0xf2,0xe2,0x57,0x1e,0x3f,0x1f,0xfb,0xd8,0xff, + 0xdc,0x72,0xef,0x43,0xcf,0x7f,0x2b,0xf6,0xaf,0x58,0xf6,0xce,0x80,0x4d,0xec,0x82, + 0x7f,0x11,0xfb,0xa9,0xd3,0x59,0xff,0xf5,0xb6,0xff,0x9b,0x9a,0x67,0xdb,0xb4,0x6a, + 0x38,0x0a,0x75,0x21,0xde,0x1f,0xe9,0xa8,0xe4,0xd3,0x4a,0xb6,0xa1,0xfe,0xd9,0xc8, + 0x18,0x3a,0xf0,0x0f,0xed,0x0e,0xef,0x93,0xfd,0xe0,0x52,0x69,0x37,0xf8,0x14,0xff, + 0x46,0x36,0x1b,0xdd,0xaa,0x0f,0x5c,0xc4,0xa5,0x2a,0x98,0xff,0x92,0x75,0x07,0xfe, + 0x39,0xaf,0xfe,0x48,0xae,0x0c,0xc9,0xed,0xe4,0x7a,0x75,0xa3,0xbf,0x72,0xb9,0x7c, + 0xf3,0x6f,0xcb,0x62,0x1b,0xe5,0xaf,0x2e,0x77,0xdd,0x5c,0x5a,0x46,0x37,0xca,0x0b, + 0xd8,0x4f,0x11,0xbb,0xfe,0x67,0xbf,0xb0,0x11,0x04,0x4d,0x6e,0x2f,0xfd,0x16,0xd9, + 0xa4,0x54,0x2e,0x2b,0x5a,0xef,0x2b,0x87,0x8d,0xe4,0xf1,0xf6,0x9a,0x76,0x52,0x06, + 0xf7,0x4b,0xde,0x56,0xff,0x90,0x1d,0xff,0x14,0x2c,0x83,0xb7,0x69,0x29,0xbe,0xa4, + 0xc4,0xd5,0xaa,0xf8,0xfe,0xe4,0xa8,0x50,0xa7,0xd5,0x72,0x43,0x9a,0xbd,0xde,0xe3, + 0xc4,0x3f,0x3f,0xd6,0x2e,0xc4,0x9a,0xd7,0xb0,0x68,0xce,0x0c,0x78,0x36,0x84,0xf9, + 0x32,0xd5,0x94,0x45,0x69,0x17,0x5c,0xcd,0x6d,0x4e,0xfc,0x03,0x31,0x48,0x68,0x75, + 0xf2,0xca,0x8e,0x56,0xb5,0x22,0xc1,0xa6,0x7d,0x10,0xf1,0x4f,0x4a,0x7f,0x85,0x8d, + 0x80,0x18,0xfe,0xd1,0x33,0xf0,0x0f,0x43,0x3b,0x51,0xae,0x76,0xbe,0x8f,0xfa,0x68, + 0xf7,0x8f,0x22,0xfe,0xae,0xfb,0xd4,0x80,0xa1,0x7f,0x3e,0x04,0x6a,0x2c,0xa3,0xfe, + 0xeb,0x0b,0xf0,0x30,0xdd,0x9d,0x94,0x83,0x91,0x07,0xa0,0x33,0x1a,0xfb,0x40,0xc6, + 0xfe,0x3f,0x9d,0x34,0x80,0x57,0xbc,0xd0,0xab,0xef,0x1e,0xc9,0xc0,0x3f,0x57,0xc3, + 0x23,0xda,0xbc,0x21,0xb6,0x6d,0x79,0x14,0xbf,0xd6,0x21,0x58,0x4f,0x14,0xd8,0x88, + 0x40,0x8b,0x19,0xea,0xd3,0xdd,0xf3,0x22,0x19,0xf8,0xa7,0x99,0xc1,0x8a,0x25,0xb1, + 0x40,0x9b,0xf8,0x2c,0x79,0x99,0xd6,0xc7,0x02,0xb2,0xd8,0x0c,0x28,0x7b,0x0e,0xac, + 0x65,0xf1,0xc5,0xec,0xff,0x63,0xc3,0x3f,0xbb,0xe1,0x1d,0x89,0xed,0x47,0xa8,0x7b, + 0x9d,0xa1,0x76,0xa6,0x90,0x24,0xe3,0x12,0xca,0xf0,0xdc,0x49,0xb6,0x43,0x61,0x3f, + 0x39,0xf0,0x4f,0xc1,0x47,0x30,0x11,0xfd,0xdb,0xb0,0x77,0xdc,0x3d,0x17,0x69,0x9f, + 0x70,0xc9,0xc1,0xd6,0x66,0xed,0x5d,0x1a,0x5f,0x53,0x62,0xec,0xe8,0x5b,0x30,0x90, + 0xd9,0xf9,0x9f,0x28,0xdb,0x3f,0x2e,0x6c,0x73,0xdf,0x25,0x96,0x22,0x9e,0x59,0xcd, + 0x1c,0x4b,0x29,0xdd,0x18,0x53,0xfd,0xf8,0xfe,0xf0,0x34,0x2c,0x00,0x79,0xbd,0x43, + 0xff,0xbc,0x0d,0x9e,0x56,0x2a,0xf5,0x9e,0x73,0xe4,0x55,0x7a,0xa0,0x62,0x41,0xc7, + 0xf7,0x35,0xd2,0x04,0x3f,0x53,0x3f,0xa5,0xb9,0x93,0xe4,0x56,0x78,0x04,0xe6,0x87, + 0xe4,0x0d,0x0e,0xfc,0xa3,0xcb,0x87,0xba,0x54,0xf4,0xff,0x5d,0xda,0x61,0x1a,0xe8, + 0x90,0x81,0x2c,0x65,0xa8,0xa5,0x5a,0x91,0x63,0x3e,0x4d,0x3b,0x04,0x01,0x45,0x76, + 0xe2,0x9f,0x9f,0xd1,0x0b,0xe1,0xba,0x11,0x77,0xdc,0x7d,0x16,0xfa,0x68,0xf3,0x91, + 0xda,0xb8,0xb8,0xe0,0xc8,0xbb,0xb0,0x7f,0xa8,0x24,0xea,0xbe,0x03,0xa1,0xf2,0x40, + 0x13,0x38,0xf0,0xcf,0x3a,0xb8,0xa0,0xa2,0xba,0x72,0x86,0x1f,0x36,0x68,0xcd,0x43, + 0xde,0xfd,0xee,0x18,0xe2,0x67,0xea,0xdd,0x26,0xee,0x40,0x69,0x62,0xd4,0xdb,0xe5, + 0xe0,0x7f,0xae,0x2c,0xbd,0xa0,0x55,0xd1,0x55,0x3a,0x9b,0xf6,0xcb,0x9f,0xab,0xa7, + 0xc5,0x89,0x19,0x57,0xe0,0x74,0xac,0xe5,0x88,0xa7,0x9f,0x34,0xd3,0xcb,0x9a,0xa8, + 0x7b,0x13,0x2e,0xb0,0xe3,0x1f,0xe1,0xa0,0xc4,0xd0,0x32,0x2d,0xad,0x85,0xb7,0x35, + 0x35,0x5a,0x4c,0xc9,0xf3,0x7a,0x37,0x06,0xb2,0x08,0x51,0xa1,0x4f,0xf0,0x3d,0xcd, + 0xb6,0x1e,0xaa,0x9d,0xff,0xa9,0x3e,0x2c,0xd7,0x68,0xee,0xb8,0x2f,0xa0,0x3d,0x29, + 0xd4,0x68,0xf2,0x5e,0x32,0x4a,0x7e,0x80,0x8d,0xc8,0xa2,0xe4,0x1f,0xd9,0x46,0xac, + 0x46,0xeb,0x89,0x44,0x32,0xf4,0xcf,0x7e,0xbf,0xb6,0x22,0x58,0x28,0xab,0x3b,0x99, + 0xf7,0x9b,0x57,0x47,0x92,0xb4,0x03,0x6a,0xaf,0x91,0x95,0x5a,0x0a,0x71,0xb6,0xe0, + 0x45,0x4a,0x22,0x19,0xf5,0x5f,0x87,0x18,0xfe,0xe9,0x09,0x74,0xbf,0x0b,0xfb,0x68, + 0x80,0xb0,0x40,0x76,0xd2,0xcf,0xdc,0x02,0x15,0x91,0x2a,0x3c,0xa4,0x4d,0xa3,0x76, + 0xfd,0x33,0xe2,0x1f,0xff,0x22,0x2c,0x53,0xba,0x34,0xfd,0x7d,0xb8,0xb1,0xdf,0xfb, + 0x81,0xf8,0x12,0x7c,0x04,0x2d,0xb2,0xb7,0x5d,0xfc,0x0e,0xef,0xf8,0xc7,0xbe,0x97, + 0xb5,0xce,0xfa,0xaf,0x94,0x7e,0x1e,0x26,0xd5,0xe6,0xb1,0xf9,0xfb,0x66,0x3c,0x13, + 0x3a,0xae,0xb4,0x0c,0x16,0x8f,0x8b,0x01,0x14,0x8a,0x24,0x3d,0x59,0xfc,0x8f,0x91, + 0xe4,0x3a,0x0b,0xcf,0x0d,0xd5,0x26,0xe4,0x31,0x22,0xd1,0xfb,0xd4,0x05,0xa7,0x96, + 0xf7,0x91,0x05,0x5a,0x8f,0xec,0x7b,0xd1,0xd5,0x07,0xd9,0xfc,0x4f,0xaa,0xde,0xdf, + 0x9f,0x90,0x17,0x92,0x6e,0x5a,0x05,0x81,0x04,0x03,0x36,0x0f,0xc8,0x9d,0x2a,0x57, + 0x68,0xd8,0xf9,0x1f,0x13,0x4f,0x96,0x8e,0xf2,0x46,0x40,0xae,0x78,0x21,0x85,0x9f, + 0xd2,0x5a,0xfd,0x9a,0xb8,0x6b,0x0f,0xed,0x94,0xfc,0x88,0x88,0xb2,0xf8,0x1f,0x0b, + 0x0f,0x63,0x19,0xd7,0x93,0xf0,0x1e,0x9d,0x8d,0x8d,0x0a,0x77,0xf3,0xd6,0x7c,0x9e, + 0x78,0x55,0x2e,0xfe,0x87,0xe7,0x5b,0x39,0xfb,0xf7,0x4d,0xed,0x5f,0x09,0xa7,0x35, + 0x6e,0x67,0x3f,0x1d,0xc8,0x91,0xff,0x4a,0x3d,0x5f,0xe6,0x40,0xbd,0x8e,0xfd,0x0f, + 0xbd,0x0d,0x4d,0xfd,0xec,0x7f,0x28,0xc1,0xe3,0x7b,0x4e,0xfd,0x0f,0xc7,0xc3,0xcf, + 0x81,0xaf,0x5f,0x1c,0x2b,0x1d,0x66,0xb0,0x6d,0x81,0x2e,0xef,0x63,0x30,0xb8,0xc7, + 0x28,0x0c,0xcc,0xd6,0xff,0xa4,0xd8,0xbf,0xb9,0x6c,0x9b,0xa0,0x0e,0x48,0xfb,0xc0, + 0xc3,0xfb,0x6f,0x28,0x9d,0x20,0xe7,0xd0,0x3f,0x5b,0xfd,0x70,0x3a,0xd8,0x6e,0x65, + 0x43,0xe4,0x74,0xd1,0xf7,0xd8,0x95,0x1a,0xac,0x90,0xda,0x1a,0xe3,0x85,0xe1,0x19, + 0xfc,0x0f,0x8a,0x9c,0x97,0xf0,0x6e,0x87,0xb3,0x46,0xbd,0x4b,0x66,0xe8,0x51,0x76, + 0xa5,0xbf,0x16,0xf3,0x5f,0xcf,0xd3,0x6b,0xb2,0xeb,0xdf,0xed,0xd9,0xc0,0x5f,0x78, + 0xc7,0x3a,0x46,0x30,0x9f,0xf8,0xaa,0x87,0xe7,0xbf,0x14,0xe4,0xc7,0xf2,0xf0,0x3f, + 0xc2,0x84,0xca,0xd0,0xf5,0xfe,0xce,0x30,0x66,0x40,0x12,0x4d,0x71,0x16,0x4f,0xb1, + 0x90,0x21,0x4f,0xff,0x1f,0xdc,0x4f,0xb5,0xe3,0xc6,0xaa,0xf4,0x04,0x3c,0x55,0xc8, + 0xfb,0xa7,0x9d,0x52,0xde,0x80,0x2a,0xe4,0x93,0xf3,0xf5,0xff,0x89,0xa0,0x31,0xf7, + 0x37,0xc2,0x81,0xae,0xf9,0xc3,0xae,0x0d,0xbe,0xdf,0xc0,0x4f,0x0c,0x68,0x64,0xc7, + 0x3f,0x19,0xfb,0x59,0x9e,0x46,0x3c,0xac,0x19,0xfc,0xb3,0x76,0x18,0x33,0xf8,0x39, + 0xfb,0xff,0xa4,0xf5,0x3f,0x55,0xdf,0x86,0x2b,0x4a,0x73,0x47,0x49,0x8c,0x2d,0x03, + 0x94,0x46,0x7b,0xd4,0xbc,0xfc,0x0f,0x33,0xdc,0x5d,0x24,0xa9,0x8e,0x5f,0x35,0x1b, + 0x3a,0x18,0xfe,0x51,0x4f,0xe4,0xae,0x7f,0xb7,0x67,0x43,0xb6,0xa3,0x50,0x04,0xea, + 0x96,0xba,0x98,0xc1,0xf0,0x0f,0xd7,0xff,0x90,0x7c,0xfc,0x0f,0x33,0xb6,0xf9,0x50, + 0x4f,0x52,0x83,0x6d,0x7f,0x06,0xe8,0x13,0x46,0x45,0xbc,0x9a,0x97,0xff,0x59,0xea, + 0x7e,0x30,0x32,0x00,0x4f,0x30,0xfc,0xe0,0x7a,0x28,0xb4,0x26,0x55,0x11,0x96,0x81, + 0x7f,0xf6,0xda,0xf4,0x3f,0x5a,0x4f,0x69,0x64,0x20,0xde,0x11,0xf0,0x2f,0x5f,0x8e, + 0xfd,0x0f,0x77,0x70,0xfd,0x8f,0x8b,0xe4,0xca,0x7f,0x21,0xdb,0x33,0x1b,0xf3,0x5f, + 0x49,0x3a,0xa2,0x06,0x65,0x06,0x7b,0x50,0x08,0x5d,0x97,0x81,0x7f,0x9c,0xfc,0x4f, + 0xf3,0xf2,0x55,0x0f,0x75,0x9e,0xdf,0x39,0xe9,0x6f,0x5e,0xfe,0xf9,0x21,0xf1,0xbc, + 0x92,0xcd,0xff,0xd8,0xf5,0x33,0xaf,0xf9,0x1b,0xb5,0x92,0xa1,0xce,0x39,0xea,0x6b, + 0xe1,0xba,0xe5,0xde,0x21,0xf1,0x7a,0x9c,0x28,0xcd,0x33,0x24,0xbe,0x20,0xd9,0xf0, + 0x8f,0x55,0xff,0xa5,0xf4,0x69,0x3e,0x90,0xef,0x25,0x95,0x0c,0xff,0x5c,0x5f,0xc1, + 0xae,0xec,0xd0,0xba,0x61,0x67,0x5e,0xfe,0x07,0x0d,0xff,0xf2,0xfb,0x82,0xd8,0xf8, + 0xe8,0x76,0x35,0x54,0xa4,0xa0,0xc2,0xc7,0xaf,0x86,0x64,0xe4,0x7f,0xec,0xfa,0x67, + 0xb3,0xfe,0x0e,0x0e,0x16,0xa0,0xfe,0xa7,0xac,0xda,0xb7,0x43,0xfd,0x4b,0x9c,0xe1, + 0x5d,0xd2,0x66,0xf6,0x85,0xf0,0x7e,0x4a,0xe6,0x7a,0x88,0xd9,0xf5,0x4b,0xaf,0x09, + 0x8d,0xda,0x17,0xa2,0xe2,0x1c,0xe5,0xdb,0x7a,0x29,0x0a,0x7b,0x76,0xf1,0x8a,0x3f, + 0xc4,0x3f,0xe9,0xf8,0x6b,0xe7,0x7f,0xfe,0x1b,0x17,0x4e,0xcf,0x44,0x84,0xcc,0xaf, + 0x0c,0x90,0x0b,0x42,0xb3,0xb6,0x20,0x13,0xff,0x98,0xf3,0x2f,0x8d,0xc1,0x3e,0xb6, + 0x47,0xed,0x54,0xe1,0x84,0x31,0xed,0x49,0x6a,0xf6,0x3f,0xb4,0xd6,0x7f,0xb6,0xfe, + 0x67,0x98,0xec,0x36,0xfa,0xff,0xf8,0x7d,0x13,0xdd,0x87,0x48,0x43,0x06,0xff,0x53, + 0xee,0xf8,0x5e,0x54,0xd4,0xff,0xac,0xe3,0x1d,0x24,0x5c,0x8b,0xe1,0xb8,0x62,0xf6, + 0x3f,0x94,0x72,0xf1,0x3f,0xec,0xd7,0xca,0x81,0xb6,0xf5,0x3c,0x71,0xf6,0xf5,0xdf, + 0xcb,0xbc,0x43,0x8e,0x92,0x23,0xff,0x65,0xf2,0x3f,0xca,0xc7,0xb4,0x7e,0xb4,0x78, + 0x9c,0x7c,0x25,0xf2,0x56,0xfc,0xc6,0xd1,0x42,0xde,0xff,0x30,0x7e,0x43,0x16,0xff, + 0xc3,0xfc,0x49,0xad,0x43,0x5d,0xb0,0x27,0xb9,0x02,0xf6,0x0d,0xa5,0x14,0x86,0x0d, + 0x27,0x32,0xf0,0x8f,0x95,0xbf,0xc0,0x6e,0x42,0x75,0xbf,0xf7,0x4c,0x88,0xcf,0x2a, + 0x2f,0x77,0xf7,0xbe,0xed,0x19,0xaf,0xba,0x82,0xfd,0x7b,0x7f,0xeb,0xd9,0x20,0x82, + 0x23,0xff,0xc5,0xf5,0x3f,0xd8,0xbd,0xe7,0x80,0x34,0x2f,0xe9,0xba,0x93,0xfc,0x90, + 0x6d,0xa3,0x3e,0x3d,0x2a,0xaf,0xaf,0x3b,0xa5,0x1e,0x80,0x4f,0x0f,0x30,0x47,0xf4, + 0xa4,0xb3,0xfe,0xcb,0xd4,0xff,0xb0,0xf1,0x26,0x5c,0x77,0x5e,0x35,0x08,0x3f,0x01, + 0x21,0xf1,0xfd,0xf5,0x64,0x48,0x7b,0x04,0xe6,0xe8,0x35,0xeb,0x09,0xcd,0xa1,0xff, + 0xf1,0x19,0x44,0x10,0xf3,0x36,0xb5,0x6c,0x3e,0xfd,0x7a,0x0d,0xf6,0xb3,0xed,0x35, + 0xf8,0xfc,0xee,0xcc,0xfa,0x2f,0x73,0xbc,0xf5,0xfa,0x17,0xe2,0xad,0x97,0xd4,0xf7, + 0xb1,0x50,0x2b,0x2e,0xbe,0x09,0x6f,0x90,0x45,0x68,0x3c,0xe9,0xe0,0x7f,0xd2,0xf7, + 0x0b,0xcd,0xfd,0xee,0xeb,0x61,0x94,0xbc,0x1e,0x69,0xd2,0xe7,0x61,0x3e,0xe2,0x30, + 0x69,0x64,0x11,0x50,0xc8,0x5b,0xff,0xc5,0x37,0xb6,0x4d,0x65,0x2f,0x4a,0x3c,0xf0, + 0x9d,0x87,0x49,0xb1,0xb7,0x7f,0xeb,0x98,0x60,0xe3,0x7f,0x80,0xb7,0xdd,0xc3,0xfa, + 0x3b,0xc3,0x28,0xea,0x8b,0x70,0xda,0x01,0xc3,0xd6,0xb0,0xc1,0x5f,0x65,0xf0,0x3f, + 0x82,0x8d,0xff,0x61,0xf1,0xab,0x2f,0x14,0x50,0x7a,0x48,0x6d,0xbf,0x6b,0x5f,0xe9, + 0x68,0x7b,0x6f,0xea,0xfe,0x6c,0xfe,0x67,0x21,0xea,0x81,0xa5,0xc0,0x51,0xb6,0xde, + 0x3c,0x72,0xa7,0xcc,0xf0,0x40,0x90,0xbc,0xa4,0xf4,0x6a,0xe1,0xa1,0x9e,0x2c,0xfe, + 0xc7,0x67,0xcd,0xcf,0x8d,0xaf,0xae,0x7a,0xaa,0xb5,0x09,0x5e,0x56,0x5b,0x12,0x25, + 0xf1,0x19,0x67,0xa4,0x8f,0x97,0xcd,0xf8,0xd5,0xd6,0x4c,0xfe,0xe7,0x0d,0xb6,0x5b, + 0x9f,0x76,0x4e,0x6c,0x82,0x37,0xa0,0xe5,0xc4,0xfd,0x47,0x66,0x8e,0x86,0x30,0x71, + 0x33,0x7f,0x88,0xc1,0x18,0x53,0xdf,0xeb,0xc0,0x3f,0x17,0x61,0x51,0x8c,0x2d,0x92, + 0xb3,0x0c,0x08,0x2d,0x31,0xda,0xfe,0xa4,0x64,0x3f,0xb9,0xea,0xbf,0xe0,0xac,0xcc, + 0x3f,0xab,0xbe,0xba,0x5a,0x06,0x84,0xaa,0xc6,0xec,0x6d,0x7f,0xd2,0xfa,0x1f,0xdb, + 0xf7,0x38,0x28,0xf7,0x41,0x35,0x95,0x83,0xb7,0x73,0xfc,0x33,0x64,0x4f,0xf3,0xd9, + 0xf2,0x7d,0xe6,0xfd,0xfa,0x9f,0xef,0x61,0xfe,0xcd,0xd7,0x01,0x46,0xdb,0x25,0x67, + 0x1b,0x01,0x9b,0xfe,0xc7,0x7c,0x1f,0xac,0xff,0xba,0x28,0x35,0x74,0x55,0x07,0x45, + 0xa3,0x50,0xab,0xc0,0xf6,0xe1,0xa4,0xeb,0xbf,0xd2,0xfd,0x2d,0x95,0x26,0xb8,0xa8, + 0xb7,0x24,0xb7,0x8e,0xf1,0xfe,0x7e,0xce,0xb2,0xa6,0xb4,0xfe,0xd9,0x56,0xff,0x15, + 0x60,0xa0,0xba,0xa1,0xdb,0xb3,0xb7,0x73,0x1d,0xbc,0xab,0x36,0x19,0x6d,0x19,0x5e, + 0x37,0x2a,0x34,0xf3,0xd4,0x7f,0xc5,0xa9,0x6f,0xc8,0xff,0x0c,0x7b,0xff,0x4e,0x6d, + 0x81,0xee,0xcf,0xf5,0xfe,0xe9,0xfa,0x2f,0x5d,0xf2,0x48,0xfb,0xe8,0x93,0xf1,0x9a, + 0xeb,0xc9,0xca,0xf0,0xe3,0x5a,0x40,0xbf,0xc6,0x10,0x8a,0xe7,0xad,0xff,0xd2,0x66, + 0xc3,0xd3,0xe3,0xf3,0x6a,0x5c,0xdf,0x26,0xb3,0xbb,0xa7,0xd1,0xe2,0x24,0xcf,0x7f, + 0xd9,0x32,0x62,0x99,0xf5,0x5f,0x15,0x1e,0xed,0x5c,0xb2,0x91,0x3e,0x50,0x27,0x7e, + 0x81,0x7e,0x15,0x9a,0x06,0x78,0xdb,0x9f,0x5f,0xc7,0x9a,0x86,0xbd,0xc1,0xaa,0x74, + 0xfd,0x57,0xa1,0xf9,0x3e,0x9a,0xe7,0x19,0xb8,0x52,0x56,0x2f,0x9b,0xb2,0xa8,0x23, + 0xc5,0xa9,0x69,0xe9,0xcf,0x5d,0xff,0x25,0x17,0x8c,0x4a,0x17,0x21,0x48,0xd9,0xb4, + 0xdc,0x81,0x68,0xd3,0xd1,0xa6,0x23,0x5d,0xbf,0x90,0xee,0xcf,0xbc,0x94,0xf9,0x13, + 0xa1,0x52,0x63,0x4e,0x66,0x16,0x6c,0x22,0xf3,0x8f,0xd8,0x65,0x03,0xe9,0xfa,0x2f, + 0xeb,0x7e,0x60,0xf8,0xa7,0x97,0x56,0xc5,0x8a,0xb0,0xde,0xcd,0x94,0x39,0xd9,0x3b, + 0x22,0xe6,0xe8,0xff,0xd3,0xfb,0xb9,0x9d,0x5a,0x51,0x30,0x64,0xc8,0xa8,0xdc,0xb9, + 0xd6,0x9b,0xad,0xff,0x8f,0xb4,0x1b,0xae,0x68,0xf5,0xd1,0xf9,0xaa,0xe8,0x27,0xf7, + 0xd9,0x81,0xd0,0x56,0x9b,0x22,0xda,0xd6,0xff,0xc7,0xc8,0x47,0x94,0x96,0x50,0xf7, + 0x99,0x54,0x21,0x58,0x0e,0x3d,0x86,0xb3,0xff,0xf3,0x07,0x4a,0x5d,0x98,0x05,0xc1, + 0x1f,0x67,0xc9,0x42,0x72,0xea,0x7f,0xaa,0xe5,0x83,0x47,0x7c,0xcb,0xe4,0x68,0xe4, + 0x53,0xea,0xc1,0x36,0xa7,0xec,0x24,0x5f,0xfd,0x97,0xb6,0x53,0xab,0x60,0xd1,0x99, + 0x66,0xde,0x96,0xaf,0xfe,0xcb,0xaf,0x6a,0x15,0x0a,0x91,0x64,0xec,0x7f,0x68,0x00, + 0x03,0x29,0x43,0xff,0x63,0xe9,0xc3,0x17,0x5f,0x8d,0xdd,0x7e,0xea,0x68,0x80,0xfd, + 0x0d,0x64,0xec,0x7f,0x98,0x73,0xbc,0xa7,0x0b,0xcd,0xf7,0xe9,0x43,0xfd,0xcf,0xbc, + 0x96,0xe5,0x6c,0xb7,0x35,0x90,0x1a,0xdd,0x0c,0xde,0x0f,0xd9,0x31,0xde,0x37,0xd3, + 0x78,0x86,0xe1,0x8d,0xcb,0x70,0xe3,0x32,0x4f,0x3b,0x43,0x3b,0x97,0x8d,0xb4,0x11, + 0xde,0x76,0xb7,0xe3,0xfe,0x34,0xff,0x53,0x01,0x49,0xb9,0x4f,0xae,0x85,0x62,0xea, + 0x42,0xd9,0x4f,0x8d,0xe2,0x36,0x64,0x57,0xb6,0x8c,0x98,0xb3,0xff,0xcf,0xb2,0x2e, + 0x79,0x6f,0xe8,0x0e,0x06,0x5a,0xae,0x5a,0x86,0xa3,0x5b,0x66,0x1f,0x66,0xae,0xfe, + 0x3f,0x65,0xbb,0x52,0x65,0x5f,0x5c,0x4f,0x5e,0x93,0x9a,0x46,0xc1,0x39,0x9f,0x69, + 0xfd,0xf3,0x4e,0xec,0x7f,0xf8,0xf7,0xcd,0x4b,0x3d,0x4a,0x2a,0xff,0xd5,0x63,0xbc, + 0x76,0xad,0xf1,0xfe,0x07,0x53,0xfa,0x1f,0xab,0xff,0xe1,0x08,0xf6,0x3f,0xe4,0x4d, + 0x0e,0x3b,0x6d,0x40,0xe8,0xed,0x8c,0xf5,0x70,0xd1,0x51,0xff,0x35,0xa2,0xd6,0xb1, + 0xf1,0x8a,0x61,0x3e,0xcc,0x9c,0xf3,0x9f,0xae,0xff,0x02,0xc9,0x0f,0xcf,0xca,0x95, + 0x54,0x3e,0x4b,0x96,0xd0,0xa7,0xb5,0x12,0x87,0xec,0xc7,0x32,0xd2,0xfd,0x0f,0x65, + 0xb6,0xff,0x7a,0x5c,0xaf,0x86,0xa2,0x26,0xd2,0xa6,0xee,0x8b,0x3b,0x65,0x87,0x36, + 0xfd,0x8f,0xf9,0x0f,0xeb,0xbf,0x9e,0xa6,0x9f,0x3a,0x22,0xaf,0x2f,0x5c,0x0d,0x4f, + 0x63,0x23,0xe8,0x5c,0xdf,0x6f,0xc2,0x7c,0x3c,0xf8,0x2b,0x66,0xc3,0x59,0xfa,0x54, + 0xac,0x78,0x83,0xf8,0xdf,0xe1,0x23,0x7b,0x22,0xcc,0x6e,0x1c,0xf3,0x59,0xeb,0xb3, + 0x78,0x0f,0x5c,0x82,0x43,0x94,0x79,0xd7,0xdd,0x46,0xa1,0x93,0xad,0x8d,0x58,0x5a, + 0xff,0x73,0xaf,0x39,0xde,0x70,0xd9,0xb3,0xda,0x95,0x68,0xbd,0xea,0x19,0x71,0x5f, + 0x05,0x03,0x74,0x89,0x19,0xb6,0x9a,0x87,0xed,0xf1,0x6b,0x28,0xad,0x7f,0xae,0x78, + 0x0c,0x9e,0x8e,0x55,0x6a,0xc5,0x9f,0x21,0xab,0xa1,0x4b,0x5b,0x88,0xb2,0xa5,0x41, + 0x7c,0xed,0xa4,0xfb,0x1b,0x36,0xfd,0x8f,0xa5,0xaf,0xa6,0xf0,0x98,0xb0,0x5f,0x79, + 0x7c,0x1b,0xf3,0x57,0xab,0x51,0xed,0xac,0x9b,0xb7,0x25,0x7a,0x6c,0xe3,0x4d,0xc7, + 0x3b,0x8d,0xc5,0xf7,0xb8,0xa6,0x52,0x16,0xe6,0xda,0x08,0x35,0x89,0xfd,0x54,0xdb, + 0x31,0x6b,0x3e,0x6d,0xf5,0x5f,0x05,0x7b,0xe0,0x43,0x8d,0xfb,0x4f,0x3f,0xca,0xfc, + 0xf4,0xeb,0x30,0x4c,0x4c,0x48,0x77,0x38,0xe2,0x4b,0x9a,0xdf,0x8b,0x29,0xa3,0x70, + 0x51,0x65,0xd1,0x19,0xe7,0x67,0xdc,0xda,0x78,0x66,0xf8,0xdb,0xf4,0xfb,0x20,0xfe, + 0xb9,0x08,0xf5,0xb4,0x03,0x37,0xf5,0x97,0x48,0xaa,0xcc,0xf9,0x0d,0xc3,0x8d,0x7f, + 0x27,0xbb,0xff,0x4f,0xbf,0xb4,0x4e,0xee,0xeb,0xa8,0x89,0xb9,0x9e,0x21,0xef,0x40, + 0x9f,0xee,0x0c,0x5b,0xb6,0xfa,0x2f,0xf3,0xef,0x85,0xf5,0x5f,0xbb,0xa9,0x2f,0xe6, + 0xde,0x4e,0xf6,0x68,0x7d,0x34,0x75,0xdb,0x0f,0x32,0xee,0x77,0xf6,0x7f,0xee,0x53, + 0x6b,0x74,0xd7,0xf5,0xe4,0x28,0xc4,0x53,0xcb,0xac,0xad,0x57,0x31,0xea,0xbf,0x72, + 0xe8,0x7f,0xe4,0x75,0x30,0xb2,0xbe,0x8e,0x2e,0xd8,0x26,0x3e,0x61,0x8d,0x17,0xe3, + 0xef,0x0b,0x56,0xc7,0x5d,0xaf,0x03,0xff,0x94,0x5d,0x82,0xf1,0xe0,0x8d,0x74,0xd5, + 0x7a,0xe6,0xb4,0x2f,0x19,0xb2,0xe7,0x4b,0x74,0x92,0xe1,0xa5,0xeb,0xec,0xf1,0x3d, + 0x9b,0xff,0xc1,0xd5,0xf2,0x06,0x2c,0x49,0x94,0x9c,0xeb,0x0c,0xb0,0xf9,0xaf,0x3d, + 0xe6,0x5d,0x2d,0x36,0x51,0xf6,0x53,0x3f,0xf2,0x3f,0x36,0xfd,0x39,0x03,0x39,0x1d, + 0xb5,0x49,0x91,0xa3,0x1d,0xdd,0x37,0x26,0x6f,0x21,0x0b,0x94,0x43,0x7a,0x6d,0x9c, + 0xcd,0xc0,0x02,0xed,0x70,0x64,0xc1,0x70,0x4e,0xfd,0x0f,0x1f,0xdd,0x0e,0xcd,0x2f, + 0x31,0x98,0x27,0xc0,0x5e,0x8d,0x77,0x08,0x07,0xe8,0x2d,0xe0,0x78,0xd8,0xd1,0xff, + 0xd0,0x36,0xdb,0x84,0x01,0xad,0x68,0xe1,0x6e,0x85,0xcf,0x67,0x37,0xf3,0x78,0x06, + 0x23,0x14,0x4a,0xe3,0x31,0xb0,0xeb,0x4f,0x5e,0x97,0x1a,0x13,0x25,0x41,0xf7,0x7c, + 0x89,0x5f,0x99,0x2d,0xd6,0x6a,0x13,0x70,0x77,0x3f,0xc3,0xcf,0xba,0x85,0x67,0x62, + 0xd3,0x1d,0xfc,0x0f,0xdb,0x68,0x24,0xb1,0xad,0x0d,0xb4,0xec,0x66,0xfb,0x4d,0x06, + 0x1d,0xc9,0xdd,0x99,0xf8,0x67,0x8f,0x59,0x54,0x38,0x0a,0x1f,0xb4,0x2d,0x2e,0x62, + 0x4f,0xdb,0x11,0x3a,0x0a,0xcd,0x47,0xbc,0xdb,0x3a,0x55,0x3d,0xa5,0x38,0x4a,0xf3, + 0x0f,0x06,0xff,0x63,0x56,0x0b,0x52,0x5f,0x54,0x7e,0xa6,0x75,0x77,0xd9,0xeb,0x43, + 0x0c,0x16,0x6e,0xef,0xbc,0x0d,0x0e,0x4b,0x0b,0x18,0x42,0x73,0xe2,0x9f,0xf4,0xd7, + 0xb1,0xef,0x66,0x7f,0xd2,0xd5,0x04,0x0f,0xd0,0xce,0x23,0x81,0xb0,0xdb,0xd6,0x88, + 0x7e,0xdc,0xda,0x7f,0x85,0x21,0xad,0xff,0x11,0x9e,0x8e,0x56,0x0e,0xcb,0x9f,0x23, + 0x3f,0xa4,0xf7,0xd2,0xf9,0xb1,0x9e,0x71,0x54,0xc8,0x74,0xcc,0x1f,0x2e,0xca,0xc0, + 0x3f,0xf0,0x61,0x0c,0x9f,0x2f,0x0e,0xc2,0x07,0xe0,0xff,0xeb,0x92,0x60,0xe7,0xa6, + 0x68,0x47,0x77,0xd3,0xed,0xd3,0x82,0xa2,0x87,0x7e,0x08,0xb3,0x74,0x8f,0x83,0xff, + 0x99,0x95,0xd2,0xff,0x18,0xab,0xe5,0x1e,0xdd,0x3b,0xd4,0x7a,0xaa,0xed,0x0d,0x58, + 0x30,0x60,0xea,0x9f,0xfb,0x9d,0xf8,0x27,0xcd,0xbf,0xad,0x83,0x8b,0xb4,0x2e,0xe9, + 0xe9,0x13,0x6b,0xb1,0xfe,0x02,0x23,0x3e,0x43,0x44,0x05,0xcd,0xaf,0x78,0x1c,0xfd, + 0x0f,0x05,0x1b,0xff,0xf3,0x34,0xcf,0x76,0xf9,0x66,0x49,0xf7,0x02,0xf3,0xd8,0xed, + 0x64,0x0b,0x6c,0x82,0xc0,0x09,0xbf,0xf3,0xfc,0x0b,0x1b,0xff,0xb3,0x97,0x56,0x87, + 0xe5,0xc5,0xe4,0x5e,0xe8,0xe8,0xf0,0x87,0xe1,0x44,0x88,0x77,0xc0,0x46,0x05,0x54, + 0x1a,0xff,0xac,0x75,0xd4,0x5f,0x40,0x4c,0xf7,0x2f,0xac,0xd9,0x42,0xb0,0x8d,0xb6, + 0x7f,0x56,0x64,0x0b,0x74,0x4a,0x01,0x83,0xff,0x31,0xef,0x1f,0x29,0xb3,0xf8,0x9f, + 0xb5,0xa8,0xfe,0xa2,0x9e,0x11,0xb1,0x0f,0x8e,0xc3,0x12,0xea,0xf9,0x4b,0x71,0x03, + 0x39,0x66,0x28,0x82,0xec,0xfd,0x0f,0x6d,0xfb,0x71,0xc3,0x10,0xc2,0xbc,0x30,0x07, + 0xeb,0xbf,0x24,0x3c,0x18,0xa2,0x20,0x13,0xff,0xe4,0x85,0x3d,0x86,0x50,0x36,0x90, + 0x81,0x7f,0x6c,0xe8,0x45,0xab,0x6d,0x77,0x6f,0x23,0xbf,0x37,0x8c,0x68,0xea,0x60, + 0x8b,0xfc,0xfa,0x9f,0xc3,0x72,0x6d,0xc8,0x1d,0x8d,0x0c,0xab,0x07,0x99,0xb1,0x22, + 0x7a,0x4d,0xc0,0xbc,0xff,0x05,0x6b,0x7e,0x32,0xf9,0x9f,0xe5,0xee,0xd2,0xc8,0xc0, + 0xee,0xbd,0x35,0x81,0xe5,0x2b,0x18,0x22,0xc2,0xf3,0x2f,0x96,0x3b,0xf5,0x3f,0xd7, + 0x3a,0xf8,0x1f,0x86,0x7f,0x90,0xff,0x19,0x57,0x67,0x23,0x10,0xe2,0x07,0x31,0x60, + 0x45,0xd8,0x69,0x6b,0xfd,0xf4,0xd9,0xfa,0xff,0x18,0xea,0xe5,0x21,0xf1,0xbc,0xf4, + 0x73,0xd2,0xa2,0xad,0x6a,0xb7,0x9d,0x7f,0x51,0x98,0xc6,0x3f,0xf6,0x69,0x91,0xeb, + 0x34,0xcf,0x43,0x9d,0xc3,0xd5,0x17,0xe4,0xe6,0x10,0x17,0xc6,0xb0,0x0f,0x2d,0x14, + 0x70,0xe2,0x9f,0x98,0xc5,0xff,0xb0,0x8d,0x55,0x43,0x99,0xdc,0xe5,0x3b,0x03,0x7d, + 0x5a,0xad,0xc2,0xc2,0xfa,0x85,0xf6,0x6e,0xa8,0x55,0xda,0x1c,0xf8,0x47,0xea,0x4a, + 0x8f,0xf7,0xe7,0xb4,0x52,0xdb,0xbc,0x9a,0xbc,0x0a,0x4f,0x75,0xcc,0x0f,0x8b,0xed, + 0xe4,0x94,0xd2,0x61,0x54,0xcc,0x39,0xf0,0x4f,0x7a,0x3e,0x9f,0x82,0x4f,0x85,0x8a, + 0x86,0x6e,0xfe,0xb7,0xe8,0xcf,0xd5,0x05,0x5a,0xcf,0x10,0x39,0x7f,0xcb,0x66,0x63, + 0x3e,0x6d,0xf5,0x5f,0x92,0xfd,0xef,0x1b,0xaa,0xd3,0xe6,0x6f,0x13,0xdf,0x82,0x0b, + 0x7a,0x73,0x3b,0xf6,0xe3,0x25,0x47,0x8d,0x83,0x3c,0x6c,0xf5,0x5f,0x8e,0xf5,0xa0, + 0x34,0x2f,0x2b,0x89,0x56,0xbd,0x99,0x42,0x44,0x88,0x18,0x85,0xeb,0xb3,0xf1,0x8f, + 0x35,0xff,0x97,0xa0,0x1e,0x3c,0xba,0xb8,0x10,0x2e,0x15,0xd4,0x43,0xc9,0x00,0x73, + 0x3b,0xe3,0x42,0x06,0xfe,0x91,0x25,0x07,0xff,0xe3,0xe7,0x69,0x2f,0x63,0xc7,0xba, + 0xb3,0x34,0x8d,0x7f,0x54,0xd3,0x3f,0xc8,0x0e,0xfd,0x0f,0x55,0xcf,0xb0,0xef,0x0b, + 0x3b,0x86,0xa9,0x49,0x66,0x0c,0x4a,0x58,0xc1,0xc4,0xf1,0x8f,0xf5,0x3d,0xda,0xf5, + 0x3f,0xfb,0xb5,0x79,0x4a,0xdb,0x4a,0xa2,0xc0,0x7e,0xbd,0x32,0x28,0x6b,0x64,0x08, + 0xb0,0x31,0x72,0x16,0xfe,0xb1,0xd0,0xce,0x39,0x1a,0x8f,0x05,0xfc,0xee,0x6b,0x0c, + 0x23,0x8d,0x7f,0xaa,0x6c,0xf8,0xe7,0x5a,0x1b,0x1f,0x72,0x01,0x65,0x84,0xd6,0xf7, + 0x42,0xed,0xe7,0x5f,0x98,0xef,0xc3,0xf0,0x8f,0x11,0xbf,0x0e,0x8a,0x58,0xc8,0x53, + 0xb7,0x66,0xeb,0x76,0x6e,0xb4,0x84,0x59,0xfc,0x2a,0x64,0x8e,0xa8,0x19,0xf3,0x17, + 0x43,0xe9,0xfe,0x87,0xf2,0x63,0x6c,0xbc,0xec,0x25,0x37,0x70,0xff,0xa3,0xc6,0x4a, + 0xd6,0x5e,0x35,0xc4,0x0c,0x6c,0x3b,0xe6,0xfb,0x3e,0xdd,0xb4,0x6b,0xfe,0xa8,0xec, + 0xd4,0xff,0xcc,0xb2,0xfa,0xff,0xc0,0x33,0x30,0x47,0x6e,0xd5,0x98,0x77,0xdd,0x8f, + 0x65,0x5f,0x43,0xe4,0x2a,0xfa,0x13,0x95,0x13,0xd7,0x76,0xfc,0xb3,0xc5,0xee,0x7f, + 0x76,0xe9,0xae,0x1b,0x23,0x03,0xa8,0x30,0x3f,0xe2,0x56,0x49,0x37,0xee,0xc8,0xfa, + 0xe5,0xcc,0xfa,0xf7,0x34,0x7a,0xa1,0x0d,0x98,0x88,0x79,0x13,0x26,0x74,0x86,0x70, + 0xd8,0x8e,0x8c,0x17,0xf2,0xec,0x71,0xe0,0x1f,0x18,0x95,0xac,0xfb,0xc7,0x69,0xa3, + 0x5a,0x82,0xec,0xdf,0x38,0xbd,0x5b,0xf5,0x46,0xdd,0xc3,0x52,0x4e,0xfc,0x93,0x8a, + 0x77,0xcf,0x60,0x98,0xc3,0xee,0x6d,0x63,0xda,0x71,0xc3,0x58,0xcc,0x22,0x7e,0xb3, + 0x13,0xff,0x38,0xfa,0xff,0x5c,0x20,0xfc,0x43,0x18,0x65,0x9f,0x61,0x89,0xd6,0xfa, + 0xbd,0xd2,0xea,0x1c,0xf8,0x47,0xb0,0xdd,0x6f,0x7d,0x38,0x9b,0x61,0xae,0x86,0x69, + 0x32,0x25,0x67,0xfd,0xbb,0x35,0x3f,0xfb,0xc0,0xb3,0x9d,0x4d,0x4b,0x82,0x44,0x20, + 0x40,0x57,0xc4,0x49,0x09,0x4d,0x29,0xa2,0x6d,0xf8,0xa7,0xc2,0x00,0x39,0xee,0x7d, + 0x9d,0x7b,0x60,0x0c,0x9a,0x67,0x7a,0x23,0x9d,0xbc,0x11,0x96,0x84,0x27,0x10,0xc5, + 0x5e,0x57,0xf9,0x8e,0xdb,0x86,0x7f,0xb0,0xff,0xb3,0x3f,0x15,0xbf,0x4c,0xe1,0x93, + 0xfa,0x4f,0x2e,0x34,0xdc,0xec,0xa7,0x50,0x06,0xfe,0x01,0xc0,0xba,0x08,0xcc,0xfa, + 0x2b,0x53,0x18,0x60,0xff,0x27,0x01,0x7b,0x3b,0x8d,0x79,0xe0,0x29,0x0c,0xfb,0xbf, + 0x2e,0xa8,0x04,0xf6,0x71,0x28,0x53,0x19,0xff,0x9e,0xe7,0x23,0xf9,0x98,0x3a,0xf3, + 0x2c,0xaf,0x61,0xfb,0x37,0xf5,0x8d,0x86,0xf1,0xef,0x79,0xfe,0x1f,0xfb,0xef,0x3f, + 0xd9,0xfc,0x2b,0x78,0x96,0xdf,0x20,0xdc,0xc9,0x80,0xd1,0x14,0x86,0xf4,0x7f,0xfc, + 0xfc,0xff,0xe0,0xf9,0x97,0x14,0xfa,0x07,0xcc,0xb9,0x60,0xf9,0x93,0x3f,0xf6,0x5f, + 0x53,0xd3,0x1f,0x72,0x97,0xd7,0xfb,0x7f,0xf8,0xf8,0xff,0x17,0xfe,0xb5,0x4c,0x4e, + 0x4e,0xea,0x9f,0x60,0xfc,0xff,0xf9,0xfe,0xff,0x64,0xdf,0xe3,0x7f,0xf9,0xc3,0xff, + 0xf2,0x87,0xff,0x8e,0xf9,0xff,0x2f,0x7f,0xf8,0x49,0xff,0xfe,0xb3,0xf9,0x9f,0xff, + 0x5c,0xf7,0xeb,0x05,0xe7,0xe1,0x38,0x6d,0xd1,0x3c,0x23,0xe2,0xb3,0xf0,0x2f,0x94, + 0x57,0xc3,0x71,0x7e,0x35,0x5f,0x7e,0x50,0xf9,0x4b,0xb8,0x8f,0x2e,0x08,0xcb,0xbb, + 0x4b,0x6b,0xf9,0x69,0xb0,0xb9,0xf3,0x83,0x69,0x7e,0x8c,0xad,0xd9,0x08,0xb6,0xd9, + 0x8f,0x95,0x6e,0x51,0xbe,0x0f,0xd5,0x7a,0xee,0xfc,0xa0,0x8d,0x1f,0x7b,0x4b,0xb9, + 0xaf,0xbb,0x96,0x3d,0x1f,0xd5,0xe0,0x42,0x9e,0xfc,0xe0,0xb8,0xb5,0xdf,0x14,0xca, + 0xfe,0x49,0x3a,0xd6,0xdf,0xec,0x0f,0xa8,0x33,0xf6,0x48,0xbf,0x56,0x1b,0x8c,0x32, + 0xc6,0x89,0x8c,0xfc,0x9d,0x2d,0x3f,0x08,0x5b,0xc8,0x15,0xb8,0x91,0xed,0x0e,0xd8, + 0x6e,0x73,0x52,0x6d,0x31,0xfa,0x23,0x4d,0x95,0x1f,0x7c,0x02,0x9b,0xe4,0x2c,0x0b, + 0x44,0xc4,0x3d,0x74,0x42,0x6e,0xd4,0x03,0xb9,0xf2,0x5f,0xce,0xfc,0xe0,0x7d,0xb4, + 0x56,0xef,0xde,0x4f,0x8a,0xd9,0xee,0x40,0x1d,0xc9,0xf9,0xfe,0x76,0x7d,0xd4,0x32, + 0x78,0x78,0x7d,0x20,0x24,0x57,0x87,0xb6,0x42,0xaf,0xe2,0x77,0xb4,0x65,0xcb,0xd9, + 0x1f,0xe0,0x2a,0xed,0x11,0x54,0x6f,0xae,0x0d,0xcd,0x56,0x5b,0x68,0x65,0x72,0x79, + 0xae,0x7c,0x99,0x5d,0x1f,0x25,0xc1,0x2b,0x5d,0x4d,0x5a,0x40,0x15,0xb7,0xc0,0x87, + 0xea,0x62,0xdd,0x93,0x6a,0x0b,0x99,0xcc,0xd7,0x1f,0x72,0x3f,0x79,0x07,0x5a,0x86, + 0xbc,0x61,0xde,0x5f,0xf4,0x46,0xfd,0xf3,0x46,0x23,0x71,0x7e,0xac,0x5e,0x8e,0xfc, + 0xa0,0x5f,0xfa,0x31,0xbc,0xc8,0xb6,0xb1,0x25,0x31,0x71,0x9d,0x34,0x41,0x50,0x48, + 0x4f,0xb2,0xe7,0x27,0xfd,0xf7,0x4d,0x28,0x8f,0xc1,0x26,0xa1,0xb2,0x5f,0xc6,0xf3, + 0x61,0x0f,0xc0,0x8e,0xdc,0xf9,0x85,0x73,0x36,0x7f,0xf5,0x00,0x3c,0x70,0xdf,0x9c, + 0xb0,0x6b,0x64,0xee,0x57,0x90,0xdf,0xe0,0x8d,0x92,0x64,0x6b,0xbc,0x3f,0x31,0x8c, + 0x84,0x3d,0x3f,0xb8,0xbc,0x9b,0xa8,0xbf,0x95,0xeb,0x78,0xbf,0x71,0xd5,0x31,0x8d, + 0x39,0xf2,0x83,0xc9,0xf2,0x43,0xf0,0x00,0x5d,0xb4,0xbd,0xe4,0x8e,0x3b,0xd7,0x96, + 0x5d,0x39,0x55,0x67,0x10,0x0b,0x99,0x1d,0x93,0xc6,0x33,0xf4,0x51,0x4d,0xe0,0xed, + 0x42,0x35,0x26,0x34,0x2b,0x9f,0x98,0x1f,0x1c,0x16,0x2e,0x44,0xeb,0xda,0x78,0xdb, + 0x9c,0x0b,0x94,0x57,0x3f,0x59,0x0c,0xc9,0x9a,0x3c,0xfd,0x01,0xc8,0xce,0x0d,0xf2, + 0xb6,0xc8,0x1c,0xd8,0x9b,0xf0,0xad,0x2d,0x49,0xa7,0xa5,0x42,0x79,0xfb,0x43,0xfa, + 0x34,0x88,0x62,0x7f,0x00,0xb5,0xa6,0xcd,0x4a,0x63,0xcd,0xcc,0x9d,0x1f,0x04,0x29, + 0x76,0x10,0x65,0xe1,0x46,0x7f,0x00,0xbf,0x36,0x33,0x57,0xbe,0x2c,0xdd,0x9f,0x64, + 0x83,0x1c,0xa6,0x87,0xa0,0x4e,0xae,0x35,0xfa,0x03,0x1c,0x72,0x0c,0xd3,0xa2,0xce, + 0x4e,0xdb,0xfa,0x43,0x9e,0x2f,0xfa,0x37,0xb8,0x11,0xcf,0x7b,0x1d,0x96,0xff,0x0d, + 0x17,0x46,0x2e,0x62,0xd0,0x5e,0x1f,0x77,0x1e,0x5e,0x82,0xfa,0x90,0x67,0x68,0xda, + 0x79,0xf9,0x32,0x2c,0xd1,0x66,0x19,0xc7,0xc8,0xb6,0x20,0x6d,0x98,0xf3,0x7c,0x90, + 0x33,0x6d,0xdd,0x05,0x3e,0x45,0x66,0xae,0x07,0x85,0x04,0x30,0xdb,0x2a,0x94,0xcb, + 0x77,0x3e,0xc8,0x35,0x9b,0xa9,0x1a,0xf6,0x07,0x0b,0x07,0xd8,0x6c,0xf8,0x35,0xab, + 0x2d,0xa4,0xbd,0x3f,0xa4,0xed,0x7c,0xd8,0xf2,0x5d,0x32,0x6f,0x4b,0xfe,0x5d,0xd4, + 0x47,0x15,0xf9,0xd2,0x6d,0x21,0xe5,0x9c,0xf9,0xc1,0xd8,0xf4,0x37,0x83,0xfd,0x74, + 0x5f,0xbb,0xe7,0xb1,0xc2,0xe1,0x32,0x2c,0x73,0x4b,0xb5,0xb5,0x6c,0x72,0xf4,0xb7, + 0xb4,0xf7,0x47,0xfa,0xf1,0xb2,0x1b,0x14,0x73,0x36,0xa2,0xf9,0xce,0x87,0xb5,0xf3, + 0x63,0x42,0xa2,0x28,0x88,0x6a,0xf0,0x58,0x45,0xe2,0xb6,0x46,0x58,0x35,0x75,0x7e, + 0x50,0x2d,0x90,0x85,0x07,0xe4,0xaa,0x7b,0xbb,0x87,0xc5,0x3e,0xf6,0x69,0x56,0xc6, + 0x3c,0x6c,0x3d,0x2b,0x87,0x60,0x81,0x33,0x3f,0x68,0xf1,0x63,0xfe,0x2e,0x8f,0x10, + 0xd1,0xd4,0xb8,0x3c,0x77,0x6e,0x1b,0xa5,0xba,0xbf,0xd4,0xcc,0x0f,0xd2,0xd4,0xf7, + 0xe2,0xcf,0xc8,0x0f,0x82,0x07,0x36,0x81,0x4a,0x65,0xec,0x0f,0xb0,0x47,0xab,0x54, + 0x52,0x65,0xf2,0x5f,0xa7,0x79,0xf2,0x83,0xdd,0xb3,0x95,0x4d,0x91,0x85,0x6a,0x60, + 0xad,0xf8,0xdf,0xa5,0x01,0x7a,0x43,0xf8,0xba,0x14,0x2d,0x16,0x4b,0xe5,0x07,0x6f, + 0xc8,0xc8,0x0f,0x7a,0xf6,0x90,0x0f,0x8d,0x8f,0x8e,0xc2,0x98,0xd0,0xa4,0xa5,0xdb, + 0x62,0x1b,0x46,0x83,0x93,0x1f,0xd3,0xca,0x4f,0x6b,0xff,0xa0,0x2c,0x8c,0x79,0xba, + 0xc9,0x69,0xed,0xf7,0x74,0xa1,0xca,0xe2,0xd7,0x03,0xe4,0xe5,0xe8,0x8d,0xb1,0x5a, + 0x7b,0x7e,0x30,0xcd,0x8f,0x5d,0xfd,0x98,0xde,0x19,0xaf,0xa4,0xf2,0x0a,0xf1,0x15, + 0x3a,0x00,0x3b,0xba,0xe5,0x31,0x32,0x9b,0x6e,0x8a,0xcd,0xdf,0x9d,0x3a,0xef,0xe3, + 0x06,0xdd,0xd9,0x1f,0x92,0x3e,0x53,0xb4,0xb5,0x6e,0x0e,0x95,0xb5,0x9b,0x4e,0xc8, + 0xfb,0xe5,0x4a,0xa1,0x68,0x8c,0x3c,0x86,0xfd,0x30,0xbb,0xe5,0x9c,0xf9,0xc1,0xb0, + 0xf4,0x92,0xd0,0x39,0xbd,0x3a,0xe6,0x87,0x7b,0x75,0xa0,0x47,0x18,0x5c,0xb3,0xca, + 0xa0,0x72,0xe7,0x07,0xa5,0x3d,0xea,0xd1,0x8e,0xeb,0x9f,0x67,0x7f,0x5f,0x5d,0x8a, + 0xd3,0x3a,0xb8,0x1f,0xeb,0xbb,0x7b,0x0a,0x9a,0x69,0x4d,0xce,0xfc,0x20,0xd6,0x67, + 0xbd,0x0b,0x8d,0x51,0xef,0x46,0xf4,0x3f,0x2a,0xef,0x86,0xed,0x98,0x9f,0xc6,0x4c, + 0x7e,0xec,0x19,0x75,0x12,0x16,0xc1,0x16,0x5d,0x8c,0xc3,0xa0,0xb6,0x44,0x33,0xdd, + 0x38,0x4d,0x19,0x8b,0xb2,0xf2,0x83,0xd0,0x3b,0xe0,0xa3,0xb2,0x4c,0xaa,0xe8,0xb8, + 0xee,0x0b,0xbb,0xb1,0x3f,0xcf,0x61,0xec,0x2f,0x91,0x3b,0x3f,0x88,0xfd,0x01,0xf4, + 0xb9,0x11,0x79,0x0b,0xd9,0x09,0xf7,0x69,0x35,0xaa,0x79,0x1b,0x4d,0x2b,0xa6,0xb2, + 0xf4,0x51,0xf2,0x5c,0x2a,0xd3,0x10,0xd0,0x3e,0xf6,0x9a,0x78,0x30,0x04,0xed,0x95, + 0x03,0x91,0xd6,0xbc,0xfd,0x01,0x26,0xd4,0x06,0xea,0x89,0x74,0xc6,0x68,0x02,0x1a, + 0xc1,0x68,0x3b,0xac,0x36,0x3f,0x66,0x5f,0x0f,0xce,0xfe,0x90,0x1f,0xce,0x5b,0x42, + 0xbd,0xba,0x98,0xfc,0x1c,0x9e,0x50,0xc1,0xcb,0x9a,0xf8,0xfc,0xe4,0xce,0x0f,0x6e, + 0x34,0x17,0x49,0x55,0xca,0x18,0x9b,0xf6,0x91,0xf6,0x46,0x74,0x91,0xd1,0x31,0xe0, + 0x8d,0xa6,0x7a,0x95,0x19,0x71,0xeb,0x3c,0x6b,0xbd,0xc2,0xc8,0x0f,0xa6,0xd1,0xce, + 0x33,0xa1,0xd1,0xd2,0x1e,0x3c,0xdf,0xb6,0x8e,0x78,0xe8,0x26,0xd5,0xb7,0x83,0xfd, + 0x34,0x66,0xf9,0xff,0x04,0x6c,0x51,0x9c,0xd1,0xe7,0x7a,0x36,0x2d,0x8f,0x73,0x1a, + 0x30,0xb2,0x52,0x7d,0x18,0x54,0x8d,0xfd,0x74,0x2e,0xad,0x0f,0x97,0xf6,0x64,0xa1, + 0x85,0x51,0x9a,0x6a,0x0b,0x19,0x80,0x99,0xc2,0xed,0xda,0x4c,0xbb,0x3e,0xfc,0xb3, + 0xe5,0xa3,0xfc,0x3c,0x3b,0x5b,0xb4,0x25,0xc7,0x95,0x17,0x85,0x06,0x7d,0x55,0x7c, + 0xfa,0x3a,0xe9,0x75,0xa9,0x6e,0x0e,0xfb,0x29,0x66,0xf9,0x9f,0x58,0x4a,0x1f,0xbe, + 0xd5,0x36,0x1b,0x57,0xe0,0x1f,0x52,0xf8,0x47,0x79,0x1f,0xbc,0xfd,0x8e,0xfe,0x90, + 0x98,0x1f,0x7c,0xd7,0xf9,0xfc,0x3f,0x31,0x96,0x19,0xf6,0x9f,0x54,0x5f,0x64,0xa1, + 0x81,0xfd,0xf4,0x81,0xb5,0x3e,0x4f,0x64,0xd4,0x4b,0xe2,0xc1,0x3a,0xcc,0xe8,0xae, + 0xfd,0x6d,0x71,0x5f,0xe7,0x1d,0xea,0x1b,0xa4,0xae,0x9d,0xcd,0xe6,0x47,0xd6,0x7a, + 0xd0,0xa5,0x95,0x59,0xd1,0x79,0x25,0xcc,0x68,0x0b,0x24,0xe4,0x7d,0x64,0x0f,0xfc, + 0x00,0xaa,0x95,0x1e,0xc7,0xf9,0x68,0x8a,0x51,0x26,0xef,0xbe,0xab,0x90,0xa3,0x9d, + 0xb7,0x2d,0xd8,0x83,0x1d,0x23,0xa3,0x07,0xa2,0x95,0x31,0x76,0x65,0xdc,0x86,0x7f, + 0x56,0x1a,0x20,0xa7,0x91,0xa1,0x9d,0x5e,0x25,0x90,0x74,0x2f,0xb9,0x69,0x50,0xf9, + 0x10,0x38,0x10,0x7a,0x80,0x3e,0x1f,0xbf,0x7e,0xd4,0xeb,0x38,0x1f,0xb6,0x1c,0xfb, + 0x43,0xde,0x63,0x76,0x43,0x42,0xf6,0x98,0x37,0x0a,0x58,0x34,0xc0,0xf3,0xe9,0x6f, + 0x40,0xcb,0x11,0xc4,0x3f,0xd6,0xfc,0xcb,0xd2,0x9e,0x74,0x7e,0x10,0x0b,0x57,0x4b, + 0xe2,0x55,0x28,0x94,0xe2,0x07,0xd5,0x8d,0x0a,0x2f,0xf6,0xd7,0xc9,0x5b,0x1d,0xfa, + 0xf0,0x0a,0x67,0x7f,0x80,0x7e,0xf7,0x37,0x7d,0x58,0x16,0x57,0xc5,0x1b,0x05,0xe0, + 0x89,0x69,0x83,0x45,0x0c,0xff,0xa8,0xe6,0xf3,0x1d,0xf9,0x41,0x6e,0x7c,0x9b,0xe0, + 0x89,0x69,0x73,0xf8,0x78,0xe1,0xe1,0xef,0xfd,0x08,0xc7,0x9b,0xb4,0xf0,0xea,0x88, + 0x9d,0x9f,0xaf,0x37,0x8c,0xe3,0xa1,0x1e,0x53,0x68,0x27,0x1a,0x08,0x3c,0xad,0x0f, + 0x4f,0x96,0x8f,0x28,0x06,0xc8,0x31,0x60,0x4f,0xc7,0x3f,0xc4,0x44,0x3c,0x31,0xad, + 0x81,0x9f,0x27,0x25,0x1e,0x33,0x5a,0x07,0xd8,0xf0,0x8f,0xe0,0xac,0xd7,0x36,0x8f, + 0x45,0xbb,0xcb,0xcc,0x18,0x36,0xc2,0xb4,0x3c,0xf9,0xc1,0x94,0xa1,0x54,0x55,0xf3, + 0x7e,0xc8,0xdd,0xbc,0x10,0x4c,0xe0,0x89,0xb0,0xbc,0xfd,0x01,0xb8,0x50,0x19,0x1b, + 0x25,0xed,0xd4,0xfc,0x51,0x57,0xb5,0x6b,0x33,0x94,0x24,0x1d,0xf8,0x67,0x71,0x41, + 0x46,0x37,0x24,0x16,0xaf,0xab,0x55,0x3c,0x1f,0xad,0x07,0x11,0xd1,0x66,0xde,0x31, + 0xc0,0xd6,0x1f,0xc0,0x5f,0x86,0xf9,0xc1,0x6a,0x5e,0x2f,0x0f,0x0f,0xf2,0xfe,0x48, + 0xf7,0xe1,0x95,0x30,0xd2,0x0f,0x58,0x3a,0x97,0xd1,0x1f,0x69,0x43,0x66,0x7f,0x00, + 0x6f,0x44,0x64,0xab,0x10,0x4a,0xa1,0x84,0x56,0x51,0x48,0x18,0x47,0xa7,0x9d,0xb5, + 0xea,0xeb,0xb7,0x67,0x9e,0x97,0xc1,0x46,0x77,0x3e,0x75,0x3e,0x48,0x64,0xf8,0x47, + 0xd8,0x3a,0xdb,0x1b,0x9d,0xf1,0x51,0xce,0xfe,0x00,0x86,0xf1,0x50,0xe7,0xef,0xe1, + 0x35,0xa5,0x41,0xf3,0x60,0x7d,0xdc,0x6b,0x59,0x7a,0xaa,0x8a,0xb4,0x3e,0x9c,0x1b, + 0x62,0x17,0x33,0xba,0x19,0x10,0xc2,0x63,0x2b,0x61,0x44,0xe5,0x3f,0x9d,0x4e,0xe3, + 0x1f,0xb0,0xe5,0x07,0x1f,0x34,0x8d,0xef,0xaa,0xf3,0x97,0xcb,0xed,0xe4,0x16,0xfa, + 0xe0,0xe7,0x02,0xe1,0x99,0xf6,0xfe,0x48,0xdb,0xa5,0x5d,0x59,0xea,0xb2,0x01,0x7a, + 0x3f,0x99,0xaf,0xe1,0xfd,0xe6,0x54,0xdb,0xf4,0xe1,0x99,0xe3,0xc5,0xb7,0xe5,0x7a, + 0x6f,0x7f,0xd4,0xbd,0x46,0x7a,0x4d,0x68,0x0e,0x7b,0xa3,0x64,0xc4,0xd2,0xe7,0x24, + 0x1c,0xfd,0x01,0xd2,0x46,0x0a,0x18,0x17,0xc1,0xec,0x35,0x0e,0xfc,0x23,0x67,0xf4, + 0x07,0x60,0xc6,0x34,0x23,0x51,0xc8,0x3c,0xfc,0x18,0x76,0xcc,0xc6,0x7a,0xcc,0x63, + 0xd4,0x5c,0xff,0x19,0xfa,0x70,0x34,0x0a,0x47,0x78,0x07,0x0c,0xbc,0x22,0x19,0x86, + 0xd8,0x9d,0x5e,0x0f,0x52,0xd6,0xee,0xe0,0xe6,0x41,0xdc,0xb8,0xa1,0x50,0x3c,0x81, + 0x19,0xf6,0x01,0x87,0x3e,0x9c,0x2a,0xb7,0x9a,0xdf,0xef,0xad,0xb6,0x44,0x21,0xcc, + 0x01,0x51,0x23,0xaf,0xc2,0x81,0x6d,0x73,0x10,0x08,0x8d,0x68,0xe6,0xf3,0xbb,0xbb, + 0xbf,0x92,0x4a,0x02,0x12,0x33,0x1b,0x48,0x4e,0xb2,0x40,0x53,0x99,0xdc,0xba,0x41, + 0x3c,0x09,0x1f,0xc6,0x17,0x1a,0xe7,0xa3,0x99,0xeb,0x4d,0x76,0xea,0xa5,0xb1,0xde, + 0x67,0xc6,0x08,0x8c,0x4b,0x77,0xa0,0x42,0x6c,0x18,0x26,0xb4,0xc6,0xed,0xec,0xa7, + 0xc8,0xbd,0xe6,0xfc,0x40,0xd9,0xb3,0x2c,0x5a,0x2d,0x31,0xce,0x77,0x78,0xc3,0x6c, + 0x14,0x90,0xd2,0xf7,0xde,0xc5,0xfe,0x87,0xee,0x39,0xcf,0xae,0x8c,0x59,0xf3,0xff, + 0xa4,0x62,0xf6,0x87,0xe4,0xfe,0x27,0xf0,0x36,0x1b,0xe6,0x69,0x6d,0xff,0xce,0x1b, + 0x02,0x6e,0x8d,0x48,0x5a,0xaf,0x52,0xcd,0xf1,0x8f,0x35,0xff,0x00,0x8f,0x09,0x76, + 0x7f,0x95,0x70,0xaf,0x57,0x4e,0x44,0x53,0x8a,0xf1,0xff,0x8e,0x57,0xda,0x57,0xac, + 0xb7,0xed,0xdf,0x55,0x65,0x4b,0x96,0x3f,0x4f,0xc8,0x71,0xc9,0x0f,0x6e,0x60,0xdf, + 0x57,0x2f,0x54,0x87,0x33,0xfa,0x03,0x18,0xd1,0xc4,0xda,0xad,0x5f,0x17,0x27,0x67, + 0xbb,0x27,0x8c,0xfe,0x72,0x6b,0xd1,0x03,0xb7,0xb1,0xf1,0x9e,0x4e,0xeb,0xc3,0x85, + 0x3d,0x52,0xc6,0xfc,0x60,0xa2,0x50,0xe0,0x65,0x02,0xc3,0xf2,0x04,0xcc,0x56,0x1c, + 0xfd,0x91,0x2a,0x95,0xac,0x78,0xd7,0x3a,0x6e,0x1c,0x14,0x82,0x8a,0x29,0x76,0x25, + 0xec,0x19,0x63,0xfb,0x77,0xf3,0xfe,0x1d,0x92,0x71,0x3e,0xac,0x01,0x7b,0x52,0x6c, + 0x03,0x3c,0xc3,0x22,0xb6,0x5b,0x27,0xe7,0xd9,0xff,0x62,0x00,0xe4,0xb8,0x2f,0xed, + 0x7f,0xb0,0x3f,0x40,0xe6,0xe9,0x15,0xa3,0x90,0x92,0x85,0x8f,0x60,0xab,0x9c,0x6d, + 0x8e,0xfe,0x00,0xae,0x32,0x4f,0x3a,0xcc,0x3d,0x0c,0x81,0xa3,0xd8,0x38,0x48,0x8d, + 0x57,0x86,0x89,0x08,0x75,0x03,0x4a,0xaf,0x52,0xdb,0xe5,0x77,0xe0,0x9f,0xfb,0x59, + 0x58,0x41,0x7d,0xf8,0x53,0x33,0x46,0xb1,0x51,0xf3,0xa9,0x9e,0xfd,0x5f,0x1d,0xa1, + 0x13,0x6a,0x5d,0xa2,0x24,0x28,0xbe,0x8d,0xf3,0x03,0x2c,0x10,0x27,0xd3,0xe7,0xc3, + 0x96,0x5f,0x82,0x09,0x85,0x9f,0x0f,0x8b,0xea,0xaf,0xe6,0x97,0x5e,0x3e,0xd7,0x39, + 0x0e,0x97,0x94,0x16,0xfc,0x5e,0xce,0xc7,0xde,0x57,0x5b,0x8a,0x1c,0xf8,0xa7,0xbf, + 0x20,0x0e,0xef,0x09,0xd3,0xcf,0x04,0xc6,0xc5,0x66,0x98,0xec,0xba,0x51,0xf5,0x8c, + 0x73,0xa1,0x78,0x4b,0x1e,0xfe,0x47,0x97,0x93,0x42,0x31,0xf5,0xe9,0xfe,0x3e,0x82, + 0xfa,0xf0,0x5a,0xd5,0x35,0x35,0xff,0x73,0x4c,0x8a,0xc1,0x0e,0xca,0x9b,0xf2,0xe1, + 0xc0,0x6b,0x21,0x27,0xbf,0x61,0xe3,0x7f,0xa4,0xc7,0xe5,0xcd,0x2a,0x46,0x2b,0x29, + 0xe0,0x61,0xf3,0xa9,0xba,0xa6,0xd6,0x87,0x2f,0x2d,0x7f,0x1b,0x76,0x40,0x10,0xa3, + 0x79,0x40,0x9a,0x90,0x9a,0x82,0xf6,0x63,0xf5,0xd2,0xfd,0x21,0xad,0xf3,0x61,0xe3, + 0xc2,0x6e,0xf9,0x02,0xe5,0x41,0x9c,0xaf,0x07,0xc8,0xad,0x0f,0xb7,0xf5,0xc7,0x7e, + 0x12,0x8e,0xc2,0x3e,0xab,0xdb,0x24,0x94,0xe4,0x7a,0xbe,0xbd,0x3e,0x4e,0x86,0x13, + 0xe0,0x3b,0xc3,0xd0,0x0b,0x7f,0xdb,0xd2,0x4f,0xe2,0x7f,0xa4,0x65,0xd0,0x19,0x56, + 0x93,0xae,0x3a,0xec,0x8e,0x0e,0x01,0xd9,0x95,0x6b,0x7e,0xc6,0xd2,0xf8,0x07,0xbe, + 0x1c,0xfa,0x2e,0xad,0x1c,0x96,0x53,0xfd,0x91,0x62,0x90,0x02,0x06,0x79,0xce,0x07, + 0x59,0x5b,0xa1,0xc1,0xf3,0x34,0x7e,0x04,0x65,0xe1,0x03,0x1f,0x4a,0x4d,0xed,0x25, + 0x4b,0xc4,0xe3,0x90,0x6a,0x0b,0x69,0xf1,0x3f,0x27,0xd3,0xfc,0xcf,0xd5,0x71,0xe1, + 0x3d,0xb0,0xce,0x97,0x69,0xd6,0xec,0x8d,0x02,0x72,0xea,0xc3,0xf7,0x28,0x2f,0xb6, + 0xd5,0x25,0x4b,0x16,0xf3,0xfe,0x00,0x4d,0x6a,0xf1,0xd4,0xfa,0xf0,0xc4,0xd5,0x8f, + 0xc1,0x2f,0x79,0x37,0x00,0xce,0xff,0xcc,0x07,0x39,0x17,0xff,0x73,0xd1,0xa6,0x8f, + 0x8a,0xa8,0x0f,0x73,0xda,0xa7,0x90,0x17,0x06,0xae,0xe7,0xb0,0xe7,0x11,0x3a,0x3f, + 0x8f,0x3e,0x3c,0x21,0xdd,0x27,0x77,0x42,0x8c,0x81,0x9c,0xab,0xf8,0x87,0xa6,0x15, + 0x05,0xe7,0x4e,0xcd,0xff,0x8c,0xc3,0x0f,0x63,0x75,0x88,0x7f,0xf0,0x34,0xb4,0x96, + 0x58,0xb1,0xa3,0x51,0x76,0x36,0xff,0x23,0xc4,0xa6,0x8d,0x85,0xd9,0x32,0xe8,0x42, + 0x7d,0xb8,0x71,0x5e,0xe7,0x27,0xe9,0xc3,0xf1,0x90,0x2f,0xef,0x43,0xfc,0x18,0xd0, + 0x86,0xb5,0xb6,0xc0,0x27,0xe4,0xd2,0x87,0xc3,0x1a,0xd8,0x9c,0xf4,0xb5,0xbb,0x51, + 0x4f,0x9e,0x57,0xef,0x6d,0xc7,0x3f,0x52,0xe1,0x66,0x69,0x67,0x78,0x66,0x94,0xfc, + 0x08,0xcf,0xf3,0xca,0xa7,0x0f,0x37,0xd7,0x83,0x5f,0x92,0xf8,0xb1,0x68,0x16,0xdb, + 0x93,0x9b,0xff,0x49,0xe3,0x1f,0x4f,0x98,0x26,0x54,0x9c,0x1f,0xce,0xff,0x38,0xdb, + 0x42,0xa6,0xf5,0xe1,0xb6,0xfa,0xb8,0xfd,0xb1,0xcb,0xd0,0xb4,0xdc,0x1b,0x9d,0xb6, + 0x8b,0xd3,0x38,0xa8,0x0f,0x97,0xa6,0xe2,0x7f,0xfe,0x8d,0xfe,0xab,0xa7,0x5e,0xf3, + 0x0c,0x89,0xdf,0x62,0xbf,0xde,0xe8,0xa0,0x4d,0x72,0x9f,0x0f,0xd2,0xd5,0xad,0xed, + 0x04,0x3f,0x0d,0x31,0xfc,0x43,0x4c,0xda,0x47,0xc8,0xab,0x0f,0xd7,0x36,0x76,0x3d, + 0x88,0x7c,0x97,0x39,0x3a,0xd7,0xd4,0xfa,0x70,0x86,0x7f,0x2a,0x1e,0x65,0xe8,0x91, + 0x57,0x03,0xb1,0xd9,0xbb,0x05,0x8c,0x69,0x2c,0xc9,0xa3,0x0f,0x8f,0x95,0xbf,0x15, + 0x7e,0xcd,0x13,0xd4,0x56,0x46,0x5b,0x39,0x9b,0xb7,0x3e,0xe0,0xd0,0x87,0x67,0xf1, + 0x3f,0x09,0xe1,0xc7,0xd2,0x19,0x78,0xd6,0xf1,0xd7,0xcf,0xc1,0xff,0x58,0xfe,0x47, + 0x56,0x76,0x40,0xe2,0xb6,0x3a,0xc9,0x13,0x31,0x66,0x5b,0x31,0x8e,0x05,0x21,0x25, + 0x79,0xfb,0x43,0x2e,0x0e,0x3f,0xa0,0x55,0xc5,0xe5,0x24,0xb9,0x60,0xf4,0x47,0xca, + 0xa5,0x0f,0xb7,0xd5,0xc7,0x49,0xff,0x03,0x22,0x5a,0xac,0x93,0xcd,0x4f,0x02,0xfb, + 0xd5,0x6c,0xe0,0x65,0xb9,0xd9,0xfa,0x70,0x2b,0xde,0x31,0xfc,0xd3,0xc9,0xd0,0x8e, + 0xbc,0x8c,0x9c,0x62,0xc0,0x60,0x41,0xf4,0xaf,0x73,0x7d,0xbf,0xe9,0xfe,0xd8,0xdd, + 0xdd,0x77,0xc3,0x2f,0x69,0x7d,0x38,0xd0,0x26,0xbe,0xa2,0x30,0xfc,0x73,0x5b,0xc9, + 0x06,0x16,0xcd,0x3f,0xee,0x72,0xea,0xc3,0x6d,0xe7,0xc3,0x16,0xec,0x99,0x31,0x81, + 0x45,0x7f,0x31,0x43,0x0d,0x05,0x39,0xfd,0x89,0xad,0x3e,0xae,0xeb,0x59,0xe5,0x97, + 0xf7,0xd6,0xc7,0x3c,0x89,0xd6,0x93,0x0c,0xff,0xdc,0xa8,0xda,0xc3,0x56,0xae,0xf3, + 0x61,0x2b,0x1e,0xd3,0xc4,0xe9,0x8b,0x40,0x5e,0x4a,0x12,0xda,0x26,0x98,0x5f,0xe8, + 0x42,0x20,0xc4,0x36,0x86,0x8e,0xf7,0x77,0xf6,0x47,0xda,0x8a,0x7a,0x7b,0x54,0x7f, + 0x3d,0x82,0xb2,0xa8,0x5c,0xe3,0xb5,0xf5,0x07,0x60,0xfb,0xaf,0x4e,0x7d,0x2e,0x66, + 0xe9,0x74,0xb6,0xdb,0x0a,0x40,0x4e,0xfe,0xd9,0x81,0x7f,0x68,0xbf,0x5e,0x47,0x3d, + 0x54,0xd0,0x91,0x66,0x0f,0x7b,0xe3,0x42,0xf6,0x78,0x6d,0xe7,0xc3,0x0a,0xbb,0xc9, + 0x05,0xb6,0xe9,0x58,0xd5,0x85,0xc7,0x94,0xb3,0xf9,0xa9,0xcd,0x35,0x3f,0xe9,0xfe, + 0xd8,0x95,0xca,0x63,0xdd,0x2f,0x03,0xfb,0xbe,0x06,0x59,0x10,0x7f,0x9f,0x7d,0x8f, + 0xa9,0x7a,0x1f,0xaf,0x23,0xde,0xd9,0xf2,0x23,0xd2,0xdf,0xd0,0x9e,0x63,0x35,0x20, + 0x77,0x93,0xdf,0xe1,0x69,0x02,0x6a,0x71,0xae,0xf8,0xe5,0xec,0x8f,0xf4,0x44,0x87, + 0x8f,0xb2,0xcf,0xd0,0xa7,0x32,0x20,0xa4,0x5e,0x9d,0xf3,0x7e,0x9b,0x3e,0x5c,0xc2, + 0x26,0x24,0xec,0xff,0x48,0x3f,0x5b,0x48,0xb5,0x70,0xf5,0x42,0x63,0x5a,0x86,0xf2, + 0xe8,0xc3,0xef,0x5f,0x09,0x3f,0x55,0xb0,0x3e,0x45,0x54,0x91,0x88,0x60,0xeb,0x61, + 0xc6,0x7b,0x5a,0x56,0xfd,0x57,0x5a,0x1f,0x55,0x7e,0x1e,0x26,0xab,0x39,0xda,0x19, + 0xa3,0x3c,0xbe,0x9f,0xc3,0x63,0x61,0xfd,0xfc,0x58,0xd8,0x3c,0xfa,0x70,0xac,0xaf, + 0x34,0xd3,0x5e,0x7a,0x71,0xa2,0xaa,0x8e,0x19,0x9c,0xff,0x39,0x07,0x83,0xb4,0x65, + 0x30,0xab,0x3f,0xb6,0xc1,0xff,0xa0,0x50,0x9c,0x2e,0x48,0xc2,0x76,0x32,0xb7,0xe2, + 0x30,0xd4,0x20,0xec,0xf9,0x2d,0x3c,0x19,0x59,0x30,0x98,0xd5,0x1f,0xbb,0x97,0xa4, + 0xce,0x87,0xc5,0xb2,0xd3,0x22,0x5a,0x0a,0xf0,0xb0,0x51,0xa6,0xbd,0x1b,0xcb,0x11, + 0x13,0x59,0xfd,0xb1,0x1d,0xb3,0x27,0x47,0x7d,0x81,0x78,0x2f,0x3f,0x28,0x84,0x6d, + 0x44,0xad,0xf3,0x41,0xcc,0xbf,0xaf,0x5a,0x6e,0x83,0xc1,0x48,0xd4,0xdc,0x5f,0x20, + 0x56,0xc2,0x84,0xd1,0xd1,0x68,0x80,0x26,0x84,0xd4,0xf9,0x68,0xe6,0xf3,0x1d,0xfd, + 0x01,0x26,0x59,0xf4,0x77,0x8f,0xfc,0xe8,0xa3,0xd4,0x15,0xe1,0x63,0xf5,0xb2,0xd1, + 0x28,0x20,0x7f,0x7f,0x48,0xdd,0x43,0xf9,0xc2,0xe3,0x34,0xe3,0xdb,0xbc,0x82,0xc3, + 0x93,0xb3,0x3f,0xb6,0xf1,0xfe,0x0b,0xf4,0xb6,0x5d,0x22,0xb6,0x05,0x6b,0x48,0xe1, + 0x61,0x76,0x05,0xec,0xf8,0x47,0xcf,0x3c,0x1f,0x56,0xae,0x26,0xcb,0xb5,0x19,0x46, + 0xe2,0x46,0xd3,0xe2,0x61,0x43,0x1f,0x9e,0xa7,0x3f,0x00,0x83,0x3d,0xfe,0xd5,0xe4, + 0xa4,0x76,0x20,0x86,0x1d,0x14,0x43,0xaf,0xc0,0xd3,0x5d,0xf3,0xb1,0x5e,0xde,0x86, + 0x7f,0xb0,0x3f,0x40,0x34,0x80,0xe7,0xc7,0x71,0xb4,0x33,0xe2,0xa9,0x14,0x5f,0x18, + 0x98,0xa0,0x1b,0x30,0xff,0x35,0x00,0x1f,0x48,0x4d,0x89,0x40,0xce,0xfe,0x00,0x06, + 0xec,0x69,0xfe,0x4d,0xed,0x83,0x33,0x9e,0x99,0x9e,0x9a,0xb1,0x61,0x6d,0x62,0x75, + 0x66,0x7f,0xc8,0xf2,0x51,0x93,0x1f,0xe3,0x13,0x75,0xc2,0xbb,0xbf,0xf3,0x9d,0xfe, + 0x89,0x54,0x7f,0xf2,0xee,0x13,0x7a,0xdd,0xb9,0x29,0xfa,0x03,0xe0,0x7e,0xea,0x9b, + 0xa1,0x13,0x9a,0x71,0xbe,0x12,0xf9,0xd7,0xd8,0x53,0xea,0xf5,0x27,0xe4,0xcc,0xfe, + 0x00,0x3f,0x71,0xa0,0x9d,0xbf,0x23,0x1f,0x75,0xe1,0x15,0xd7,0x06,0xf2,0x06,0x3c, + 0x4b,0x2b,0x51,0x1f,0x3e,0x66,0xf1,0x3f,0x6d,0x52,0xca,0x7b,0xc7,0xcd,0xaf,0xa9, + 0x29,0x82,0x07,0x0d,0xf3,0xc6,0x77,0x83,0x65,0xbd,0x72,0x75,0x46,0x7f,0x80,0x82, + 0xdd,0xf0,0x8e,0x03,0xed,0xfc,0x18,0x0d,0x81,0xcb,0xc2,0xdf,0xd6,0x4e,0xf6,0xd7, + 0xd1,0xda,0xfc,0xfd,0x21,0x31,0x11,0x86,0xc6,0x76,0xa1,0x19,0xa6,0xb1,0xf8,0xcb, + 0xfb,0x43,0x16,0xe4,0x39,0x1f,0xd6,0x50,0x83,0x17,0x6f,0x47,0x22,0xc8,0xaa,0x17, + 0xe3,0xa9,0x10,0xe2,0xc4,0x3f,0x46,0x90,0x15,0x0d,0xa3,0xbb,0x8f,0xbc,0x4f,0x31, + 0xc3,0xc5,0xc2,0x2e,0xdb,0x91,0xe9,0x99,0xf9,0xaf,0x72,0x4b,0x1f,0x6e,0x18,0xf3, + 0xf6,0x62,0x9b,0x56,0x06,0x84,0xb0,0x9f,0x2a,0x0a,0xc5,0xf3,0xf6,0xc7,0xe6,0xf5, + 0x62,0x0c,0x18,0x84,0x10,0x06,0xa8,0x08,0x84,0x96,0x09,0xa9,0x8a,0xb9,0x9c,0xfd, + 0xb1,0xf1,0x7c,0xae,0x66,0xb9,0x98,0xb6,0xc6,0xa4,0x71,0x78,0xd6,0x8a,0xbf,0x28, + 0x14,0x3f,0x6b,0xef,0x0f,0xe0,0x44,0x3b,0x2f,0x47,0x2b,0x07,0xc0,0xa0,0x7d,0xd8, + 0x95,0x0f,0x60,0x8a,0xfe,0x90,0xfc,0x74,0x54,0x34,0xe4,0x0b,0xc8,0xff,0xa4,0xae, + 0xb4,0x79,0x1c,0xfc,0x8f,0xe2,0xe4,0x7f,0x14,0x99,0x03,0x21,0xf0,0xc1,0xe7,0x28, + 0x19,0x91,0xb1,0x51,0x76,0x76,0x7f,0x00,0x5e,0xfd,0x17,0x4a,0xe3,0x1f,0x61,0xaf, + 0x9a,0x46,0x80,0x37,0xcb,0x59,0xfd,0xb1,0xed,0xe8,0x91,0xa7,0xbd,0xf6,0xb2,0xf9, + 0x2f,0xe2,0x57,0xa8,0xd1,0x1f,0x32,0xcd,0xff,0x94,0x65,0xf0,0x39,0x0f,0x30,0xa3, + 0xeb,0x02,0x3c,0x8d,0xef,0xff,0xe6,0xe7,0x2e,0x84,0x67,0x63,0x22,0x2f,0xcd,0xff, + 0xec,0x06,0xc7,0xfd,0x4d,0x5a,0x49,0xb4,0x6a,0x98,0x66,0xe2,0xe1,0xcc,0xf3,0xd1, + 0x6c,0x68,0x73,0x6b,0x87,0x78,0x86,0x5a,0x1d,0xb3,0xc7,0x8d,0x83,0xd2,0x6c,0xfd, + 0x01,0xa4,0x0c,0xfe,0x47,0xde,0x43,0xde,0xa5,0x68,0x30,0x84,0xff,0x0e,0x1c,0x52, + 0x79,0x7f,0xb9,0x74,0x7d,0x9c,0xdf,0xd9,0x9f,0x84,0x7d,0x2f,0x8d,0xd2,0xcb,0xf0, + 0xb0,0x10,0xd0,0x85,0x20,0xf9,0x82,0xd2,0x4b,0x3d,0xe8,0x7f,0xd2,0xfc,0x8f,0x43, + 0x1f,0x6e,0xf6,0x77,0x85,0x03,0x41,0x7e,0xe5,0x9f,0x19,0x3e,0xe6,0x57,0xd2,0xfc, + 0x8f,0xdf,0xde,0x1f,0xf2,0x00,0x6d,0x4a,0x7a,0x57,0x8b,0xa7,0x85,0x8f,0x77,0xf3, + 0x2b,0x27,0xe1,0x6f,0x69,0xcb,0x48,0x20,0xbb,0x3f,0x80,0xcd,0xdf,0x2e,0xf8,0x1e, + 0x5b,0xc6,0xd8,0x78,0x84,0xf9,0x93,0x61,0x3a,0xa1,0x35,0x1f,0xf1,0x66,0x9c,0x8f, + 0x66,0x80,0x9c,0x0b,0x29,0xb4,0xe3,0x19,0x65,0x61,0x2b,0x05,0x7b,0x26,0x61,0x52, + 0x6f,0x79,0xd3,0x11,0xbf,0x76,0x9b,0xfe,0xe7,0x2e,0xe3,0xfd,0x93,0xdd,0x77,0x1b, + 0x65,0xfb,0x03,0xee,0x6f,0x90,0xdf,0xd0,0xa7,0xd1,0xc3,0x64,0xe2,0x1f,0xc7,0x78, + 0xdb,0x42,0x85,0x27,0xd4,0xd4,0x95,0x13,0xf4,0x29,0x82,0x8c,0x90,0x0d,0xff,0x84, + 0xcb,0x32,0xd0,0x8e,0x5c,0xc1,0x76,0xf7,0xa9,0x0a,0x20,0xb6,0xde,0x64,0x03,0x4f, + 0xe6,0xd1,0x87,0x63,0x34,0xe9,0xeb,0x3c,0x2b,0x4d,0x9a,0xf5,0x80,0x17,0x84,0x16, + 0xec,0xaf,0x7b,0xda,0xde,0x1f,0xc0,0xc9,0xff,0x2c,0xd8,0x35,0xe3,0x3d,0xf3,0x09, + 0x6f,0xc3,0x38,0x4d,0xe1,0x1f,0xf3,0xf9,0x19,0xfd,0x01,0x9a,0x74,0xcf,0x07,0x9d, + 0xe3,0xaa,0x75,0x0c,0xc4,0x95,0x23,0x2d,0x48,0x04,0xa5,0xf9,0x9f,0x8c,0xf3,0x61, + 0x59,0xfc,0x8d,0x91,0x33,0xb0,0xc4,0xb8,0xf2,0x36,0x1c,0x0a,0xd7,0xea,0x33,0x9d, + 0xf8,0x27,0xf3,0x7e,0xca,0xfe,0x5e,0xa9,0xfa,0xb8,0xe1,0x18,0xfb,0x82,0xf4,0xd6, + 0x78,0x69,0x86,0x3e,0x5c,0x33,0xfa,0x43,0xe2,0xfc,0x9c,0x90,0x09,0x9b,0x16,0x63, + 0xc6,0x4a,0x75,0x1a,0x37,0x0e,0x4a,0x73,0xd6,0xc7,0xf1,0xd3,0x39,0x53,0xe3,0x3d, + 0xc9,0x56,0xfb,0xdb,0x78,0x10,0xf9,0xab,0x7c,0x98,0xe3,0xbc,0x51,0x80,0x98,0x74, + 0xf6,0x47,0xc2,0xd1,0xed,0xaf,0xe2,0xf1,0x2b,0xb1,0xa0,0x43,0x1c,0x8b,0xa5,0x14, + 0xe3,0x49,0x6d,0xdc,0x10,0x72,0xd8,0xf1,0xcf,0x2b,0xf0,0x91,0xba,0x88,0x06,0x6c, + 0x68,0x79,0x2a,0xfe,0x87,0x2a,0x6f,0xc2,0x73,0x7a,0xd5,0x58,0x1b,0x67,0x7b,0xc0, + 0x79,0x2c,0x48,0xce,0xf3,0x41,0x58,0xbc,0x57,0xe6,0x76,0xe5,0xa4,0x7d,0x72,0x9e, + 0x0f,0x32,0x57,0x62,0xde,0x3b,0xb7,0xec,0x27,0xd7,0xf9,0xb0,0xe5,0xbf,0xa5,0x13, + 0xbb,0x1a,0xda,0x73,0xd2,0x3e,0x39,0xce,0x87,0x4d,0x0a,0xfb,0x61,0x32,0xda,0xd8, + 0x96,0x93,0xf6,0x49,0x9f,0x0f,0x62,0xd3,0xff,0xc4,0xc2,0x47,0xa1,0xb4,0x3d,0xa7, + 0xec,0x27,0x27,0xff,0xf3,0x29,0xe8,0xe8,0xbe,0x3e,0x3c,0xf5,0xfb,0xdb,0xce,0x87, + 0x15,0xbe,0x40,0xe8,0x6d,0x6a,0x41,0x4e,0xda,0x27,0xf7,0xf9,0x20,0xca,0x46,0x3a, + 0x27,0xe8,0x4a,0x9d,0x06,0x92,0xc4,0x46,0xaf,0x53,0xea,0x7f,0x64,0x38,0x02,0x41, + 0x85,0xb7,0x05,0xf8,0x10,0x66,0x8d,0x78,0x1b,0xd1,0x10,0x9a,0xfa,0xf3,0xe8,0x7f, + 0x8a,0xfb,0xd8,0xfc,0xb4,0xa8,0xd7,0x8e,0x99,0xb4,0xcf,0x07,0x9c,0x08,0x72,0xce, + 0x8f,0xbd,0x3f,0x12,0x5b,0x84,0xae,0xba,0x23,0xa9,0xf9,0x6f,0x4c,0xae,0x8c,0xb7, + 0x9e,0x85,0xcc,0xf3,0x53,0x9c,0xf8,0xe7,0x29,0xa8,0xd4,0x8b,0xd1,0x9f,0x3c,0x67, + 0xa4,0xbd,0x2e,0xc1,0xbf,0x64,0xe9,0x7f,0xcc,0xe7,0xf7,0xc3,0x43,0xb0,0x8f,0xde, + 0x96,0xe4,0x7c,0xd7,0x73,0x74,0x1e,0x1a,0x57,0xb0,0x2c,0xce,0x31,0x5e,0x5b,0x7f, + 0xa4,0x6d,0xc7,0xa1,0x37,0x1c,0x1e,0x9b,0x97,0xea,0xf7,0xa2,0x43,0xae,0x7e,0x0b, + 0xf6,0xfe,0x48,0x7d,0x70,0x45,0xeb,0xc5,0xfe,0x90,0x88,0x7f,0x1a,0x29,0x37,0x96, + 0x67,0xf0,0x3f,0x69,0xfc,0xb3,0x1c,0x92,0xfa,0x18,0x34,0x95,0x5a,0xf1,0x28,0xa7, + 0x1e,0xc3,0xce,0xff,0xbc,0xa9,0x1d,0x55,0xf7,0x99,0x6a,0x96,0xba,0xdc,0xfb,0x7d, + 0x7b,0xfe,0xeb,0x26,0xd8,0xac,0xee,0xbc,0xd9,0x50,0x9b,0x10,0x9f,0x11,0x88,0x1f, + 0x9d,0xf2,0x7c,0x90,0xcd,0x82,0x2f,0x1d,0xa6,0x3f,0xb1,0x3f,0x40,0x21,0xf6,0x87, + 0x34,0xf9,0x90,0x58,0x46,0x62,0x28,0x4b,0xff,0xd3,0xc7,0xf0,0x4f,0x42,0xdd,0x27, + 0x07,0x8c,0xd1,0xd5,0xe1,0xe9,0x6f,0xd9,0xe3,0xb5,0x9f,0x0f,0x7b,0x9e,0x5c,0x46, + 0xfd,0x0f,0x1f,0x1d,0xef,0x86,0x34,0x23,0x7b,0xbc,0x69,0xfc,0xb3,0x5d,0x38,0x0f, + 0xef,0x75,0xd7,0xaf,0x4d,0xa1,0x9d,0xda,0xf6,0x9c,0xf3,0xe3,0xec,0x8f,0x8d,0x6d, + 0x91,0xba,0x39,0xfe,0x51,0x03,0x82,0x9d,0xf6,0xc9,0x79,0x3e,0xc8,0x0b,0xb0,0x03, + 0xaa,0x97,0xad,0x56,0x4a,0x79,0xf4,0xe1,0xc3,0x14,0xb2,0xf9,0x2e,0x1b,0xfe,0x91, + 0x0e,0xaa,0x73,0x1d,0x6a,0x9f,0x1c,0xf3,0x99,0xe6,0x7f,0xbe,0xfb,0x7b,0x78,0x1b, + 0x7e,0xcc,0xfe,0xbe,0xa1,0x29,0xf8,0x1c,0x5b,0x7f,0xc8,0xa5,0xd5,0xea,0x07,0x74, + 0x71,0x28,0xe7,0x6d,0x39,0xf0,0x4f,0x4d,0xea,0x7c,0x58,0x8f,0x39,0xff,0x9e,0x5c, + 0xf3,0x6f,0xd7,0xff,0x2c,0x66,0xd8,0xb4,0x8a,0xa6,0x68,0x9f,0x3a,0xea,0x8a,0xd5, + 0x4d,0xd5,0x1f,0xc0,0x5f,0xb0,0x4c,0xeb,0xa5,0xfe,0x32,0x0b,0xff,0xe4,0x74,0xd4, + 0xe9,0xf3,0x61,0x63,0x42,0x05,0x8b,0x5f,0xf3,0x84,0x22,0xfc,0x5a,0x17,0xd1,0x4a, + 0xc7,0xb1,0x1a,0x69,0xfd,0xcf,0x32,0xf3,0xf9,0xbb,0xe5,0x6b,0x18,0xfe,0xe9,0x53, + 0xe7,0x6f,0xa8,0x3a,0x0d,0x93,0x7b,0x3e,0x73,0xde,0x93,0xb3,0x3f,0x80,0xd5,0x9f, + 0x44,0x2e,0xde,0x8d,0xa2,0x0e,0x8b,0x66,0x3f,0x61,0xf0,0x3f,0x66,0x07,0xe9,0xd7, + 0x21,0xe3,0x7c,0x10,0xbd,0xe0,0x9c,0x36,0x11,0xfd,0x46,0x75,0xc9,0x78,0xd5,0x59, + 0x6d,0x72,0x7b,0xcb,0x70,0x49,0x5f,0x8e,0xfe,0x36,0xf6,0xf3,0x61,0xa3,0xeb,0x37, + 0x45,0x2b,0x1f,0x63,0xfe,0xe7,0x38,0x1c,0x88,0xd6,0x26,0xe5,0x46,0x74,0xa4,0x71, + 0x0e,0x7b,0x72,0xf1,0x3f,0xda,0x5e,0x6d,0x87,0x5a,0xc9,0x69,0x6a,0x7a,0x80,0xed, + 0x5e,0xf1,0x3c,0x14,0x7a,0xa0,0xc0,0x39,0xde,0xb4,0xde,0x46,0x2d,0xd3,0xb0,0xfb, + 0x71,0xf4,0xea,0xa0,0x71,0x3e,0x23,0x56,0xc3,0xb1,0x1d,0x59,0xde,0xfe,0x00,0x6b, + 0xcb,0xff,0x09,0x7e,0x87,0x85,0x62,0x18,0x1d,0xd0,0xbb,0x96,0xf0,0x7a,0x7f,0xc9, + 0xe9,0x3f,0xed,0xe7,0xc3,0x8e,0x20,0xcd,0x1e,0xc2,0x5f,0xa5,0x09,0x21,0x4f,0x3c, + 0x4a,0xe3,0x1f,0x5d,0x61,0x20,0x47,0xee,0xcd,0x4d,0xfb,0xd8,0xf8,0x9f,0x34,0xfe, + 0xf9,0x6b,0x38,0x1c,0xf6,0xa5,0xe2,0x97,0x90,0x2f,0xfe,0xda,0xf0,0x0f,0x1e,0x0b, + 0xe2,0x0b,0xa7,0xd2,0x34,0x7f,0x9d,0xfb,0x7e,0xbb,0xfe,0x07,0x94,0xc3,0xb2,0xaa, + 0xd5,0x04,0xc9,0x4b,0xb4,0x57,0xf5,0x0c,0xe0,0xc1,0xe8,0xb2,0x79,0x42,0x4d,0x36, + 0xff,0x43,0x8b,0x79,0x7f,0x12,0xad,0x04,0xcf,0xcb,0x9b,0x54,0x97,0xf0,0xfe,0x33, + 0x5d,0x13,0x55,0xce,0x46,0x34,0xf6,0xfe,0x48,0x43,0x38,0x28,0x3e,0x5e,0xec,0x86, + 0x3d,0xe0,0x3d,0x2f,0x8e,0x26,0x27,0xcb,0x9c,0xf9,0x8b,0x5c,0xfa,0x9f,0x94,0xec, + 0xf9,0xe5,0xed,0x55,0xcd,0xcc,0xa8,0x4f,0x7a,0x93,0x6c,0x1a,0x4f,0xa8,0x75,0xb2, + 0xf7,0x15,0x5b,0x7f,0x6c,0xae,0xff,0xa1,0x77,0xd8,0xd0,0xce,0x76,0xf8,0x19,0x33, + 0x6a,0x92,0xee,0x3d,0xe4,0x7d,0xed,0xa7,0xd1,0x9a,0x31,0x66,0xc4,0xd3,0xe7,0xc3, + 0x66,0xe9,0x7f,0xf0,0xfc,0x2f,0x6c,0xd3,0xe7,0xae,0x24,0xba,0x42,0x41,0x95,0xdc, + 0xd3,0x49,0x5d,0x0e,0xfd,0x4f,0x68,0x1d,0x36,0x9e,0xea,0x5f,0xb1,0x37,0x75,0x50, + 0x88,0x3b,0xf6,0x90,0xd1,0x6f,0x9c,0x7d,0xbf,0x71,0x6b,0x3d,0x2c,0xe5,0xfc,0x8f, + 0xd9,0x4f,0x0c,0x97,0x4d,0x05,0x4f,0xc4,0xd4,0xe1,0xc1,0xf7,0x63,0x80,0x1a,0x10, + 0xef,0x90,0xb8,0xd0,0xf2,0x3f,0x71,0x27,0xff,0xc3,0x8c,0x13,0xa6,0x91,0x14,0x53, + 0x47,0xcd,0xc6,0x9c,0xe7,0xc3,0x9a,0x22,0xab,0x14,0xd1,0x14,0x4d,0xc9,0xae,0x3c, + 0xbb,0x44,0x5d,0xd1,0xd1,0x23,0x29,0x8e,0xfe,0xd8,0x99,0xfa,0x9f,0x68,0xca,0x28, + 0x8e,0x11,0xfc,0x7e,0x1b,0xfa,0x8b,0x63,0xe2,0xff,0x9a,0x42,0xff,0xa3,0x30,0xe3, + 0xb0,0xe1,0x88,0x74,0xa3,0xe0,0x41,0xb1,0xf5,0xc7,0xb6,0xf4,0x3f,0x56,0xda,0x6b, + 0xb5,0x91,0x08,0xe3,0x7a,0x18,0xe5,0x91,0xd8,0x1c,0xec,0x8f,0xbd,0x21,0x5b,0xff, + 0x83,0x68,0xa7,0x17,0x9a,0x46,0xdc,0x4b,0x0a,0x07,0x35,0x3c,0xaf,0xc7,0x13,0x14, + 0x8f,0x80,0x1e,0x0b,0xaa,0xec,0xfd,0x6d,0xfd,0xb1,0xcb,0x9f,0x01,0xdb,0xf9,0xb9, + 0x46,0x7f,0x6c,0x63,0x06,0x3e,0x30,0xcf,0x17,0x1e,0xb1,0xe7,0xbf,0x9c,0xfa,0x1f, + 0xbe,0x4d,0xdb,0x63,0x74,0xb0,0xef,0x13,0x55,0x38,0x41,0x1b,0xc0,0x1b,0x75,0xd7, + 0xe4,0xd5,0xff,0xd8,0x0c,0x43,0x28,0x58,0x89,0xe7,0x33,0xd6,0x55,0x9b,0xcf,0x57, + 0xb5,0x1f,0xca,0x99,0xe8,0xce,0x32,0x4a,0x61,0x1b,0x9d,0xa3,0xba,0x2b,0x88,0x9a, + 0xee,0xbf,0xe4,0xac,0xcf,0x0d,0xe8,0x3d,0x41,0x9e,0x8f,0x0e,0x98,0xcf,0xe7,0xe7, + 0x0f,0x96,0x5a,0xe7,0xa3,0x25,0xcb,0x47,0xf0,0xfc,0xf7,0xf4,0xf9,0x20,0xde,0xdd, + 0x16,0xec,0x71,0xfb,0xe1,0xa4,0xa1,0xff,0x59,0x9c,0x43,0xff,0x33,0x23,0x15,0x7d, + 0x3a,0xd2,0x61,0x68,0x0c,0x2e,0x49,0x2d,0xe0,0xd5,0xa6,0xea,0x0f,0x50,0x90,0x2a, + 0x7b,0x37,0xea,0xc1,0xdf,0x36,0x84,0xb2,0x91,0x2c,0xfd,0xcf,0xcc,0x28,0xd8,0xc2, + 0xee,0x6b,0x66,0xfe,0x25,0x55,0x9f,0xae,0xda,0xf5,0x3f,0xd2,0x0d,0xf6,0xee,0x3d, + 0x45,0x56,0x7d,0x6e,0x94,0x9c,0x87,0x7f,0xc4,0x13,0xe8,0x86,0xc8,0xbd,0x19,0xfa, + 0x1f,0x67,0xf4,0x1f,0x4e,0x09,0x81,0x22,0xaf,0xc6,0x36,0xd6,0xce,0x5f,0xee,0xbf, + 0xf9,0x08,0x71,0xe8,0x7f,0x78,0x1b,0x4c,0x33,0xda,0x16,0xa3,0x91,0x30,0x84,0x40, + 0xd8,0x28,0xb2,0x59,0xf6,0x1c,0x11,0x1f,0x48,0xf3,0x3f,0x59,0x7a,0x98,0xa1,0xcc, + 0xf8,0x3e,0x2d,0x2a,0x4e,0xa5,0xff,0x49,0x0b,0x81,0xc4,0x35,0xf4,0xa8,0x5a,0x17, + 0x2a,0x8e,0x76,0xde,0x64,0xe9,0x0f,0xb3,0xf4,0x3f,0x56,0x7f,0xa4,0x99,0x5d,0xbe, + 0x4a,0x14,0x02,0x29,0x72,0x17,0x99,0x6d,0xcd,0xbf,0x43,0xff,0x63,0x1a,0x12,0x67, + 0x84,0xa6,0x93,0x65,0x5a,0x87,0x56,0xad,0x15,0x29,0x24,0x34,0x85,0xfe,0x67,0x3b, + 0x33,0x9e,0x30,0x19,0x36,0x9c,0x58,0x36,0xc3,0x85,0xb9,0xcf,0x87,0xb5,0x0c,0x6c, + 0x8b,0x84,0x0c,0x9e,0x82,0x1d,0xd1,0x99,0xc7,0x58,0x6b,0xcb,0x7f,0x4d,0xd1,0x2f, + 0x62,0x80,0x7c,0x00,0x87,0xb4,0x12,0xc5,0x91,0xff,0xca,0xd2,0xff,0x98,0x06,0xf0, + 0x3f,0xc4,0x62,0x58,0x49,0x67,0xb8,0x6c,0xf9,0xaf,0xdd,0x59,0x68,0xc7,0x66,0xf0, + 0x46,0x91,0x31,0xe2,0x52,0xac,0xf5,0x90,0x43,0x7f,0x98,0x36,0x48,0x27,0xf8,0x75, + 0x7f,0xd0,0xe5,0xb2,0xfc,0x8f,0x4d,0xff,0x93,0x0d,0x7b,0x4e,0xf1,0xef,0x97,0x41, + 0x05,0xbf,0xb5,0xde,0xba,0xbb,0xbf,0xa2,0xd8,0xd0,0xce,0xb5,0x0e,0xd8,0x73,0x1c, + 0x7e,0x49,0x17,0x27,0x3d,0x8b,0xc5,0x1a,0xf3,0xf5,0xb3,0xf5,0x3f,0x39,0x0d,0xdb, + 0xf9,0xb0,0x66,0x7f,0x00,0xb3,0x2d,0xd2,0xaa,0xf1,0x19,0x57,0xe4,0x54,0xfe,0x22, + 0x9d,0xff,0x4a,0xf3,0x6f,0xca,0x63,0x9a,0xfd,0xb5,0xf1,0x34,0x10,0xc4,0x3f,0x46, + 0xa3,0xa7,0xf0,0x81,0x0a,0x03,0xff,0xa4,0xcf,0x87,0xa5,0x39,0xfc,0x15,0x03,0x42, + 0xce,0xc6,0x50,0xf6,0xfe,0xd8,0xd9,0xfa,0x1f,0x34,0xf8,0x09,0x50,0x2f,0x21,0xf5, + 0x71,0x9e,0x45,0xfc,0x4c,0xfd,0x8f,0x35,0x3a,0x0c,0x64,0xa5,0xc8,0xf0,0xf0,0x88, + 0xf3,0x3e,0x4c,0x74,0xdd,0x3d,0xe4,0x7d,0xd6,0xde,0x1f,0x3b,0x53,0xff,0xb3,0x35, + 0x3e,0x03,0x8d,0xd9,0xfc,0x0a,0xfd,0x50,0x66,0xc0,0x60,0x5f,0x0e,0xfd,0x8f,0x3d, + 0xfa,0xdb,0xae,0xb4,0xc0,0x42,0xdd,0x63,0xc7,0x3f,0x3b,0x32,0xf9,0x1f,0x77,0xbc, + 0x70,0xd4,0x3a,0x31,0x44,0x4a,0x75,0x2c,0x74,0xea,0x7f,0x32,0xee,0xf7,0x39,0xf0, + 0x8f,0x2f,0xe3,0x7c,0x90,0xb4,0xfe,0x87,0xcf,0x0f,0x6f,0x8b,0x44,0xcd,0x46,0xbe, + 0x32,0xef,0xe8,0x92,0xa1,0x7f,0x96,0xd3,0xe3,0x15,0xee,0x1e,0x5c,0xb5,0xbf,0x75, + 0x0f,0xea,0x9f,0xf9,0x15,0x6d,0xa2,0xbd,0xee,0xd5,0x2d,0x76,0xfc,0xb3,0xb3,0xdc, + 0x89,0xee,0x5e,0xea,0x39,0xd7,0xf9,0x1e,0x3f,0x31,0x16,0xaf,0xf0,0x46,0x49,0xf9, + 0xce,0x47,0xbb,0x43,0xb0,0x16,0xd2,0xdf,0x4d,0x51,0xff,0x75,0xb6,0x28,0x83,0xed, + 0xb9,0x6a,0x6a,0xfe,0x27,0xbd,0x0c,0x2a,0xd2,0x03,0x27,0xeb,0xf2,0xf2,0x3f,0xe9, + 0xfc,0x97,0xf4,0x07,0xf0,0x3f,0xd8,0x1f,0xfb,0xb0,0x89,0x96,0x0d,0x21,0x74,0x8e, + 0xfa,0xa3,0x3c,0xfd,0xb1,0xf3,0xf3,0x3f,0xf9,0xf3,0x5f,0xc6,0x36,0x24,0xa3,0x5f, + 0x59,0x8e,0xfe,0xd8,0xfb,0xec,0xaf,0x3d,0xf5,0xf9,0xb0,0xd9,0xdf,0x8b,0xc1,0x57, + 0x14,0xe6,0xe6,0x7f,0x6c,0xdd,0x20,0x0d,0x03,0xf9,0x90,0xe2,0xbc,0xfc,0x0f,0x3f, + 0x1f,0x0d,0xd9,0x9e,0xe3,0xfa,0x87,0x94,0x97,0x7d,0x9d,0xd5,0x7f,0x1d,0xcf,0x5f, + 0xff,0xf5,0x87,0xcc,0x4f,0x8e,0xfe,0xd8,0x8b,0xc5,0x29,0x1c,0x57,0xce,0xfc,0xd7, + 0xac,0xfc,0x8e,0xd4,0x9e,0xff,0xb2,0xf2,0x7d,0x99,0x42,0xe8,0xdc,0xfc,0x4f,0x99, + 0xd5,0x16,0xdb,0x93,0xdf,0xb1,0xe7,0xea,0x8f,0x4d,0xb2,0x1a,0x65,0xe7,0xe2,0x7f, + 0x1c,0xf9,0xaf,0xc5,0xe9,0x78,0x54,0x9b,0x97,0xff,0x49,0x45,0x37,0x3c,0xf6,0x1d, + 0xd3,0x5e,0xee,0x4f,0xe2,0x7f,0xb2,0xf4,0xcf,0x53,0xf7,0x87,0xb4,0xf7,0x47,0x9a, + 0xa2,0x3f,0xa4,0xb9,0x1e,0x9c,0xfd,0x91,0xf2,0x19,0x39,0xf3,0x5f,0x38,0xba,0xd9, + 0xb9,0xf5,0x3f,0x79,0xcf,0x47,0xcb,0x63,0x38,0xf3,0x5f,0xaf,0x19,0x30,0xe9,0x3c, + 0x87,0x85,0xc5,0x46,0x5b,0xec,0x0c,0xfe,0x27,0x8d,0x7f,0x8c,0xfc,0x17,0xa7,0x7d, + 0x48,0x37,0xc7,0x3f,0x2e,0x35,0x65,0xe4,0x39,0x1f,0x36,0xcd,0x6e,0x61,0x37,0xa4, + 0x22,0x2e,0xf3,0x9e,0x8a,0xff,0xb1,0xb7,0x79,0xb1,0x60,0xcf,0x54,0xe7,0xc3,0x1a, + 0x22,0x6d,0x62,0xc0,0xda,0x22,0x2e,0x6b,0xcf,0xcf,0xff,0xd8,0xf1,0xcf,0x6b,0x79, + 0xf9,0x9f,0xbc,0xe7,0xa3,0x99,0x46,0x43,0x5e,0xfd,0x4f,0x2a,0xff,0xb5,0x9b,0x24, + 0x0c,0x23,0x6c,0x1a,0xf9,0xcf,0x87,0xc5,0x8f,0xa2,0xc2,0xfc,0x3a,0xd4,0x74,0xbc, + 0xb6,0xe9,0x7f,0xd2,0xfc,0x4f,0xea,0xb3,0xbd,0x25,0xf5,0xb5,0x8a,0xe1,0x9c,0xfa, + 0x1f,0xf3,0xf9,0xbc,0x3f,0x76,0xc7,0x8d,0x67,0x30,0xed,0x05,0x1f,0x47,0x18,0xec, + 0x59,0xcb,0xf1,0xcf,0x67,0x50,0xff,0x9c,0xe7,0x7c,0x58,0x0e,0x03,0xa2,0xa6,0xf7, + 0x88,0xf1,0xc0,0x97,0x81,0x7f,0x1c,0xe7,0xc3,0xa6,0xf2,0x5f,0x67,0xe5,0x7b,0xd0, + 0x18,0x11,0xf1,0x7c,0xd8,0x25,0x8e,0xfe,0x90,0x7a,0x66,0xfe,0x6b,0xc0,0xdd,0xce, + 0xbc,0x07,0x1f,0x5d,0x98,0x94,0xd0,0xcc,0xf7,0xcf,0x91,0xff,0x6a,0xbf,0x2a,0x65, + 0x18,0x85,0xab,0xf3,0xf4,0x9e,0x3c,0xf8,0x87,0xd3,0x3e,0x7c,0x1b,0x2b,0x18,0xf3, + 0xe9,0xca,0x76,0x44,0xce,0xf3,0xd1,0x78,0xd8,0x8a,0x8a,0xc6,0xc0,0xff,0x22,0x16, + 0x0a,0x28,0x13,0xd2,0x35,0x6c,0x98,0x7f,0x6a,0xd3,0xff,0x98,0xef,0x63,0xf5,0xc7, + 0x76,0xcc,0x4f,0x46,0x05,0x50,0xae,0xfc,0xd7,0x10,0xf7,0xde,0x4b,0x70,0x9b,0x3f, + 0x35,0xff,0x93,0xc2,0x3f,0xd1,0xd2,0x54,0xb4,0x8a,0xd9,0x03,0xd9,0xbb,0xb9,0xf4, + 0x3f,0x4e,0xfd,0x73,0xec,0x13,0xf8,0x1f,0x8f,0xa1,0xb6,0x52,0x42,0x83,0x46,0x22, + 0x8c,0xad,0xb7,0xca,0xd4,0x46,0x75,0x90,0x2b,0x64,0xb2,0xea,0xbf,0xde,0xd5,0xf8, + 0x78,0xdf,0xc3,0xec,0xe7,0x90,0x3b,0xf6,0xa7,0xef,0x9d,0x60,0xc6,0x40,0x3e,0xfe, + 0x27,0x3d,0xde,0x24,0x43,0x3b,0xc7,0x8c,0x42,0x66,0x53,0xff,0xf3,0x7e,0x2e,0xfd, + 0xcf,0xfb,0x19,0x68,0xf9,0x2c,0xbc,0x1e,0x31,0x80,0x90,0xfc,0x5c,0x0e,0xfc,0x93, + 0x85,0x76,0x4c,0xa3,0x34,0x0f,0xfe,0x79,0x3c,0x4f,0x7c,0x9f,0x1a,0xff,0x84,0x46, + 0x61,0x89,0x94,0x32,0x8c,0x2b,0x90,0x07,0xff,0xbc,0x6b,0xe7,0x67,0xec,0x34,0x69, + 0x5e,0xfc,0x73,0x9d,0x33,0xac,0x2b,0x7f,0x2c,0xfe,0x99,0x2a,0xff,0x95,0x85,0x87, + 0xc9,0xa8,0x62,0xbf,0xd2,0xff,0xc9,0xf8,0x47,0xa9,0x9f,0x2a,0xff,0x95,0x0d,0x03, + 0xa8,0x01,0x84,0x42,0x78,0x62,0xc8,0xfc,0x33,0x22,0xc3,0x3f,0xd6,0xfe,0xce,0x3a, + 0x1f,0xc4,0x2c,0x7b,0x7f,0x99,0x27,0xc2,0x52,0x27,0xc6,0x2a,0x78,0x50,0xc8,0xb4, + 0xa9,0xf0,0x4f,0x8a,0x36,0x54,0x3e,0x11,0xff,0xe4,0x9e,0x9f,0xbf,0xcb,0x85,0x7f, + 0xde,0x72,0x7a,0x9b,0x50,0x96,0xff,0xf4,0x4d,0xa5,0xff,0xe1,0xc3,0x9c,0x12,0xff, + 0x64,0xaf,0xb7,0xde,0x0c,0x3c,0xe9,0xc4,0x3f,0x0e,0xfd,0x8f,0x3b,0x97,0xe1,0xc4, + 0x3f,0x23,0xb9,0xf7,0xe3,0x53,0xe3,0x9f,0x29,0xf1,0xc0,0x27,0xe2,0x1f,0xe1,0x8f, + 0xc4,0x3f,0xd2,0x7f,0x10,0xfe,0x31,0x8d,0x42,0xab,0xf0,0xed,0x93,0xf0,0xcf,0x75, + 0x59,0xe3,0xbd,0x6e,0x2a,0xfd,0x8f,0x69,0x60,0x63,0xc0,0xd6,0xdc,0xf9,0x2f,0x21, + 0x83,0xff,0xe1,0xfa,0x9f,0x3b,0xf2,0xe8,0x9f,0x33,0xce,0x07,0xc9,0x3b,0xde,0x7c, + 0xfa,0x9f,0xa5,0x9f,0x94,0xff,0x2a,0xb7,0x9a,0x60,0xa7,0xdf,0x5f,0xba,0x00,0x73, + 0xff,0x10,0xfc,0x63,0x33,0x4a,0xfe,0x48,0xfc,0xd3,0xfc,0x49,0xf8,0x27,0x8b,0xff, + 0x11,0xa7,0xc6,0x3f,0x53,0xe6,0xdf,0xf3,0x9f,0x0f,0x9b,0xc3,0xe8,0x59,0xef,0x9b, + 0xe2,0x7c,0xd8,0x5c,0x86,0x30,0x85,0xfe,0x27,0x37,0xff,0xe3,0x38,0x1f,0xc4,0x91, + 0xbf,0x30,0x0e,0xba,0x32,0x03,0xd9,0x44,0x14,0x1b,0x65,0xcf,0xc8,0xc2,0x3f,0xe6, + 0xdb,0x06,0x92,0xb3,0xef,0x22,0xa7,0x84,0xb7,0x8c,0x63,0x4d,0x4e,0xeb,0x07,0x3e, + 0x51,0xff,0xb3,0xe2,0x9b,0x85,0xf6,0xf1,0xaa,0x19,0xfa,0x1f,0x35,0x53,0xff,0xe3, + 0xb2,0x85,0xf5,0x3c,0xf8,0x27,0x63,0x74,0x55,0x19,0x8c,0x90,0x3b,0x27,0xfe,0x31, + 0xef,0x2f,0x31,0x85,0xaf,0x46,0x46,0x2c,0x2f,0xfe,0xc9,0xd8,0xc6,0x2e,0xf9,0x24, + 0xfc,0x33,0xa5,0x7e,0x23,0xff,0xf9,0xb0,0x4e,0x43,0xc8,0x8d,0x7f,0x9c,0xfc,0x4f, + 0x64,0xd0,0x40,0x44,0xc1,0x3a,0x06,0x84,0xaa,0x32,0xfb,0x43,0x16,0xaf,0x73,0x8c, + 0xf7,0x05,0xef,0x3e,0xf1,0xbd,0xb6,0x94,0xfe,0x76,0x94,0x4e,0xc8,0x99,0xfd,0x21, + 0xaf,0xcd,0x31,0x5e,0xa4,0x7d,0xcc,0x2b,0xf7,0xe8,0xd7,0x39,0xf1,0xcf,0x45,0x6d, + 0x30,0xba,0xa8,0xda,0x73,0x54,0xac,0x63,0x46,0xbd,0xea,0x39,0x21,0x5e,0x92,0x26, + 0xa1,0x1e,0xdb,0x8a,0xe6,0xe4,0x7f,0x46,0x90,0x64,0x96,0xf1,0xb4,0x38,0xda,0x8d, + 0xa7,0x51,0x6f,0x27,0xef,0xc8,0x87,0x33,0x1a,0x01,0xd9,0xfb,0xff,0x74,0x77,0x53, + 0x9f,0x0a,0x32,0x31,0xda,0x57,0x91,0x22,0x48,0x09,0x33,0x64,0xc7,0xf7,0x65,0xae, + 0x1f,0xbd,0x7c,0xc4,0xac,0x66,0x0d,0x73,0xa3,0x88,0x92,0x51,0xf9,0x70,0x85,0xb3, + 0x11,0xd0,0xb8,0xad,0xfe,0x6b,0x94,0x1c,0xa5,0xfb,0xc2,0x81,0xed,0xee,0xb9,0xdc, + 0x98,0xcf,0x27,0x8a,0xee,0x73,0x34,0xea,0x49,0xd7,0x7f,0xc5,0x84,0x67,0xa4,0xcb, + 0xd1,0x25,0x6b,0xb6,0xbe,0x26,0x3e,0xad,0x5d,0x8e,0xb6,0xac,0x29,0x19,0xab,0xba, + 0xa8,0x7d,0x48,0xf3,0xd5,0x7f,0xe9,0xca,0xcf,0xe0,0x42,0xac,0x39,0xec,0xdd,0x2e, + 0xf2,0x36,0xb6,0x61,0x63,0x3f,0xd2,0x5e,0x97,0x17,0xff,0xd4,0xc2,0x41,0xbd,0x36, + 0xec,0xde,0x4e,0xde,0x84,0x83,0x94,0x19,0x31,0xc4,0x3f,0xba,0x9a,0x87,0xff,0xd1, + 0x0b,0xd6,0x66,0xf8,0x2b,0x74,0xcb,0xfb,0x92,0xce,0xc6,0x35,0x76,0xfc,0x73,0x0d, + 0x3c,0x1d,0x9d,0x1f,0x73,0xaf,0x25,0x27,0xe1,0x69,0xca,0x0c,0xd4,0x3f,0x3f,0xcd, + 0x2b,0xa4,0x72,0xd6,0x7f,0xc9,0xb2,0x76,0x4e,0x69,0xa2,0x5e,0x55,0x4c,0xc0,0x39, + 0x60,0x06,0x88,0x03,0x0c,0x08,0xc5,0xf5,0x7c,0xfc,0x4f,0x1f,0x5c,0x51,0x5a,0xba, + 0xbc,0x67,0xc4,0x71,0x8d,0x1b,0x47,0xf9,0x7a,0xc8,0x87,0x7f,0xfc,0x98,0xff,0x32, + 0xda,0x62,0xdf,0x81,0x6d,0xb1,0x93,0x9e,0xb8,0x7b,0x2e,0x24,0xa8,0x73,0x7e,0xd2, + 0xf5,0x7d,0x23,0xdc,0x9f,0xa4,0xea,0xbf,0x8c,0x63,0x61,0x49,0x05,0x74,0x19,0xc7, + 0x4c,0xe7,0xea,0xff,0xa3,0xfc,0x70,0xfa,0x81,0x48,0x25,0xca,0x7e,0xf0,0x7c,0x10, + 0x66,0x8c,0x90,0x42,0xe8,0xa0,0xb7,0xe5,0x3d,0x1f,0x64,0x8b,0xb9,0xba,0x8c,0x6c, + 0x97,0x1c,0x23,0x1e,0xd2,0xb1,0x2d,0x96,0x9a,0x4f,0x29,0x85,0x7f,0xcc,0xfb,0x93, + 0xe5,0x4f,0xc0,0x45,0x6d,0x5f,0x34,0xb0,0xcb,0x3d,0x8f,0x1c,0x43,0xe3,0x49,0xb2, + 0x18,0x8e,0x43,0x9d,0x89,0x88,0xee,0xce,0xea,0xff,0xa3,0x8e,0xcb,0x78,0x4c,0x79, + 0x67,0xca,0xd0,0xad,0x30,0xd4,0x9a,0x1f,0xff,0x2c,0x33,0xf8,0x1f,0x1e,0xdd,0xaa, + 0x8c,0xb6,0x3f,0x9e,0xfc,0xf8,0x47,0xab,0x5d,0xef,0x7e,0x2c,0xdd,0x16,0x7b,0x0e, + 0x33,0x02,0x0e,0x45,0x8a,0x13,0xff,0xfc,0x1c,0x16,0x68,0xee,0x21,0x72,0xde,0x34, + 0xd6,0x70,0xd9,0x33,0xde,0x2f,0xe7,0xc4,0x3f,0x4f,0xd1,0xf9,0x61,0xb6,0x6c,0x7e, + 0x63,0x18,0x43,0xd8,0x16,0xdb,0x1f,0x30,0xce,0x87,0xcd,0xae,0xff,0x2a,0x08,0xc3, + 0x18,0xca,0xbc,0x81,0x6d,0xa2,0xb9,0xa1,0x8b,0x61,0x8a,0x8d,0x47,0xec,0x42,0x94, + 0xd3,0xf6,0xfc,0x17,0xaf,0x76,0xf7,0x3e,0xd4,0x69,0x18,0xab,0x14,0xf1,0x3c,0x9e, + 0x97,0x97,0x97,0xff,0xc1,0x5f,0xeb,0x97,0x71,0xfe,0xe7,0xb2,0xd2,0x82,0xd3,0x52, + 0x0d,0x17,0xfc,0x8b,0xf2,0xeb,0x7f,0xd4,0x3e,0xd9,0x07,0xee,0x48,0x24,0x49,0xfb, + 0xd4,0x5a,0xe2,0xa7,0x44,0x6d,0x7b,0x46,0xf3,0xe5,0xab,0xff,0x2a,0x18,0xa0,0x7b, + 0xd9,0xb2,0xee,0x29,0x25,0x03,0xb1,0xbd,0x6a,0xa0,0xcd,0xb5,0x9a,0x5c,0x25,0x3f, + 0x45,0x55,0x07,0xfe,0x71,0xf4,0xff,0x61,0x17,0x77,0x9a,0x68,0x27,0xa0,0xb9,0xa2, + 0xae,0xfd,0x6c,0x62,0x9d,0xc2,0xaa,0x37,0x33,0xf2,0x5f,0xbe,0xf4,0xdb,0x96,0x28, + 0xe2,0x1c,0xb8,0xa0,0xed,0xcb,0x83,0x7f,0x46,0x32,0xf1,0x4f,0xb1,0xad,0x0d,0x54, + 0x8e,0xfa,0x2f,0x7e,0x3e,0x08,0x36,0xd9,0x88,0xa4,0x67,0x5b,0x85,0x41,0x3c,0x16, + 0x36,0x1f,0xfe,0x91,0xcf,0x42,0x55,0xd4,0x3d,0x4c,0x50,0xa4,0xbe,0x20,0xe6,0xde, + 0x45,0xfc,0x10,0x81,0xaa,0xbc,0xf5,0x5f,0x2b,0xa1,0xca,0xd6,0x26,0x2b,0xe9,0x6a, + 0x20,0x25,0x10,0xa1,0x2a,0xcd,0x5d,0xff,0x15,0x83,0x5b,0xe0,0x47,0x50,0xa9,0xb9, + 0xdb,0xc9,0xab,0xf2,0x53,0x30,0x3f,0xc4,0xbe,0xd6,0xeb,0xe0,0x5e,0xad,0x92,0xe6, + 0xae,0xff,0xda,0xdd,0xfd,0x15,0x38,0x4b,0x17,0xc6,0xbc,0x6b,0xc5,0x93,0x78,0x3e, + 0x08,0xb6,0xfd,0x71,0x91,0xe7,0xe9,0xde,0x58,0x9e,0xfa,0xaf,0x22,0x9c,0x9f,0x67, + 0x29,0xaf,0xff,0xe2,0xa3,0x0b,0xba,0x51,0xf1,0x62,0xf5,0xb7,0xc9,0x81,0x7f,0xde, + 0x8f,0xb6,0x24,0x1f,0xc0,0xfa,0xe5,0x97,0x51,0xb6,0x31,0x22,0xfe,0x58,0x1e,0x8c, + 0xde,0x18,0x0b,0xe4,0xcc,0x7f,0x3d,0x31,0x7d,0x3f,0x6c,0xa4,0x0b,0x34,0xb9,0x9d, + 0x5c,0xa5,0x6f,0xd4,0x2a,0x87,0xdc,0xe1,0x9d,0x57,0xe9,0x5d,0xe9,0xfe,0x3f,0x19, + 0xe7,0x83,0x20,0xfe,0xf9,0xb1,0x3a,0x07,0x0f,0x6d,0xac,0x80,0xef,0xc1,0x1c,0xea, + 0xbe,0x0d,0xcf,0xc3,0xa5,0xce,0xfe,0x3f,0x76,0xfc,0xc3,0x69,0x46,0x8c,0x56,0x2a, + 0x6c,0x87,0xb9,0xd4,0x5d,0x1d,0x11,0xf0,0x8a,0xa3,0xff,0x8f,0x33,0xff,0xf5,0xae, + 0x34,0x97,0xc1,0x18,0x12,0x40,0x75,0x84,0xee,0x9d,0x25,0x3e,0x80,0x1d,0xe7,0xa8, + 0x3d,0x7e,0xd9,0xeb,0xbf,0x38,0x5e,0xd2,0x38,0xff,0xf3,0xae,0xd6,0xd8,0xbe,0x35, + 0x3a,0xed,0xac,0x41,0x53,0x3b,0xf8,0x1f,0xf3,0xfd,0x05,0xe5,0x59,0xb8,0x12,0x6d, + 0xa1,0xc5,0x49,0xd2,0xc4,0xe6,0xa7,0x4a,0xf7,0x0c,0x89,0x8b,0xfd,0x2f,0x43,0x0b, + 0x75,0xe7,0xac,0xff,0x62,0xf8,0x47,0x63,0x41,0x1c,0x93,0xa4,0x01,0xe8,0xe9,0xe2, + 0xc2,0x42,0x3f,0xe6,0x2f,0x3a,0xa6,0xc2,0x3f,0x7e,0xbd,0x28,0x4e,0x7e,0x06,0x3f, + 0x55,0x6b,0x74,0xb9,0xbb,0xb4,0x1a,0xf0,0x3c,0xd9,0x29,0xf8,0x1f,0x99,0x77,0xdf, + 0x7a,0x80,0xc1,0xc2,0xb5,0xba,0x0c,0x44,0xda,0x42,0xe5,0x40,0x77,0x9e,0xfa,0x2f, + 0x86,0x7f,0x2e,0xaa,0x8d,0x78,0xda,0xe9,0x96,0xe8,0xef,0xb0,0xed,0x0c,0x15,0x54, + 0x38,0xaa,0x3a,0xc7,0xeb,0xc0,0x3f,0xca,0x84,0x31,0xa8,0x75,0x1a,0x9e,0x2e,0xe7, + 0xd5,0xc4,0x21,0x8d,0x7d,0x56,0x5d,0xf9,0xeb,0xbf,0x26,0x23,0x46,0xfd,0x97,0x92, + 0x99,0x36,0xcd,0x9d,0xff,0x72,0xf4,0xff,0x39,0x93,0x32,0xe6,0xe2,0x95,0x3b,0xa6, + 0xcc,0x7f,0x39,0x13,0xa3,0xfd,0xd6,0x41,0x3c,0x3d,0xb9,0xf9,0x9f,0x9b,0x4c,0xf4, + 0x18,0x32,0xdb,0x28,0xdd,0xb4,0x2e,0x9b,0xff,0x51,0xa7,0xa7,0xeb,0xbf,0x94,0x09, + 0xa9,0xc1,0x89,0x9f,0xa5,0x94,0x90,0xcc,0x51,0xff,0x95,0xc5,0xf6,0xfc,0xf1,0xf9, + 0x2f,0x0b,0x78,0x4f,0xc1,0xff,0x08,0xc6,0x40,0x4a,0x9c,0xc0,0x58,0xc8,0xc2,0x3f, + 0x59,0xfb,0x2f,0x18,0x94,0xea,0xa5,0xd4,0xc6,0x21,0x17,0xff,0x23,0x18,0x41,0xdf, + 0xe8,0xff,0x33,0xe2,0x72,0x12,0x41,0x1d,0x5f,0xcf,0xc4,0x3f,0x6c,0xbd,0x09,0x4d, + 0xfd,0xab,0x82,0x7f,0x6a,0xd4,0x7f,0x79,0x17,0x8b,0xd8,0xd2,0xb5,0x49,0x2f,0x09, + 0x0a,0xc7,0xa3,0x1f,0xd2,0xa6,0xd1,0xac,0xfc,0xd7,0x44,0x3a,0x4d,0xdc,0xac,0x4f, + 0xfb,0x60,0xc6,0x25,0xb8,0x47,0x30,0xe6,0x47,0x4b,0x11,0x41,0x9f,0xc8,0xff,0x10, + 0x73,0xfe,0x85,0x66,0x7d,0x55,0xbc,0x35,0x7f,0xfd,0x57,0xff,0x27,0xe6,0xbf,0xcc, + 0xb4,0xd7,0x4d,0xe9,0x61,0xf2,0x19,0x98,0x69,0xe7,0x7f,0xd2,0xf5,0x5f,0x65,0x83, + 0x12,0x4e,0xda,0x8a,0x1c,0xdb,0x58,0xdf,0x94,0xf9,0xaf,0x1c,0x69,0xaf,0x4f,0xca, + 0x7f,0xd9,0x84,0x40,0xb3,0xff,0x63,0xf9,0x9f,0xff,0xd8,0xfc,0x97,0xf2,0x47,0xf3, + 0x3f,0x19,0xc6,0xd9,0x7f,0x57,0xfe,0xcb,0xb8,0xd8,0x6a,0xbf,0x4d,0xca,0xec,0xa8, + 0x93,0x91,0xff,0x4a,0xa3,0x9d,0x22,0x6e,0x14,0x18,0x57,0xa4,0x3f,0x94,0xff,0x11, + 0x9c,0x85,0xff,0x53,0xd4,0x7f,0x19,0x65,0x5f,0x70,0x47,0x3e,0xfe,0x27,0xb3,0xfe, + 0xeb,0x93,0xf4,0xcf,0xf0,0x87,0xdc,0x3f,0x45,0xfd,0xd7,0x27,0xf1,0x3f,0xa9,0xfa, + 0x2f,0x3b,0xdb,0x33,0x22,0x35,0x0a,0x19,0xfa,0xe7,0x74,0xff,0xc3,0xbc,0xfc,0x8f, + 0x18,0xd4,0x72,0xf0,0x3f,0x59,0xf5,0x5f,0x39,0x8d,0x3c,0xf5,0x5f,0x79,0x8d,0x5c, + 0xfc,0x4f,0x8e,0x32,0xf0,0x1c,0xf8,0x47,0x2b,0xc8,0x8e,0x56,0x48,0xfb,0xe4,0x8b, + 0x5f,0x99,0xfc,0xcf,0x08,0x1b,0x1d,0x73,0x9b,0xfb,0xf9,0x15,0x14,0x46,0x06,0x74, + 0x47,0xff,0xc3,0x4c,0xfe,0x27,0x61,0xe8,0x7f,0x54,0xa7,0xfe,0x27,0xbd,0xbf,0xcb, + 0xa8,0xff,0xaa,0xcd,0xcd,0xa7,0xa5,0xf1,0x4f,0x56,0xfd,0x57,0x4a,0xe8,0xd2,0xd0, + 0x6f,0xbf,0x72,0x3a,0x3f,0xff,0x63,0x13,0x7e,0x4c,0x9b,0x2a,0xff,0x65,0xd2,0x3e, + 0x1e,0x6e,0x48,0xbc,0xec,0xeb,0x92,0x72,0x8f,0xf1,0x53,0xbe,0xfa,0x2f,0x52,0xa2, + 0x17,0xe7,0x12,0xf6,0xe4,0xaa,0xff,0x2a,0x4c,0xd5,0x7f,0x7d,0x82,0xfe,0xd9,0x76, + 0x3e,0x88,0x84,0xf3,0x53,0xc4,0x69,0x1f,0xd9,0x9c,0x1f,0x81,0x17,0xc2,0x3b,0xeb, + 0xbf,0x6c,0xd9,0xbd,0xc6,0x53,0x9e,0xa7,0x90,0xf6,0x51,0x79,0xfc,0x7d,0x4f,0x9b, + 0x68,0x6f,0xc6,0x83,0x83,0x6d,0xfd,0x7f,0x9c,0xfc,0x4f,0xf3,0x60,0x06,0x11,0x04, + 0x86,0xfe,0xe7,0x2a,0x73,0x3d,0x1c,0x29,0x40,0xd8,0xd3,0x9b,0xf4,0x26,0xd8,0xfe, + 0x8b,0xe1,0xe7,0x30,0xfb,0xb5,0x76,0x0a,0xfc,0xa3,0xf3,0xfc,0x97,0xef,0x8c,0xbb, + 0x3b,0xf4,0x26,0xef,0xff,0xec,0x5e,0x88,0x07,0xb9,0xe6,0xd5,0xff,0x24,0x0a,0x8c, + 0xfd,0xb8,0x1b,0xd8,0xd7,0xf7,0x30,0x57,0x9f,0xfa,0xb2,0xf3,0xa1,0x69,0xfe,0x27, + 0xa9,0xec,0xe1,0xa2,0x29,0xe6,0xc4,0xce,0xc2,0x0f,0x54,0xdf,0x80,0x3b,0x16,0x09, + 0x28,0x99,0xf3,0x69,0xeb,0xff,0xcc,0xf5,0xb7,0x75,0x3a,0x0b,0x43,0x6f,0x92,0xd7, + 0x60,0x9f,0xee,0xdd,0xef,0x0e,0x64,0xd7,0x7f,0x59,0xf8,0x76,0x2f,0x3c,0x23,0xa5, + 0xf2,0x83,0xe7,0x81,0x37,0xba,0x59,0x9f,0xab,0xff,0x8f,0x15,0x4f,0xc7,0xc0,0x58, + 0x9f,0xd7,0x75,0xb3,0xcf,0xea,0x28,0x65,0x4f,0xeb,0x16,0x03,0x59,0xf5,0x4d,0xce, + 0xfe,0xcf,0xbd,0x46,0x1a,0x74,0x10,0x7e,0xc5,0x8c,0x9e,0x0e,0x12,0x50,0x5f,0xcf, + 0x5b,0xff,0xa5,0x9b,0x7c,0x20,0xd2,0x62,0x1d,0x12,0x76,0x5b,0x75,0x95,0x64,0x1d, + 0x6c,0x9a,0xee,0xff,0x33,0xa4,0x60,0xfe,0x8b,0x81,0x9c,0x36,0x72,0x85,0x7c,0xd7, + 0x88,0xfe,0xd7,0x75,0x3c,0x12,0xcb,0xd7,0xff,0xc7,0xcc,0x7f,0xb9,0xa1,0xf5,0x25, + 0xe8,0xe7,0x8d,0x10,0xab,0x6a,0xe1,0x79,0x7b,0xff,0x9f,0xad,0x8e,0xfe,0x3f,0x65, + 0x7b,0x38,0x68,0xd9,0x4a,0xd9,0xaf,0x17,0x14,0x36,0xba,0x7d,0xee,0x1c,0x7a,0x2a, + 0x27,0xff,0x83,0x6c,0x64,0xb7,0xb8,0x05,0x65,0x0f,0xf8,0x6b,0xad,0xd2,0x03,0x4d, + 0x49,0x7b,0x45,0x9e,0xad,0xff,0xb3,0x95,0x4f,0x27,0xb3,0xd8,0x46,0x92,0xcb,0x9e, + 0x9b,0xe0,0x27,0xcc,0xf0,0xe7,0xe6,0x7f,0x10,0xff,0x74,0xcc,0x4b,0x76,0x26,0xc8, + 0xb3,0xb8,0xed,0x4a,0xba,0x6f,0x45,0x22,0x28,0x32,0x3f,0x29,0xe7,0xee,0xff,0x93, + 0xd2,0x1f,0xce,0xac,0x26,0xc5,0xf2,0x8e,0x28,0x43,0xd7,0x0a,0xf1,0xc0,0xe3,0x92, + 0x59,0xd8,0x22,0xf0,0xf9,0x3c,0x69,0x3d,0x5f,0x97,0x76,0xf3,0xb2,0x2f,0xef,0x6f, + 0xc5,0x83,0x7c,0xdb,0xe5,0x1d,0x71,0xfb,0xe1,0x08,0x33,0x3c,0x79,0xfa,0x3f,0x9b, + 0xf1,0x08,0xf9,0x9f,0x3f,0x20,0xff,0x95,0x8e,0x77,0x03,0x70,0x94,0x34,0xb3,0x68, + 0xeb,0xae,0xce,0x2a,0x04,0xcb,0x3e,0x1f,0x6d,0x26,0x9e,0xcf,0xfe,0x9a,0xa9,0x3f, + 0x79,0x3b,0x83,0x7f,0xb0,0xe1,0x1f,0xa8,0x96,0x78,0x76,0x0c,0xf9,0xc6,0xcd,0xd4, + 0xb8,0x5f,0x3b,0x98,0x71,0xbf,0xad,0xfe,0x4b,0x49,0xe3,0x9f,0x18,0x17,0xc6,0x5c, + 0x13,0x29,0x84,0x1d,0xa9,0x42,0x30,0x29,0xab,0xfe,0x6b,0x75,0x45,0x5a,0xff,0x4c, + 0x51,0xf6,0xfc,0x72,0x84,0x17,0xc2,0x3b,0xf9,0x07,0x5b,0xff,0x67,0xce,0x87,0xd4, + 0x2e,0xf5,0xb6,0x8b,0xe7,0xa5,0xcb,0xe0,0xd5,0xbc,0xaf,0x74,0x0e,0xc7,0xde,0xe6, + 0x1d,0x6f,0xc4,0x61,0x25,0x27,0xfe,0xb9,0x6c,0xe8,0x7f,0xae,0x87,0x97,0xe0,0x7a, + 0x7d,0xc5,0xab,0x0f,0x5f,0x2f,0xf3,0x83,0xd5,0xf0,0xfe,0x83,0x99,0xfc,0x4f,0x85, + 0xa9,0xff,0x89,0x85,0x54,0xce,0x0f,0xbb,0x77,0x11,0xd5,0x7e,0x62,0x5a,0x06,0xfe, + 0x59,0x9b,0xd6,0x3f,0xff,0x15,0x3c,0x9a,0x6a,0xfc,0xa8,0xe6,0xef,0xff,0xd3,0xa7, + 0x18,0xf8,0xa7,0x27,0xea,0x5a,0x23,0x3d,0xca,0xa6,0xb1,0xe7,0xa1,0xd0,0xba,0xac, + 0x7c,0x62,0xf6,0xf9,0x68,0xee,0xc7,0x66,0xfc,0x15,0xf9,0x15,0x34,0x20,0x51,0xbc, + 0x26,0x2b,0x23,0x96,0x3e,0x1f,0x36,0x01,0xbb,0xa4,0x94,0xba,0xfb,0x47,0x78,0x2c, + 0x6c,0xbb,0x77,0xbb,0xdb,0x81,0x88,0x78,0xe3,0x20,0x5b,0xff,0x43,0x73,0xbd,0x75, + 0x89,0x49,0xf9,0x84,0xd0,0x0c,0x01,0x49,0x54,0xf9,0x1f,0x22,0xcf,0xf9,0xb0,0x5d, + 0xa9,0xfc,0x97,0xca,0x9c,0xea,0x49,0x99,0x6d,0xe4,0x47,0x48,0xa3,0x7a,0x5f,0x46, + 0x46,0x2c,0x91,0x9d,0x8f,0x58,0xc8,0x16,0xc9,0xc3,0x94,0x7d,0x26,0x8b,0x4b,0x3c, + 0xd0,0x49,0x32,0xfd,0xb3,0xf9,0x4f,0xe0,0xe7,0x85,0x7d,0x1d,0xbf,0xdf,0xf3,0xea, + 0x23,0xb0,0x20,0xd9,0xdd,0x7e,0x2f,0xfb,0x1e,0xf3,0x9e,0x0f,0x2b,0x77,0x9b,0xf8, + 0x67,0xc6,0x6f,0xe4,0x7f,0x61,0x86,0x67,0x44,0x6c,0x20,0xbf,0xcc,0x7b,0x3e,0xac, + 0x7f,0x96,0xe1,0x6f,0x57,0xc5,0xd9,0xf7,0x92,0x12,0xba,0x0c,0x5b,0xfe,0xc7,0x94, + 0xc2,0xda,0xfa,0x3f,0x7b,0x9e,0x6d,0xe3,0x41,0xea,0xdb,0x9c,0xff,0x69,0x19,0xf6, + 0x8e,0x57,0x35,0xda,0xe2,0x97,0x01,0x84,0xd2,0xe7,0xc3,0x3e,0x29,0x5b,0x78,0xe6, + 0x7a,0x7c,0xed,0xdf,0xba,0x97,0xb8,0x66,0x99,0xb0,0x27,0x07,0xff,0x13,0x83,0xc7, + 0x14,0x7e,0x71,0xcc,0xb8,0x7f,0xd0,0x7d,0x3b,0xd9,0x66,0x43,0x44,0x24,0xeb,0x7c, + 0x58,0xac,0xf7,0xf1,0xe8,0x33,0x9b,0x48,0x01,0xf6,0xb7,0x41,0x6f,0x5f,0x9d,0x15, + 0xef,0xd2,0xf5,0x5f,0xb2,0xc4,0xfc,0x2d,0xdb,0x2d,0xba,0x9f,0x13,0x0b,0xe0,0xc5, + 0x82,0xda,0x33,0xde,0xf8,0xa7,0xab,0xa5,0xcc,0x8d,0xa4,0xad,0xff,0x33,0x98,0x78, + 0xc9,0x3d,0x4c,0xf8,0x44,0x45,0x45,0xab,0xfe,0x1d,0x0f,0x8a,0xbd,0xdb,0xc0,0x3f, + 0xe6,0xfd,0x02,0x18,0x7a,0x86,0x92,0x8b,0xe2,0x79,0xdf,0xcb,0xcc,0x28,0x4e,0x8a, + 0xdf,0x02,0x34,0xdc,0x63,0x58,0x21,0x4e,0xf0,0x04,0x84,0x2a,0x7b,0xff,0x67,0x16, + 0xcd,0x89,0x51,0xbd,0x0e,0x3d,0x65,0xb5,0x7a,0x5b,0x94,0x7c,0x8a,0xeb,0x57,0x57, + 0xe4,0x3d,0x1f,0xd6,0x8c,0xce,0x04,0x6f,0x2b,0x8a,0xc3,0x1d,0x59,0x7a,0x57,0x07, + 0xfe,0xe1,0x65,0x71,0x6c,0x12,0x86,0x71,0x7e,0x12,0xdd,0x7b,0x49,0xfa,0x20,0x6f, + 0x39,0x9b,0xff,0x81,0x75,0xe6,0x7a,0x18,0x96,0x8f,0x0a,0xcd,0x89,0xfb,0xe7,0x3e, + 0xfc,0x35,0xf2,0x22,0xd7,0xff,0xa4,0x89,0x8e,0x34,0xff,0xd3,0x51,0x60,0x06,0xf1, + 0x19,0xe7,0x11,0xff,0x0c,0x79,0xf7,0x89,0xe7,0xb1,0xfe,0x3d,0xb1,0x2a,0x2f,0xff, + 0xf3,0xf2,0xa6,0xfa,0x33,0xeb,0xc6,0x5b,0x11,0xed,0xd4,0x25,0xef,0xb7,0xf3,0x3f, + 0xe4,0x0d,0x64,0x14,0x33,0xf9,0x1f,0x84,0x3d,0x6d,0x7d,0x75,0x1c,0x08,0x25,0xed, + 0xfc,0xcf,0x59,0xa9,0xc7,0xb8,0x32,0xe6,0xe0,0x7f,0xb0,0x88,0x40,0x0e,0x02,0xfe, + 0xf5,0x79,0x37,0xf5,0xb4,0x10,0x5a,0x78,0xd8,0xa0,0x5e,0xcf,0x39,0xf8,0x9f,0x1e, + 0xa1,0x26,0x05,0x23,0x25,0x9f,0xde,0x93,0xe6,0x7f,0x4a,0x47,0xa1,0x47,0xf2,0x65, + 0xd4,0xbf,0x97,0xed,0x61,0x68,0x84,0x77,0x63,0xc6,0xea,0xad,0x3a,0xdd,0xd9,0x2f, + 0xeb,0x75,0xa3,0x11,0x50,0xd2,0xc2,0x4b,0x67,0xe0,0x99,0xd2,0x49,0x38,0x80,0xf3, + 0x83,0x30,0xf8,0x39,0xe3,0xfc,0x8b,0x7b,0xd2,0xf8,0xe7,0xb9,0xcc,0xfc,0xd7,0x1e, + 0xd9,0x90,0xd9,0x5b,0x8f,0x6d,0x75,0xe8,0x5b,0xf8,0xf3,0x3f,0xb0,0xf1,0x3f,0x1e, + 0x5e,0xef,0xb6,0x02,0x5f,0xbb,0xd7,0x5a,0x06,0x5c,0xc8,0x54,0x8a,0x33,0xc0,0xdf, + 0xff,0x23,0xa7,0xfe,0x47,0xf2,0xf4,0xdb,0xb6,0x5d,0x1c,0x18,0x7b,0xcc,0xef,0x25, + 0xe6,0xe4,0x7f,0x6e,0xcb,0xec,0xff,0xe3,0xd4,0x03,0x2f,0xea,0xe0,0x89,0xb0,0xf1, + 0x2c,0xfc,0x63,0xaa,0x7d,0x46,0xbd,0xf5,0xa8,0xff,0xe9,0xc2,0x2b,0x4b,0x11,0xff, + 0x04,0xfb,0xbd,0x0b,0xf3,0xeb,0x7f,0xd8,0x32,0xdb,0xdb,0x7a,0x49,0x9f,0xac,0xe6, + 0x2b,0x6a,0x94,0xdd,0xcf,0x96,0xe2,0x58,0xab,0xbd,0xff,0xcf,0xa0,0x89,0x06,0x2d, + 0xe3,0x0b,0x0c,0x5f,0x19,0xf9,0x2f,0xe5,0x43,0xc3,0xb0,0xf1,0x3f,0x57,0x3f,0x06, + 0x9b,0xa4,0x94,0xf7,0x40,0x63,0xc5,0xfa,0xba,0x53,0x65,0x9b,0xd2,0xf9,0x2f,0x6e, + 0x9c,0xb3,0xea,0xbf,0x74,0xf8,0x21,0x31,0xbb,0x1d,0x92,0x4d,0x74,0x1e,0x27,0x82, + 0xc8,0x26,0x23,0xdf,0xf7,0x43,0xe1,0x00,0xdd,0x81,0x8a,0xa0,0x74,0xff,0xe7,0x36, + 0xc9,0x54,0x97,0xf9,0x06,0xf9,0x67,0xf5,0x7f,0xc5,0xd9,0x32,0xc3,0x15,0xb8,0xc2, + 0xf8,0xbe,0xc2,0x19,0xfc,0x4f,0x41,0x37,0x9c,0x34,0x40,0x4e,0xc2,0xc0,0x3f,0x08, + 0x7b,0x8e,0xc1,0x3e,0x66,0x7c,0x11,0x5b,0x43,0xd7,0x65,0xe0,0x1f,0x16,0x7f,0x47, + 0x24,0x5b,0xb6,0xcb,0xcd,0xf9,0x1f,0xc1,0xd0,0xa3,0x2a,0x1b,0x8c,0x13,0x63,0xd3, + 0xf8,0xa7,0x5b,0x19,0x16,0x4d,0x35,0x2c,0x31,0x8c,0x19,0xd5,0xe9,0x78,0x77,0x43, + 0x16,0xfe,0xc1,0xfe,0x87,0x1c,0xff,0x88,0x86,0xfe,0xb6,0xc4,0xc0,0x3f,0x8d,0x3c, + 0xfe,0x4a,0x07,0x0d,0xc3,0x71,0xfe,0x85,0x60,0xaa,0x73,0xa5,0xcd,0xc2,0x1d,0xda, + 0x0a,0xb3,0x11,0xd0,0x4c,0x9b,0x70,0xc8,0xc6,0xff,0x80,0xa5,0xfe,0xed,0xe2,0x86, + 0x2b,0xea,0x92,0xf8,0xa9,0x53,0x29,0x3c,0xe0,0x5f,0xea,0xe0,0x7f,0xfa,0x64,0x4c, + 0x43,0x37,0x1b,0x7c,0x8b,0x11,0x76,0x89,0x6a,0xc3,0x7b,0xe2,0x6c,0xac,0x88,0x77, + 0xf0,0x3f,0x8a,0x83,0xcd,0x78,0x20,0x5a,0x35,0x0c,0x6f,0x4b,0x8d,0xe6,0x15,0x34, + 0x6c,0xfd,0x9f,0xb7,0x17,0x9c,0xe7,0x65,0x31,0xec,0x57,0x34,0xf6,0xa5,0x0c,0xc2, + 0x9f,0x80,0x47,0x63,0x34,0x6b,0xab,0x32,0xf9,0x1f,0x0e,0x7b,0x28,0xb1,0x1b,0xa9, + 0xfe,0x87,0x0c,0xcc,0x66,0xf4,0x7f,0x46,0xfe,0xa7,0x03,0x9b,0xcc,0x63,0xff,0x1f, + 0x41,0x50,0x35,0xd1,0x14,0x42,0xbb,0x95,0xc2,0x61,0x6e,0xcc,0xcc,0xe4,0x7f,0x36, + 0x9b,0xe8,0xd1,0x30,0x42,0xc3,0x69,0xfd,0xf3,0x13,0x52,0x0e,0xfe,0xe7,0xa8,0x89, + 0x66,0x6d,0x46,0xb3,0xc3,0xc8,0xe6,0x7f,0x1c,0xb2,0x28,0x05,0x85,0xf1,0xc5,0xa9, + 0x2b,0x4b,0xbd,0x79,0xcf,0x87,0xcd,0x34,0x8c,0x9f,0x3c,0x8e,0xfa,0x77,0xf6,0x17, + 0xde,0xc7,0x40,0x4e,0x49,0xac,0x34,0x21,0xed,0x4b,0xa1,0x1d,0x01,0x61,0xcf,0x8a, + 0x58,0xeb,0x6e,0x38,0x24,0x94,0x20,0xb0,0xef,0x4e,0xf3,0x3f,0x1b,0xb3,0xf8,0x9f, + 0x9b,0xad,0x30,0xbd,0x87,0x3b,0xa2,0xa2,0x60,0x28,0xcd,0xff,0x54,0xa6,0xf8,0x9f, + 0x8c,0xb2,0x77,0xe3,0x58,0xd8,0xc7,0x0a,0x0e,0x30,0x44,0x54,0xb1,0x9e,0xec,0xb6, + 0xf3,0x3f,0x4a,0xba,0xdb,0x61,0xd7,0x7c,0x66,0xb4,0x1a,0xfe,0x8a,0x5d,0xf9,0x21, + 0xc3,0x3f,0x2d,0xc9,0x62,0x47,0xff,0xe7,0x14,0xff,0x53,0xe2,0x70,0xb3,0x48,0xe3, + 0x6f,0x75,0xe0,0x1f,0x73,0x7e,0xb4,0xf2,0x2b,0xda,0x64,0x9a,0xed,0x59,0x62,0x18, + 0x5c,0xd1,0x7a,0x81,0xfd,0x2f,0xbe,0x8c,0xc2,0x06,0x16,0xbf,0xec,0xe7,0x5f,0x68, + 0x07,0x14,0xf3,0xb5,0x95,0xf9,0xd8,0x4f,0x0c,0xf5,0x27,0x5c,0x88,0x78,0x3a,0xb4, + 0x89,0xce,0x1f,0xed,0xb1,0xeb,0x7f,0xa2,0xf0,0x98,0x74,0x40,0xb2,0xa1,0xbb,0x15, + 0xeb,0x2d,0xfd,0x4f,0xe9,0x29,0x03,0x11,0x39,0xfa,0xff,0x48,0x56,0x10,0x47,0xa3, + 0xd6,0x22,0xa2,0x0d,0x0f,0x9f,0x0a,0xf4,0xb9,0xfa,0xff,0x60,0x34,0x2f,0xb4,0x02, + 0x4d,0x83,0x71,0x22,0xf9,0x8b,0x46,0xfe,0xe2,0xa4,0xf5,0x3e,0xdb,0x72,0xf2,0x3f, + 0x68,0xfc,0x85,0x69,0xb0,0x27,0x0c,0x5b,0xfe,0xa7,0x43,0xb9,0x24,0x18,0xfe,0xfc, + 0xab,0x86,0xfa,0xd7,0x93,0x86,0x01,0x55,0x16,0x1e,0x48,0xc7,0xeb,0xfe,0xae,0x34, + 0xff,0xc3,0xcb,0xbe,0x8a,0x6d,0xb2,0x55,0x1b,0x9e,0xb1,0xf8,0x1f,0x29,0x20,0x3b, + 0xd8,0x09,0x8b,0xff,0xe1,0x15,0xf1,0x46,0xe3,0x20,0x5f,0x16,0xff,0xd3,0x6f,0xf2, + 0x3f,0x2f,0x14,0xd5,0x61,0x3d,0xb2,0x62,0xcc,0x18,0xed,0x55,0xb1,0x1f,0x20,0xd8, + 0xea,0xdf,0xed,0xfc,0xcf,0xbb,0x52,0x73,0xc2,0xb3,0xaf,0x33,0x3d,0x70,0x75,0xc2, + 0xdf,0x7c,0xcc,0x9b,0xb3,0xff,0x4f,0x2a,0x7e,0xa1,0x3a,0xc8,0xd2,0xff,0xa4,0xfe, + 0x8b,0x63,0x33,0xb2,0xcf,0x87,0xbd,0xd3,0x95,0xeb,0x3c,0xbe,0xce,0xe0,0xbf,0xff, + 0x3c,0x3e,0xb9,0x8b,0x54,0x42,0xb7,0xc6,0xeb,0x52,0x6d,0xc6,0x27,0x9c,0x87,0x78, + 0xe7,0xbf,0xf3,0x3c,0xc4,0xc1,0xff,0x64,0xe7,0x21,0x0e,0xe6,0xfd,0xe5,0xff,0x2b, + 0xe7,0x21,0x6a,0x86,0x01,0x9f,0x70,0x1e,0xe2,0x9d,0x7f,0xe4,0x79,0x88,0xda,0x1f, + 0x39,0xff,0xda,0x7f,0x9d,0x87,0xf8,0xef,0xfb,0xf7,0x9f,0xeb,0xfc,0xc1,0xff,0x7c, + 0xf7,0x93,0xae,0xb2,0x0e,0xd1,0xdf,0x4e,0xca,0x60,0xa0,0x7a,0x47,0x27,0x03,0x88, + 0x65,0x91,0x2e,0xa9,0x72,0x85,0x3f,0x44,0x94,0xc8,0xa6,0xb2,0xbd,0x62,0xd6,0xf7, + 0x58,0xe0,0x17,0x28,0x84,0x65,0x05,0x0a,0x64,0x21,0x01,0x21,0xa8,0xd0,0xa6,0xc9, + 0xd3,0x11,0x61,0x54,0xe8,0xd3,0xfc,0x02,0x48,0x99,0xdf,0xe3,0xbd,0x50,0x19,0x92, + 0xf1,0xf9,0xf7,0xaa,0xea,0x11,0xe6,0x0f,0xb7,0x75,0x6f,0x2a,0x3c,0xf3,0x85,0xee, + 0x90,0xaf,0xa2,0xfb,0x97,0x85,0x95,0x04,0x3d,0xa4,0xe3,0x7e,0xa9,0x02,0x3f,0x6a, + 0xa1,0x0c,0x24,0x79,0xba,0x0c,0x4b,0x81,0x19,0x52,0x87,0xc6,0x1e,0x3b,0x8b,0x16, + 0x96,0xe5,0xf8,0xde,0x3b,0x41,0x6d,0x93,0xc1,0x25,0x91,0xe7,0x41,0xa5,0x1e,0xfc, + 0x3a,0x96,0xaa,0x6a,0x9b,0xca,0x0c,0x4a,0xd5,0x60,0x37,0x57,0x62,0xda,0xc7,0x2b, + 0x2a,0x51,0x03,0x3e,0x89,0x40,0x07,0xf0,0x7b,0x8a,0x84,0x20,0xba,0x52,0x62,0xff, + 0x5b,0xcc,0x9b,0xd0,0x65,0xd5,0x42,0xc6,0xf7,0xd8,0x59,0x8d,0xcf,0xbf,0x4f,0x22, + 0x9d,0x92,0x9a,0xc0,0xa7,0x85,0x3b,0xaa,0xe9,0xa0,0x4c,0x5c,0x40,0x87,0xaa,0x55, + 0xf6,0xfc,0x88,0xe3,0x76,0x45,0xa8,0x86,0x22,0x80,0x22,0xe6,0x9b,0x24,0xa5,0x08, + 0x5f,0x47,0x63,0x17,0xfb,0xab,0x7d,0x1a,0x66,0x67,0xf0,0xa7,0x8c,0xf9,0xdf,0xe4, + 0xaf,0x1c,0xf4,0x7f,0xd3,0x35,0x2b,0xb4,0x49,0xde,0xe1,0x09,0xb4,0x2e,0x9f,0x15, + 0xd9,0x54,0xb1,0x50,0x63,0x7f,0x88,0x8a,0xa1,0x17,0xd4,0x4a,0x8a,0x48,0xdd,0xf1, + 0x5f,0x98,0x26,0x4d,0xa7,0x10,0x92,0x2b,0xd4,0x69,0x52,0x47,0x9b,0xda,0xaa,0x29, + 0x74,0x9a,0xbf,0x03,0x27,0xaa,0x42,0x2f,0x58,0xcc,0xfe,0x22,0xad,0x19,0xf3,0xf3, + 0x4b,0x55,0x0d,0xb1,0x69,0x91,0xe8,0x26,0x58,0xf8,0x00,0xb4,0x8a,0x8a,0xc6,0x8c, + 0x9b,0x20,0x44,0xca,0x8e,0xdc,0xbb,0xb8,0xf2,0x05,0x4f,0x6b,0x96,0x3f,0xec,0x20, + 0x7c,0x92,0x99,0xf7,0x0b,0x49,0xdf,0x84,0x59,0x63,0xd3,0xd4,0xe9,0x2f,0x4a,0x77, + 0xea,0xb3,0xa2,0x05,0xc1,0x8e,0xad,0xf0,0x4d,0xee,0x78,0xd3,0xff,0xba,0xca,0x2a, + 0x25,0x99,0x2d,0x1b,0xe8,0x62,0xef,0xe3,0x69,0xd7,0x14,0x3d,0x12,0x5c,0xe8,0xf2, + 0x68,0x11,0x45,0xf9,0xa5,0x52,0x19,0xf1,0x2f,0x15,0x33,0xfc,0xa1,0xaa,0xb8,0x54, + 0xd0,0x64,0x36,0x33,0x4a,0xa1,0xa0,0x16,0x41,0x52,0x08,0x40,0x1b,0xfe,0x21,0x42, + 0x42,0x35,0xd5,0x40,0x6c,0x73,0xbc,0x7e,0x50,0x57,0x62,0x05,0x1e,0x08,0x49,0x41, + 0x0a,0xc1,0xcf,0x79,0x94,0x56,0x69,0x28,0x12,0x0c,0xde,0x8f,0x6e,0xf0,0x21,0x86, + 0xf4,0x3b,0x40,0x0c,0xd9,0xee,0x96,0x18,0x7e,0x96,0x29,0xe0,0xa4,0xab,0x20,0x51, + 0xad,0x1a,0x34,0x29,0x54,0x08,0x51,0xfe,0xc2,0xaa,0x28,0xe3,0xff,0x43,0x1d,0xfe, + 0xd0,0x78,0x39,0xf6,0x9f,0xa3,0x2a,0xd2,0x1d,0xcc,0x8e,0x72,0x9f,0xaa,0xda,0x0c, + 0x6a,0xdd,0xdd,0xd4,0x14,0x8c,0x53,0xaa,0xa9,0x0a,0x28,0x63,0x94,0xb2,0xeb,0x8a, + 0x86,0x46,0x0c,0x18,0x62,0xe6,0x57,0xf8,0x4f,0x2f,0xdb,0xfc,0x61,0x53,0x47,0xe4, + 0x47,0xf4,0xc6,0xef,0xdf,0xfd,0x67,0x91,0xce,0x8e,0x99,0xb4,0xa9,0xe2,0x33,0x0f, + 0x76,0x74,0x2e,0xfd,0x2b,0x76,0xe5,0x3b,0xd7,0x2c,0x5d,0x2d,0xb4,0xea,0x4d,0x57, + 0xef,0xa9,0x70,0x2e,0x08,0xbe,0x66,0x94,0x72,0x42,0x09,0xa5,0xec,0x7b,0x6a,0xd7, + 0x22,0x94,0x2d,0x31,0x6d,0x29,0xe0,0x40,0x69,0x59,0x59,0x99,0x85,0xae,0xcc,0x7f, + 0xf5,0x84,0x74,0xf3,0x55,0x58,0x2f,0x09,0x1d,0x7c,0xa8,0xf5,0x82,0x20,0xf3,0x75, + 0x5f,0x2f,0x77,0x2f,0x5b,0x66,0xbf,0x37,0xed,0x0d,0xee,0xc9,0xf2,0x0f,0x57,0xee, + 0x99,0xa4,0x90,0xf1,0x2f,0xfd,0xeb,0xc7,0xef,0x67,0xdc,0xbf,0xe4,0x4a,0xcb,0x64, + 0xe6,0xab,0xd8,0xee,0x7f,0xe3,0x0d,0xf3,0xfe,0xe7,0xde,0x37,0x8c,0xf7,0x5b,0xa6, + 0xf2,0x57,0xf7,0xb4,0x98,0xf7,0xdf,0xf3,0x07,0xf9,0xb7,0x67,0x5b,0x3e,0x4e,0xdd, + 0x66,0xfd,0x17,0x27,0x3f,0x9e,0xe2,0xfe,0x2b,0x0b,0x8c,0xd1,0xb5,0x5c,0x99,0x34, + 0x8c,0xeb,0x26,0xaf,0x64,0x3d,0xff,0x17,0x4b,0xc5,0xf5,0xda,0x29,0x65,0x11,0x14, + 0xf4,0x1b,0x46,0x59,0xf1,0x2f,0xc4,0x6f,0x68,0xb7,0x5a,0x46,0xfb,0x9f,0x48,0xc5, + 0xfa,0x42,0xeb,0xfe,0xcf,0x2e,0x93,0xbe,0x21,0xdc,0xaa,0x7d,0x99,0x05,0xff,0x02, + 0x66,0x2c,0xfd,0x72,0x45,0xf9,0x00,0x33,0xda,0xb4,0x56,0xa5,0x7c,0x40,0x60,0x57, + 0xc2,0x5f,0x56,0xca,0xf5,0xe9,0x26,0x5e,0x05,0x4a,0x04,0xb5,0xab,0x4d,0x2d,0x95, + 0xa5,0x88,0xa0,0xd2,0x94,0x51,0xc9,0x8c,0x3f,0x91,0xa5,0x7b,0xcd,0x2b,0xd6,0xf1, + 0x3e,0xb8,0xf4,0xd8,0x5e,0x75,0x35,0x5c,0x05,0xdb,0xa8,0x10,0x46,0x43,0x29,0xb8, + 0x57,0x08,0x0b,0xab,0xc9,0x55,0x15,0x05,0x54,0xb8,0xad,0x63,0xb5,0xf6,0x25,0x28, + 0xb0,0xdd,0xff,0xd9,0xd5,0x05,0x0d,0xc2,0xe7,0xe9,0x97,0x97,0x4a,0xdd,0x05,0xdf, + 0x14,0x6e,0xa5,0x5f,0x56,0xcb,0x13,0x05,0x77,0xa6,0x0c,0x21,0x75,0xc5,0xf6,0x3e, + 0xbf,0xd0,0xc2,0xaa,0x22,0x4b,0x84,0xb9,0x3e,0x08,0x43,0x05,0x14,0x82,0x60,0x19, + 0x5d,0x92,0x79,0x25,0x3d,0xde,0x5f,0x68,0xd2,0xed,0x42,0x05,0xbd,0x49,0x85,0x2d, + 0x92,0x4f,0x90,0xf5,0x90,0xaa,0x74,0x4b,0x6a,0x87,0x4c,0x43,0x41,0xe5,0x5e,0x49, + 0x65,0xce,0x93,0x5d,0xb1,0xdf,0xbf,0xbc,0xe0,0xe6,0x8e,0x5b,0x62,0xb7,0xf8,0x0b, + 0x5c,0x05,0xa1,0x8e,0xf6,0xf8,0x2d,0xfe,0x72,0x57,0xc1,0x52,0xda,0xce,0xae,0x94, + 0x93,0x02,0x8d,0xb6,0xab,0x65,0x4d,0xe5,0xb0,0x30,0x3d,0x3f,0xb3,0x84,0x69,0xda, + 0x9f,0xeb,0xe5,0xb7,0x48,0xb3,0x84,0x2f,0xc3,0x9f,0xeb,0xd3,0xd7,0x17,0xdc,0x2a, + 0x7c,0x11,0x6e,0xd1,0xcb,0x83,0xcc,0x10,0xd1,0x58,0x2c,0x59,0xf4,0x0f,0xbb,0xdf, + 0xcf,0x1c,0x47,0x29,0x48,0x54,0xc1,0xa6,0x37,0x4a,0x58,0x40,0x48,0x88,0x2e,0x90, + 0x85,0x11,0x89,0x7d,0x49,0x0a,0x95,0x14,0x16,0x10,0xd2,0xef,0xb3,0x96,0xc8,0x5a, + 0x04,0xd4,0xae,0x0a,0x95,0x30,0xd7,0x0f,0x95,0x54,0x36,0x0c,0x95,0x19,0x85,0x29, + 0x63,0x69,0xfa,0x7d,0x7e,0xd1,0x5e,0x50,0x2d,0xfc,0x37,0xf8,0x92,0x56,0x1e,0x2d, + 0x58,0x63,0x1a,0x61,0xe1,0x04,0x7c,0x09,0x52,0xc6,0xff,0x82,0x72,0xc7,0xfc,0x88, + 0x61,0x38,0xc1,0xfe,0x5e,0x05,0x94,0x1b,0x0d,0xd8,0x41,0xe7,0x76,0xf6,0x87,0xfb, + 0x5b,0x66,0x4c,0x63,0x06,0xbd,0x8a,0x19,0xb6,0xf5,0xc3,0x1c,0x5b,0x87,0x07,0x3d, + 0x53,0x44,0x52,0x3a,0x3c,0x95,0xad,0xb2,0x72,0x84,0x5d,0x91,0xd4,0x9b,0x98,0x01, + 0xc1,0x7e,0x4f,0x90,0x5d,0xd1,0xd3,0xef,0xc3,0xfe,0x05,0xd9,0x9e,0x4a,0xc4,0x95, + 0x91,0x32,0x74,0x6e,0x10,0x4c,0xb6,0x98,0x57,0x6c,0xf3,0x43,0x84,0x20,0x5d,0xa9, + 0xce,0x90,0xcb,0x22,0x29,0x43,0x3a,0x22,0x04,0xfb,0xb9,0xf1,0x22,0xf3,0xe7,0x2b, + 0xd5,0x2f,0xca,0x92,0xed,0xfe,0x5f,0x84,0x0a,0xc2,0x1d,0xab,0x55,0xb6,0xa8,0x22, + 0x86,0x21,0x97,0x33,0xa3,0x7f,0xb5,0x7a,0x95,0x5c,0xde,0x59,0xa0,0xf6,0xaf,0x0e, + 0xb2,0x2b,0xd4,0x36,0x3f,0x21,0x3e,0x73,0xd6,0x14,0xa6,0x0c,0x8f,0x1a,0x32,0x0d, + 0x36,0x34,0xfb,0x78,0x6f,0x96,0xc2,0x1d,0x15,0x95,0x37,0xb5,0xc1,0x43,0xcc,0xb8, + 0x9a,0x0d,0x73,0x7a,0x44,0x5a,0xc3,0x66,0xe0,0xa6,0xb6,0xe9,0x0f,0xb1,0x85,0xe4, + 0x51,0x5b,0xdb,0xa6,0xd3,0xe9,0x56,0xc8,0xf8,0x6c,0xb8,0x60,0xb5,0xf0,0x25,0xf8, + 0x2c,0x95,0x54,0x6e,0xfc,0x39,0x2d,0x0f,0x4b,0xab,0xe1,0x26,0x6e,0x08,0x15,0xcc, + 0x98,0x4e,0xcb,0x35,0xdb,0xf7,0x55,0x08,0x7f,0x46,0x6f,0x09,0x97,0x6f,0x97,0x0a, + 0x05,0xb6,0xcc,0xc2,0x65,0x15,0x05,0x68,0xdc,0x62,0x1a,0xfc,0x0a,0x0b,0x41,0xe6, + 0xfd,0xfd,0xa5,0x1c,0x56,0xdf,0xdc,0x06,0xa5,0xec,0x13,0x58,0x6a,0x7c,0x0b,0x12, + 0xba,0xf1,0x36,0x09,0xaf,0x70,0xc3,0xda,0xee,0x03,0x0c,0xdc,0x44,0xa6,0xd3,0xae, + 0xf0,0xd7,0x2a,0x2a,0x6e,0x12,0xff,0x8c,0xbe,0x1a,0xfe,0x4c,0x45,0x31,0x1a,0xdb, + 0xb8,0x31,0x6d,0xba,0x71,0x45,0x4b,0xcf,0x4f,0xd7,0x4d,0x05,0xdf,0xe8,0x40,0x27, + 0x70,0xed,0x0b,0x45,0x68,0xfc,0x49,0x45,0xf9,0x0b,0xec,0xca,0x29,0xed,0xcb,0x68, + 0xdc,0xd6,0x71,0x2a,0xfc,0xb7,0x15,0xe5,0x76,0x7f,0x72,0x93,0xf0,0x0d,0x7a,0x2a, + 0xbc,0xa8,0xa2,0xf8,0x05,0x11,0x8d,0x69,0x86,0x71,0xab,0x71,0xe5,0x36,0x8a,0x4f, + 0xb8,0x56,0x9f,0x6e,0xbb,0x5f,0xe2,0xcf,0x5f,0xdd,0xf6,0x42,0x41,0xfa,0xf9,0x1b, + 0x3d,0x61,0x7c,0x3e,0x2c,0xec,0xf0,0x84,0x5b,0x2b,0xec,0xdf,0x3b,0xe0,0x7a,0x40, + 0x27,0x03,0x86,0xff,0x69,0x37,0x1c,0xd1,0xad,0xa6,0x47,0xba,0x15,0x1d,0x11,0xb5, + 0xad,0xb6,0x42,0xe1,0x36,0xba,0x3a,0x7c,0x55,0x05,0xf3,0x4e,0x86,0xc1,0xfc,0x0f, + 0x73,0x3b,0x86,0x51,0xc9,0x8c,0x2f,0x55,0x94,0xdb,0xee,0xff,0xac,0x56,0x1e,0x14, + 0x56,0xc2,0x17,0x41,0xd2,0x0b,0xd6,0x0b,0xb7,0xc2,0x97,0xa1,0x3c,0x6d,0x08,0xc1, + 0x94,0x91,0x7e,0x9f,0xcf,0xb6,0x82,0x1a,0x93,0xfd,0x0c,0x4d,0x45,0x20,0x4c,0x2b, + 0xd8,0x27,0x28,0xa4,0x0d,0x49,0x35,0x0c,0x6a,0x1b,0xef,0x72,0x29,0xbc,0xa3,0x42, + 0xbd,0x89,0xdd,0x8f,0x6e,0x87,0x2d,0x33,0xc5,0x66,0x84,0x0d,0xc3,0x7e,0xbf,0x36, + 0xa7,0x7d,0xe9,0x2d,0xa5,0x7f,0x0e,0x5d,0xcc,0xdb,0x74,0xb4,0x57,0xde,0x22,0x73, + 0xb7,0xf3,0x67,0x2a,0x33,0xc4,0x82,0x76,0xf4,0x3f,0x72,0x01,0xd8,0xe6,0xc7,0x2d, + 0xb4,0x27,0x6e,0x09,0x96,0xcb,0x52,0xab,0xd0,0xae,0xdf,0xa2,0x96,0x7b,0x0a,0xb8, + 0x11,0x64,0x46,0xc8,0x30,0xe4,0x02,0xcd,0x36,0x3f,0xa0,0x85,0x15,0x45,0x92,0x04, + 0xc4,0x2f,0xa0,0x74,0x14,0x72,0x17,0xc8,0xb6,0x65,0xcc,0x17,0x02,0x5e,0xe1,0x46, + 0x1a,0x01,0x7d,0xb6,0xf5,0xff,0x69,0xef,0xfc,0x42,0xe3,0x38,0xee,0x38,0xfe,0x9b, + 0xbb,0xd9,0xf3,0x9e,0x7d,0x72,0x77,0xa5,0xbd,0x66,0xd5,0x08,0xb3,0xfa,0x53,0x4b, + 0xa6,0xa4,0xac,0x82,0x95,0xba,0x08,0xa2,0x39,0xdd,0x9d,0x7c,0x12,0x8e,0x7c,0x96, + 0x1c,0xc5,0x18,0x53,0xd6,0x46,0x34,0x26,0x50,0x90,0x0d,0xa5,0xee,0x43,0x9d,0x39, + 0xf5,0x9c,0xaa,0xc5,0x85,0x8b,0xac,0x62,0x19,0x04,0x3d,0x13,0xd5,0xf4,0x25,0xd0, + 0x42,0x8d,0xf3,0xd6,0x93,0x62,0xab,0x2e,0xf4,0xc1,0xa4,0xaa,0xc9,0x43,0xa9,0x6c, + 0xd0,0x4b,0xa1,0x26,0x2f,0x86,0xa2,0x16,0x45,0xfd,0xcd,0xec,0xdd,0xed,0xc8,0x0d, + 0x86,0xa4,0xd0,0x42,0x99,0xef,0xd3,0x97,0xd9,0xb9,0xd5,0x6f,0x67,0x67,0x7e,0xf3, + 0xf9,0xed,0xea,0xa4,0x58,0x17,0xe7,0x37,0xbd,0xc2,0xe2,0xac,0x04,0x54,0x30,0x05, + 0x52,0xf2,0x52,0x9f,0x87,0x26,0x21,0x5a,0xd0,0x28,0xf1,0xe4,0xd9,0x1e,0xcc,0xf6, + 0x30,0x15,0x4f,0x73,0x43,0x98,0x87,0x20,0x0c,0x7c,0x4c,0x31,0xff,0xe0,0x8e,0x50, + 0xcf,0x3f,0xd1,0xf5,0x5e,0x61,0x69,0xb1,0x4d,0xbc,0x12,0xff,0x29,0x8f,0x37,0xf3, + 0x4f,0x00,0x67,0xa8,0x30,0x7b,0x3c,0x1c,0xff,0x17,0xd0,0xa8,0xf1,0xcb,0xa4,0x91, + 0xa5,0x9c,0x3b,0x3e,0x49,0x89,0xd4,0x59,0xa3,0x3e,0x71,0x63,0xc2,0xe0,0xbc,0x17, + 0x2b,0x0c,0x4d,0x24,0x1a,0x26,0x19,0x86,0xc5,0x6e,0x3f,0xa4,0x82,0x78,0x11,0xd6, + 0xe1,0x30,0x62,0x2d,0xb6,0xac,0x83,0x40,0xdf,0x98,0xc8,0x48,0x4a,0x7f,0xa3,0x9f, + 0x1d,0x2b,0xb6,0x2d,0x94,0x7f,0x47,0xfa,0x6b,0xc7,0x58,0x9b,0x93,0xbb,0x47,0xfa, + 0x33,0xe3,0xc5,0x36,0x87,0xde,0x25,0x9d,0xb9,0x63,0xc5,0x49,0x8b,0xaa,0xfd,0xbb, + 0x8d,0xf3,0x2b,0xdf,0xf2,0xa7,0xe6,0xe8,0x7b,0x68,0x4e,0xfb,0x53,0x57,0xd3,0xd2, + 0x78,0xa1,0xa9,0xc9,0x16,0x35,0x7e,0x23,0xfc,0xf6,0x14,0x6b,0x14,0xdf,0x45,0x58, + 0xc0,0x18,0x65,0x3c,0x0b,0x8d,0x78,0x76,0x5d,0x6f,0x2e,0xb0,0x5d,0x3a,0x42,0x60, + 0x2e,0xdc,0xc8,0x7c,0x1b,0x8d,0xed,0x96,0xb3,0x9d,0x36,0x9f,0x3e,0x67,0xb9,0xe5, + 0x11,0x34,0x6a,0xff,0xb3,0x45,0x3b,0x47,0xf3,0xc4,0x61,0x46,0xd1,0x3e,0x49,0x5f, + 0x27,0xe9,0x5c,0xbe,0xe8,0x9d,0xa4,0x27,0x20,0x9d,0xbb,0x27,0x5a,0xd2,0x24,0xad, + 0xce,0x07,0xb3,0x53,0xa4,0x40,0xcb,0x2b,0x9b,0xa2,0xec,0x99,0x75,0xc4,0x7f,0x28, + 0x6e,0x98,0xce,0x09,0x57,0x98,0x2b,0xea,0xe9,0xf7,0x1a,0xb1,0x12,0x54,0xa1,0x0f, + 0xf6,0x92,0x18,0x67,0x55,0xab,0x8f,0xa2,0xa9,0x44,0xe6,0x16,0x1a,0xb5,0x7f,0x2a, + 0x31,0x49,0xca,0xb5,0x4e,0x1f,0x8e,0xc5,0x27,0x61,0xbd,0x36,0xe0,0xb7,0x44,0xe6, + 0xe0,0xa4,0x75,0xf2,0xee,0xc0,0xcb,0x2d,0x6a,0x3c,0x49,0xe3,0x62,0xe6,0x4c,0xe5, + 0x0d,0xcf,0xbe,0x4f,0x71,0xf7,0x9f,0x7d,0xc1,0x33,0xee,0x23,0x18,0xfc,0x39,0x04, + 0x83,0x8b,0xf1,0x25,0xfe,0x3d,0xef,0x67,0xea,0xf8,0xbf,0x38,0x36,0xfc,0xb0,0x72, + 0x7b,0xf9,0xa5,0xe4,0x3e,0x61,0x7e,0xb3,0xfc,0xd2,0xe8,0xbe,0x89,0xb1,0x07,0xf3, + 0xb7,0x7b,0xde,0x4f,0xee,0x1b,0x1e,0x5b,0x17,0xe6,0x90,0x1a,0xcf,0xe0,0xdb,0xe3, + 0x3b,0x7f,0xfc,0xed,0xd3,0x27,0x5b,0xd2,0xdc,0x79,0xfa,0xc9,0xd6,0xe0,0xa7,0xc7, + 0x37,0xae,0xed,0x6c,0x6e,0x6f,0x0d,0x5e,0x3e,0xbe,0x23,0xcc,0x36,0xfc,0x07,0x7a, + 0xf5,0x46,0xf2,0xe0,0xf0,0x68,0x65,0x7e,0x7a,0x68,0xeb,0x4b,0xb7,0xb2,0x3b,0x95, + 0x7f,0xfc,0xe0,0xd5,0x9f,0x8f,0xbe,0xfd,0xd1,0x68,0xe5,0xfa,0xf6,0xd0,0xce,0x68, + 0xef,0x47,0xa3,0x4f,0xaf,0x6f,0xaa,0xfd,0x87,0x2e,0x8f,0x6f,0x5c,0xbb,0xb3,0xf9, + 0x64,0x6b,0xa8,0x1e,0xc6,0xf6,0x90,0x0c,0x6c,0xf3,0x13,0xec,0x3f,0xbe,0x21,0x23, + 0x54,0xfb,0x77,0x1f,0x28,0x6c,0xcc,0x7f,0x63,0xf3,0xea,0xd9,0x41,0xf1,0xc1,0x5f, + 0xe3,0x07,0xd1,0xfc,0xa5,0xed,0x4e,0xf9,0xc9,0x56,0xb7,0x2b,0xcd,0xdf,0xbe,0xbf, + 0x2b,0xa0,0xec,0x0c,0x5b,0xb2,0x7a,0x5b,0x93,0xb5,0xae,0x99,0xcc,0x12,0xbc,0x49, + 0x5b,0x56,0x40,0xb6,0xd0,0xe4,0x4a,0x0c,0x8d,0xdf,0x4b,0x89,0x3a,0x9e,0x38,0xff, + 0x05,0x1f,0xba,0x20,0xb0,0x50,0x80,0xa2,0x7d,0x57,0x24,0x6a,0x34,0x98,0xa8,0x4f, + 0xc8,0x16,0x43,0xed,0x1f,0x23,0x81,0xc8,0xcf,0x2e,0x34,0xf9,0x70,0x95,0x78,0x20, + 0x8d,0xe4,0xc3,0xa0,0x75,0x77,0x7e,0x46,0xe6,0x11,0x90,0x16,0x2b,0x21,0xb6,0xc9, + 0xfd,0xb0,0xc4,0x43,0x6c,0x73,0x11,0xe4,0xce,0x72,0xc1,0x6f,0x27,0xd4,0xfe,0x66, + 0xee,0x62,0x32,0xc5,0xb3,0x06,0xcc,0x4d,0xbf,0x0c,0x1d,0xe5,0x3d,0xe1,0xc4,0xe8, + 0xe0,0x47,0x9b,0xa6,0xc7,0x56,0xe3,0x01,0x08,0xea,0x7c,0x88,0xd4,0xe5,0x5a,0x2a, + 0x1f,0x2a,0x26,0x52,0x12,0xb1,0x10,0x97,0x55,0x20,0xd6,0x97,0xfc,0x5a,0xa3,0x55, + 0xa1,0xbd,0x04,0xf9,0x30,0xb0,0x16,0xe9,0x41,0x92,0xe4,0xc3,0xc5,0x5d,0xcf,0xac, + 0x0e,0xd1,0xb1,0xd2,0x97,0xab,0xf9,0x0f,0xec,0x3e,0x7a,0xba,0xdc,0x7a,0x93,0xfe, + 0xd2,0xee,0x82,0xb1,0x52,0x6b,0x35,0xf7,0x81,0xfd,0x75,0x2a,0xcd,0x9c,0xf2,0x76, + 0xdc,0xac,0xb5,0x40,0x1b,0x38,0x0f,0x8c,0x8a,0x24,0x1d,0xa7,0x06,0xbf,0x92,0xbb, + 0x8d,0x53,0x33,0xfc,0xc8,0xb0,0xe8,0x03,0x35,0x8a,0xc9,0x17,0x2f,0x60,0x02,0xde, + 0x01,0x59,0xec,0x31,0x1c,0xa4,0x00,0xeb,0x3c,0x6a,0x92,0xb0,0xcc,0xa5,0xc8,0x8c, + 0x7e,0x74,0x7e,0xf1,0xf8,0x8e,0x5b,0x1e,0x16,0xeb,0x22,0x71,0x58,0xf2,0x81,0x1b, + 0x35,0xc5,0x93,0xbb,0x39,0xab,0x8b,0x9a,0xa5,0x18,0x1e,0xda,0xd5,0xbf,0x3e,0xec, + 0x32,0xd1,0xbb,0x98,0xf1,0x6d,0x9e,0x68,0x80,0x09,0x0d,0x4d,0x3b,0x6f,0xf6,0xb7, + 0x08,0x8b,0x05,0xe2,0x8b,0x32,0x82,0xcc,0x84,0xc1,0xd1,0xbb,0x0f,0xd3,0xa2,0x45, + 0xfc,0xea,0xf1,0x34,0xdc,0x80,0x83,0x1e,0x89,0x9e,0x28,0xb0,0x3a,0x1f,0x66,0x0b, + 0xb8,0xdf,0x49,0x50,0x2c,0xe0,0xb6,0xe8,0xff,0x58,0x80,0x62,0x65,0xb5,0x47,0x1e, + 0x32,0x2b,0xb5,0xe6,0xef,0x43,0x32,0xf8,0x77,0x3e,0xe4,0xac,0x81,0x85,0x4d,0xd3, + 0xfc,0x7b,0x11,0x0c,0xd3,0xa3,0x2f,0x21,0xcd,0x9a,0xad,0x1b,0xf8,0x90,0xd6,0xcd, + 0x6a,0xd8,0x92,0xb2,0x6a,0x56,0x14,0x0f,0x13,0xfc,0xe6,0x8d,0xe0,0x4d,0x17,0x06, + 0x90,0xdf,0x7e,0x28,0x2e,0xd3,0x93,0xd7,0xcb,0xf0,0xd0,0x04,0xb5,0x79,0x14,0x0f, + 0xf9,0x2c,0x3e,0xf4,0x9f,0x69,0xa9,0x35,0x2b,0xda,0x22,0x19,0x0e,0xcf,0x2f,0x78, + 0x38,0x34,0xb6,0xb8,0xf0,0xba,0x11,0x2d,0xb8,0xbf,0x47,0xf3,0x53,0xc4,0x53,0x24, + 0x0e,0xe4,0xd1,0xd7,0x8d,0x8d,0x37,0xb5,0x6e,0x1a,0x87,0x86,0x9b,0xfb,0x69,0x01, + 0x07,0x3c,0xc3,0x9d,0xc0,0x70,0x89,0x58,0x17,0x56,0x40,0x85,0xc9,0x3c,0x63,0xa2, + 0xe9,0x53,0x00,0x31,0xf3,0x4d,0x9c,0x05,0x8e,0x88,0x96,0xd5,0x6b,0xa5,0x72,0xc3, + 0x84,0x2d,0xa0,0xc4,0x33,0x85,0x34,0x58,0x0e,0x3a,0x4f,0xb9,0x53,0x08,0x8a,0x7f, + 0x0a,0xd2,0xae,0xd1,0x00,0xc5,0x54,0x93,0x18,0x15,0x5e,0x25,0x82,0xdf,0x3a,0x82, + 0xa3,0x96,0xb3,0x26,0xcd,0x9b,0x56,0xfb,0x5a,0xe2,0xbb,0x04,0x5b,0x8a,0xce,0x3a, + 0x96,0x96,0x1d,0xec,0xe8,0xa9,0x43,0xca,0xf5,0x92,0x84,0x73,0x81,0x77,0x04,0xbd, + 0x2e,0x59,0x8b,0x5d,0xe0,0x4b,0x68,0x92,0x6b,0x20,0x4c,0x1b,0x9a,0xd8,0x85,0x92, + 0x68,0x51,0xf2,0x49,0x31,0x3f,0x22,0xe9,0xf1,0x0d,0xd7,0x8c,0xf8,0x90,0x0e,0x94, + 0xcf,0x04,0x6d,0xa7,0xd2,0x0f,0xc9,0x85,0x2b,0x02,0x1d,0xed,0xd5,0x66,0x3c,0x0c, + 0xa1,0x57,0xa6,0x1d,0xe4,0x73,0x34,0xa3,0x21,0x16,0xce,0xf0,0xdd,0x15,0xab,0x12, + 0x0f,0xce,0x64,0x4c,0x32,0x41,0x62,0x11,0x6e,0xa1,0xf9,0x4a,0x80,0x69,0xe7,0x1d, + 0x2a,0x5b,0xd0,0x84,0x87,0x5c,0x75,0x3f,0xcd,0x07,0x70,0x89,0xec,0x87,0xec,0x2c, + 0x3c,0x2a,0x1f,0x21,0x07,0x20,0xcb,0xed,0x47,0xf4,0x12,0x9a,0xa3,0x68,0x7a,0x2e, + 0x81,0x34,0x11,0x1f,0x32,0x32,0x01,0xde,0x32,0xf2,0x21,0xc6,0xc3,0x3d,0xde,0xee, + 0xc7,0x10,0x0b,0xf9,0xb4,0xc0,0xc2,0x02,0x99,0xe7,0x41,0x68,0xb8,0x12,0x0f,0xce, + 0xb7,0x9b,0x72,0xfe,0xfc,0xa4,0x8c,0x34,0x58,0xc5,0x32,0x6a,0xb6,0xdc,0xe0,0xc3, + 0xb2,0x98,0x6f,0x82,0x0f,0xd5,0xf5,0x45,0x20,0xe3,0xb4,0x86,0xf3,0xa7,0x64,0x79, + 0x79,0x13,0x59,0x8a,0xa1,0xc9,0xa1,0xa1,0xa1,0xc9,0x44,0x3c,0xc6,0x18,0x96,0x94, + 0xf7,0x1d,0xdf,0x30,0x61,0x2f,0xae,0x23,0xa7,0x4a,0x52,0x24,0xeb,0x15,0x6b,0xd8, + 0x82,0x06,0xea,0x86,0x91,0x28,0x1e,0x93,0xfa,0xb6,0xe4,0x43,0xce,0xba,0x30,0xdb, + 0xc4,0x91,0x0f,0x59,0x1d,0x0b,0x9b,0x06,0x94,0xf5,0x35,0xec,0xb5,0x96,0x78,0xd5, + 0x33,0x17,0x63,0x5d,0x48,0x83,0x58,0x62,0x0b,0x3e,0x9c,0x43,0x12,0xdb,0x3b,0x87, + 0x09,0xa3,0x22,0xf8,0x70,0x0e,0x94,0xf5,0xc5,0xae,0xca,0x24,0x83,0x39,0xb7,0xec, + 0x49,0x53,0xc2,0xfc,0x63,0xbb,0xf0,0x6d,0x62,0xf3,0x3f,0x04,0x16,0xa2,0x4e,0xac, + 0x9d,0x37,0xd7,0x17,0xf6,0xe7,0xd3,0xd0,0x0e,0x89,0x8c,0x59,0xe1,0x01,0xdc,0x88, + 0x63,0x46,0xae,0xc0,0x4c,0x1f,0xe6,0x9f,0x18,0xa9,0xac,0x61,0x8e,0x46,0x53,0x52, + 0xd7,0x57,0xc0,0x8e,0xc0,0x7e,0x88,0xcf,0xd6,0xaa,0xfc,0x08,0xd9,0x4f,0xb2,0xbc, + 0xf2,0x88,0x9e,0x6f,0x11,0x77,0x90,0x3f,0x9a,0x3e,0x92,0xdc,0x1f,0xc7,0x3b,0xc8, + 0x9b,0xe3,0x53,0xc4,0xf2,0xfb,0x9b,0xc1,0xfe,0x53,0xf1,0x05,0xf8,0x05,0xf8,0x2c, + 0x65,0xc5,0x29,0x7c,0x88,0xb9,0x53,0x9a,0x95,0x46,0x8b,0x7a,0xbf,0x28,0x0c,0xb0, + 0x96,0x62,0x7c,0xa2,0xb2,0xc0,0xfb,0x59,0x4b,0x26,0xee,0xc0,0x3d,0xda,0x5f,0x48, + 0x15,0x43,0xc3,0x52,0x13,0x71,0xc7,0x5a,0x25,0x56,0x33,0x9e,0x2c,0x0d,0x56,0x5c, + 0x7f,0xc4,0x85,0x1f,0x95,0x99,0x30,0xa6,0x7d,0x2d,0x6c,0x49,0xd9,0xd7,0x21,0x58, + 0x29,0x08,0xc3,0x2d,0x65,0x7c,0xa0,0x1b,0xb3,0xb4,0xfa,0xf2,0xe4,0xee,0x67,0xbc, + 0xd7,0x8a,0xd6,0x57,0xa1,0xc1,0x87,0x3c,0x77,0x4e,0x98,0x4e,0xeb,0x63,0xe4,0x43, + 0x4b,0x60,0xe1,0x22,0x9c,0xb3,0xcd,0x90,0x0f,0x9b,0xe3,0x99,0x67,0xb9,0xd7,0xed, + 0xb4,0x93,0xcf,0xf3,0x13,0xd3,0x45,0xdb,0x31,0xf2,0xc4,0x62,0x0c,0xd3,0x8e,0x81, + 0xf9,0x27,0x07,0xd8,0x42,0xf3,0x40,0xa2,0xf5,0x8e,0xf3,0x21,0xac,0x8c,0xbb,0x64, + 0xe6,0xb3,0x66,0x0d,0x39,0x37,0x41,0x14,0x31,0xc4,0xac,0xd7,0x0b,0x25,0x88,0x78, + 0x5e,0xf0,0x21,0x87,0x2a,0x43,0x1a,0xa4,0xb1,0x32,0x43,0x50,0xa4,0x2a,0x28,0x86, + 0x26,0xea,0xcd,0xf2,0xaf,0x91,0x49,0x46,0x1f,0x9c,0x7d,0xc5,0x6d,0x49,0xb4,0xb1, + 0xf5,0x07,0x9d,0x87,0x53,0x2d,0xf1,0x49,0x34,0x03,0x87,0x8d,0xd7,0xea,0x46,0xc9, + 0x3f,0x78,0xbd,0x3d,0x17,0x33,0x4b,0xc8,0x87,0xef,0xfe,0xbe,0x47,0xec,0xfe,0x7b, + 0xbc,0x74,0x2d,0x31,0x23,0x79,0xa0,0xbd,0x01,0x06,0x4a,0xfe,0x01,0xf8,0xda,0x5b, + 0x23,0x0f,0xdf,0xbd,0xbd,0xfc,0x9d,0x1b,0x2f,0xbe,0x35,0x26,0xf8,0xf0,0xfd,0x3a, + 0x1f,0x2e,0x47,0x7c,0xb8,0xeb,0x19,0xf7,0x50,0xc4,0x87,0xc7,0x05,0x1f,0xee,0xd4, + 0xf9,0xf0,0x69,0xc4,0x87,0xbb,0x78,0xec,0xf3,0xea,0xab,0x02,0x0b,0xff,0x5a,0xd9, + 0xd9,0x1e,0xda,0xaa,0x83,0x22,0x12,0xe3,0x73,0xf8,0x50,0xfe,0xf4,0xbf,0x6f,0x62, + 0xff,0x4f,0x1b,0xa0,0x78,0xf9,0x79,0x7c,0x38,0xd8,0xe0,0xc3,0xee,0x03,0xe3,0x1b, + 0xf3,0xfd,0x9b,0x4f,0x1e,0x0f,0x5d,0x7a,0xa6,0xff,0xe3,0x2f,0x1e,0xbd,0x0f,0x1e, + 0x11,0x2f,0x28,0x7c,0xc8,0xa6,0xbe,0xf8,0x59,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4,0xb4, + 0xb4,0xb4,0xb4,0xb4,0xfe,0xdf,0x25,0x6b,0x07,0xaa,0x6b,0x07,0x2d,0x2d,0x2d,0x2d, + 0x2d,0x2d,0x2d,0x2d,0x2d,0x2d,0xad,0xe7,0x4b,0xd6,0x0e,0x09,0x5d,0x3b,0x68,0x69, + 0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x3d,0x5f,0xb2,0x76,0x30,0x65,0xed, + 0xf0,0xbf,0x0e,0x45,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0x4b,0xeb,0xbf, + 0x28,0x5f,0xfc,0xd1,0x24,0xf8,0xe7,0x79,0x1f,0xb8,0xf8,0xce,0x53,0xdc,0x07,0xf6, + 0xb9,0xdf,0x27,0xd4,0x3f,0x6b,0xf8,0x50,0x25,0xd1,0x39,0x1f,0x9f,0x7e,0xb6,0xdf, + 0xbf,0x00,0x34,0x34,0xbf,0x69,0xee,0x33,0x01,0x00, diff --git a/board/fads/fads.h b/board/fads/fads.h index 9aed226..aff1b7e 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -197,9 +197,25 @@ #define CFG_DIRECT_FLASH_TFTP #if (CONFIG_COMMANDS & CFG_CMD_JFFS2) -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS -#define CFG_JFFS2_FIRST_SECTOR 4 + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3" +#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" +*/ + #define CFG_JFFS2_SORT_FRAGMENTS #endif /* CFG_CMD_JFFS2 */ diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c index 4073453..7dd0d3f 100644 --- a/board/funkwerk/vovpn-gw/flash.c +++ b/board/funkwerk/vovpn-gw/flash.c @@ -447,60 +447,3 @@ flash_real_protect(flash_info_t *info, long sector, int prot) *addr = FLASH_CMD_RESET; return (0); } - -/*----------------------------------------------------------------------- - * Support for flash file system (JFFS2) - * - * We use custom partition info function because we have to fit the - * file system image between first sector (containing hard reset - * configuration word) and the sector containing U-Boot image. Standard - * partition info function does not allow for last sector specification - * and assumes that the file system occupies flash bank up to and - * including bank's last sector. - */ -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART) -#error TODO - -#ifndef CFG_JFFS2_FIRST_SECTOR -#define CFG_JFFS2_FIRST_SECTOR 0 -#endif -#ifndef CFG_JFFS2_FIRST_BANK -#define CFG_JFFS2_FIRST_BANK 0 -#endif -#ifndef CFG_JFFS2_NUM_BANKS -#define CFG_JFFS2_NUM_BANKS 1 -#endif -#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - -#include <jffs2/jffs2.h> - -static struct part_info partition; - -struct part_info *jffs2_part_info(int part_num) -{ - int i; - - if (part_num == 0) { - if (partition.usr_priv == 0) { - partition.offset = - (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR]; - for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++) - partition.size += flash_info[i].size; - partition.size -= - flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - - flash_info[CFG_JFFS2_FIRST_BANK].start[0]; -#ifdef CFG_JFFS2_LAST_SECTOR - i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1; - partition.size -= - flash_info[CFG_JFFS2_LAST_BANK].start[i] - - flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR]; -#endif - - partition.usr_priv = (void *)1; - } - return &partition; - } - return 0; -} - -#endif /* JFFS2 */ diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index 03b3cdf..4acddef 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -208,22 +208,22 @@ void reset_phy (void) } static unsigned long UPMATable[] = { - 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, //Words 0 to 3 - 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, //Words 4 to 7 - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 8 to 11 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 12 to 15 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 16 to 19 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23 - 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, //Words 24 to 27 - 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, //Words 28 to 31 - 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, //Words 32 to 35 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 36 to 39 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47 - 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, //Words 48 to 51 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55 - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59 - 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 //Words 60 to 63 + 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */ + 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ + 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */ }; int board_early_init_f (void) diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 8980209..fca11d0 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -170,3 +170,13 @@ int board_early_init_r (void) *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); return 0; } +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index c17b8fe..29878f9 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -173,6 +173,7 @@ void flash_preinit(void) *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ } +#define GPIO_WKUP_7 0x80000000UL #define GPIO_PSC3_9 0x04000000UL int misc_init_f (void) @@ -189,13 +190,13 @@ int misc_init_f (void) /* Initialize GPIO output pins. */ - /* Configure GPT as GPIO output */ + /* Configure GPT as GPIO output (and set them as they control low-active LEDs */ *(vu_long *)MPC5XXX_GPT0_ENABLE = *(vu_long *)MPC5XXX_GPT1_ENABLE = *(vu_long *)MPC5XXX_GPT2_ENABLE = *(vu_long *)MPC5XXX_GPT3_ENABLE = *(vu_long *)MPC5XXX_GPT4_ENABLE = - *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x24; + *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34; /* Configure GPT7 as PWM timer, 1kHz, no ints. */ *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */ @@ -216,6 +217,8 @@ int misc_init_f (void) *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000; *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000; + /* Set LR mirror bit because it is low-active */ + *(vu_long *)MPC5XXX_WU_GPIO_DATA |= GPIO_WKUP_7; /* * Reset Coral-P graphics controller */ diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 29c9166..298acc8 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -35,10 +35,6 @@ #include <common.h> #include <asm/arch/pxa-regs.h> -#if defined CFG_JFFS_CUSTOM_PART -#include <jffs2/jffs2.h> -#endif - /* Debugging macros ------------------------------------------------------ */ #undef FLASH_DEBUG @@ -78,179 +74,6 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -#if defined CFG_JFFS_CUSTOM_PART - -/** - * jffs2_part_info - get information about a JFFS2 partition - * - * @part_num: number of the partition you want to get info about - * @return: struct part_info* in case of success, 0 if failure - */ - -static struct part_info part; -static int current_part = -1; - -#ifdef CONFIG_MTD_INNOKOM_16MB -#ifdef CONFIG_MTD_INNOKOM_64MB -#error Please define only one CONFIG_MTD_INNOKOM_XXMB option. -#endif -struct part_info* jffs2_part_info(int part_num) { - void *jffs2_priv_saved = part.jffs2_priv; - - PRINTK2("jffs2_part_info: part_num=%i\n",part_num); - - if (current_part == part_num) - return ∂ - - /* u-boot partition */ - if(part_num==0){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00000000; - part.size=256*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* primary OS+firmware partition */ - if(part_num==1){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00040000; - part.size=768*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* secondary OS+firmware partition */ - if(part_num==2){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00100000; - part.size=8*1024*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* data partition */ - if(part_num==3){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00900000; - part.size=7*1024*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - if (current_part == part_num) { - part.usr_priv = ¤t_part; - part.jffs2_priv = jffs2_priv_saved; - return ∂ - } - - PRINTK("jffs2_part_info: end of partition table\n"); - return 0; -} -#endif /* CONFIG_MTD_INNOKOM_16MB */ - -#ifdef CONFIG_MTD_INNOKOM_64MB -#ifdef CONFIG_MTD_INNOKOM_16MB -#error Please define only one CONFIG_MTD_INNOKOM_XXMB option. -#endif -struct part_info* jffs2_part_info(int part_num) { - void *jffs2_priv_saved = part.jffs2_priv; - - PRINTK2("jffs2_part_info: part_num=%i\n",part_num); - - if (current_part == part_num) - return ∂ - - /* u-boot partition */ - if(part_num==0){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00000000; - part.size=256*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* primary OS+firmware partition */ - if(part_num==1){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00040000; - part.size=16*1024*1024-128*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* secondary OS+firmware partition */ - if(part_num==2){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x01020000; - part.size=16*1024*1024-128*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* data partition */ - if(part_num==3){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x02000000; - part.size=32*1024*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - PRINTK("part.offset = 0x%08x\n",(unsigned int)part.offset); - PRINTK("part.size = 0x%08x\n",(unsigned int)part.size); - } - - if (current_part == part_num) { - part.usr_priv = ¤t_part; - part.jffs2_priv = jffs2_priv_saved; - return ∂ - } - - PRINTK("jffs2_part_info: end of partition table\n"); - return 0; -} -#endif /* CONFIG_MTD_INNOKOM_64MB */ -#endif /* defined CFG_JFFS_CUSTOM_PART */ - - /** * flash_init: - initialize data structures for flash chips * diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index 5b2b41a..7cf5778 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -185,7 +185,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ int checkboard (void) { - puts ("Board: LICCON Konsole LCD2\n"); + puts ("Board: LICCON Konsole LCD3\n"); return (0); } diff --git a/board/mpc8260ads/flash.c b/board/mpc8260ads/flash.c index b2e9df2..59997aa 100644 --- a/board/mpc8260ads/flash.c +++ b/board/mpc8260ads/flash.c @@ -490,59 +490,3 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) return rc; } - -/*----------------------------------------------------------------------- - * Support for flash file system (JFFS2) - * - * We use custom partition info function because we have to fit the - * file system image between first sector (containing hard reset - * configuration word) and the sector containing U-Boot image. Standard - * partition info function does not allow for last sector specification - * and assumes that the file system occupies flash bank up to and - * including bank's last sector. - */ -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART) - -#ifndef CFG_JFFS2_FIRST_SECTOR -#define CFG_JFFS2_FIRST_SECTOR 0 -#endif -#ifndef CFG_JFFS2_FIRST_BANK -#define CFG_JFFS2_FIRST_BANK 0 -#endif -#ifndef CFG_JFFS2_NUM_BANKS -#define CFG_JFFS2_NUM_BANKS 1 -#endif -#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1) - -#include <jffs2/jffs2.h> - -static struct part_info partition; - -struct part_info *jffs2_part_info(int part_num) -{ - int i; - - if (part_num == 0) { - if (partition.usr_priv == 0) { - partition.offset = - (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR]; - for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++) - partition.size += flash_info[i].size; - partition.size -= - flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - - flash_info[CFG_JFFS2_FIRST_BANK].start[0]; -#ifdef CFG_JFFS2_LAST_SECTOR - i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1; - partition.size -= - flash_info[CFG_JFFS2_LAST_BANK].start[i] - - flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR]; -#endif - - partition.usr_priv = (void *)1; - } - return &partition; - } - return 0; -} - -#endif /* JFFS2 */ diff --git a/board/mpc8349ads/Makefile b/board/mpc8349ads/Makefile new file mode 100644 index 0000000..4327b0d --- /dev/null +++ b/board/mpc8349ads/Makefile @@ -0,0 +1,45 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8349ads/config.mk b/board/mpc8349ads/config.mk new file mode 100644 index 0000000..4602169 --- /dev/null +++ b/board/mpc8349ads/config.mk @@ -0,0 +1,27 @@ +# +# Copyright 2004 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MPC83xxADS +# + +TEXT_BASE = 0xFE700000 diff --git a/board/mpc8349ads/mpc8349ads.c b/board/mpc8349ads/mpc8349ads.c new file mode 100644 index 0000000..da8d3d7 --- /dev/null +++ b/board/mpc8349ads/mpc8349ads.c @@ -0,0 +1,276 @@ +/* + * Copyright Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Change log: + * 20050101: Eran Liberty (liberty@freescale.com) + * Initial file creating (porting from 85XX & 8260) + */ + +#include <common.h> +#include <ioports.h> +#include <mpc83xx.h> +#include <asm/mpc8349_pci.h> +#include <i2c.h> +#include <spd.h> +#include <miiphy.h> +#if defined(CONFIG_PCI) +#include <pci.h> +#endif +#if defined(CONFIG_SPD_EEPROM) +#include <spd_sdram.h> +#endif +int fixed_sdram(void); +void sdram_init(void); + +int board_early_init_f (void) +{ + volatile u8* bcsr = (volatile u8*)CFG_BCSR; + + /* Enable flash write */ + bcsr[1] &= ~0x01; + + return 0; +} + + +#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) + +long int initdram (int board_type) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; +#if defined(CONFIG_SPD_EEPROM) + msize = spd_sdram(NULL); +#else + msize = fixed_sdram(); +#endif + /* + * Initialize SDRAM if it is on local bus. + */ + sdram_init(); + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMRBAR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size>>1, ddr_size_log2++) { + if (ddr_size & 1) { + return -1; + } + } + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); +#if (CFG_DDR_SIZE != 256) +#warning Currenly any ddr size other than 256 is not supported +#endif + + im->ddr.csbnds[0].csbnds = 0x00100017; + im->ddr.csbnds[1].csbnds = 0x0018001f; + im->ddr.csbnds[2].csbnds = 0x00000007; + im->ddr.csbnds[3].csbnds = 0x0008000f; + im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[1] = CFG_DDR_CONFIG; + im->ddr.cs_config[2] = CFG_DDR_CONFIG; + im->ddr.cs_config[3] = CFG_DDR_CONFIG; + im->ddr.timing_cfg_1 = + 3 << TIMING_CFG1_PRETOACT_SHIFT | + 7 << TIMING_CFG1_ACTTOPRE_SHIFT | + 3 << TIMING_CFG1_ACTTORW_SHIFT | + 4 << TIMING_CFG1_CASLAT_SHIFT | + 3 << TIMING_CFG1_REFREC_SHIFT | + 3 << TIMING_CFG1_WRREC_SHIFT | + 2 << TIMING_CFG1_ACTTOACT_SHIFT | + 1 << TIMING_CFG1_WRTORD_SHIFT; + im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; + im->ddr.sdram_cfg = + SDRAM_CFG_SREN +#if defined(CONFIG_DDR_2T_TIMING) + | SDRAM_CFG_2T_EN +#endif + | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; + im->ddr.sdram_mode = + 0x2000 << SDRAM_MODE_ESD_SHIFT | + 0x0162 << SDRAM_MODE_SD_SHIFT; + + im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | + 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; + udelay(200); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return msize; +} +#endif/*!CFG_SPD_EEPROM*/ + + +int checkboard (void) +{ + puts("Board: Freescale MPC8349ADS\n"); + return 0; +} + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found + */ +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc83xxads_config_table[] = { + {PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMON_MEMORY | PCI_COMMAND_MASTER + } }, + {} +} +#endif + + +volatile static struct pci_controller hose[] = { + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + }, + { +#ifndef CONFIG_PCI_PNP + config_table:pci_mpc83xxads_config_table, +#endif + } +}; +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc83xx_init(volatile struct pci_controller *hose); + + pci_mpc83xx_init(hose); +#endif /* CONFIG_PCI */ +} + +/* + * if MPC8349ADS is soldered with SDRAM + */ +#if defined(CFG_BR2_PRELIM) \ + && defined(CFG_OR2_PRELIM) \ + && defined(CFG_LBLAWBAR2_PRELIM) \ + && defined(CFG_LBLAWAR2_PRELIM) +/* + * Initialize SDRAM memory on the Local Bus. + */ + +void +sdram_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; + volatile lbus8349_t *lbc= &immap->lbus; + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + + puts("\n SDRAM on Local Bus: "); + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + + /* + * Setup SDRAM Base and Option Registers, already done in cpu_init.c + */ + + /*setup mtrpt, lsrt and lbcr for LB bus*/ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + + /* + * Configure the SDRAM controller Machine Mode Register. + */ + lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ + + lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ + asm("sync"); + /*1 times*/ + *sdram_addr = 0xff; + udelay(100); + /*2 times*/ + *sdram_addr = 0xff; + udelay(100); + /*3 times*/ + *sdram_addr = 0xff; + udelay(100); + /*4 times*/ + *sdram_addr = 0xff; + udelay(100); + /*5 times*/ + *sdram_addr = 0xff; + udelay(100); + /*6 times*/ + *sdram_addr = 0xff; + udelay(100); + /*7 times*/ + *sdram_addr = 0xff; + udelay(100); + /*8 times*/ + *sdram_addr = 0xff; + udelay(100); + + /* 0x58636733;mode register write operation */ + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + *sdram_addr = 0xff; + udelay(100); + + lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ + asm("sync"); + *sdram_addr = 0xff; + udelay(100); +} +#else +void +sdram_init(void) +{ + put("SDRAM on Local Bus is NOT available!\n"); +} +#endif diff --git a/board/mpc8349ads/u-boot.lds b/board/mpc8349ads/u-boot.lds new file mode 100644 index 0000000..12c2d6f --- /dev/null +++ b/board/mpc8349ads/u-boot.lds @@ -0,0 +1,119 @@ +/* + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc83xx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/board/mpc8540ads/mpc8540ads.c b/board/mpc8540ads/mpc8540ads.c index 01b0386..d0eb690 100644 --- a/board/mpc8540ads/mpc8540ads.c +++ b/board/mpc8540ads/mpc8540ads.c @@ -31,7 +31,7 @@ #include <asm/immap_85xx.h> #include <spd.h> -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -96,7 +96,7 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ diff --git a/board/mpc8540ads/u-boot.lds b/board/mpc8540ads/u-boot.lds index 56dd457..85852d5 100644 --- a/board/mpc8540ads/u-boot.lds +++ b/board/mpc8540ads/u-boot.lds @@ -70,7 +70,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/mpc8540eval/Makefile b/board/mpc8540eval/Makefile new file mode 100644 index 0000000..6f1995e --- /dev/null +++ b/board/mpc8540eval/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o +#OBJS := $(BOARD).o flash.o $(BOARD)_slave.o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mpc8540eval/config.mk b/board/mpc8540eval/config.mk new file mode 100644 index 0000000..68271bd --- /dev/null +++ b/board/mpc8540eval/config.mk @@ -0,0 +1,34 @@ +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# gda8540 board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +#TEXT_BASE = 0x1000000 +TEXT_BASE = 0xfff80000 + + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c new file mode 100644 index 0000000..7300a04 --- /dev/null +++ b/board/mpc8540eval/flash.c @@ -0,0 +1,892 @@ +/* + * (C) Copyright 2003 Motorola Inc. + * Xianghua Xiao,(X.Xiao@motorola.com) + * + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com + * Add support the Sharp chips on the mpc8260ads. + * I started with board/ip860/flash.c and made changes I found in + * the MTD project by David Schleef. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if !defined(CFG_NO_FLASH) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +#if defined(CFG_ENV_IS_IN_FLASH) +# ifndef CFG_ENV_ADDR +# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +# endif +# ifndef CFG_ENV_SIZE +# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# endif +# ifndef CFG_ENV_SECT_SIZE +# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# endif +#endif + +/* + * The variable should be in the flash info structure. Since it + * is only used in this board specific file it is declared here. + * In the future I think an endian flag should be part of the + * flash_info_t structure. (Ron Alder) + */ +static ulong big_endian = 0; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt); +static int write_short (flash_info_t *info, ulong dest, ushort data); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static int clear_block_lock_bit(flash_info_t *info, vu_long * addr); +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size; + int i; + + /* Init: enable write, + * or we cannot even write flash commands + */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + + /* set the default sector offset */ + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size, size<<20); + } + + /* Re-do sizing to get full correct info */ + size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + + flash_info[0].size = size; + +#if !defined(CONFIG_RAM_AS_FLASH) +#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + /* monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE+monitor_flash_len-1, + &flash_info[0]); +#endif + +#ifdef CFG_ENV_IS_IN_FLASH + /* ENV protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + &flash_info[0]); +#endif +#endif + return (size); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: printf ("Intel "); break; + case FLASH_MAN_SHARP: printf ("Sharp "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); + break; + case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); + break; + case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); + break; + case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); + break; + case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); +} + + /* only deal with 16 bit and 32 bit port width, 16bit chip */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + ulong value,va,vb,vc,vd; + ulong base = (ulong)addr; + ulong sector_offset; + +#ifdef DEBUG + printf("Check flash at 0x%08x\n",(uint)addr); +#endif + /* Write "Intelligent Identifier" command: read Manufacturer ID */ + *addr = 0x90909090; + udelay(20); + asm("sync"); + +#ifndef CFG_FLASH_CFI + printf("Not define CFG_FLASH_CFI\n"); + return (0); +#else + value = addr[0]; + va=(value & 0xFF000000)>>24; + vb=(value & 0x00FF0000)>>16; + vc=(value & 0x0000FF00)>>8; + vd=(value & 0x000000FF); + if ((va==0) && (vb==0)) { + printf("cannot identify Flash\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + else if ((va==0) && (vb!=0)) { + big_endian = 1; + info->chipwidth = FLASH_CFI_BY16; + if(vb == vd) info->portwidth = FLASH_CFI_32BIT; + else info->portwidth = FLASH_CFI_16BIT; + } + else if ((va!=0) && (vb==0)) { + big_endian = 0; + info->chipwidth = FLASH_CFI_BY16; + if(va == vc) info->portwidth = FLASH_CFI_32BIT; + else info->portwidth = FLASH_CFI_16BIT; + } + else if ((va!=0) && (vb!=0)) { + big_endian = 1; /* no meaning for 8bit chip */ + info->chipwidth = FLASH_CFI_BY8; + if(va == vb) info->portwidth = FLASH_CFI_16BIT; + else info->portwidth = FLASH_CFI_8BIT; + } +#ifdef DEBUG + switch (info->portwidth) { + case FLASH_CFI_8BIT: + printf("port width is 8 bit.\n"); + break; + case FLASH_CFI_16BIT: + printf("port width is 16 bit, "); + break; + case FLASH_CFI_32BIT: + printf("port width is 32 bit, "); + break; + } + switch (info->chipwidth) { + case FLASH_CFI_BY16: + printf("chip width is 16 bit, "); + switch (big_endian) { + case 0: + printf("Little Endian.\n"); + break; + case 1: + printf("Big Endian.\n"); + break; + } + break; + } +#endif +#endif /*#ifdef CFG_FLASH_CFI*/ + + if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; + else value = (addr[0] & 0x00FF0000); +#ifdef DEBUG + printf("manufacturer=0x%x\n",(uint)(value>>16)); +#endif + switch (value) { + case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */ + case INTEL_ALT_MANU & 0xFFFF0000: + info->flash_id = FLASH_MAN_INTEL; + break; + default: + printf("unknown manufacturer: %x\n", (unsigned int)value); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + if (info->portwidth==FLASH_CFI_16BIT) { + switch (big_endian) { + case 0: + value = (addr[0] & 0x0000FF00)>>8; + break; + case 1: + value = (addr[0] & 0x000000FF); + break; + } + } + else if (info->portwidth == FLASH_CFI_32BIT) { + switch (big_endian) { + case 0: + value = (addr[1] & 0x0000FF00)>>8; + break; + case 1: + value = (addr[1] & 0x000000FF); + break; + } + } + +#ifdef DEBUG + printf("deviceID=0x%x\n",(uint)value); +#endif + switch (value) { + case (INTEL_ID_28F016S & 0x0000FFFF): + info->flash_id += FLASH_28F016SV; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + case (INTEL_ID_28F160S3 & 0x0000FFFF): + info->flash_id += FLASH_28F160S3; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + case (INTEL_ID_28F320S3 & 0x0000FFFF): + info->flash_id += FLASH_28F320S3; + info->sector_count = 64; + sector_offset = 0x10000; + break; /* => 4 MB */ + + case (INTEL_ID_28F640J3A & 0x0000FFFF): + info->flash_id += FLASH_28F640J3A; + info->sector_count = 64; + sector_offset = 0x20000; + break; /* => 8 MB */ + + case SHARP_ID_28F016SCL & 0x0000FFFF: + case SHARP_ID_28F016SCZ & 0x0000FFFF: + info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; + info->sector_count = 32; + sector_offset = 0x10000; + break; /* => 2 MB */ + + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + sector_offset = sector_offset * (info->portwidth / info->chipwidth); + info->size = info->sector_count * sector_offset; + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base; + base += sector_offset; + /* don't know how to check sector protection */ + info->protect[i] = 0; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr = (vu_long *)info->start[0]; + *addr = 0xFFFFFF; /* reset bank to read array mode */ + asm("sync"); + } + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong start, now, last, ready, erase_err_status; + + if (big_endian == 1) { + ready = 0x0080; + erase_err_status = 0x00a0; + } + else { + ready = 0x8000; + erase_err_status = 0xa000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + erase_err_status += (erase_err_status <<16); + } + +#ifdef DEBUG + printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status); +#endif + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) + && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + +#ifdef DEBUG + printf("\nFlash Erase:\n"); +#endif + /* Make Sure Block Lock Bit is not set. */ + if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){ + return 1; + } + + /* Start erase on unprotected sectors */ +#if defined(DEBUG) + printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); +#endif + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + vu_short *addr16 = (vu_short *)(info->start[sect]); + vu_long *addr = (vu_long *)(info->start[sect]); + printf("."); + switch (info->portwidth) { + case FLASH_CFI_16BIT: + asm("sync"); + last = start = get_timer (0); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + /* Reset Array */ + *addr16 = 0xffff; + asm("sync"); + /* Clear Status Register */ + *addr16 = 0x5050; + asm("sync"); + /* Single Block Erase Command */ + *addr16 = 0x2020; + asm("sync"); + /* Confirm */ + *addr16 = 0xD0D0; + asm("sync"); + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr16 = 0xD0D0; + asm("sync"); + } + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* wait at least 80us - let's wait 1 ms */ + *addr16 = 0x7070; + udelay (1000); + while ((*addr16 & ready) != ready) { + if((*addr16 & erase_err_status)== erase_err_status){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr16); + *addr16 = 0xFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr16 = 0xFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + /* reset to read mode */ + *addr16 = 0xFFFF; + asm("sync"); + break; + case FLASH_CFI_32BIT: + asm("sync"); + last = start = get_timer (0); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + /* Single Block Erase Command */ + *addr = 0x20202020; + asm("sync"); + /* Confirm */ + *addr = 0xD0D0D0D0; + asm("sync"); + if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { + /* Resume Command, as per errata update */ + *addr = 0xD0D0D0D0; + asm("sync"); + } + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* wait at least 80us - let's wait 1 ms */ + *addr = 0x70707070; + udelay (1000); + while ((*addr & ready) != ready) { + if((*addr & erase_err_status)==erase_err_status){ + printf("Error in Block Erase - Lock Bit may be set!\n"); + printf("Status Register = 0x%X\n", (uint)*addr); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + /* reset to read mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + break; + } /* end switch */ + } /* end if */ + } /* end for */ + + printf ("flash erase done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +#define FLASH_BLOCK_SIZE 32 + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data, count, temp; +/* ulong temp[FLASH_BLOCK_SIZE/4];*/ + int i, l, rc; + + count = cnt; + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + cp = wp; + /* handle unaligned block bytes , flash block size = 16bytes */ + wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1); + if ((wp-cp)>=cnt) { + if ((rc = write_block(info,src,cp,wp-cp)) !=0) + return (rc); + src += wp-cp; + cnt -= wp-cp; + } + /* handle aligned block bytes */ + temp = 0; + printf("\n"); + while ( cnt >= FLASH_BLOCK_SIZE) { + if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) { + return (rc); + } + src += FLASH_BLOCK_SIZE; + cp += FLASH_BLOCK_SIZE; + cnt -= FLASH_BLOCK_SIZE; + if (((count-cnt)>>10)>temp) { + temp=(count-cnt)>>10; + printf("\r%d KB",temp); + } + } + printf("\n"); + wp = cp; + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} +#undef FLASH_BLOCK_SIZE + +/*----------------------------------------------------------------------- + * Write block to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * -1 Error + */ +static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) +{ + vu_short *baddr, *addr = (vu_short *)dest; + ushort data; + ulong start, now, xsr,csr, ready; + int flag; + + if (cnt==0) return 0; + else if(cnt != (cnt& ~1)) return -1; + + /* Check if Flash is (sufficiently) erased */ + data = * src; + data = (data<<8) | *(src+1); + if ((*addr & data) != data) { + return (2); + } + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + do { + /* Write Command */ + *addr = 0xe8e8; + asm("sync"); + xsr = *addr; + asm("sync"); + } while (!(xsr & ready)); /*wait until read */ + /*write count=BLOCK SIZE -1 */ + data=(cnt>>1)-1; + data=(data<<8)|data; + *addr = data; /* word mode, cnt/2 */ + asm("sync"); + baddr = addr; + while(cnt) { + data = * src++; + data = (data<<8) | *src++; + asm("sync"); + *baddr = data; + asm("sync"); + ++baddr; + cnt = cnt -2; + } + *addr = 0xd0d0; /* confirm write */ + start = get_timer(0); + asm("sync"); + if (flag) + enable_interrupts(); + /* data polling for D7 */ + flag = 0; + while (((csr = *addr) & ready) != ready) { + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x4040) { + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x5050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFF; + asm("sync"); + return (flag); +} + + +/*----------------------------------------------------------------------- + * Write a short word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_short (flash_info_t *info, ulong dest, ushort data) +{ + vu_short *addr = (vu_short *)dest; + ulong start, now, csr, ready; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Write Command */ + *addr = 0x1010; + start = get_timer (0); + asm("sync"); + /* Write Data */ + *addr = data; + asm("sync"); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + /* data polling for D7 */ + flag = 0; + while (((csr = *addr) & ready) != ready) { + if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x4040) { + printf ("CSR indicates write error (%04x) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x5050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFF; + asm("sync"); + return (flag); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + vu_long *addr = (vu_long *)dest; + ulong start, csr, ready; + int flag=0; + + switch (info->portwidth) { + case FLASH_CFI_32BIT: + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + } + else { + ready = ready << 16; + } + /* Write Command */ + *addr = 0x10101010; + asm("sync"); + /* Write Data */ + *addr = data; + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + /* data polling for D7 */ + start = get_timer (0); + flag = 0; + while (((csr = *addr) & ready) != ready) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + flag = 1; + break; + } + } + if (csr & 0x40404040) { + printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); + flag = 1; + } + /* Clear Status Registers Command */ + *addr = 0x50505050; + asm("sync"); + /* Reset to read array mode */ + *addr = 0xFFFFFFFF; + asm("sync"); + break; + case FLASH_CFI_16BIT: + flag = write_short (info, dest, (unsigned short) (data>>16)); + if (flag == 0) + flag = write_short (info, dest+2, (unsigned short) (data)); + break; + } + return (flag); +} + +/*----------------------------------------------------------------------- + * Clear Block Lock Bit, returns: + * 0 - OK + * 1 - Timeout + */ + +static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) +{ + ulong start, now, ready; + + /* Reset Array */ + *addr = 0xffffffff; + asm("sync"); + /* Clear Status Register */ + *addr = 0x50505050; + asm("sync"); + + *addr = 0x60606060; + asm("sync"); + *addr = 0xd0d0d0d0; + asm("sync"); + + + if (big_endian == 1) { + ready = 0x0080; + } + else { + ready = 0x8000; + } + if ((info->portwidth / info->chipwidth)==2) { + ready += (ready <<16); + } + else { + ready = ready << 16; + } +#ifdef DEBUG + printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready); +#endif + *addr = 0x70707070; /* read status */ + start = get_timer (0); + while((*addr & ready) != ready){ + if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout on clearing Block Lock Bit\n"); + *addr = 0xFFFFFFFF; /* reset bank */ + asm("sync"); + return 1; + } + } + return 0; +} + +#endif /* !CFG_NO_FLASH */ diff --git a/board/mpc8540eval/init.S b/board/mpc8540eval/init.S new file mode 100644 index 0000000..8c2ca65 --- /dev/null +++ b/board/mpc8540eval/init.S @@ -0,0 +1,178 @@ +/* +* Copyright (C) 2002,2003, Motorola Inc. +* Xianghua Xiao <X.Xiao@motorola.com> +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +/* TLB1 entries configuration: */ + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + .long 0x0a /* the following data table uses a few of 16 TLB entries */ + + .long TLB1_MAS0(1,1,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if defined(CFG_FLASH_PORT_WIDTH_16) + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M) + .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,2,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M) + .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,3,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + #if !defined(CONFIG_SPD_EEPROM) + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0) + .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,4,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,5,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + + .long TLB1_MAS0(1,6,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M) + #if defined(CONFIG_RAM_AS_FLASH) + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + #else + .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,7,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + #ifdef CONFIG_L2_INIT_RAM + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0) + #else + .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0) + #endif + .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,8,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M) + .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(1,9,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K) + .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + + #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0) + .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1) + #else + .long TLB1_MAS0(1,15,0) + .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M) + .long TLB1_MAS2(0,0,0,0,0,0,0,0,0) + .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1) + #endif + entry_end + +/* LAW(Local Access Window) configuration: + * 0000_0000-0800_0000: DDR(128M) -or- larger + * f000_0000-f3ff_ffff: PCI(256M) + * f400_0000-f7ff_ffff: RapidIO(128M) + * f800_0000-ffff_ffff: localbus(128M) + * f800_0000-fbff_ffff: LBC SDRAM(64M) + * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M) + * fdf0_0000-fdff_ffff: CCSRBAR(1M) + * fe00_0000-ffff_ffff: Flash(32M) + * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access + * Window. + * Note: If flash is 8M at default position(last 8M),no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#if !defined(CONFIG_RAM_AS_FLASH) +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) +#else +#define LAWBAR2 0 +#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x03 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2 + entry_end diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c new file mode 100644 index 0000000..3b3c8ed --- /dev/null +++ b/board/mpc8540eval/mpc8540eval.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2002,2003, Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <spd.h> + +extern long int spd_sdram (void); + +long int fixed_sdram (void); + +int board_pre_init (void) +{ +#if defined(CONFIG_PCI) + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; + + pci->peer &= 0xffffffdf; /* disable master abort */ +#endif + return 0; +} + +int checkboard (void) +{ + sys_info_t sysinfo; + + get_sys_info (&sysinfo); + + printf ("Board: Freescale MPC8540EVAL Board\n"); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); + printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); + if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ + || (CFG_LBC_LCRR & 0x0f) == 8) { + printf ("\tLBC: %lu MHz\n", + sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f)); + } else { + printf("\tLBC: unknown\n"); + } + printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); + return (0); +} + +long int initdram (int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; +#if !defined(CONFIG_RAM_AS_FLASH) + volatile ccsr_lbc_t *lbc= &immap->im_lbc; + sys_info_t sysinfo; + uint temp_lbcdll = 0; +#endif +#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) + volatile ccsr_gur_t *gur= &immap->im_gur; +#endif + +#if defined(CONFIG_DDR_DLL) + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CFG_RAMBOOT) + return dram_size; +#endif + +#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ + get_sys_info(&sysinfo); + /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ + if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; + } else { + lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; + udelay(200); + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; + asm("sync;isync;msync"); + } + lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ + lbc->br2 = CFG_BR2_PRELIM; + lbc->lbcr = CFG_LBC_LBCR; + lbc->lsdmr = CFG_LBC_LSDMR_1; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_2; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_3; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_4; + asm("sync"); + * (ulong *)0 = 0x000000ff; + lbc->lsdmr = CFG_LBC_LSDMR_5; + asm("sync"); + lbc->lsrt = CFG_LBC_LSRT; + asm("sync"); + lbc->mrtpr = CFG_LBC_MRTPR; + asm("sync"); +#endif + +#if defined(CONFIG_DDR_ECC) + { + /* Initialize all of memory for ECC, then + * enable errors */ + uint *p = 0; + uint i = 0; + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + dma_init(); + for (*p = 0; p < (uint *)(8 * 1024); p++) { + if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } + *p = (unsigned int)0xdeadbeef; + if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); } + } + + /* 8K */ + dma_xfer((uint *)0x2000,0x2000,(uint *)0); + /* 16K */ + dma_xfer((uint *)0x4000,0x4000,(uint *)0); + /* 32K */ + dma_xfer((uint *)0x8000,0x8000,(uint *)0); + /* 64K */ + dma_xfer((uint *)0x10000,0x10000,(uint *)0); + /* 128k */ + dma_xfer((uint *)0x20000,0x20000,(uint *)0); + /* 256k */ + dma_xfer((uint *)0x40000,0x40000,(uint *)0); + /* 512k */ + dma_xfer((uint *)0x80000,0x80000,(uint *)0); + /* 1M */ + dma_xfer((uint *)0x100000,0x100000,(uint *)0); + /* 2M */ + dma_xfer((uint *)0x200000,0x200000,(uint *)0); + /* 4M */ + dma_xfer((uint *)0x400000,0x400000,(uint *)0); + + for (i = 1; i < dram_size / 0x800000; i++) { + dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0); + } + + /* Enable errors for ECC */ + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + } +#endif + + return dram_size; +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ +#ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; +#if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; +#endif + asm("sync;isync;msync"); + udelay(500); +#if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); +#else + ddr->sdram_cfg = CFG_DDR_CONTROL; +#endif + asm("sync; isync; msync"); + udelay(500); +#endif + return (CFG_SDRAM_SIZE * 1024 * 1024); +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds new file mode 100644 index 0000000..2479af1 --- /dev/null +++ b/board/mpc8540eval/u-boot.lds @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2002,2003, Motorola,Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Assumes that the size of u-boot is less than 512K and the + * start address is aligned on a 512K block. + * Boot page and reset vector is put at that end of the 512K block. */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/mpc8540eval/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + cpu/mpc85xx/pci.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); + + . = (. & 0xFFF80000) + 0x0007F000; + .bootpg : + { + cpu/mpc85xx/start.o (.bootpg) + board/mpc8540eval/init.o (.bootpg) + } = 0xffff + + . = (. & 0xFFF80000) + 0x0007FFFC; + .resetvec : + { + *(.resetvec) + } = 0xffff + +} diff --git a/board/mpc8560ads/config.mk b/board/mpc8560ads/config.mk index 53e3edb..9aef2bb 100644 --- a/board/mpc8560ads/config.mk +++ b/board/mpc8560ads/config.mk @@ -29,5 +29,4 @@ TEXT_BASE = 0xfff80000 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index 1990e54..9accc5c 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -33,7 +33,7 @@ #include <spd.h> #include <miiphy.h> -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); #endif @@ -293,7 +293,7 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* * Initialize and enable DDR ECC. */ diff --git a/board/mpc8560ads/u-boot.lds b/board/mpc8560ads/u-boot.lds index 4c6c7db..c307d63 100644 --- a/board/mpc8560ads/u-boot.lds +++ b/board/mpc8560ads/u-boot.lds @@ -73,7 +73,6 @@ SECTIONS cpu/mpc85xx/ether_fcc.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 4a10b79..84c91c4 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -1,6 +1,25 @@ /* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland + * Part of this code has been derived from linux: + * Universal Host Controller Interface driver for USB (take II). + * + * (c) 1999-2001 Georg Acher, acher@in.tum.de (executive slave) (base guitar) + * Deti Fliegl, deti@fliegl.de (executive slave) (lead voice) + * Thomas Sailer, sailer@ife.ee.ethz.ch (chief consultant) (cheer leader) + * Roman Weissgaerber, weissg@vienna.at (virt root hub) (studio porter) + * (c) 2000 Yggdrasil Computing, Inc. (port of new PCI interface support + * from usb-ohci.c by Adam Richter, adam@yggdrasil.com). + * (C) 2000 David Brownell, david-b@pacbell.net (usb-ohci.c) + * + * HW-initalization based on material of + * + * (C) Copyright 1999 Linus Torvalds + * (C) Copyright 1999 Johannes Erdfelt + * (C) Copyright 1999 Randy Dunlap + * (C) Copyright 1999 Gregory P. Smith + * + * + * Adapted for U-Boot: + * (C) Copyright 2001 Denis Peter, MPL AG Switzerland * * See file CREDITS for list of people who contributed to this * project. @@ -20,7 +39,6 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * - * Note: Part of this code has been derived from linux * */ diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c index 3a79a9e..3806310 100644 --- a/board/mx1fs2/flash.c +++ b/board/mx1fs2/flash.c @@ -25,10 +25,6 @@ #include <common.h> -#if defined CFG_JFFS_CUSTOM_PART -#include <jffs2/jffs2.h> -#endif - #define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE #define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE @@ -70,67 +66,6 @@ static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); static void flash_sync_real_protect(flash_info_t * info); #endif -#if defined CFG_JFFS_CUSTOM_PART - -/** - * jffs2_part_info - get information about a JFFS2 partition - * - * @part_num: number of the partition you want to get info about - * @return: struct part_info* in case of success, 0 if failure - */ - -static struct part_info part; -static int current_part = -1; - -struct part_info * -jffs2_part_info(int part_num) -{ - void *jffs2_priv_saved = part.jffs2_priv; - - printf("jffs2_part_info: part_num=%i\n", part_num); - - if (current_part == part_num) - return ∂ - - /* rootfs */ - if (part_num == 0) { - memset(&part, 0, sizeof (part)); - - part.offset = (char *) MX1FS2_JFFS2_PART0_START; - part.size = MX1FS2_JFFS2_PART0_SIZE; - - /* Mark the struct as ready */ - current_part = part_num; - - printf("part.offset = 0x%08x\n", (unsigned int) part.offset); - printf("part.size = 0x%08x\n", (unsigned int) part.size); - } - - /* userfs */ - if (part_num == 1) { - memset(&part, 0, sizeof (part)); - - part.offset = (char *) MX1FS2_JFFS2_PART1_START; - part.size = MX1FS2_JFFS2_PART1_SIZE; - - /* Mark the struct as ready */ - current_part = part_num; - - printf("part.offset = 0x%08x\n", (unsigned int) part.offset); - printf("part.size = 0x%08x\n", (unsigned int) part.size); - } - - if (current_part == part_num) { - part.usr_priv = ¤t_part; - part.jffs2_priv = jffs2_priv_saved; - return ∂ - } - - printf("jffs2_part_info: end of partition table\n"); - return 0; -} -#endif /* CFG_JFFS_CUSTOM_PART */ - /*----------------------------------------------------------------------- * flash_init() * diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 572cc9b..3868221 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -75,6 +75,8 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info); static int write_data (flash_info_t *info, ulong dest, FPW data); static void flash_get_offsets (ulong base, flash_info_t *info); void inline spin_wheel (void); +static void flash_sync_real_protect (flash_info_t * info); +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector); /*----------------------------------------------------------------------- */ @@ -101,6 +103,9 @@ unsigned long flash_init (void) break; } size += flash_info[i].size; + + /* get the h/w and s/w protection status in sync */ + flash_sync_real_protect(&flash_info[i]); } /* Protect monitor and environment sectors @@ -138,7 +143,6 @@ static void flash_get_offsets (ulong base, flash_info_t *info) if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { for (i = 0; i < info->sector_count; i++) { info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; } } } @@ -270,6 +274,83 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) } +/* + * This function gets the u-boot flash sector protection status + * (flash_info_t.protect[]) in sync with the sector protection + * status stored in hardware. + */ +static void flash_sync_real_protect (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + + case FLASH_28F128J3A: + case FLASH_28F640J3A: + case FLASH_28F320J3A: + for (i = 0; i < info->sector_count; ++i) { + info->protect[i] = intel_sector_protected(info, i); + } + break; + default: + /* no h/w protect support */ + break; + } +} + + +/* + * checks if "sector" in bank "info" is protected. Should work on intel + * strata flash chips 28FxxxJ3x in 8-bit mode. + * Returns 1 if sector is protected (or timed-out while trying to read + * protection status), 0 if it is not. + */ +static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) +{ + FPWV *addr; + FPWV *lock_conf_addr; + ulong start; + unsigned char ret; + + /* + * first, wait for the WSM to be finished. The rationale for + * waiting for the WSM to become idle for at most + * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * because of: (1) erase, (2) program or (3) lock bit + * configuration. So we just wait for the longest timeout of + * the (1)-(3), i.e. the erase timeout. + */ + + /* wait at least 35ns (W12) before issuing Read Status Register */ + udelay(1); + addr = (FPWV *) info->start[sector]; + *addr = (FPW) INTEL_STATUS; + + start = get_timer (0); + while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + *addr = (FPW) INTEL_RESET; /* restore read mode */ + printf("WSM busy too long, can't get prot status\n"); + return 1; + } + } + + /* issue the Read Identifier Codes command */ + *addr = (FPW) INTEL_READID; + + /* wait at least 35ns (W12) before reading */ + udelay(1); + + /* Intel example code uses offset of 2 for 16 bit flash */ + lock_conf_addr = (FPWV *) info->start[sector] + 2; + ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0; + + /* put flash back in read mode */ + *addr = (FPW) INTEL_RESET; + + return ret; +} + /*----------------------------------------------------------------------- */ @@ -491,7 +572,7 @@ void inline spin_wheel (void) * 0 - OK * 1 - Error (timeout, voltage problems, etc.) */ -int flash_real_protect(flash_info_t *info, long sector, int prot) +int flash_real_protect (flash_info_t *info, long sector, int prot) { ulong start; int i; @@ -531,6 +612,11 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) /* * Clear lock bit command clears all sectors lock bits, so * we have to restore lock bits of protected sectors. + * WARNING: code below re-locks sectors only for one bank (info). + * This causes problems on boards where several banks share + * the same chip, as sectors in othere banks will be unlocked + * but not re-locked. It works fine on pm520 though, as there + * is only one chip and one bank. */ if (!prot) { @@ -553,6 +639,11 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) } } } + /* + * get the s/w sector protection status in sync with the h/w, + * in case something went wrong during the re-locking. + */ + flash_sync_real_protect(info); /* resets flash to read mode */ } if (flag) diff --git a/board/pm854/Makefile b/board/pm854/Makefile index c6b4cae..7828166 100644 --- a/board/pm854/Makefile +++ b/board/pm854/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS := $(BOARD).o flash.o +OBJS := $(BOARD).o SOBJS := init.o #SOBJS := diff --git a/board/pm854/flash.c b/board/pm854/flash.c deleted file mode 100644 index d714589..0000000 --- a/board/pm854/flash.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * (C) Copyright 2003 Motorola Inc. - * Xianghua Xiao,(X.Xiao@motorola.com) - * - * (C) Copyright 2000-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com - * Add support the Sharp chips on the mpc8260ads. - * I started with board/ip860/flash.c and made changes I found in - * the MTD project by David Schleef. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#if !defined(CFG_NO_FLASH) - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -# endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE -# endif -#endif - -#undef DEBUG - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static int clear_block_lock_bit(vu_long * addr); -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size; - int i; - - /* Init: enable write, - * or we cannot even write flash commands - */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - - /* set the default sector offset */ - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - } - - /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size; - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, - &flash_info[0]); -#endif -#endif - return (size); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: printf ("Intel "); break; - case FLASH_MAN_SHARP: printf ("Sharp "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n"); - break; - case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n"); - break; - case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n"); - break; - case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n"); - break; - case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n"); - break; - case FLASH_28F128J3A: printf ("28F128J3A (128 Mbit, 128 x 128K)\n"); - break; - - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - ulong sector_offset; - -#ifdef DEBUG - printf("Check flash at 0x%08x\n",(uint)addr); -#endif - /* Write "Intelligent Identifier" command: read Manufacturer ID */ - *addr = 0x90909090; - udelay(20); - asm("sync"); - - value = addr[0] & 0x00FF00FF; - -#ifdef DEBUG - printf("manufacturer=0x%x\n",(uint)value); -#endif - switch (value) { - case MT_MANUFACT: /* SHARP, MT or => Intel */ - case INTEL_ALT_MANU: - info->flash_id = FLASH_MAN_INTEL; - break; - default: - printf("unknown manufacturer: %x\n", (unsigned int)value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1] & 0x00FF00FF; /* device ID */ - -#ifdef DEBUG - printf("deviceID=0x%x\n",(uint)value); -#endif - switch (value) { - case (INTEL_ID_28F016S): - info->flash_id += FLASH_28F016SV; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F160S3): - info->flash_id += FLASH_28F160S3; - info->sector_count = 32; - info->size = 0x00400000; - sector_offset = 0x20000; - break; /* => 2x2 MB */ - - case (INTEL_ID_28F320S3): - info->flash_id += FLASH_28F320S3; - info->sector_count = 64; - info->size = 0x00800000; - sector_offset = 0x20000; - break; /* => 2x4 MB */ - - case (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - sector_offset = 0x40000; - break; /* => 2x8 MB */ - - case (INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - sector_offset = 0x40000; - break; /* => 2x16 MB */ - - - case SHARP_ID_28F016SCL: - case SHARP_ID_28F016SCZ: - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT; - info->sector_count = 32; - info->size = 0x00800000; - sector_offset = 0x40000; - break; /* => 4x2 MB */ - - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += sector_offset; - /* don't know how to check sector protection */ - info->protect[i] = 0; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (vu_long *)info->start[0]; - *addr = 0xFFFFFF; /* reset bank to read array mode */ - asm("sync"); - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - -#ifdef DEBUG - printf("\nFlash Erase:\n"); -#endif - /* Make Sure Block Lock Bit is not set. */ - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){ - return 1; - } - - /* Start erase on unprotected sectors */ -#if defined(DEBUG) - printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last); -#endif - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *)(info->start[sect]); - asm("sync"); - - last = start = get_timer (0); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - /* Single Block Erase Command */ - *addr = 0x20202020; - asm("sync"); - /* Confirm */ - *addr = 0xD0D0D0D0; - asm("sync"); - - if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) { - /* Resume Command, as per errata update */ - *addr = 0xD0D0D0D0; - asm("sync"); - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - while ((*addr & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - - /* reset to read mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - } - } - - printf ("flash erase done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)dest; - ulong start, csr; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Write Command */ - *addr = 0x10101010; - asm("sync"); - - /* Write Data */ - *addr = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - flag = 0; - - while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - flag = 1; - break; - } - } - if (csr & 0x40404040) { - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr); - flag = 1; - } - - /* Clear Status Registers Command */ - *addr = 0x50505050; - asm("sync"); - /* Reset to read array mode */ - *addr = 0xFFFFFFFF; - asm("sync"); - - return (flag); -} - -/*----------------------------------------------------------------------- - * Clear Block Lock Bit, returns: - * 0 - OK - * 1 - Timeout - */ - -static int clear_block_lock_bit(vu_long * addr) -{ - ulong start, now; - - /* Reset Array */ - *addr = 0xffffffff; - asm("sync"); - /* Clear Status Register */ - *addr = 0x50505050; - asm("sync"); - - *addr = 0x60606060; - asm("sync"); - *addr = 0xd0d0d0d0; - asm("sync"); - - start = get_timer (0); - while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout on clearing Block Lock Bit\n"); - *addr = 0xFFFFFFFF; /* reset bank */ - asm("sync"); - return 1; - } - } - return 0; -} - -#endif /* !CFG_NO_FLASH */ diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds index 5f24f76..4db6b34 100644 --- a/board/pm854/u-boot.lds +++ b/board/pm854/u-boot.lds @@ -70,7 +70,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/pm856/Makefile b/board/pm856/Makefile new file mode 100644 index 0000000..5d8ea34 --- /dev/null +++ b/board/pm856/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o +SOBJS := init.o +#SOBJS := + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/pm856/config.mk b/board/pm856/config.mk new file mode 100644 index 0000000..1f98b33 --- /dev/null +++ b/board/pm856/config.mk @@ -0,0 +1,33 @@ +# Copyright 2004 Freescale Semiconductor. +# Modified by Xianghua Xiao, X.Xiao@motorola.com +# (C) Copyright 2002,2003 Motorola Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# PM856 board +# default CCARBAR is at 0xff700000 +# assume U-Boot is less than 0.5MB +# +TEXT_BASE = 0xfff80000 + +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/pm856/init.S b/board/pm856/init.S new file mode 100644 index 0000000..ade5d6e --- /dev/null +++ b/board/pm856/init.S @@ -0,0 +1,263 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * Copyright (C) 2002,2003, Motorola Inc. + * Xianghua Xiao <X.Xiao@motorola.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> +#include <config.h> +#include <mpc85xx.h> + + +/* + * TLB0 and TLB1 Entries + * + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after + * these TLB entries are established. + * + * The TLB entries for DDR are dynamically setup in spd_sdram() + * and use TLB1 Entries 8 through 15 as needed according to the + * size of DDR memory. + * + * MAS0: tlbsel, esel, nv + * MAS1: valid, iprot, tid, ts, tsize + * MAS2: epn, sharen, x0, x1, w, i, m, g, e + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr + */ + +#define entry_start \ + mflr r1 ; \ + bl 0f ; + +#define entry_end \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + + + .section .bootpg, "ax" + .globl tlb1_entry +tlb1_entry: + entry_start + + /* + * Number of TLB0 and TLB1 entries in the following table + */ + .long 13 + +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) + /* + * TLB0 4K Non-cacheable, guarded + * 0xff700000 4K Initial CCSRBAR mapping + * + * This ends up at a TLB0 Index==0 entry, and must not collide + * with other TLB0 Entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) +#else +#error("Update the number of table entries in tlb1_entry") +#endif + + /* + * TLB0 16K Cacheable, non-guarded + * 0xd001_0000 16K Temporary Global data for initialization + * + * Use four 4K TLB0 entries. These entries must be cacheable + * as they provide the bootstrap memory before the memory + * controler and real memory have been configured. + * + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, + * and must not collide with other TLB0 entries. + */ + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + .long TLB1_MAS0(0, 0, 0) + .long TLB1_MAS1(1, 0, 0, 0, 0) + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), + 0,0,0,0,0,1,0,1,0,1) + + + /* + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 64M FLASH (8,16,32 or 64 MB) + * Out of reset this entry is only 4K. + */ + .long TLB1_MAS0(1, 0, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(0xfc000000), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(0xfc000000), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 1: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + .long TLB1_MAS0(1, 1, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 2: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + .long TLB1_MAS0(1, 2, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 3: 256M Non-cacheable, guarded + * 0xc0000000 256M Rapid IO MEM First half + */ + .long TLB1_MAS0(1, 3, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xd0000000 256M Rapid IO MEM Second half + */ + .long TLB1_MAS0(1, 4, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), + 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 16M PCI1 IO + */ + .long TLB1_MAS0(1, 5, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) + + /* + * TLB 6: 64M Cacheable, non-guarded + * 0xf000_0000 64M LBC SDRAM + */ + .long TLB1_MAS0(1, 6, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) + +#if !defined(CONFIG_SPD_EEPROM) + /* + * TLB 7: 256M DDR + * 0x00000000 256M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + + .long TLB1_MAS0(1, 7, 0) + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) +#endif + + entry_end + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xe000_0000 0xe000_ffff CCSR 1M + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + */ + +#if !defined(CONFIG_SPD_EEPROM) +#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) +#else +#define LAWBAR0 0 +#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) +#endif + +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M)) + +/* + * This is not so much the SDRAM map as it is the whole localbus map. + */ +#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) + +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) + +/* + * Rapid IO at 0xc000_0000 for 512 M + */ +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)) + + + .section .bootpg, "ax" + .globl law_entry +law_entry: + entry_start + .long 0x05 + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 + .long LAWBAR4,LAWAR4 + entry_end diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c new file mode 100644 index 0000000..5044708 --- /dev/null +++ b/board/pm856/pm856.c @@ -0,0 +1,449 @@ +/* + * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2003,Motorola Inc. + * Xianghua Xiao, (X.Xiao@motorola.com) + * + * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include <common.h> +#include <pci.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <ioports.h> +#include <spd.h> +#include <miiphy.h> + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + +extern long int spd_sdram(void); + +void local_bus_init(void); +long int fixed_sdram(void); + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ + +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + }, + + /* Port B configuration */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ + /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + } +}; + + +int board_early_init_f (void) +{ + return 0; +} + +void reset_phy (void) +{ +} + + +int checkboard (void) +{ + puts("Board: MicroSys PM856\n"); + +#ifdef CONFIG_PCI + printf(" PCI1: 32 bit, %d MHz (compiled)\n", + CONFIG_SYS_CLK_FREQ / 1000000); +#else + printf(" PCI1: disabled\n"); +#endif + + /* + * Initialize local bus. + */ + local_bus_init(); + + return 0; +} + + +long int +initdram(int board_type) +{ + long dram_size = 0; + extern long spd_sdram (void); + volatile immap_t *immap = (immap_t *)CFG_IMMR; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + volatile ccsr_gur_t *gur= &immap->im_gur; + int i,x; + + x = 10; + + /* + * Work around to stabilize DDR DLL + */ + gur->ddrdllcr = 0x81000000; + asm("sync;isync;msync"); + udelay (200); + while (gur->ddrdllcr != 0x81000100) + { + gur->devdisr = gur->devdisr | 0x00010000; + asm("sync;isync;msync"); + for (i=0; i<x; i++) + ; + gur->devdisr = gur->devdisr & 0xfff7ffff; + asm("sync;isync;msync"); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (); +#else + dram_size = fixed_sdram (); +#endif + +#if defined(CONFIG_DDR_ECC) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + puts(" DDR: "); + return dram_size; +} + + +/* + * Initialize Local Bus + */ + +void +local_bus_init(void) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile ccsr_lbc_t *lbc = &immap->im_lbc; + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + /* + * Errata LBC11. + * Fix Local Bus clock glitch when DLL is enabled. + * + * If localbus freq is < 66Mhz, DLL bypass mode must be used. + * If localbus freq is > 133Mhz, DLL can be safely enabled. + * Between 66 and 133, the DLL is enabled with an override workaround. + */ + + get_sys_info(&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + if (lbc_hz < 66) { + lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + + } else if (lbc_hz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + + } else { + /* + * On REV1 boards, need to change CLKDIV before enable DLL. + * Default CLKDIV is 8, change it to 4 temporarily. + */ + uint pvr = get_pvr(); + uint temp_lbcdll = 0; + + if (pvr == PVR_85xx_REV1) { + /* FIXME: Justify the high bit here. */ + lbc->lcrr = 0x10000004; + } + + lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + udelay(200); + + /* + * Sample LBC DLL ctrl reg, upshift it to set the + * override bits. + */ + temp_lbcdll = gur->lbcdllcr; + gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); + asm("sync;isync;msync"); + } +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("SDRAM test phase 1:\n"); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test phase 2:\n"); + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("SDRAM test passed.\n"); + return 0; +} +#endif + + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + ************************************************************************/ +long int fixed_sdram (void) +{ + #ifndef CFG_RAMBOOT + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_ddr_t *ddr= &immap->im_ddr; + + ddr->cs0_bnds = CFG_DDR_CS0_BNDS; + ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CFG_DDR_TIMING_1; + ddr->timing_cfg_2 = CFG_DDR_TIMING_2; + ddr->sdram_mode = CFG_DDR_MODE; + ddr->sdram_interval = CFG_DDR_INTERVAL; + #if defined (CONFIG_DDR_ECC) + ddr->err_disable = 0x0000000D; + ddr->err_sbe = 0x00ff0000; + #endif + asm("sync;isync;msync"); + udelay(500); + #if defined (CONFIG_DDR_ECC) + /* Enable ECC checking */ + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + #else + ddr->sdram_cfg = CFG_DDR_CONTROL; + #endif + asm("sync; isync; msync"); + udelay(500); + #endif + return CFG_SDRAM_SIZE * 1024 * 1024; +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_PCI) +/* + * Initialize PCI Devices, report devices found. + */ + +#ifndef CONFIG_PCI_PNP +static struct pci_config_table pci_mpc85xxads_config_table[] = { + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, + PCI_IDSEL_NUMBER, PCI_ANY_ID, + pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, + PCI_ENET0_MEMADDR, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + } }, + { } +}; +#endif + + +static struct pci_controller hose = { +#ifndef CONFIG_PCI_PNP + config_table: pci_mpc85xxads_config_table, +#endif +}; + +#endif /* CONFIG_PCI */ + + +void +pci_init_board(void) +{ +#ifdef CONFIG_PCI + extern void pci_mpc85xx_init(struct pci_controller *hose); + + pci_mpc85xx_init(&hose); +#endif /* CONFIG_PCI */ +} diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds new file mode 100644 index 0000000..dae8347 --- /dev/null +++ b/board/pm856/u-boot.lds @@ -0,0 +1,147 @@ +/* + * (C) Copyright 2005 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2002,2003, Motorola,Inc. + * Xianghua Xiao, X.Xiao@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/mpc85xx/start.o (.bootpg) + board/pm856/init.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc85xx/start.o (.text) + board/pm856/init.o (.text) + cpu/mpc85xx/traps.o (.text) + cpu/mpc85xx/interrupts.o (.text) + cpu/mpc85xx/cpu_init.o (.text) + cpu/mpc85xx/cpu.o (.text) + cpu/mpc85xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c new file mode 100644 index 0000000..762fb73 --- /dev/null +++ b/board/sandburst/common/flash.c @@ -0,0 +1,512 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Ported from Ebony flash support + * Travis B. Sawyer + * Sandburst Corporation + */ +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + + +#undef DEBUG +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { + {0xfff80000} /* Boot Flash */ +}; + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); + + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size( + (vu_long *)flash_addr_table[index][i], &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i]<<20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + total_b += flash_info[i].size; + } + + return total_b; +} + + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; k<size; k++) + { + if (*flash++ != 0xffffffff) + { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); + return; + } + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr ); + + /* Write auto select command: read Manufacturer ID */ + udelay(10000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + udelay(1000); + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + udelay(1000); + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + udelay(1000); + + value = addr2[0]; + + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x00080000; /* => 512 kb */ + break; + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + if (info->flash_id == FLASH_AM040) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* reset to return to reading data */ + addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + DEBUGF("Erasing sector %p\n", addr2); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ + for (i=0; i<50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t * info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *) dest) & + (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { + return (2); + } + + for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c new file mode 100644 index 0000000..858b38c --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -0,0 +1,512 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation. + */ +#include <common.h> +#include <ppc4xx.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include <i2c.h> +#include <440_i2c.h> +#include <command.h> +#include "ppc440gx_i2c.h" + +#ifdef CONFIG_I2C_BUS1 + +#define IIC_OK 0 +#define IIC_NOK 1 +#define IIC_NOK_LA 2 /* Lost arbitration */ +#define IIC_NOK_ICT 3 /* Incomplete transfer */ +#define IIC_NOK_XFRA 4 /* Transfer aborted */ +#define IIC_NOK_DATA 5 /* No data in buffer */ +#define IIC_NOK_TOUT 6 /* Transfer timeout */ + +#define IIC_TIMEOUT 1 /* 1 second */ +#if defined(CFG_I2C_NOPROBES) +static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#endif + +static void _i2c_bus1_reset (void) +{ + int i, status; + + /* Reset status register */ + /* write 1 in SCMP and IRQA to clear these fields */ + out8 (IIC_STS1, 0x0A); + + /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ + out8 (IIC_EXTSTS1, 0x8F); + __asm__ volatile ("eieio"); + + /* + * Get current state, reset bus + * only if no transfers are pending. + */ + i = 10; + do { + /* Get status */ + status = in8 (IIC_STS1); + udelay (500); /* 500us */ + i--; + } while ((status & IIC_STS_PT) && (i > 0)); + /* Soft reset controller */ + status = in8 (IIC_XTCNTLSS1); + out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); + __asm__ volatile ("eieio"); + + /* make sure where in initial state, data hi, clock hi */ + out8 (IIC_DIRECTCNTL1, 0xC); + for (i = 0; i < 10; i++) { + if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { + /* clock until we get to known state */ + out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ + udelay (100); /* 100us */ + out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ + udelay (100); /* 100us */ + } else { + break; + } + } + /* send start condition */ + out8 (IIC_DIRECTCNTL1, 0x4); + udelay (1000); /* 1ms */ + /* send stop condition */ + out8 (IIC_DIRECTCNTL1, 0xC); + udelay (1000); /* 1ms */ + /* Unreset controller */ + out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); + udelay (1000); /* 1ms */ +} + +void i2c1_init (int speed, int slaveadd) +{ + sys_info_t sysInfo; + unsigned long freqOPB; + int val, divisor; + +#ifdef CFG_I2C_INIT_BOARD + /* call board specific i2c bus reset routine before accessing the */ + /* environment, which might be in a chip on that bus. For details */ + /* about this problem see doc/I2C_Edge_Conditions. */ + i2c_init_board(); +#endif + + /* Handle possible failed I2C state */ + /* FIXME: put this into i2c_init_board()? */ + _i2c_bus1_reset (); + + /* clear lo master address */ + out8 (IIC_LMADR1, 0); + + /* clear hi master address */ + out8 (IIC_HMADR1, 0); + + /* clear lo slave address */ + out8 (IIC_LSADR1, 0); + + /* clear hi slave address */ + out8 (IIC_HSADR1, 0); + + /* Clock divide Register */ + /* get OPB frequency */ + get_sys_info (&sysInfo); + freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; + /* set divisor according to freqOPB */ + divisor = (freqOPB - 1) / 10000000; + if (divisor == 0) + divisor = 1; + out8 (IIC_CLKDIV1, divisor); + + /* no interrupts */ + out8 (IIC_INTRMSK1, 0); + + /* clear transfer count */ + out8 (IIC_XFRCNT1, 0); + + /* clear extended control & stat */ + /* write 1 in SRC SRS SWC SWS to clear these fields */ + out8 (IIC_XTCNTLSS1, 0xF0); + + /* Mode Control Register + Flush Slave/Master data buffer */ + out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); + __asm__ volatile ("eieio"); + + + val = in8(IIC_MDCNTL1); + __asm__ volatile ("eieio"); + + /* Ignore General Call, slave transfers are ignored, + disable interrupts, exit unknown bus state, enable hold + SCL + 100kHz normaly or FastMode for 400kHz and above + */ + + val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; + if( speed >= 400000 ){ + val |= IIC_MDCNTL_FSM; + } + out8 (IIC_MDCNTL1, val); + + /* clear control reg */ + out8 (IIC_CNTL1, 0x00); + __asm__ volatile ("eieio"); + +} + +/* + This code tries to use the features of the 405GP i2c + controller. It will transfer up to 4 bytes in one pass + on the loop. It only does out8(lbz) to the buffer when it + is possible to do out16(lhz) transfers. + + cmd_type is 0 for write 1 for read. + + addr_len can take any value from 0-255, it is only limited + by the char, we could make it larger if needed. If it is + 0 we skip the address write cycle. + + Typical case is a Write of an addr followd by a Read. The + IBM FAQ does not cover this. On the last byte of the write + we don't set the creg CHT bit, and on the first bytes of the + read we set the RPST bit. + + It does not support address only transfers, there must be + a data part. If you want to write the address yourself, put + it in the data pointer. + + It does not support transfer to/from address 0. + + It does not check XFRCNT. +*/ +static +int i2c_transfer1(unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len ) +{ + unsigned char* ptr; + int reading; + int tran,cnt; + int result; + int status; + int i; + uchar creg; + + if( data == 0 || data_len == 0 ){ + /*Don't support data transfer of no length or to address 0*/ + printf( "i2c_transfer: bad call\n" ); + return IIC_NOK; + } + if( addr && addr_len ){ + ptr = addr; + cnt = addr_len; + reading = 0; + }else{ + ptr = data; + cnt = data_len; + reading = cmd_type; + } + + /*Clear Stop Complete Bit*/ + out8(IIC_STS1,IIC_STS_SCMP); + /* Check init */ + i=10; + do { + /* Get status */ + status = in8(IIC_STS1); + __asm__ volatile("eieio"); + i--; + } while ((status & IIC_STS_PT) && (i>0)); + + if (status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + return(result); + } + /*flush the Master/Slave Databuffers*/ + out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); + /*need to wait 4 OPB clocks? code below should take that long*/ + + /* 7-bit adressing */ + out8(IIC_HMADR1,0); + out8(IIC_LMADR1, chip); + __asm__ volatile("eieio"); + + tran = 0; + result = IIC_OK; + creg = 0; + + while ( tran != cnt && (result == IIC_OK)) { + int bc,j; + + /* Control register = + Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, + Transfer is a sequence of transfers + */ + creg |= IIC_CNTL_PT; + + bc = (cnt - tran) > 4 ? 4 : + cnt - tran; + creg |= (bc-1)<<4; + /* if the real cmd type is write continue trans*/ + if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) + creg |= IIC_CNTL_CHT; + + if (reading) + creg |= IIC_CNTL_READ; + else { + for(j=0; j<bc; j++) { + /* Set buffer */ + out8(IIC_MDBUF1,ptr[tran+j]); + __asm__ volatile("eieio"); + } + } + out8(IIC_CNTL1, creg ); + __asm__ volatile("eieio"); + + /* Transfer is in progress + we have to wait for upto 5 bytes of data + 1 byte chip address+r/w bit then bc bytes + of data. + udelay(10) is 1 bit time at 100khz + Doubled for slop. 20 is too small. + */ + i=2*5*8; + do { + /* Get status */ + status = in8(IIC_STS1); + __asm__ volatile("eieio"); + udelay (10); + i--; + } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) + && (i>0)); + + if (status & IIC_STS_ERR) { + result = IIC_NOK; + status = in8 (IIC_EXTSTS1); + /* Lost arbitration? */ + if (status & IIC_EXTSTS_LA) + result = IIC_NOK_LA; + /* Incomplete transfer? */ + if (status & IIC_EXTSTS_ICT) + result = IIC_NOK_ICT; + /* Transfer aborted? */ + if (status & IIC_EXTSTS_XFRA) + result = IIC_NOK_XFRA; + } else if ( status & IIC_STS_PT) { + result = IIC_NOK_TOUT; + } + /* Command is reading => get buffer */ + if ((reading) && (result == IIC_OK)) { + /* Are there data in buffer */ + if (status & IIC_STS_MDBS) { + /* + even if we have data we have to wait 4OPB clocks + for it to hit the front of the FIFO, after that + we can just read. We should check XFCNT here and + if the FIFO is full there is no need to wait. + */ + udelay (1); + for(j=0;j<bc;j++) { + ptr[tran+j] = in8(IIC_MDBUF1); + __asm__ volatile("eieio"); + } + } else + result = IIC_NOK_DATA; + } + creg = 0; + tran+=bc; + if( ptr == addr && tran == cnt ) { + ptr = data; + cnt = data_len; + tran = 0; + reading = cmd_type; + if( reading ) + creg = IIC_CNTL_RPST; + } + } + return (result); +} + +int i2c_probe1 (uchar chip) +{ + uchar buf[1]; + + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was <ACK>ed (i.e. there was a chip at that address which + * drove the data line low). + */ + return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0); +} + + +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + int ret; + + if ( alen > 4 ) { + printf ("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { + printf( "I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) +{ + uchar xaddr[4]; + + if ( alen > 4 ) { + printf ("I2C write: addr len %d not supported\n", alen); + return 1; + + } + if ( alen > 0 ) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if( alen > 0 ) + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); +#endif + + return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); +} + +/*----------------------------------------------------------------------- + * Read a register + */ +uchar i2c_reg_read1(uchar i2c_addr, uchar reg) +{ + char buf; + + i2c_read1(i2c_addr, reg, 1, &buf, 1); + + return(buf); +} + +/*----------------------------------------------------------------------- + * Write a register + */ +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) +{ + i2c_write1(i2c_addr, reg, 1, &val, 1); +} + + +int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int j; +#if defined(CFG_I2C_NOPROBES) + int k, skip; +#endif + + puts ("Valid chip addresses:"); + for(j = 0; j < 128; j++) { +#if defined(CFG_I2C_NOPROBES) + skip = 0; + for (k = 0; k < sizeof(i2c_no_probes); k++){ + if (j == i2c_no_probes[k]){ + skip = 1; + break; + } + } + if (skip) + continue; +#endif + if(i2c_probe1(j) == 0) { + printf(" %02X", j); + } + } + putc ('\n'); + +#if defined(CFG_I2C_NOPROBES) + puts ("Excluded chip addresses:"); + for( k = 0; k < sizeof(i2c_no_probes); k++ ) + printf(" %02X", i2c_no_probes[k] ); + putc ('\n'); +#endif + + return 0; +} + +U_BOOT_CMD( + iprobe1, 1, 1, do_i2c1_probe, + "iprobe1 - probe to discover valid I2C chip addresses\n", + "\n -discover valid I2C chip addresses\n" +); + +#endif /* CONFIG_I2C_BUS1 */ diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h new file mode 100644 index 0000000..cd4fc86 --- /dev/null +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ported from i2c driver for ppc4xx by AS HARNOIS by + * Travis B. Sawyer + * Sandburst Corporation + */ +#include <common.h> +#include <ppc4xx.h> +#if defined(CONFIG_440) +# include <440_i2c.h> +#else +# include <405gp_i2c.h> +#endif +#include <i2c.h> + +#ifdef CONFIG_HARD_I2C + +#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) +#define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR +#define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) +#define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) +#define IIC_LMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLMADR) +#define IIC_HMADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHMADR) +#define IIC_CNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCNTL) +#define IIC_MDCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDCNTL) +#define IIC_STS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSTS) +#define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) +#define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) +#define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) +#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) +#define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) +#define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) +#define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) +#define IIC_DIRECTCNTL1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICDIRECTCNTL) + +void i2c1_init (int speed, int slaveadd); +int i2c_probe1 (uchar chip); +int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len); +uchar i2c_reg_read1(uchar i2c_addr, uchar reg); +void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val); + +#endif /* CONFIG_HARD_I2C */ diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c new file mode 100644 index 0000000..3530416 --- /dev/null +++ b/board/sandburst/common/sb_common.c @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "ppc440gx_i2c.h" +#include "sb_common.h" + +long int fixed_sdram (void); + +/************************************************************************* + * metrobox_get_master + * + * PRI_N - active low signal. If the GPIO pin is low we are the master + * + ************************************************************************/ +int sbcommon_get_master(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { + return 0; + } + else { + return 1; + } +} + +/************************************************************************* + * metrobox_secondary_present + * + * Figure out if secondary/slave board is present + * + ************************************************************************/ +int sbcommon_secondary_present(void) +{ + ppc440_gpio_regs_t *gpio_regs; + + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + + if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) + return 0; + else + return 1; +} + +/************************************************************************* + * sbcommon_get_serial_number + * + * Retrieve the board serial number via the mac address in eeprom + * + ************************************************************************/ +unsigned short sbcommon_get_serial_number(void) +{ + unsigned char buff[0x100]; + unsigned short sernum; + + /* Get the board serial number from eeprom */ + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + memcpy(&sernum, &buff[0xF4], 2); + sernum /= 32; + + return (sernum); +} + +/************************************************************************* + * sbcommon_fans + * + * Spin up fans 2 & 3 to get some air moving. OS will take care + * of the rest. This is mostly a precaution... + * + * Assumes i2c bus 1 is ready. + * + ************************************************************************/ +void sbcommon_fans(void) +{ + /* + * Attempt to turn on 2 of the fans... + * Need to go through the bridge + */ + puts ("FANS: "); + + /* select fan4 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x08); /* val = bus 4 */ + + /* Turn on FAN 4 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 4 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan3 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x04); /* val = bus 3 */ + + /* Turn on FAN 3 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 3 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan2 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x02); /* val = bus 4 */ + + /* Turn on FAN 2 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 2 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + /* select fan1 through the bridge */ + i2c_reg_write1(0x73, /* addr */ + 0x00, /* reg */ + 0x01); /* val = bus 0 */ + + /* Turn on FAN 1 */ + i2c_reg_write1(0x2e, + 1, + 0x80); + + i2c_reg_write1(0x2e, + 0, + 0x19); + + /* Deselect bus 1 on the bridge */ + i2c_reg_write1(0x73, + 0x00, + 0x00); + + puts ("on\n"); + + return; + +} + +/************************************************************************* + * initdram + * + * Initialize sdram + * + ************************************************************************/ +long int initdram (int board_type) +{ + long dram_size = 0; + +#if defined(CONFIG_SPD_EEPROM) + dram_size = spd_sdram (0); +#else + dram_size = fixed_sdram (); +#endif + return dram_size; +} + + +/************************************************************************* + * testdram + * + * + ************************************************************************/ +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + uint *pstart = (uint *) CFG_MEMTEST_START; + uint *pend = (uint *) CFG_MEMTEST_END; + uint *p; + + printf("Testing SDRAM: "); + for (p = pstart; p < pend; p++) + *p = 0xaaaaaaaa; + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + for (p = pstart; p < pend; p++) + *p = 0x55555555; + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { + printf ("SDRAM test fails at: %08x\n", (uint) p); + return 1; + } + } + + printf("OK\n"); + return 0; +} +#endif + +#if !defined(CONFIG_SPD_EEPROM) +/************************************************************************* + * fixed sdram init -- doesn't use serial presence detect. + * + * Assumes: 128 MB, non-ECC, non-registered + * PLB @ 133 MHz + * + ************************************************************************/ +long int fixed_sdram (void) +{ + uint reg; + + /*-------------------------------------------------------------------- + * Setup some default + *------------------------------------------------------------------*/ + mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ + mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + + /*-------------------------------------------------------------------- + * Setup for board-specific specific mem + *------------------------------------------------------------------*/ + /* + * Following for CAS Latency = 2.5 @ 133 MHz PLB + */ + mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ + mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ + /* RA=10 RD=3 */ + mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ + mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ + mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ + udelay (400); /* Delay 200 usecs (min) */ + + /*-------------------------------------------------------------------- + * Enable the controller, then wait for DCEN to complete + *------------------------------------------------------------------*/ + mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + for (;;) { + mfsdram (mem_mcsts, reg); + if (reg & 0x80000000) + break; + } + + return (128 * 1024 * 1024); /* 128 MB */ +} +#endif /* !defined(CONFIG_SPD_EEPROM) */ + + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller * hose ) +{ + unsigned long strap; + + /*--------------------------------------------------------------------------+ + * The metrobox is always configured as the host & requires the + * PCI arbiter to be enabled. + *--------------------------------------------------------------------------*/ + mfsdr(sdr_sdstp1, strap); + if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ + printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); + return 0; + } + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller * hose ) +{ + DECLARE_GLOBAL_DATA_PTR; + + /*--------------------------------------------------------------------------+ + * Disable everything + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0SA, 0 ); /* disable */ + out32r( PCIX0_PIM1SA, 0 ); /* disable */ + out32r( PCIX0_PIM2SA, 0 ); /* disable */ + out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + + /*--------------------------------------------------------------------------+ + * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping + * options to not support sizes such as 128/256 MB. + *--------------------------------------------------------------------------*/ + out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAH, 0 ); + out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + + out32r( PCIX0_BAR0, 0 ); + + /*--------------------------------------------------------------------------+ + * Program the board's subsystem id/vendor id + *--------------------------------------------------------------------------*/ + out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + + out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + + +/************************************************************************* + * is_pci_host + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* The metrobox is always configured as host. */ + return(1); +} +#endif /* defined(CONFIG_PCI) */ + +/************************************************************************* + * board_get_enetaddr + * + * Get the ethernet MAC address for the management ethernet from the + * strap EEPROM. Note that is the BASE address for the range of + * external ethernet MACs on the board. The base + 31 is the actual + * mgmt mac address. + * + ************************************************************************/ +static int macaddr_idx = 0; + +void board_get_enetaddr (uchar * enet) +{ + int i; + unsigned short tmp; + unsigned char buff[0x100], *cp; + + if (0 == macaddr_idx) { + + /* Initialize I2C */ + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + + /* Read 256 bytes in EEPROM */ + i2c_read (0x50, 0, 1, buff, 0x100); + + cp = &buff[0xF0]; + + for (i = 0; i < 6; i++,cp++) + enet[i] = *cp; + + memcpy(&tmp, &enet[4], 2); + tmp += 31; + memcpy(&enet[4], &tmp, 2); + + macaddr_idx++; + } else { + enet[0] = 0x02; + enet[1] = 0x00; + enet[2] = 0x00; + enet[3] = 0x00; + enet[4] = 0x00; + if (1 == sbcommon_get_master() ) { + /* Master/Primary card */ + enet[5] = 0x01; + } else { + /* Slave/Secondary card */ + enet [5] = 0x02; + } + } + + return; +} + +#ifdef CONFIG_POST +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + + return (ctrlc()); +} +#endif diff --git a/board/sandburst/common/sb_common.h b/board/sandburst/common/sb_common.h new file mode 100644 index 0000000..888e4f0 --- /dev/null +++ b/board/sandburst/common/sb_common.h @@ -0,0 +1,76 @@ +#ifndef __SBCOMMON_H__ +#define __SBCOMMON_H__ +/* + * Copyright (C) 2005 Sandburst Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "ppc440gx_i2c.h" + +/* + * GPIO Settings + */ +/* Chassis settings */ +#define SBCOMMON_GPIO_PRI_N 0x00001000 /* 0 = Chassis Master, 1 = Slave */ +#define SBCOMMON_GPIO_SEC_PRES 0x00000800 /* 1 = Other board present */ + +/* Debug LEDs */ +#define SBCOMMON_GPIO_DBGLED_0 0x00000400 +#define SBCOMMON_GPIO_DBGLED_1 0x00000200 +#define SBCOMMON_GPIO_DBGLED_2 0x00100000 +#define SBCOMMON_GPIO_DBGLED_3 0x00000100 + +#define SBCOMMON_GPIO_DBGLEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3) + +#define SBCOMMON_GPIO_SYS_FAULT 0x00000080 +#define SBCOMMON_GPIO_SYS_OTEMP 0x00000040 +#define SBCOMMON_GPIO_SYS_STATUS 0x00000020 + +#define SBCOMMON_GPIO_SYS_LEDS (SBCOMMON_GPIO_SYS_STATUS) + +#define SBCOMMON_GPIO_LEDS (SBCOMMON_GPIO_DBGLED_0 | \ + SBCOMMON_GPIO_DBGLED_1 | \ + SBCOMMON_GPIO_DBGLED_2 | \ + SBCOMMON_GPIO_DBGLED_3 | \ + SBCOMMON_GPIO_SYS_STATUS) + +typedef struct ppc440_gpio_regs { + volatile unsigned long out; + volatile unsigned long tri_state; + volatile unsigned long dummy[4]; + volatile unsigned long open_drain; + volatile unsigned long in; +} __attribute__((packed)) ppc440_gpio_regs_t; + +int sbcommon_get_master(void); +int sbcommon_secondary_present(void); +unsigned short sbcommon_get_serial_number(void); +void sbcommon_fans(void); + +#endif /* __SBCOMMON_H__ */ diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile new file mode 100644 index 0000000..8b3173c --- /dev/null +++ b/board/sandburst/karef/Makefile @@ -0,0 +1,59 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# Travis B. Sawyer +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o + +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk new file mode 100644 index 0000000..65c1e48 --- /dev/null +++ b/board/sandburst/karef/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2005 +# Sandburst Corporation +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Sandburst Corporation Metrobox Reference Design +# Travis B. Sawyer +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/karef/hal_ka_of_auto.h b/board/sandburst/karef/hal_ka_of_auto.h new file mode 100644 index 0000000..cc501c9 --- /dev/null +++ b/board/sandburst/karef/hal_ka_of_auto.h @@ -0,0 +1,324 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_of + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_OF_AUTO_H +#define HAL_KA_OF_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'ofem' + */ + +/* ---- Block instance addressing (for block-select) */ +#define OFEM_BLOCK_ADDR_BIT_L 6 +#define OFEM_BLOCK_ADDR_BIT_H 9 +#define OFEM_BLOCK_ADDR_WIDTH 4 + +#define OFEM_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define OFEM_REG_ADDR_BIT_L 2 +#define OFEM_REG_ADDR_BIT_H 5 +#define OFEM_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_REVISION_MSB 31 +#define SAND_HAL_KA_OF_OFEM_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_RESET_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_RESET_MSB 31 +#define SAND_HAL_KA_OF_OFEM_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_OFFSET 0x018 +#ifndef SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_CNTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_OFFSET 0x008 +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_OFFSET 0x00c +#ifndef SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_OFFSET 0x010 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_OFFSET 0x014 +#ifndef SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_OF_OFEM_REVISION */ +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_DEFAULT 0x00000024 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_RESET */ +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_CNTL */ +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_MAC_FLOW_CTL */ +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_MSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_LSB 8 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_LOCH_APS_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_INTERRUPT_MASK */ +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00000100 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 8 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 7 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 6 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000020 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 5 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 4 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 3 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 2 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_OF_OFEM_SCRATCH_MASK */ +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_OF_OFEM_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_OF_AUTO_H */ diff --git a/board/sandburst/karef/hal_ka_sc_auto.h b/board/sandburst/karef/hal_ka_sc_auto.h new file mode 100644 index 0000000..db1cec2 --- /dev/null +++ b/board/sandburst/karef/hal_ka_sc_auto.h @@ -0,0 +1,836 @@ +/* **************************************************************** + * Common defs for reg spec for chip ka_sc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_KA_SC_AUTO_H +#define HAL_KA_SC_AUTO_H + + +/* ---------------------------------------------------------------- + * For block: 'scan' + */ + +/* ---- Block instance addressing (for block-select) */ +#define SCAN_BLOCK_ADDR_BIT_L 7 +#define SCAN_BLOCK_ADDR_BIT_H 9 +#define SCAN_BLOCK_ADDR_WIDTH 3 + +#define SCAN_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define SCAN_REG_ADDR_BIT_L 2 +#define SCAN_REG_ADDR_BIT_H 6 +#define SCAN_REG_ADDR_WIDTH 5 + + +/* ================================================================ + * ---- Register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_REVISION_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_REVISION_MSB 31 +#define SAND_HAL_KA_SC_SCAN_REVISION_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_OFFSET 0x004 +#ifndef SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_RESET_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_RESET_MSB 31 +#define SAND_HAL_KA_SC_SCAN_RESET_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_STATUS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_STATUS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_STATUS_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CNTL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CNTL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CNTL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_OFFSET 0x024 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_OFFSET 0x028 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_OFFSET 0x02c +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_OFFSET 0x030 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_OFFSET 0x034 +#ifndef SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_OFFSET 0x038 +#ifndef SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_MSB 31 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_OFFSET 0x03c +#ifndef SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_OFFSET 0x040 +#ifndef SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_OFFSET 0x044 +#ifndef SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_OFFSET 0x048 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_OFFSET 0x04c +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_OFFSET 0x050 +#ifndef SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_OFFSET 0x054 +#ifndef SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_MISC_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_MISC_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_MISC_MSB 31 +#define SAND_HAL_KA_SC_SCAN_MISC_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register KA_SC_SCAN_REVISION */ +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_DEFAULT 0x00000023 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MSB 7 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_LSB 0 +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_RESET */ +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_LSB 9 +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_LSB 8 +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_LSB 7 +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_LSB 6 +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_LSB 5 +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_LSB 4 +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_STATUS */ +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_SPI_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_MSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_LSB 5 +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_DR_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_MSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_LSB 4 +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_CORE_LOCK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_MSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_LSB 3 +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_OFEM_DONE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CNTL */ +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_MSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_LSB 9 +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_MSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_LSB 8 +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MASK 0x000000c0 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_MSB 7 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_LSB 6 +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK 0x00000030 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MSB 5 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_LSB 4 +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MASK 0x0000000c +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_MSB 3 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_LSB 2 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_MSB 1 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CNTL_RS232_L_LED_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_INFO */ +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK 0x0000f000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MSB 15 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_LSB 12 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK 0x00000300 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MSB 9 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_LSB 8 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_0_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_FROM_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SCAN_FROM_1_SCAN_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_0 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_0_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_TO_1 */ +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_TO_1_SCAN_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCAN_CTRL */ +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MASK 0x04000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_SHIFT 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_MSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_LSB 26 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCI_SEL_BM_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MASK 0x03000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_TEST_MODE_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MASK 0x00100000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_SHIFT 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_LSB 20 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_TEST_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MASK 0x00080000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_SHIFT 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_MSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_LSB 19 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PO_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MASK 0x00040000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_SHIFT 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_MSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_LSB 18 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_PI_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MASK 0x00020000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_SHIFT 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_MSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_LSB 17 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MASK 0x00010000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_SHIFT 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_MSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_LSB 16 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_KA_SCAN_EN_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_MSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_LSB 12 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_ENABLE_DRIVERS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_MSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_LSB 11 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_MSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_LSB 10 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_MSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_LSB 8 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MASK 0x00000018 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_MSB 4 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_LSB 3 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_REF_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_LSB 2 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_SPI_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_MSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_LSB 1 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_DR_CLK_SEL_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_MSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCAN_CTRL_CORE_CLK_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_PLL_CTRL */ +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MASK 0x00002000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_SHIFT 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_MSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_LSB 13 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RIPPLE_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MASK 0x00001000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_SHIFT 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_MSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_LSB 12 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_RESET_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MASK 0x00000800 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_SHIFT 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_MSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_LSB 11 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MASK 0x00000400 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_SHIFT 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_MSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_LSB 10 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MASK 0x00000200 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_SHIFT 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_MSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_LSB 9 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_SPI_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MASK 0x00000100 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_SHIFT 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_MSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_LSB 8 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MASK 0x00000080 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_SHIFT 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_MSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_LSB 7 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MASK 0x00000040 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_SHIFT 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_MSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_LSB 6 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_DR_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MASK 0x00000020 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_SHIFT 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_MSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_LSB 5 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_BYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_MSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_LSB 4 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_ACBYPASS_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_MSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_LSB 3 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_EXTCLK_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MASK 0x00000007 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_MSB 2 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_LSB 0 +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_PLL_CTRL_KA_PLL_CORE_M_N_SEL_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_CORE_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_CORE_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_DR_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_DR_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SPI_CLK_COUNT */ +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MASK 0x02000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_SHIFT 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_MSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_LSB 25 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_CLEAR_RIPPLE_CNT_N_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MASK 0x01000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_SHIFT 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_MSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_LSB 24 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_ENABLE_RIPPLE_CNT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MASK 0x00ffffff +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_MSB 23 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_SPI_CLK_COUNT_RIPPLE_COUNT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_DATA */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_DATA_BRD_OUT_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_OUT_ENABLE */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_OUT_ENABLE_BRD_OUT_EN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_BRD_BRD_IN */ +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MASK 0x001fffff +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_MSB 20 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_LSB 0 +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_BRD_BRD_IN_BRD_IN_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_MISC */ +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_MSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_LSB 1 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_START_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_MSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_LSB 0 +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_MISC_MARG_READY_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_INTERRUPT_MASK */ +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00000010 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 4 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000008 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 3 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000004 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 2 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000002 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 1 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000001 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register KA_SC_SCAN_SCRATCH_MASK */ +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_KA_SC_SCAN_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_KA_SC_AUTO_H */ diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S new file mode 100644 index 0000000..b1d47a4 --- /dev/null +++ b/board/sandburst/karef/init.S @@ -0,0 +1,101 @@ +/* +* Copyright (C) 2005 Sandburst Corporation +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ +/* + * Ported from Ebony init.S by Travis B. Sawyer + */ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c new file mode 100644 index 0000000..3856a39 --- /dev/null +++ b/board/sandburst/karef/karef.c @@ -0,0 +1,577 @@ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <command.h> +#include "karef.h" +#include "karef_version.h" +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "../common/sb_common.h" +#include "../common/ppc440gx_i2c.h" + +void fpga_init (void); + +KAREF_BOARD_ID_ST board_id_as[] = +{ + {"Undefined"}, /* Not specified */ + {"Kamino Reference Design"}, + {"Reserved"}, /* Reserved for future use */ + {"Reserved"}, /* Reserved for future use */ +}; + +KAREF_BOARD_ID_ST ofem_board_id_as[] = +{ + {"Undefined"}, + {"1x10 + 10x2"}, + {"Reserved"}, + {"Reserved"}, +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | KaRef Scan FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | OFEM FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char scan_rev, scan_id, ofem_rev, ofem_id; + unsigned char ofem_brd_rev, ofem_brd_id; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + + scan_id = (unsigned char)((karef_ps->revision_ul & + SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT); + + scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK) + >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT); + + brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT); + + ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + + ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT); + + if (0xF != ofem_brd_id) { + ofem_id = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT); + + ofem_rev = (unsigned char)((ofem_ps->revision_ul & + SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK) + >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT); + } + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + + printf ("Board: Sandburst Corporation Kamino Reference Design " + "Serial Number: %d\n", sernum); + printf ("%s\n", KAREF_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev); + printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id); + if(0xF != ofem_brd_id) { + printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev); + printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev); + } + + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans 3 & 4 */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + unsigned char ofem_id; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", KAREF_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; + karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + KAREF_FPGA_REGS_ST *karef_ps; + /* TODO: ide reset */ + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + + if (on) { + karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } else { + karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + KAREF_FPGA_REGS_ST *karef_ps; + OFEM_FPGA_REGS_ST *ofem_ps; + unsigned char ofem_id; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + tmp = + SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK | + SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK; + + karef_ps->reset_ul = tmp; + + /* + * Wait a bit to allow the ofem fpga to get its brains + */ + udelay(5000); + + /* + * Check to see if the ofem is there + */ + ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK) + >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT); + if(0xF != ofem_id) { + tmp = + SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | + SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; + + ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps->reset_ul = tmp; + + ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; + } + + karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT; + + asm("eieio"); + + return; +} + +int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.70.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d " + "nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:" + "255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000"); + + saveenv(); + + return(1); +} + +int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + + setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot<cr>.\nWhen the kernel has booted" + " please type fsrecover.sh<cr>\n"); + + return(1); +} + +U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, + "kasetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(karecover, 1, 1, karefRecover, + "karecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/karef/karef.h b/board/sandburst/karef/karef.h new file mode 100644 index 0000000..7790819 --- /dev/null +++ b/board/sandburst/karef/karef.h @@ -0,0 +1,76 @@ +#ifndef __KAREF_H__ +#define __KAREF_H__ +/* + * (C) Copyright 2005 + * Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Ka Reference Design OFEM FPGA Registers & definitions */ +#include "hal_ka_sc_auto.h" +#include "hal_ka_of_auto.h" + +typedef struct karef_board_id_s { + const char name[40]; +} KAREF_BOARD_ID_ST, *KAREF_BOARD_ID_PST; + +/* SCAN FPGA */ +typedef struct karef_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ + volatile unsigned long scan_from0_ul; /* Read Only */ + volatile unsigned long scan_from1_ul; /* Read Only */ + volatile unsigned long scan_to0_ul; /* Read/Write */ + volatile unsigned long scan_to1_ul; /* Read/Write */ + volatile unsigned long scan_control_ul; /* Read/Write */ + volatile unsigned long pll_control_ul; /* Read/Write */ + volatile unsigned long core_clock_cnt_ul; /* Read/Write */ + volatile unsigned long dr_clock_cnt_ul; /* Read/Write */ + volatile unsigned long spi_clock_cnt_ul; /* Read/Write */ + volatile unsigned long brdout_data_ul; /* Read/Write */ + volatile unsigned long brdout_enable_ul; /* Read/Write */ + volatile unsigned long brdin_data_ul; /* Read Only */ + volatile unsigned long misc_ul; /* Read/Write */ +} KAREF_FPGA_REGS_ST __attribute__((packed)), * KAREF_FPGA_REGS_PST; + +/* OFEM FPGA */ +typedef struct ofem_fpga_regs_s +{ + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long mac_flow_ctrl_ul; /* Read/Write */ +} OFEM_FPGA_REGS_ST __attribute__((packed)), * OFEM_FPGA_REGS_PST; + + +#endif /* __KAREF_H__ */ diff --git a/board/sandburst/karef/karef_version.h b/board/sandburst/karef/karef_version.h new file mode 100644 index 0000000..9960b9a --- /dev/null +++ b/board/sandburst/karef/karef_version.h @@ -0,0 +1,26 @@ +#ifndef _KAREF_VERSION_H_ +#define _KAREF_VERSION_H_ +/* + * Copyright (C) 2005 Sandburst Corporation + * Travis B. Sawyer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define KAREF_U_BOOT_REL_STR "Release 0.0.7" +#endif diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds new file mode 100644 index 0000000..ff8658f --- /dev/null +++ b/board/sandburst/karef/u-boot.lds @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/karef/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/ocotea/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 41534de..c6522b9 100644 --- a/board/ocotea/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -1,6 +1,7 @@ /* - * (C) Copyright 2002-2004 + * (C) Copyright 2002-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com * * See file CREDITS for list of people who contributed to this * project. @@ -33,22 +34,22 @@ SECTIONS .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } + .rel.text : { *(.rel.text) } .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } + .rel.data : { *(.rel.data) } .rela.data : { *(.rela.data) } .rel.rodata : { *(.rel.rodata) } .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } .init : { *(.init) } .plt : { *(.plt) } .text : @@ -57,7 +58,7 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - board/ocotea/init.o (.text) + board/sandburst/karef/init.o (.text) cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile new file mode 100644 index 0000000..06a9a22 --- /dev/null +++ b/board/sandburst/metrobox/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# TBS: add for debugging purposes +BUILDUSER := $(shell whoami) +FORCEBUILD := $(shell rm -f $(LIB) $(BOARD).o) + +CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +# TBS: end debugging + + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/ppc440gx_i2c.o \ + ../common/sb_common.o +SOBJS = init.o + + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk new file mode 100644 index 0000000..91aee2f --- /dev/null +++ b/board/sandburst/metrobox/config.mk @@ -0,0 +1,38 @@ +# +# (C) Copyright 2005 +# Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(ramsym),1) +TEXT_BASE = 0x07FD0000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/sandburst/metrobox/hal_xc_auto.h b/board/sandburst/metrobox/hal_xc_auto.h new file mode 100644 index 0000000..c99b38c --- /dev/null +++ b/board/sandburst/metrobox/hal_xc_auto.h @@ -0,0 +1,553 @@ +/* **************************************************************** + * Common defs for reg spec for chip xc + * Auto-generated by trex2: DO NOT HAND-EDIT!! + * **************************************************************** + */ + +#ifndef HAL_XC_AUTO_H +#define HAL_XC_AUTO_H + +/* ---------------------------------------------------------------- + * For block: 'xcvr_cntl' + */ + +/* ---- Block instance addressing (for block-select) */ +#define XCVR_CNTL_BLOCK_ADDR_BIT_L 6 +#define XCVR_CNTL_BLOCK_ADDR_BIT_H 9 +#define XCVR_CNTL_BLOCK_ADDR_WIDTH 4 + +#define XCVR_CNTL_ADDR 0x0 + +/* ---- Reg addressing (within block) */ +#define XCVR_CNTL_REG_ADDR_BIT_L 2 +#define XCVR_CNTL_REG_ADDR_BIT_H 5 +#define XCVR_CNTL_REG_ADDR_WIDTH 4 + + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_OFFSET 0x000 +#ifndef SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_REVISION_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_OFFSET 0x004 +#ifndef SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_RESET_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_RESET_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_RESET_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_OFFSET 0x008 +#ifndef SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_STATUS_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_STATUS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OFFSET 0x01c +#ifndef SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_CNTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_CNTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_OFFSET 0x020 +#ifndef SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_OFFSET 0x024 +#ifndef SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OFFSET 0x00c +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OFFSET 0x010 +#ifndef SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_OFFSET 0x014 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_LSB 0 + +/* ================================================================ + * ---- Register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_OFFSET 0x018 +#ifndef SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_NO_TEST_MASK 0x000 +#endif +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_LSB 0 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_REVISION */ +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK 0x0000ff00 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK 0x000000ff +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_RESET */ +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK 0x00020000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_SHIFT 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_LSB 17 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK 0x00010000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_SHIFT 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_LSB 16 +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK 0x00008000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_SHIFT 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_LSB 15 +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK 0x00004000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_SHIFT 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_LSB 14 +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_STATUS */ +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_A_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_PS_B_PRES_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_STATUS_ALL_GOOD_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_CNTL */ +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_SW_PWR_DOWN_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MASK 0x00000300 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_OVER_TEMP_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK 0x000000c0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MASK 0x00000030 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_R_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MASK 0x0000000c +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_RS232_L_LED_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_CORE_CLK_50_EN_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_CNTL_PCI_CLK_EN_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_BRD_INFO */ +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK 0x000000f0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK 0x00000003 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_MAC_FLOW_CTL */ +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MASK 0x00000f00 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACB_TXPAUSE_ADDR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_FR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MASK 0x0000000f +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_MAC_FLOW_CTL_MACA_TXPAUSE_ADDR_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_BME_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC_TIMEOUT_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_A_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_QK_B_LOSOUT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_NR_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_A_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_XFP_B_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_OVER_TEMP_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_A_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_POWER_FAIL_B_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC1_INT_N_DEFAULT 0x00000000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_TYPE (SAND_HAL_TYPE_READ) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MAC0_INT_N_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_INTERRUPT_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MASK 0x00002000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_SHIFT 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_MSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_LSB 13 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_BME_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MASK 0x00001000 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_SHIFT 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_MSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_LSB 12 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC_TIMEOUT_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MASK 0x00000800 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_SHIFT 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_MSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_LSB 11 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_A_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MASK 0x00000400 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_SHIFT 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_MSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_LSB 10 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_QK_B_LOSOUT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MASK 0x00000200 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_SHIFT 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_MSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_LSB 9 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MASK 0x00000100 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_SHIFT 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_MSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_LSB 8 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_NR_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MASK 0x00000080 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_SHIFT 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_MSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_LSB 7 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_A_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MASK 0x00000040 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_SHIFT 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_MSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_LSB 6 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_XFP_B_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MASK 0x00000020 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_SHIFT 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_MSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_LSB 5 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MASK 0x00000010 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_SHIFT 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_MSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_LSB 4 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_OVER_TEMP_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MASK 0x00000008 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_SHIFT 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_MSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_LSB 3 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_A_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MASK 0x00000004 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_SHIFT 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_MSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_LSB 2 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_POWER_FAIL_B_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MASK 0x00000002 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_SHIFT 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_MSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_LSB 1 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC1_INT_N_DISINT_DEFAULT 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MASK 0x00000001 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_MSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_INTERRUPT_MASK_MAC0_INT_N_DISINT_DEFAULT 0x00000001 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_TEST_BITS_DEFAULT 0x00000000 + +/* ================================================================ + * Field info for register XC_XCVR_CNTL_SCRATCH_MASK */ +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MASK 0xffffffff +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_SHIFT 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_MSB 31 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_LSB 0 +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_TYPE (SAND_HAL_TYPE_WRITE) +#define SAND_HAL_XC_XCVR_CNTL_SCRATCH_MASK_TEST_BITS_DISINT_DEFAULT 0xffffffff + +#endif /* matches #ifndef HAL_XC_AUTO_H */ diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S new file mode 100644 index 0000000..e398f00 --- /dev/null +++ b/board/sandburst/metrobox/init.S @@ -0,0 +1,99 @@ +/* +* Copyright (C) 2005 +* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +/* General */ +#define TLB_VALID 0x00000200 + +/* Supported page sizes */ + +#define SZ_1K 0x00000000 +#define SZ_4K 0x00000010 +#define SZ_16K 0x00000020 +#define SZ_64K 0x00000030 +#define SZ_256K 0x00000040 +#define SZ_1M 0x00000050 +#define SZ_16M 0x00000070 +#define SZ_256M 0x00000090 + +/* Storage attributes */ +#define SA_W 0x00000800 /* Write-through */ +#define SA_I 0x00000400 /* Caching inhibited */ +#define SA_M 0x00000200 /* Memory coherence */ +#define SA_G 0x00000100 /* Guarded */ +#define SA_E 0x00000080 /* Endian */ + +/* Access control */ +#define AC_X 0x00000024 /* Execute */ +#define AC_W 0x00000012 /* Write */ +#define AC_R 0x00000009 /* Read */ + +/* Some handy macros */ + +#define EPN(e) ((e) & 0xfffffc00) +#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) ) +#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) ) +#define TLB2(a) ( (a)&0x00000fbf ) + +#define tlbtab_start\ + mflr r1 ;\ + bl 0f ; + +#define tlbtab_end\ + .long 0, 0, 0 ; \ +0: mflr r0 ; \ + mtlr r1 ; \ + blr ; + +#define tlbentry(epn,sz,rpn,erpn,attr)\ + .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr) + + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c new file mode 100644 index 0000000..869367d --- /dev/null +++ b/board/sandburst/metrobox/metrobox.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <common.h> +#include <command.h> +#include "metrobox.h" +#include "metrobox_version.h" +#include <asm/processor.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <i2c.h> +#include "../common/ppc440gx_i2c.h" +#include "../common/sb_common.h" + +void fpga_init (void); + +METROBOX_BOARD_ID_ST board_id_as[] = +{ {"Undefined"}, /* Not specified */ + {"2x10Gb"}, /* 2 ports, 10 GbE */ + {"20x1Gb"}, /* 20 ports, 1 GbE */ + {"Reserved"}, /* Reserved for future use */ +}; + +/************************************************************************* + * board_early_init_f + * + * Setup chip selects, initialize the Opto-FPGA, initialize + * interrupt polarity and triggers. + ************************************************************************/ +int board_early_init_f (void) +{ + ppc440_gpio_regs_t *gpio_regs; + + /* Enable GPIO interrupts */ + mtsdr(sdr_pfc0, 0x00103E00); + + /* Setup access for LEDs, and system topology info */ + gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; + gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; + + /* Turn on all the leds for now */ + gpio_regs->out = SBCOMMON_GPIO_LEDS; + + /*--------------------------------------------------------------------+ + | Initialize EBC CONFIG + +-------------------------------------------------------------------*/ + mtebc(xbcfg, + EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | + EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | + EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | + EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | + EBC_CFG_PR_32); + + /*--------------------------------------------------------------------+ + | 1/2 MB FLASH. Initialize bank 0 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb0ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + /*--------------------------------------------------------------------+ + | 8KB NVRAM/RTC. Initialize bank 1 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb1ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb2ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | OPTO & OFEM FPGA. Initialize bank 3 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb3ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | MAC A for metrobox + | MAC A & B for Kamino. OFEM FPGA decodes the addresses + | Initialize bank 4 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb4ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Metrobox MAC B Initialize bank 5 with default values. + | KA REF FPGA Initialize bank 5 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb5ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + | Compact Flash, uses 2 Chip Selects (2 & 6) + +-------------------------------------------------------------------*/ + mtebc(pb6ap, + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | + EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | + EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | + EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) | + EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | + EBC_BXAP_PEN_DISABLED); + + mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); + + /*--------------------------------------------------------------------+ + | BME-32. Initialize bank 7 with default values. + +-------------------------------------------------------------------*/ + mtebc(pb7ap, + EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | + EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | + EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | + EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | + EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); + + mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); + + /*--------------------------------------------------------------------+ + * Setup the interrupt controller polarities, triggers, etc. + +-------------------------------------------------------------------*/ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + mtdcr (uic0er, 0x00000000); /* disable all */ + mtdcr (uic0cr, 0x00000000); /* all non- critical */ + mtdcr (uic0pr, 0xfffffe03); /* polarity */ + mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */ + mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic0sr, 0xffffffff); /* clear all */ + + mtdcr (uic1sr, 0xffffffff); /* clear all */ + mtdcr (uic1er, 0x00000000); /* disable all */ + mtdcr (uic1cr, 0x00000000); /* all non-critical */ + mtdcr (uic1pr, 0xffffc8ff); /* polarity */ + mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */ + mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic1sr, 0xffffffff); /* clear all */ + + mtdcr (uic2sr, 0xffffffff); /* clear all */ + mtdcr (uic2er, 0x00000000); /* disable all */ + mtdcr (uic2cr, 0x00000000); /* all non-critical */ + mtdcr (uic2pr, 0xffff83ff); /* polarity */ + mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */ + mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr (uic2sr, 0xffffffff); /* clear all */ + + mtdcr (uicb0sr, 0xfc000000); /* clear all */ + mtdcr (uicb0er, 0x00000000); /* disable all */ + mtdcr (uicb0cr, 0x00000000); /* all non-critical */ + mtdcr (uicb0pr, 0xfc000000); + mtdcr (uicb0tr, 0x00000000); + mtdcr (uicb0vr, 0x00000001); + + fpga_init(); + + return 0; +} + +/************************************************************************* + * checkboard + * + * Dump pertinent info to the console + ************************************************************************/ +int checkboard (void) +{ + sys_info_t sysinfo; + unsigned char brd_rev, brd_id; + unsigned short sernum; + unsigned char opto_rev, opto_id; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + opto_id = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT); + + brd_rev = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT); + + brd_id = (unsigned char)((opto_ps->boardinfo_ul & + SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK) + >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT); + + get_sys_info (&sysinfo); + + sernum = sbcommon_get_serial_number(); + printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); + printf ("%s\n", METROBOX_U_BOOT_REL_STR); + + printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + if (sbcommon_get_master()) { + printf("Slot 0 - Master\nSlave board"); + if (sbcommon_secondary_present()) + printf(" present\n"); + else + printf(" not detected\n"); + } else { + printf("Slot 1 - Slave\n\n"); + } + + printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev); + printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]); + + printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); + printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); + printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); + + + /* Fix the ack in the bme 32 */ + udelay(5000); + out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + asm("eieio"); + + + return (0); +} + +/************************************************************************* + * misc_init_f + * + * Initialize I2C bus one to gain access to the fans + ************************************************************************/ +int misc_init_f (void) +{ + /* Turn on i2c bus 1 */ + puts ("I2C1: "); + i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + puts ("ready\n"); + + /* Turn on fans */ + sbcommon_fans(); + + return (0); +} + +/************************************************************************* + * misc_init_r + * + * Do nothing. + ************************************************************************/ +int misc_init_r (void) +{ + unsigned short sernum; + char envstr[255]; + unsigned char opto_rev; + OPTO_FPGA_REGS_ST *opto_ps; + + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if(NULL != getenv("secondserial")) { + puts("secondserial is set, switching to second serial port\n"); + setenv("stderr", "serial1"); + setenv("stdout", "serial1"); + setenv("stdin", "serial1"); + } + + setenv("ubrelver", METROBOX_U_BOOT_REL_STR); + + memset(envstr, 0, 255); + sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + setenv("bldstr", envstr); + saveenv(); + + if( getenv("autorecover")) { + setenv("autorecover", NULL); + saveenv(); + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for automatic filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type allow the system to continue to boot\n"); + } + + if( getenv("fakeled")) { + setenv("bootdelay", "-1"); + saveenv(); + printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n"); + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + + if(0x12 <= opto_rev) { + opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK; + } + } + + return (0); +} + +/************************************************************************* + * ide_set_reset + ************************************************************************/ +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) +{ + OPTO_FPGA_REGS_ST *opto_ps; + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + if (on) { /* assert RESET */ + opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } else { /* release RESET */ + opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; + } +} +#endif /* CONFIG_IDE_RESET */ + +/************************************************************************* + * fpga_init + ************************************************************************/ +void fpga_init(void) +{ + OPTO_FPGA_REGS_ST *opto_ps; + unsigned char opto_rev; + unsigned long tmp; + + /* Ensure we have power all around */ + udelay(500); + + /* + * Take appropriate hw bits out of reset + */ + opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + + tmp = + SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK | + SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK; + opto_ps->reset_ul = tmp; + /* + * Turn on the 'Slow Blink' for the System Error Led. + * Ensure FPGA rev is up to at least rev 0x12 + */ + opto_rev = (unsigned char)((opto_ps->revision_ul & + SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) + >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT); + if(0x12 <= opto_rev) { + opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT; + } + + asm("eieio"); + + return; +} + +int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + memset(envstr, 0, 255); + /* + * Setup our ip address + */ + sprintf(envstr, "10.100.60.%d", sernum); + + setenv("ipaddr", envstr); + /* + * Setup the host ip address + */ + setenv("serverip", "10.100.17.10"); + + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + + sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs " + "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d " + "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1" + ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33", + sernum, sernum, sernum); + + setenv("bootargs_nfs", envstr); + setenv("bootargs", envstr); + + /* + * Setup CF bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33", + sernum, sernum); + + setenv("bootargs_cf", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000"); + setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000"); + + /* + * Setup compact flash boot command + */ + setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000"); + + saveenv(); + + + return(1); +} + +int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned short sernum; + char envstr[255]; + + sernum = sbcommon_get_serial_number(); + + printf("\nSetting up environment for filesystem recovery\n"); + /* + * Setup default bootargs + */ + memset(envstr, 0, 255); + sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 " + "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none", + sernum, sernum); + + setenv("bootargs", envstr); + + /* + * Setup Default boot command + */ + setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;" + "fatload ide 0 8100000 pramdisk;" + "bootm 8000000 8100000"); + + printf("Done. Please type boot<cr>.\nWhen the kernel has booted" + " please type fsrecover.sh<cr>\n"); + + return(1); +} + +U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, + "mbsetup - Set environment to factory defaults\n", NULL); + +U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, + "mbrecover - Set environment to allow for fs recovery\n", NULL); diff --git a/board/sandburst/metrobox/metrobox.h b/board/sandburst/metrobox/metrobox.h new file mode 100644 index 0000000..cb7a83c --- /dev/null +++ b/board/sandburst/metrobox/metrobox.h @@ -0,0 +1,45 @@ +#ifndef __METROBOX_H__ +#define __METROBOX_H__ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +typedef struct metrobox_board_id_s { + const char name[40]; +} METROBOX_BOARD_ID_ST, *METROBOX_BOARD_ID_PST; + + +/* Metrobox Opto-FPGA registers and definitions */ +#include "hal_xc_auto.h" +typedef struct opto_fpga_regs_s { + volatile unsigned long revision_ul; /* Read Only */ + volatile unsigned long reset_ul; /* Read/Write */ + volatile unsigned long status_ul; /* Read Only */ + volatile unsigned long interrupt_ul; /* Read Only */ + volatile unsigned long mask_ul; /* Read/Write */ + volatile unsigned long scratch_ul; /* Read/Write */ + volatile unsigned long scrmask_ul; /* Read/Write */ + volatile unsigned long control_ul; /* Read/Write */ + volatile unsigned long boardinfo_ul; /* Read Only */ +} OPTO_FPGA_REGS_ST __attribute__ ((packed)), *OPTO_FPGA_REGS_PST; + +#endif /* __METROBOX_H__ */ diff --git a/board/sandburst/metrobox/metrobox_version.h b/board/sandburst/metrobox/metrobox_version.h new file mode 100644 index 0000000..1b6fee5 --- /dev/null +++ b/board/sandburst/metrobox/metrobox_version.h @@ -0,0 +1,27 @@ +#ifndef _METROBOX_VERSION_H_ +#define _METROBOX_VERSION_H_ +/* + * (C) Copyright 2005 + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define METROBOX_U_BOOT_REL_STR "Release 2.0.3" + +#endif diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds new file mode 100644 index 0000000..0fdb166 --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug new file mode 100644 index 0000000..459a1d8 --- /dev/null +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/sandburst/metrobox/init.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + cpu/ppc4xx/440gx_enet.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* common/environment.o(.text) */ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/sbc8560/config.mk b/board/sbc8560/config.mk index 3c8cfbe..6d9ae45 100644 --- a/board/sbc8560/config.mk +++ b/board/sbc8560/config.mk @@ -30,5 +30,4 @@ TEXT_BASE = 0xfffc0000 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 42d1497..c31ea53 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -601,70 +601,3 @@ long int initdram(int board_type) return (size_sdram); } - -#ifdef CFG_JFFS_CUSTOM_PART - -static struct part_info part; - -#define jffs2_block(i) \ - ((struct jffs2_unknown_node*)(CFG_JFFS2_BASE + (i) * 65536)) - -struct part_info* jffs2_part_info(int part_num) -{ - DECLARE_GLOBAL_DATA_PTR; - bd_t *bd = gd->bd; - char* s; - int i; - int bootnor = 0; /* assume booting from NAND flash */ - - if (part_num != 0) - return 0; /* only support one partition */ - - if (part.usr_priv == (void*)1) - return ∂ /* already have part info */ - - memset(&part, 0, sizeof(part)); - - if (nand_dev_desc[0].ChipID == NAND_ChipID_UNKNOWN) - bootnor = 1; - else if (bd->bi_flashsize < 0x800000) - bootnor = 0; - else for (i = 0; !bootnor && i < 4; ++i) { - /* boot from NOR if JFFS2 info in any of - * first 4 erase blocks - */ - - if (jffs2_block(i)->magic == JFFS2_MAGIC_BITMASK) - bootnor = 1; - } - - if (bootnor) { - /* no NAND flash or boot in NOR, use NOR flash */ - part.offset = (unsigned char *)CFG_JFFS2_BASE; - part.size = CFG_JFFS2_SIZE; - } - else { - char readcmd[60]; - - /* boot info in NAND flash, get and use copy in RAM */ - - /* override info from environment if present */ - s = getenv("fsaddr"); - part.offset = s ? (void *)simple_strtoul(s, NULL, 16) - : (void *)CFG_JFFS2_RAMBASE; - s = getenv("fssize"); - part.size = s ? simple_strtoul(s, NULL, 16) - : CFG_JFFS2_RAMSIZE; - - /* read from nand flash */ - sprintf(readcmd, "nand read.jffs2 %x 0 %x", - (uint32_t)part.offset, part.size); - run_command(readcmd, 0); - } - - part.erasesize = 0; /* unused */ - part.usr_priv=(void*)1; /* ready */ - - return ∂ -} -#endif /* ifdef CFG_JFFS_CUSTOM_PART */ diff --git a/board/stxgp3/config.mk b/board/stxgp3/config.mk index 14c1f01..2427818 100644 --- a/board/stxgp3/config.mk +++ b/board/stxgp3/config.mk @@ -29,5 +29,4 @@ TEXT_BASE = 0xfff80000 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 -PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1 PLATFORM_CPPFLAGS += -DCONFIG_E500=1 diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index 5879946..dae5acb 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -78,7 +78,6 @@ SECTIONS cpu/mpc85xx/ether_fcc.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/i2c.o (.text) cpu/mpc85xx/spd_sdram.o (.text) diff --git a/board/stxxtc/Makefile b/board/stxxtc/Makefile new file mode 100644 index 0000000..8c529a0 --- /dev/null +++ b/board/stxxtc/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/stxxtc/config.mk b/board/stxxtc/config.mk new file mode 100644 index 0000000..f5dc034 --- /dev/null +++ b/board/stxxtc/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# STx XTc +# + +TEXT_BASE = 0x40F00000 diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c new file mode 100644 index 0000000..b38b4be --- /dev/null +++ b/board/stxxtc/stxxtc.c @@ -0,0 +1,638 @@ +/* + * (C) Copyright 2000-2004 + * Pantelis Antoniou, Intracom S.A., panto@intracom.gr + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2005 + * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * U-Boot port on STx XTc board + * Mostly copied from Netta + */ + +#include <common.h> +#include <miiphy.h> + +#include "mpc8xx.h" + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> +#endif + +/****************************************************************/ + +/* some sane bit macros */ +#define _BD(_b) (1U << (31-(_b))) +#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) + +#define _BW(_b) (1U << (15-(_b))) +#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1)) + +#define _BB(_b) (1U << (7-(_b))) +#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1)) + +#define _B(_b) _BD(_b) +#define _BR(_l, _h) _BDR(_l, _h) + +/****************************************************************/ + +/* + * Check Board Identity: + * + * Return 1 always. + */ + +int checkboard(void) +{ + printf ("Silicon Turnkey eXpress XTc\n"); + return (0); +} + +/****************************************************************/ + +#define _NOT_USED_ 0xFFFFFFFF + +/****************************************************************/ + +#define CS_0000 0x00000000 +#define CS_0001 0x10000000 +#define CS_0010 0x20000000 +#define CS_0011 0x30000000 +#define CS_0100 0x40000000 +#define CS_0101 0x50000000 +#define CS_0110 0x60000000 +#define CS_0111 0x70000000 +#define CS_1000 0x80000000 +#define CS_1001 0x90000000 +#define CS_1010 0xA0000000 +#define CS_1011 0xB0000000 +#define CS_1100 0xC0000000 +#define CS_1101 0xD0000000 +#define CS_1110 0xE0000000 +#define CS_1111 0xF0000000 + +#define BS_0000 0x00000000 +#define BS_0001 0x01000000 +#define BS_0010 0x02000000 +#define BS_0011 0x03000000 +#define BS_0100 0x04000000 +#define BS_0101 0x05000000 +#define BS_0110 0x06000000 +#define BS_0111 0x07000000 +#define BS_1000 0x08000000 +#define BS_1001 0x09000000 +#define BS_1010 0x0A000000 +#define BS_1011 0x0B000000 +#define BS_1100 0x0C000000 +#define BS_1101 0x0D000000 +#define BS_1110 0x0E000000 +#define BS_1111 0x0F000000 + +#define GPL0_AAAA 0x00000000 +#define GPL0_AAA0 0x00200000 +#define GPL0_AAA1 0x00300000 +#define GPL0_000A 0x00800000 +#define GPL0_0000 0x00A00000 +#define GPL0_0001 0x00B00000 +#define GPL0_111A 0x00C00000 +#define GPL0_1110 0x00E00000 +#define GPL0_1111 0x00F00000 + +#define GPL1_0000 0x00000000 +#define GPL1_0001 0x00040000 +#define GPL1_1110 0x00080000 +#define GPL1_1111 0x000C0000 + +#define GPL2_0000 0x00000000 +#define GPL2_0001 0x00010000 +#define GPL2_1110 0x00020000 +#define GPL2_1111 0x00030000 + +#define GPL3_0000 0x00000000 +#define GPL3_0001 0x00004000 +#define GPL3_1110 0x00008000 +#define GPL3_1111 0x0000C000 + +#define GPL4_0000 0x00000000 +#define GPL4_0001 0x00001000 +#define GPL4_1110 0x00002000 +#define GPL4_1111 0x00003000 + +#define GPL5_0000 0x00000000 +#define GPL5_0001 0x00000400 +#define GPL5_1110 0x00000800 +#define GPL5_1111 0x00000C00 +#define LOOP 0x00000080 + +#define EXEN 0x00000040 + +#define AMX_COL 0x00000000 +#define AMX_ROW 0x00000020 +#define AMX_MAR 0x00000030 + +#define NA 0x00000008 + +#define UTA 0x00000004 + +#define TODT 0x00000002 + +#define LAST 0x00000001 + +#define A10_AAAA GPL0_AAAA +#define A10_AAA0 GPL0_AAA0 +#define A10_AAA1 GPL0_AAA1 +#define A10_000A GPL0_000A +#define A10_0000 GPL0_0000 +#define A10_0001 GPL0_0001 +#define A10_111A GPL0_111A +#define A10_1110 GPL0_1110 +#define A10_1111 GPL0_1111 + +#define RAS_0000 GPL1_0000 +#define RAS_0001 GPL1_0001 +#define RAS_1110 GPL1_1110 +#define RAS_1111 GPL1_1111 + +#define CAS_0000 GPL2_0000 +#define CAS_0001 GPL2_0001 +#define CAS_1110 GPL2_1110 +#define CAS_1111 GPL2_1111 + +#define WE_0000 GPL3_0000 +#define WE_0001 GPL3_0001 +#define WE_1110 GPL3_1110 +#define WE_1111 GPL3_1111 + +/* #define CAS_LATENCY 3 */ +#define CAS_LATENCY 2 + +const uint sdram_table[0x40] = { + +#if CAS_LATENCY == 3 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, +#endif + +#if CAS_LATENCY == 2 + /* RSS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* RBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, + _NOT_USED_, + + /* WBS */ + CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */ + CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */ + CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */ + CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + +#endif + + /* UPT */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */ + CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA, + CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST, +}; + +static const uint nandcs_table[0x40] = { + /* RSS */ + CS_1000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1110 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111 | UTA, + CS_0000 | GPL4_0000 | GPL5_1111, + CS_0000 | GPL4_0001 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */ + + /* RBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* WSS */ + CS_1000 | GPL4_1111 | GPL5_1110 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0000 | UTA, + CS_0000 | GPL4_1111 | GPL5_0001 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111 | UTA, + CS_0000 | GPL4_1111 | GPL5_1111, + CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, + + /* WBS */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* UPT */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* EXC */ + CS_0001 | LAST, + _NOT_USED_, + + /* REG */ + CS_1110 , + CS_0001 | LAST, +}; + +/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */ +/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */ +#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) + +/* 9 */ +#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +void check_ram(unsigned int addr, unsigned int size) +{ + unsigned int i, j, v, vv; + volatile unsigned int *p; + unsigned int pv; + + p = (unsigned int *)addr; + pv = (unsigned int)p; + for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int)) + *p++ = pv; + + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + v = (unsigned int)p; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + p++; + } + + for (j = 0; j < 5; j++) { + switch (j) { + case 0: v = 0x00000000; break; + case 1: v = 0xffffffff; break; + case 2: v = 0x55555555; break; + case 3: v = 0xaaaaaaaa; break; + default:v = 0xdeadbeef; break; + } + p = (unsigned int *)addr; + for (i = 0; i < size / sizeof(unsigned int); i++) { + *p = v; + vv = *p; + if (vv != v) { + printf("%p: read %08x instead of %08x\n", p, vv, v); + hang(); + } + *p = ~v; + p++; + } + } +} + +#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0) + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size; + u32 d1, d2; + + upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0])); + + /* + * Preliminary prescaler for refresh + */ + memctl->memc_mptpr = MPTPR_PTP_DIV8; + + memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ + + /* + * Map controller bank 3 to the SDRAM bank at preliminary address. + */ + memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CFG_BR4_PRELIM; + + memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + + udelay(200); + + /* perform SDRAM initialisation sequence */ + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */ + udelay(1); + + memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/ + udelay(1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + + udelay(10000); + + + d1 = 0xAA55AA55; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x55AA55AA; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + d1 = 0x12345678; + *(volatile u32 *)0 = d1; + d2 = *(volatile u32 *)0; + if (d1 != d2) { + printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2); + DO_LOOP; + } + + size = get_ram_size((long *)0, SDRAM_MAX_SIZE); + + return size; +} + +/* ------------------------------------------------------------------------- */ + +void reset_phys(void) +{ + int phyno; + unsigned short v; + + udelay(10000); + /* reset the damn phys */ + mii_init(); + + for (phyno = 0; phyno < 32; ++phyno) { + miiphy_read(phyno, PHY_PHYIDR1, &v); + if (v == 0xFFFF) + continue; + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD); + udelay(10000); + miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON); + udelay(10000); + } +} + +/* ------------------------------------------------------------------------- */ + +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + +/* bits that can have a special purpose or can be configured as inputs/outputs */ +#define PA_GP_INMASK _BW(6) +#define PA_GP_OUTMASK (_BW(7)) +#define PA_SP_MASK 0 +#define PA_ODR_VAL 0 +#define PA_GP_OUTVAL (_BW(7)) +#define PA_SP_DIRVAL 0 + +#define PB_GP_INMASK 0 +#define PB_GP_OUTMASK (_B(23)) +#define PB_SP_MASK 0 +#define PB_ODR_VAL 0 +#define PB_GP_OUTVAL (_B(23)) +#define PB_SP_DIRVAL 0 + +#define PC_GP_INMASK 0 +#define PC_GP_OUTMASK (_BW(15)) + +#define PC_SP_MASK 0 +#define PC_SOVAL 0 +#define PC_INTVAL 0 +#define PC_GP_OUTVAL 0 +#define PC_SP_DIRVAL 0 + +#define PE_GP_INMASK 0 +#define PE_GP_OUTMASK 0 +#define PE_GP_OUTVAL 0 + +#define PE_SP_MASK 0 +#define PE_ODR_VAL 0 +#define PE_SP_DIRVAL 0 + +int board_early_init_f(void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + (void)ioport; + (void)cpm; +#if 1 + /* NAND chip select */ + upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0])); + memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS); + memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB); + memctl->memc_mbmr = 0; /* all clear */ +#endif + + memctl->memc_br5 &= ~BR_V; + memctl->memc_br6 &= ~BR_V; + memctl->memc_br7 &= ~BR_V; + +#if 1 + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + cpm->cp_pedat = PE_GP_OUTVAL; + cpm->cp_peodr = PE_ODR_VAL; + cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL; + cpm->cp_pepar = PE_SP_MASK; +#endif + + return 0; +} + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <linux/mtd/nand.h> + +extern ulong nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + unsigned long totlen; + + totlen = nand_probe(CFG_NAND_BASE); + printf ("%4lu MB\n", totlen >> 20); +} +#endif + +#ifdef CONFIG_HW_WATCHDOG + +void hw_watchdog_reset(void) +{ + /* XXX add here the really funky stuff */ +} + +#endif + +#ifdef CONFIG_SHOW_ACTIVITY + +/* called from timer interrupt every 1/CFG_HZ sec */ +void board_show_activity(ulong timestamp) +{ +} + +/* called when looping */ +void show_activity(int arg) +{ +} + +#endif + +#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +int overwrite_console(void) +{ + /* printf("overwrite_console called\n"); */ + return 0; +} +#endif + +extern int drv_phone_init(void); +extern int drv_phone_use_me(void); +extern int drv_phone_is_idle(void); + +int misc_init_r(void) +{ + return 0; +} + +int last_stage_init(void) +{ + reset_phys(); + + return 0; +} diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds new file mode 100644 index 0000000..c3dac0e --- /dev/null +++ b/board/stxxtc/u-boot.lds @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8xx/start.o (.text) + cpu/mpc8xx/traps.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + lib_ppc/cache.o (.text) + lib_ppc/time.o (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/walnut405/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug index d483424..21b7e6a 100644 --- a/board/walnut405/u-boot.lds.debug +++ b/board/stxxtc/u-boot.lds.debug @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -56,12 +56,12 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - mpc8xx/start.o (.text) - common/dlmalloc.o (.text) + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) lib_generic/vsprintf.o (.text) lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) + . = env_offset; common/environment.o(.text) *(.text) diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index 43d89b0..90275ec 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -250,6 +250,10 @@ long int initdram (int board_type) int checkboard (void) { +#if defined (CONFIG_AEVFIFO) + puts ("Board: AEVFIFO\n"); + return 0; +#endif #if defined (CONFIG_TQM5200_AA) puts ("Board: TQM5200-AA (TQ-Components GmbH)\n"); #elif defined (CONFIG_TQM5200_AB) diff --git a/board/tqm8540/u-boot.lds b/board/tqm8540/u-boot.lds index eb84aeb..ffd7562 100644 --- a/board/tqm8540/u-boot.lds +++ b/board/tqm8540/u-boot.lds @@ -70,7 +70,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/tqm8560/u-boot.lds b/board/tqm8560/u-boot.lds index 19b77be..ebe2240 100644 --- a/board/tqm8560/u-boot.lds +++ b/board/tqm8560/u-boot.lds @@ -70,7 +70,6 @@ SECTIONS cpu/mpc85xx/interrupts.o (.text) cpu/mpc85xx/cpu_init.o (.text) cpu/mpc85xx/cpu.o (.text) - cpu/mpc85xx/tsec.o (.text) cpu/mpc85xx/speed.o (.text) cpu/mpc85xx/pci.o (.text) common/dlmalloc.o (.text) diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c index 5597790..6fc68e5 100644 --- a/board/uc100/uc100.c +++ b/board/uc100/uc100.c @@ -28,6 +28,7 @@ #include <common.h> #include <mpc8xx.h> #include <i2c.h> +#include <miiphy.h> /*********************************************************************/ @@ -252,6 +253,14 @@ int misc_init_r (void) val |= 0x80; i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val); + /* + * Configure PHY to setup LED's correctly and use 100MBit, FD + */ + mii_init(); + + miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */ + miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */ + return 0; } diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile index 44be6ca..6302fa8 100644 --- a/board/voiceblue/Makefile +++ b/board/voiceblue/Makefile @@ -32,21 +32,23 @@ SOBJS := setup.o gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) LOAD_ADDR = 0x10400000 +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/eeprom.lds all: $(LIB) eeprom.srec eeprom.bin $(LIB): $(OBJS) $(SOBJS) $(AR) crv $@ $(OBJS) $(SOBJS) -eeprom.srec: eeprom.o - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \ +eeprom.srec: eeprom.o eeprom_start.o + $(LD) -T $(LDSCRIPT) -g -Ttext $(LOAD_ADDR) \ + -o $(<:.o=) -e $(<:.o=) $^ \ -L../../examples -lstubs \ -L../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ eeprom.bin: eeprom.srec - $(OBJCOPY) -O binary $< $@ 2>/dev/null + $(OBJCOPY) -I srec -O binary $< $@ 2>/dev/null clean: rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index 6383a02..0ad1b66 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -30,40 +30,6 @@ #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE -static int verify_macaddr(char *); -static int set_mac(char *); - -int eeprom(int argc, char *argv[]) -{ - app_startup(argv); - if (get_version() != XF_VERSION) { - printf("Wrong XF_VERSION.\n"); - printf("Application expects ABI version %d\n", XF_VERSION); - printf("Actual U-Boot ABI version %d\n", (int)get_version()); - return 1; - } - - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { - printf("SMSC91111 not found.\n"); - return 2; - } - - if (argc != 2) { - printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); - printf("Usage:\n\t<mac_address>"); - return 3; - } - - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - printf("*** ERROR ***\n"); - return 4; - } - - return 0; -} - static u16 read_eeprom_reg(u16 reg) { int timeout; @@ -106,17 +72,28 @@ static int write_eeprom_reg(u16 value, u16 reg) return 1; } +static int write_data(u16 *buf, int len) +{ + u16 reg = 0x23; + + while (len--) + write_eeprom_reg(*buf++, reg++); + + return 0; +} + static int verify_macaddr(char *s) { u16 reg; int i, err = 0; - printf("Verifying MAC Address: "); + printf("MAC Address: "); err = i = 0; for (i = 0; i < 3; i++) { reg = read_eeprom_reg(0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - err |= reg != ((u16 *)s)[i]; + if (s) + err |= reg != ((u16 *)s)[i]; } return err ? 0 : 1; @@ -138,3 +115,97 @@ static int set_mac(char *s) return 0; } + +static int parse_element(char *s, unsigned char *buf, int len) +{ + int cnt; + char *p, num[3]; + unsigned char id; + + id = simple_strtoul(s, &p, 16); + if (*p++ != ':') + return -1; + cnt = 2; + num[2] = 0; + for (; *p; p += 2) { + if (p[1] == 0) + return -2; + if (cnt + 3 > len) + return -3; + num[0] = p[0]; + num[1] = p[1]; + buf[cnt++] = simple_strtoul(num, NULL, 16); + } + buf[0] = id; + buf[1] = cnt - 2; + + return cnt; +} + +int eeprom(int argc, char *argv[]) +{ + int i, len, ret; + unsigned char buf[58], *p; + + app_startup(argv); + if (get_version() != XF_VERSION) { + printf("Wrong XF_VERSION.\n"); + printf("Application expects ABI version %d\n", XF_VERSION); + printf("Actual U-Boot ABI version %d\n", (int)get_version()); + return 1; + } + + if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + printf("SMSC91111 not found.\n"); + return 2; + } + + /* Called without parameters - print MAC address */ + if (argc < 2) { + verify_macaddr(NULL); + return 0; + } + + /* Print help message */ + if (argv[1][1] == 'h') { + printf("VoiceBlue EEPROM writer\n"); + printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); + return 0; + } + + /* Try to parse information elements */ + len = sizeof(buf); + p = buf; + for (i = 2; i < argc; i++) { + ret = parse_element(argv[i], p, len); + switch (ret) { + case -1: + printf("Element %d: malformed\n", i - 1); + return 3; + case -2: + printf("Element %d: odd character count\n", i - 1); + return 3; + case -3: + printf("Out of EEPROM memory\n"); + return 3; + default: + p += ret; + len -= ret; + } + } + + /* First argument (MAC) is mandatory */ + set_mac(argv[1]); + if (verify_macaddr(argv[1])) { + printf("*** MAC address does not match! ***\n"); + return 4; + } + + while (len--) + *p++ = 0; + + write_data((u16 *)buf, sizeof(buf) >> 1); + + return 0; +} diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds new file mode 100644 index 0000000..317550d --- /dev/null +++ b/board/voiceblue/eeprom.lds @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * (C) Copyright 2005 + * Ladislav Michl, 2N Telekomunikace, <michl@2n.cz> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = ALIGN(4); + .text : + { + eeprom_start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/voiceblue/eeprom_start.S b/board/voiceblue/eeprom_start.S new file mode 100644 index 0000000..8f88de5 --- /dev/null +++ b/board/voiceblue/eeprom_start.S @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2005 2N Telekomunikace + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +.globl _start +_start: b eeprom diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c index 9691106..7a2d243 100644 --- a/board/voiceblue/voiceblue.c +++ b/board/voiceblue/voiceblue.c @@ -56,90 +56,10 @@ int dram_init(void) return 0; } -#ifndef VOICEBLUE_SMALL_FLASH - -#include <jffs2/jffs2.h> - -extern flash_info_t flash_info[]; -static struct part_info partinfo; -static int current_part = -1; - -/* Partition table (Linux MTD see it this way) - * - * 0 - U-Boot - * 1 - env - * 2 - redundant env - * 3 - data1 (jffs2) - * 4 - data2 (jffs2) - */ - -static struct { - ulong offset; - ulong size; -} part[5]; - -static void partition_flash(flash_info_t *info) -{ - char mtdparts[128]; - int i, n, size, psize; - const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE }; - - size = n = 0; - for (i = 0; i < 4; i++) { - part[i].offset = info->start[n]; - psize = i < 3 ? plen[i] : (info->size - size) / 2; - while (part[i].size < psize) { - if (++n > info->sector_count) { - printf("Partitioning error. System halted.\n"); - while (1) ; - } - part[i].size += info->start[n] - info->start[n - 1]; - } - size += part[i].size; - } - part[4].offset = info->start[n]; - part[4].size = info->start[info->sector_count - 1] - info->start[n]; - - sprintf(mtdparts, "omapflash.0:" - "%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)", - part[0].size >> 10, part[1].size >> 10, - part[2].size >> 10, part[3].size >> 10); - setenv ("mtdparts", mtdparts); -} - -struct part_info* jffs2_part_info(int part_num) -{ - void *jffs2_priv_saved = partinfo.jffs2_priv; - - if (part_num != 3 && part_num != 4) - return NULL; - - if (current_part != part_num) { - memset(&partinfo, 0, sizeof(partinfo)); - current_part = part_num; - partinfo.offset = (char*) part[part_num].offset; - partinfo.size = part[part_num].size; - partinfo.usr_priv = ¤t_part; - partinfo.jffs2_priv = jffs2_priv_saved; - } - - return &partinfo; -} - -#endif - int misc_init_r(void) { *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; -#ifndef VOICEBLUE_SMALL_FLASH - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf("Unknown flash. System halted.\n"); - while (1) ; - } - partition_flash(&flash_info[0]); -#endif - return 0; } diff --git a/board/walnut405/flash.c b/board/walnut405/flash.c deleted file mode 100644 index 462c09e..0000000 --- a/board/walnut405/flash.c +++ /dev/null @@ -1,729 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Modified 4/5/2001 - * Wait for completion of each sector erase command issued - * 4/5/2001 - * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com - */ - -#include <common.h> -#include <ppc4xx.h> -#include <asm/processor.h> - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -#ifdef CONFIG_ADCIOP -#define ADDR0 0x0aa9 -#define ADDR1 0x0556 -#define FLASH_WORD_SIZE unsigned char -#endif - -#ifdef CONFIG_CPCI405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned short -#endif - -#ifdef CONFIG_WALNUT405 -#define ADDR0 0x5555 -#define ADDR1 0x2aaa -#define FLASH_WORD_SIZE unsigned char -#endif - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - unsigned long size_b0, size_b1; - int i; - uint pbcr; - unsigned long base_b0, base_b1; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) - { - /* Setup offsets */ - flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE0_PRELIM, - FLASH_BASE0_PRELIM+monitor_flash_len-1, - &flash_info[0]); - size_b1 = 0 ; - flash_info[0].size = size_b0; - } - - /* 2 banks */ - else - { - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - /* Re-do sizing to get full correct info */ - - if (size_b1) - { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); - base_b1 = -size_b1; - pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ - } - - if (size_b0) - { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); - base_b0 = base_b1 - size_b0; - pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ - } - - size_b0 = flash_get_size((vu_long *)base_b0, &flash_info[0]); - - flash_get_offsets (base_b0, &flash_info[0]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b0+size_b0-monitor_flash_len, - base_b0+size_b0-1, - &flash_info[0]); - - if (size_b1) { - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)base_b1, &flash_info[1]); - - flash_get_offsets (base_b1, &flash_info[1]); - - /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - base_b1+size_b1-monitor_flash_len, - base_b1+size_b1-1, - &flash_info[1]); - /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0+size_b0-monitor_flash_len, - base_b0+size_b0-1, - &flash_info[0]); - } else { - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - } - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - }/* else 2 banks */ - return (size_b0 + size_b1); -} - - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)){ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - int k; - int size; - int erased; - volatile unsigned long *flash; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); - break; - case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); -#if 0 /* test-only */ - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " -#else - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " " -#endif - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - FLASH_WORD_SIZE value; - ulong base = (ulong)addr; - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; - - /* Write auto select command: read Manufacturer ID */ - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; - -#ifdef CONFIG_ADCIOP - value = addr2[2]; -#else - value = addr2[0]; -#endif - - switch (value) { - case (FLASH_WORD_SIZE)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case (FLASH_WORD_SIZE)FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - case (FLASH_WORD_SIZE)SST_MANUFACT: - info->flash_id = FLASH_MAN_SST; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - -#ifdef CONFIG_ADCIOP - value = addr2[0]; /* device ID */ - /* printf("\ndev_code=%x\n", value); */ -#else - value = addr2[1]; /* device ID */ -#endif - - switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x0080000; /* => 512 ko */ - break; - case (FLASH_WORD_SIZE)AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00080000; - break; /* => 0.5 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00200000; - break; /* => 2 MB */ -#if 0 /* enable when device IDs are available */ - case (FLASH_WORD_SIZE)AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (FLASH_WORD_SIZE)AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00400000; - break; /* => 4 MB */ -#endif - case (FLASH_WORD_SIZE)SST_ID_xF800A: - info->flash_id += FLASH_SST800A; - info->sector_count = 16; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (FLASH_WORD_SIZE)SST_ID_xF160A: - info->flash_id += FLASH_SST160A; - info->sector_count = 32; - info->size = 0x00200000; - break; /* => 2 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - - /* set up sector start address table */ - if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || - (info->flash_id == FLASH_AM040)){ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * 0x00010000); - } else { - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00004000; - info->start[2] = base + 0x00006000; - info->start[3] = base + 0x00008000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00010000) - 0x00030000; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00004000; - info->start[i--] = base + info->size - 0x00006000; - info->start[i--] = base + info->size - 0x00008000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00010000; - } - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - info->protect[i] = addr2[4] & 1; -#else - addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) - info->protect[i] = 0; - else - info->protect[i] = addr2[2] & 1; -#endif - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { -#if 0 /* test-only */ -#ifdef CONFIG_ADCIOP - addr2 = (volatile unsigned char *)info->start[0]; - addr2[ADDR0] = 0xAA; - addr2[ADDR1] = 0x55; - addr2[ADDR0] = 0xF0; /* reset bank */ -#else - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif -#else /* test-only */ - addr2 = (FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ -#endif /* test-only */ - } - - return (info->size); -} - -int wait_for_DQ7(flash_info_t *info, int sect) -{ - ulong start, now, last; - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); - - start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - return 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); - volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; - int i; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); /* CLH */ - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */ - for (i=0; i<50; i++) - udelay(1000); /* wait 1 ms */ - } else { - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; - addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; - addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; - addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - } - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - -#if 0 - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - wait_for_DQ7(info, l_sect); - -DONE: -#endif - /* reset to read mode */ - addr = (FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); - volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; - volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((*((volatile FLASH_WORD_SIZE *) dest) & - (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) { - return (2); - } - - for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) { - int flag; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; - addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; - addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; - - dest2[i] = data2[i]; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - } - - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/walnut405/init.S b/board/walnut405/init.S deleted file mode 100644 index 70d029a..0000000 --- a/board/walnut405/init.S +++ /dev/null @@ -1,99 +0,0 @@ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ - -/*----------------------------------------------------------------------------- */ -/* Function: ext_bus_cntlr_init */ -/* Description: Initializes the External Bus Controller for the external */ -/* peripherals. IMPORTANT: For pass1 this code must run from */ -/* cache since you can not reliably change a peripheral banks */ -/* timing register (pbxap) while running code from that bank. */ -/* For ex., since we are running from ROM on bank 0, we can NOT */ -/* execute the code that modifies bank 0 timings from ROM, so */ -/* we run it from cache. */ -/* Bank 0 - Flash and SRAM */ -/* Bank 1 - NVRAM/RTC */ -/* Bank 2 - Keyboard/Mouse controller */ -/* Bank 3 - IR controller */ -/* Bank 4 - not used */ -/* Bank 5 - not used */ -/* Bank 6 - not used */ -/* Bank 7 - FPGA registers */ -/*----------------------------------------------------------------------------- */ -#include <ppc4xx.h> - -#include <ppc_asm.tmpl> -#include <ppc_defs.h> - -#include <asm/cache.h> -#include <asm/mmu.h> - - - .globl ext_bus_cntlr_init -ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr -..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ -..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ - - /*------------------------------------------------------------------- */ - /* Delay to ensure all accesses to ROM are complete before changing */ - /* bank 0 timings. 200usec should be enough. */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*------------------------------------------------------------------- */ - addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 -..spinlp: - bdnz ..spinlp /* spin loop */ - - /*----------------------------------------------------------------------- */ - /* Memory Bank 0 (Flash and SRAM) initialization */ - /*----------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 - addis r4,0,0x9B01 - ori r4,r4,0x5480 - mtdcr ebccfgd,r4 - - addi r4,0,pb0cr - mtdcr ebccfga,r4 - addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ - ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 - - blr - - -/*----------------------------------------------------------------------------- */ -/* Function: sdram_init */ -/* Description: Dummy implementation here - done in C later */ -/*----------------------------------------------------------------------------- */ - .globl sdram_init -sdram_init: - blr diff --git a/board/walnut405/walnut405.c b/board/walnut405/walnut405.c deleted file mode 100644 index 7035599..0000000 --- a/board/walnut405/walnut405.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include "walnut405.h" -#include <asm/processor.h> -#include <spd_sdram.h> - -int board_early_init_f (void) -{ - /*-------------------------------------------------------------------------+ - | Interrupt controller setup for the Walnut board. - | Note: IRQ 0-15 405GP internally generated; active high; level sensitive - | IRQ 16 405GP internally generated; active low; level sensitive - | IRQ 17-24 RESERVED - | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive - | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive - | IRQ 27 (EXT IRQ 2) Not Used - | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive - | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive - | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive - | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive - | Note for Walnut board: - | An interrupt taken for the FPGA (IRQ 25) indicates that either - | the Mouse, Keyboard, IRDA, or External Expansion caused the - | interrupt. The FPGA must be read to determine which device - | caused the interrupt. The default setting of the FPGA clears - | - +-------------------------------------------------------------------------*/ - - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) - /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */ - mtebc (pb1ap, 0x02815480); - mtebc (pb1cr, 0xF0018000); - - /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ - mtebc (pb2ap, 0x04815A80); - mtebc (pb2cr, 0xF0118000); - - /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */ - mtebc (pb3ap, 0x01815280); - mtebc (pb3cr, 0xF0218000); - - /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */ - mtebc (pb7ap, 0x01815280); - mtebc (pb7cr, 0xF0318000); - - /* set UART1 control to select CTS/RTS */ -#define FPGA_BRDC 0xF0300004 - *(volatile char *) (FPGA_BRDC) |= 0x1; - - return 0; -} - - -/* ------------------------------------------------------------------------- */ - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - unsigned char *s = getenv ("serial#"); - unsigned char *e; - - puts ("Board: "); - - if (!s || strncmp (s, "WALNUT405", 9)) { - puts ("### No HW ID - assuming WALNUT405"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - for (; s < e; ++s) { - putc (*s); - } - } - putc ('\n'); - - return (0); -} - - -/* ------------------------------------------------------------------------- - initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of - the necessary info for SDRAM controller configuration - ------------------------------------------------------------------------- */ -long int initdram (int board_type) -{ - return spd_sdram (0); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: xxx MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/walnut405/walnut405.h b/board/walnut405/walnut405.h deleted file mode 100644 index 5fc313a..0000000 --- a/board/walnut405/walnut405.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/**************************************************************************** - * FLASH Memory Map as used by TQ Monitor: - * - * Start Address Length - * +-----------------------+ 0x4000_0000 Start of Flash ----------------- - * | MON8xx code | 0x4000_0100 Reset Vector - * +-----------------------+ 0x400?_???? - * | (unused) | - * +-----------------------+ 0x4001_FF00 - * | Ethernet Addresses | 0x78 - * +-----------------------+ 0x4001_FF78 - * | (Reserved for MON8xx) | 0x44 - * +-----------------------+ 0x4001_FFBC - * | Lock Address | 0x04 - * +-----------------------+ 0x4001_FFC0 ^ - * | Hardware Information | 0x40 | MON8xx - * +=======================+ 0x4002_0000 (sector border) ----------------- - * | Autostart Header | | Applications - * | ... | v - * - *****************************************************************************/ diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c index bfa287b..3f93700 100644 --- a/board/xsengine/flash.c +++ b/board/xsengine/flash.c @@ -27,10 +27,6 @@ #include <common.h> #include <linux/byteorder/swab.h> -#if defined CFG_JFFS_CUSTOM_PART -#include <jffs2/jffs2.h> -#endif - #define SWAP(x) __swab32(x) flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -40,80 +36,6 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); static void flash_get_offsets (ulong base, flash_info_t *info); -#if defined CFG_JFFS_CUSTOM_PART - -/* - * jffs2_part_info - get information about a JFFS2 partition - * - * @part_num: number of the partition you want to get info about - * @return: struct part_info* in case of success, 0 if failure - */ - -static struct part_info part; -static int current_part = -1; - -struct part_info* jffs2_part_info(int part_num) { - void *jffs2_priv_saved = part.jffs2_priv; - - printf("jffs2_part_info: part_num=%i\n",part_num); - - if (current_part == part_num) - return ∂ - - /* u-boot partition */ - if(part_num==0){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00000000; - part.size=256*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - printf("part.offset = 0x%08x\n",(unsigned int)part.offset); - printf("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* primary OS+firmware partition */ - if(part_num==1){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00040000; - part.size=1024*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - printf("part.offset = 0x%08x\n",(unsigned int)part.offset); - printf("part.size = 0x%08x\n",(unsigned int)part.size); - } - - /* secondary OS+firmware partition */ - if(part_num==2){ - memset(&part, 0, sizeof(part)); - - part.offset=(char*)0x00140000; - part.size=8*1024*1024; - - /* Mark the struct as ready */ - current_part = part_num; - - printf("part.offset = 0x%08x\n",(unsigned int)part.offset); - printf("part.size = 0x%08x\n",(unsigned int)part.size); - } - - if (current_part == part_num) { - part.usr_priv = ¤t_part; - part.jffs2_priv = jffs2_priv_saved; - return ∂ - } - - printf("jffs2_part_info: end of partition table\n"); - return 0; -} -#endif - - /*----------------------------------------------------------------------- */ unsigned long flash_init (void) |