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-rw-r--r--board/gth2/Makefile41
-rw-r--r--board/gth2/config.mk42
-rw-r--r--board/gth2/ee_access.c347
-rw-r--r--board/gth2/ee_access.h30
-rw-r--r--board/gth2/ee_dev.h96
-rw-r--r--board/gth2/flash.c43
-rw-r--r--board/gth2/gth2.c435
-rw-r--r--board/gth2/lowlevel_init.S454
-rw-r--r--board/gth2/u-boot.lds68
-rw-r--r--board/mcc200/mcc200.c8
-rw-r--r--board/mcc200/mt48lc16m32s2-75.h43
-rw-r--r--board/ppmc7xx/Makefile47
-rw-r--r--board/ppmc7xx/config.mk33
-rw-r--r--board/ppmc7xx/flash.c494
-rw-r--r--board/ppmc7xx/init.S336
-rw-r--r--board/ppmc7xx/pci.c97
-rw-r--r--board/ppmc7xx/ppmc7xx.c104
-rw-r--r--board/ppmc7xx/u-boot.lds135
-rw-r--r--board/tqm5200/Makefile1
-rw-r--r--board/tqm5200/flash.c497
-rw-r--r--board/tqm5200/tqm5200.c20
-rw-r--r--board/tqm834x/tqm834x.c24
-rw-r--r--board/tqm85xx/tqm85xx.c14
-rw-r--r--board/trab/cmd_trab.c1
-rw-r--r--board/trab/trab.c13
-rw-r--r--board/trab/tsc2000.c2
-rw-r--r--board/trab/vfd.c6
-rw-r--r--board/voiceblue/config.mk2
28 files changed, 2913 insertions, 520 deletions
diff --git a/board/gth2/Makefile b/board/gth2/Makefile
new file mode 100644
index 0000000..8ef3a51
--- /dev/null
+++ b/board/gth2/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o ee_access.o
+SOBJS = lowlevel_init.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/board/gth2/config.mk b/board/gth2/config.mk
new file mode 100644
index 0000000..6d21ba1
--- /dev/null
+++ b/board/gth2/config.mk
@@ -0,0 +1,42 @@
+#
+# (C) Copyright 2004-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD Alchemy AU1000, MIPS32 core
+#
+
+ifeq ($(TBASE),0)
+TEXT_BASE = 0
+else
+ifeq ($(TBASE),1)
+TEXT_BASE = 0xbfc10070
+else
+ifeq ($(TBASE),2)
+TEXT_BASE = 0xbfc30070
+else
+## Only to make ordinary make work
+TEXT_BASE = 0x90000000
+endif
+endif
+endif
+
diff --git a/board/gth2/ee_access.c b/board/gth2/ee_access.c
new file mode 100644
index 0000000..e293139
--- /dev/null
+++ b/board/gth2/ee_access.c
@@ -0,0 +1,347 @@
+/* Module for handling DALLAS DS2438, smart battery monitor
+ Chip can store up to 40 bytes of user data in EEPROM,
+ perform temp, voltage and current measurements.
+ Chip also contains a unique serial number.
+
+ Always read/write LSb first
+
+ For documentaion, see data sheet for DS2438, 2438.pdf
+
+ By Thomas.Lange@corelatus.com 001025
+
+ Copyright (C) 2000-2005 Corelatus AB */
+
+/* This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/io.h>
+#include "ee_dev.h"
+#include "ee_access.h"
+
+/* static int Debug = 1; */
+#undef E_DEBUG
+#define E_DEBUG(fmt,args...) /* */
+/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
+
+/* We dont have kernel functions */
+#define printk printf
+#define KERN_DEBUG
+#define KERN_ERR
+#define EIO 1
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
+
+static u8 crc_lookup[256] = {
+ 0, 94, 188, 226, 97, 63, 221, 131,
+ 194, 156, 126, 32, 163, 253, 31, 65,
+ 157, 195, 33, 127, 252, 162, 64, 30,
+ 95, 1, 227, 189, 62, 96, 130, 220,
+ 35, 125, 159, 193, 66, 28, 254, 160,
+ 225, 191, 93, 3, 128, 222, 60, 98,
+ 190, 224, 2, 92, 223, 129, 99, 61,
+ 124, 34, 192, 158, 29, 67, 161, 255,
+ 70, 24, 250, 164, 39, 121, 155, 197,
+ 132, 218, 56, 102, 229, 187, 89, 7,
+ 219, 133, 103, 57, 186, 228, 6, 88,
+ 25, 71, 165, 251, 120, 38, 196, 154,
+ 101, 59, 217, 135, 4, 90, 184, 230,
+ 167, 249, 27, 69, 198, 152, 122, 36,
+ 248, 166, 68, 26, 153, 199, 37, 123,
+ 58, 100, 134, 216, 91, 5, 231, 185,
+ 140, 210, 48, 110, 237, 179, 81, 15,
+ 78, 16, 242, 172, 47, 113, 147, 205,
+ 17, 79, 173, 243, 112, 46, 204, 146,
+ 211, 141, 111, 49, 178, 236, 14, 80,
+ 175, 241, 19, 77, 206, 144, 114, 44,
+ 109, 51, 209, 143, 12, 82, 176, 238,
+ 50, 108, 142, 208, 83, 13, 239, 177,
+ 240, 174, 76, 18, 145, 207, 45, 115,
+ 202, 148, 118, 40, 171, 245, 23, 73,
+ 8, 86, 180, 234, 105, 55, 213, 139,
+ 87, 9, 235, 181, 54, 104, 138, 212,
+ 149, 203, 41, 119, 244, 170, 72, 22,
+ 233, 183, 85, 11, 136, 214, 52, 106,
+ 43, 117, 151, 201, 74, 20, 246, 168,
+ 116, 42, 200, 150, 21, 75, 169, 247,
+ 182, 232, 10, 84, 215, 137, 107, 53
+};
+
+static void
+write_gpio_data(int value ){
+ if(value){
+ /* Tristate */
+ gpio_tristate(GPIO_EEDQ);
+ }
+ else{
+ /* Drive 0 */
+ gpio_clear(GPIO_EEDQ);
+ }
+}
+
+static u8 make_new_crc( u8 Old_crc, u8 New_value ){
+ /* Compute a new checksum with new byte, using previous checksum as input
+ See DS app note 17, understanding and using cyclic redundancy checks...
+ Also see DS2438, page 11 */
+ return( crc_lookup[Old_crc ^ New_value ]);
+}
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
+ /* Check if the checksum for this buffer is correct */
+ u8 Curr_crc=0;
+ int i;
+ u8 *Curr_byte = Buffer;
+
+ for(i=0;i<Len;i++){
+ Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
+ Curr_byte++;
+ }
+ E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+
+ if(Curr_crc == Crc){
+ /* Good */
+ return(TRUE);
+ }
+ printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
+ return(FALSE);
+}
+
+static void
+set_idle(void){
+ /* Send idle and keep start time
+ Continous 1 is idle */
+ WRITE_PORT(1);
+}
+
+
+static int
+do_cpu_reset(void){
+ /* Release reset and verify that chip responds with presence pulse */
+ int Retries=0;
+ while(Retries<15){
+ udelay(RESET_LOW_TIME);
+
+ /* Send reset */
+ WRITE_PORT(0);
+ udelay(RESET_LOW_TIME);
+
+ /* Release reset */
+ WRITE_PORT(1);
+
+ /* Wait for EEPROM to drive output */
+ udelay(PRESENCE_TIMEOUT);
+ if(!READ_PORT){
+ /* Ok, EEPROM is driving a 0 */
+ E_DEBUG("Presence detected\n");
+ if(Retries){
+ E_DEBUG("Retries %d\n",Retries);
+ }
+ /* Make sure chip releases pin */
+ udelay(PRESENCE_LOW_TIME);
+ return 0;
+ }
+ Retries++;
+ }
+
+ printk(KERN_ERR"eeprom did not respond when releasing reset\n");
+
+ /* Make sure chip releases pin */
+ udelay(PRESENCE_LOW_TIME);
+
+ /* Set to idle again */
+ set_idle();
+
+ return(-EIO);
+}
+
+static u8
+read_cpu_byte(void){
+ /* Read a single byte from EEPROM
+ Read LSb first */
+ int i;
+ int Value;
+ u8 Result=0;
+ u32 Flags;
+
+ E_DEBUG("Reading byte\n");
+
+ for(i=0;i<8;i++){
+ /* Small delay between pulses */
+ udelay(1);
+
+#ifdef __KERNEL__
+ /* Disable irq */
+ save_flags(Flags);
+ cli();
+#endif
+
+ /* Pull down pin short time to start read
+ See page 26 in data sheet */
+
+ WRITE_PORT(0);
+ udelay(READ_LOW);
+ WRITE_PORT(1);
+
+ /* Wait for chip to drive pin */
+ udelay(READ_TIMEOUT);
+
+ Value = READ_PORT;
+ if(Value)
+ Value=1;
+
+#ifdef __KERNEL__
+ /* Enable irq */
+ restore_flags(Flags);
+#endif
+
+ /* Wait for chip to release pin */
+ udelay(TOTAL_READ_LOW-READ_TIMEOUT);
+
+ /* LSb first */
+ Result|=Value<<i;
+ /* E_DEBUG("Read %d\n",Value); */
+
+ }
+
+ E_DEBUG("Read byte 0x%x\n",Result);
+
+ return(Result);
+}
+
+static void
+write_cpu_byte(u8 Byte){
+ /* Write a single byte to EEPROM
+ Write LSb first */
+ int i;
+ int Value;
+ u32 Flags;
+
+ E_DEBUG("Writing byte 0x%x\n",Byte);
+
+ for(i=0;i<8;i++){
+ /* Small delay between pulses */
+ udelay(1);
+ Value = Byte&1;
+
+#ifdef __KERNEL__
+ /* Disable irq */
+ save_flags(Flags);
+ cli();
+#endif
+
+ /* Pull down pin short time for a 1, long time for a 0
+ See page 26 in data sheet */
+
+ WRITE_PORT(0);
+ if(Value){
+ /* Write a 1 */
+ udelay(WRITE_1_LOW);
+ }
+ else{
+ /* Write a 0 */
+ udelay(WRITE_0_LOW);
+ }
+
+ WRITE_PORT(1);
+
+#ifdef __KERNEL__
+ /* Enable irq */
+ restore_flags(Flags);
+#endif
+
+ if(Value)
+ /* Wait for chip to read the 1 */
+ udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
+
+ /* E_DEBUG("Wrote %d\n",Value); */
+ Byte>>=1;
+ }
+}
+
+int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
+ /* Execute this command string, including
+ giving reset and setting to idle after command
+ if Rx_len is set, we read out data from EEPROM */
+ int i;
+
+ E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
+
+ if(do_cpu_reset()){
+ /* Failed! */
+ return(-EIO);
+ }
+
+ if(Send_skip)
+ /* Always send SKIP_ROM first to tell chip we are sending a command,
+ except when we read out rom data for chip */
+ write_cpu_byte(SKIP_ROM);
+
+ /* Always have Tx data */
+ for(i=0;i<Tx_len;i++){
+ write_cpu_byte(Tx[i]);
+ }
+
+ if(Rx_len){
+ for(i=0;i<Rx_len;i++){
+ Rx[i]=read_cpu_byte();
+ }
+ }
+
+ set_idle();
+
+ E_DEBUG("Command done\n");
+
+ return(0);
+}
+
+int ee_init_cpu_data(void){
+ int i;
+ u8 Tx[10];
+
+ /* Leave it floting since altera is driving the same pin */
+ set_idle();
+
+ /* Copy all User EEPROM data to scratchpad */
+ for(i=0;i<USER_PAGES;i++){
+ Tx[0]=RECALL_MEMORY;
+ Tx[1]=EE_USER_PAGE_0+i;
+ if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+ }
+
+ /* Make sure chip doesnt store measurements in NVRAM */
+ Tx[0]=WRITE_SCRATCHPAD;
+ Tx[1]=0; /* Page */
+ Tx[2]=9;
+ if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
+
+ Tx[0]=COPY_SCRATCHPAD;
+ if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
+
+ for(i=0;i<10;i++){
+ udelay(1000);
+ }
+
+ return(0);
+}
diff --git a/board/gth2/ee_access.h b/board/gth2/ee_access.h
new file mode 100644
index 0000000..c21730e
--- /dev/null
+++ b/board/gth2/ee_access.h
@@ -0,0 +1,30 @@
+/* By Thomas.Lange@Corelatus.com 001025 */
+
+/* Definitions for EEPROM/VOLT METER DS2438 */
+/* Copyright (C) 2000-2005 Corelatus AB */
+
+#ifndef INCeeaccessh
+#define INCeeaccessh
+
+#include <asm/types.h>
+#include "ee_dev.h"
+
+int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
+int ee_init_cpu_data(void);
+
+int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
+
+/* Defs for altera reg */
+#define EE_WRITE_SHIFT 8 /* bits to shift left */
+#define EE_READ_SHIFT 16 /* bits to shift left */
+#define EE_DONE 0x80000000
+#define EE_BUSY 0x40000000
+#define EE_ERROR 0x20000000
+
+/* Commands */
+#define EE_CMD_NOP 0
+#define EE_CMD_INIT_RES 1
+#define EE_CMD_WR_BYTE 2
+#define EE_CMD_RD_BYTE 3
+
+#endif /* INCeeaccessh */
diff --git a/board/gth2/ee_dev.h b/board/gth2/ee_dev.h
new file mode 100644
index 0000000..acc3418
--- /dev/null
+++ b/board/gth2/ee_dev.h
@@ -0,0 +1,96 @@
+/* By Thomas.Lange@Corelatus.com 001025 */
+/* Definitions for EEPROM/VOLT METER DS2438 */
+/* Copyright (C) 2000-2005 Corelatus AB */
+
+/* This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef INCeedevh
+#define INCeedevh
+
+#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
+
+/* MIPS */
+#define WRITE_PORT(Value) write_gpio_data(Value)
+
+#define READ_PORT (gpio_read()&GPIO_EEDQ)
+
+/* 64 bytes chip */
+#define EE_CHIP_SIZE 64
+
+/* Board with new current resistor */
+#define EE_GTH_0304 1
+
+/* new dsp and 64 MB SDRAM */
+#define EE_DSP_64 0x10
+
+/* microsecs */
+/* Pull line down at least this long for reset pulse */
+#define RESET_LOW_TIME 490
+
+/* Read presence pulse after we release reset pulse */
+#define PRESENCE_TIMEOUT 100
+#define PRESENCE_LOW_TIME 200
+
+#define WRITE_0_LOW 60
+#define WRITE_1_LOW 1
+#define TOTAL_WRITE_LOW 60
+
+#define READ_LOW 1
+#define READ_TIMEOUT 10
+#define TOTAL_READ_LOW 70
+
+/* Rom function commands */
+#define READ_ROM 0x33
+#define MATCH_ROM 0x55
+#define SKIP_ROM 0xCC
+#define SEARCH_ROM 0xF0
+
+
+/* Memory_command_function */
+#define WRITE_SCRATCHPAD 0x4E
+#define READ_SCRATCHPAD 0xBE
+#define COPY_SCRATCHPAD 0x48
+#define RECALL_MEMORY 0xB8
+#define CONVERT_TEMP 0x44
+#define CONVERT_VOLTAGE 0xB4
+
+/* Chip is divided in 8 pages, 8 bytes each */
+
+#define EE_PAGE_SIZE 8
+
+/* All chip data we want are in page 0 */
+
+/* Bytes in page 0 */
+#define EE_P0_STATUS 0
+#define EE_P0_TEMP_LSB 1
+#define EE_P0_TEMP_MSB 2
+#define EE_P0_VOLT_LSB 3
+#define EE_P0_VOLT_MSB 4
+#define EE_P0_CURRENT_LSB 5
+#define EE_P0_CURRENT_MSB 6
+
+
+/* 40 byte user data is located at page 3-7 */
+#define EE_USER_PAGE_0 3
+#define USER_PAGES 5
+
+/* Layout of gth user pages usage */
+/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
+
+#define EE_ETHERNET_OFFSET 0
+
+#endif /* INCeedevh */
diff --git a/board/gth2/flash.c b/board/gth2/flash.c
new file mode 100644
index 0000000..f96edff
--- /dev/null
+++ b/board/gth2/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+ printf ("Skipping flash_init\n");
+ return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ printf ("write_buff not implemented\n");
+ return (-1);
+}
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
new file mode 100644
index 0000000..77fc5b4
--- /dev/null
+++ b/board/gth2/gth2.c
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2005
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/addrspace.h>
+#include <asm/mipsregs.h>
+#include <watchdog.h>
+
+#include "ee_access.h"
+
+static int wdi_status = 0;
+
+unsigned long mips_io_port_base = 0;
+
+#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
+
+
+#define SERIAL_LOG_BUFFER KSEG1ADDR(SDRAM_SIZE + (8*4096))
+
+void inline log_serial_char(char c){
+ char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
+ int serial_log_offset;
+ u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
+
+ serial_log_offset = *serial_log_offsetp;
+
+ *(serial_log_buffer + serial_log_offset) = c;
+
+ serial_log_offset++;
+
+ if(serial_log_offset >= 4096){
+ serial_log_offset = 4;
+ }
+ *serial_log_offsetp = serial_log_offset;
+}
+
+void init_log_serial(void){
+ char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
+ u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
+
+ /* Copy buffer from last run */
+ memcpy(serial_log_buffer + 4096,
+ serial_log_buffer,
+ 4096);
+
+ memset(serial_log_buffer, 0, 4096);
+
+ *serial_log_offsetp = 4;
+}
+
+
+void hw_watchdog_reset(void){
+ volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+ volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
+ if(wdi_status){
+ *sys_outputset = GPIO_CPU_LED|GPIO_WDI;
+ wdi_status = 0;
+ }
+ else{
+ *sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
+ wdi_status = 1;
+ }
+}
+
+long int initdram(int board_type)
+{
+ /* Sdram is setup by assembler code */
+ /* If memory could be changed, we should return the true value here */
+
+ WATCHDOG_RESET();
+
+ return (SDRAM_SIZE);
+}
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+void set_ledcard(u32 value){
+ /* Clock 24 bits to led card */
+ int i;
+ volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+ volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
+
+ /* Start with known values */
+ *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
+
+ for(i=0;i<24;i++){
+ if(value&0x00800000){
+ *sys_outputset = GPIO_LEDD;
+ }
+ else{
+ *sys_outputclr = GPIO_LEDD;
+ }
+ udelay(1);
+ *sys_outputset = GPIO_LEDCLK;
+ udelay(1);
+ *sys_outputclr = GPIO_LEDCLK;
+ udelay(1);
+
+ value<<=1;
+ }
+ /* Data is enable output */
+ *sys_outputset = GPIO_LEDD;
+}
+
+int checkboard (void)
+{
+ volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+ volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
+ volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
+ u32 proc_id;
+
+ WATCHDOG_RESET();
+
+ *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+ proc_id = read_32bit_cp0_register(CP0_PRID);
+
+ switch (proc_id >> 24) {
+ case 0:
+ puts ("Board: GTH2\n");
+ printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
+ (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+ break;
+ default:
+ printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+ }
+#ifdef CONFIG_IDE_PCMCIA
+ /* PCMCIA is on a 36 bit physical address.
+ We need to map it into a 32 bit addresses */
+ write_one_tlb(20, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_IO_BASE, /* Hi */
+ 0x3C000017, /* Lo0 */
+ 0x3C200017); /* Lo1 */
+
+ write_one_tlb(21, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_ATTR_BASE, /* Hi */
+ 0x3D000017, /* Lo0 */
+ 0x3D200017); /* Lo1 */
+
+ write_one_tlb(22, /* index */
+ 0x01ffe000, /* Pagemask, 16 MB pages */
+ CFG_PCMCIA_MEM_ADDR, /* Hi */
+ 0x3E000017, /* Lo0 */
+ 0x3E200017); /* Lo1 */
+
+#endif /* CONFIG_IDE_PCMCIA */
+
+ /* Wait for GPIO ports to become stable */
+ udelay(5000); /* FIXME */
+
+ /* Release reset of ethernet PHY chips */
+ /* Always do this, because linux does not know about it */
+ *sys_outputset = GPIO_ERESET;
+
+ /* Kill FPGA:s */
+ *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
+ udelay(2);
+ *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
+
+ /* Turn front led yellow */
+ set_ledcard(0x00100000);
+
+ return 0;
+}
+
+#define POWER_OFFSET 0xF0000
+#define SW_WATCHDOG_REASON 13
+
+#define BOOTDATA_OFFSET 0xF8000
+#define MAX_ATTEMPTS 5
+
+#define FAILSAFE_BOOT 1
+#define SYSTEM_BOOT 2
+#define SYSTEM2_BOOT 3
+
+#define WRITE_FLASH16(a, d) \
+do \
+{ \
+ *((volatile u16 *) (a)) = (d);\
+ } while(0)
+
+static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
+{
+ u16 data;
+ volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+
+ switch(System){
+ case FAILSAFE_BOOT:
+ printf ("Setting failsafe boot in flash\n");
+ break;
+ case SYSTEM_BOOT:
+ printf ("Setting system boot in flash\n");
+ break;
+ case SYSTEM2_BOOT:
+ printf ("Setting system2 boot in flash\n");
+ break;
+ default:
+ printf ("Invalid system data %u, setting failsafe\n", System);
+ System = FAILSAFE_BOOT;
+ }
+
+ if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
+ printf ("Invalid boot count %u, setting 1\n", Count);
+ Count = 1;
+ }
+
+ printf ("Boot attempt %d\n", Count);
+
+ data = (System << 8) | Count;
+ /* AMD 16 bit */
+ WRITE_FLASH16 (&flash[0x555], 0xAAAA);
+ WRITE_FLASH16 (&flash[0x2AA], 0x5555);
+ WRITE_FLASH16 (&flash[0x555], 0xA0A0);
+
+ WRITE_FLASH16 (addr, data);
+}
+
+static int random_system(void){
+ /* EEPROM read failed. Just try to choose one
+ system release and hope it works */
+
+ /* FIXME */
+ return(SYSTEM_BOOT);
+}
+
+static int switch_system(int old_system){
+ u8 Rx[10];
+ u8 Tx[5];
+ int valid_release;
+
+ if(old_system==FAILSAFE_BOOT){
+ /* Find out which system release to use */
+
+ /* Copy from nvram to scratchpad */
+ Tx[0] = RECALL_MEMORY;
+ Tx[1] = 7; /* Page */
+ if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
+ printf ("EE user page 7 recall failed\n");
+ return (random_system());
+ }
+
+ Tx[0] = READ_SCRATCHPAD;
+ if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
+ printf ("EE user page 7 read failed\n");
+ return (random_system());
+ }
+ /* Crc in 9:th byte */
+ if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
+ printf ("EE read failed, page 7. CRC error\n");
+ return (random_system());
+ }
+
+ valid_release = Rx[7];
+ if((valid_release==0xFF)|
+ ((valid_release&1) == 0)){
+ return(SYSTEM_BOOT);
+ }
+ else{
+ return(SYSTEM2_BOOT);
+ }
+ }
+ else{
+ return(FAILSAFE_BOOT);
+ }
+}
+
+static void check_boot_tries (void)
+{
+ /* Count the number of boot attemps
+ switch system if too many */
+
+ int i;
+ volatile u16 *addr;
+ volatile u16 data;
+ u8 system = FAILSAFE_BOOT;
+ u8 count;
+
+ addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
+
+ if (*addr == 0xFFFF) {
+ printf ("*** No bootdata exists. ***\n");
+ write_bootdata (addr, FAILSAFE_BOOT, 1);
+ } else {
+ /* Search for latest written bootdata */
+ i = 0;
+ while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
+ addr++;
+ i++;
+ }
+ if (i >= 8000) {
+ /* Whoa, dont write any more */
+ printf ("*** No bootdata found. Not updating flash***\n");
+ } else {
+ /* See how many times we have tried to boot real system */
+ data = *addr;
+ system = data >> 8;
+ count = data & 0xFF;
+ if ((system != SYSTEM_BOOT) &
+ (system != SYSTEM2_BOOT) &
+ (system != FAILSAFE_BOOT)) {
+ printf ("*** Wrong system %d\n", system);
+ system = FAILSAFE_BOOT;
+ count = 1;
+ } else {
+ switch (count) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ /* Try same system again if needed */
+ count++;
+ break;
+
+ case 5:
+ /* Switch system and reset tries */
+ count = 1;
+ system = switch_system(system);
+ printf ("***Too many boot attempts, switching system***\n");
+ break;
+ default:
+ /* Switch system, start over and hope it works */
+ printf ("***Unexpected data on addr 0x%x, %u***\n",
+ (u32) addr, data);
+ count = 1;
+ system = switch_system(system);
+ }
+ }
+ write_bootdata (addr + 1, system, count);
+ }
+ }
+ switch(system){
+ case FAILSAFE_BOOT:
+ printf ("Booting failsafe system\n");
+ setenv ("bootargs", "panic=1 root=/dev/hda7");
+ setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
+ break;
+
+ case SYSTEM_BOOT:
+ printf ("Using normal system\n");
+ setenv ("bootargs", "panic=1 root=/dev/hda4");
+ setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
+ break;
+
+ case SYSTEM2_BOOT:
+ printf ("Using normal system2\n");
+ setenv ("bootargs", "panic=1 root=/dev/hda9");
+ setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
+ break;
+ default:
+ printf ("Invalid system %d\n", system);
+ printf ("Hanging\n");
+ while(1);
+ }
+}
+
+int misc_init_r(void){
+ u8 Rx[80];
+ u8 Tx[5];
+ int page;
+ int read = 0;
+
+ WATCHDOG_RESET();
+
+ if (ee_init_cpu_data ()) {
+ printf ("EEPROM init failed\n");
+ return (0);
+ }
+
+ /* Check which release to boot */
+ check_boot_tries ();
+
+ /* Read the pages where ethernet address is stored */
+
+ for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
+ /* Copy from nvram to scratchpad */
+ Tx[0] = RECALL_MEMORY;
+ Tx[1] = page;
+ if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
+ printf ("EE user page %d recall failed\n", page);
+ return (0);
+ }
+
+ Tx[0] = READ_SCRATCHPAD;
+ if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
+ printf ("EE user page %d read failed\n", page);
+ return (0);
+ }
+ /* Crc in 9:th byte */
+ if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
+ printf ("EE read failed, page %d. CRC error\n", page);
+ return (0);
+ }
+ read += 8;
+ }
+
+ /* Add eos after eth addr */
+ Rx[17] = 0;
+
+ printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
+
+ if ((Rx[2] != ':') |
+ (Rx[5] != ':') |
+ (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
+ printf ("*** ethernet addr invalid, using default ***\n");
+ } else {
+ setenv ("ethaddr", Rx);
+ }
+ return (0);
+}
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
new file mode 100644
index 0000000..62e3657
--- /dev/null
+++ b/board/gth2/lowlevel_init.S
@@ -0,0 +1,454 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define CP0_Config0 $16
+#define MEM_1MS ((CFG_MHZ) * 1000)
+#define GPIO_RJ1LY (1<<22)
+#define GPIO_CFRESET (1<<10)
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /*
+ * Step 2) Establish Status Register
+ * (set BEV, clear ERL, clear EXL, clear IE)
+ */
+ li t1, 0x00400000
+ mtc0 t1, CP0_STATUS
+
+ /*
+ * Step 3) Establish CP0 Config0
+ * (set OD, set K0=3)
+ */
+ li t1, 0x00080003
+ mtc0 t1, CP0_CONFIG
+
+ /*
+ * Step 4) Disable Watchpoint facilities
+ */
+ li t1, 0x00000000
+ mtc0 t1, CP0_WATCHLO
+ mtc0 t1, CP0_IWATCHLO
+ /*
+ * Step 5) Disable the performance counters
+ */
+ mtc0 zero, CP0_PERFORMANCE
+ nop
+
+ /*
+ * Step 6) Establish EJTAG Debug register
+ */
+ mtc0 zero, CP0_DEBUG
+ nop
+
+ /*
+ * Step 7) Establish Cause
+ * (set IV bit)
+ */
+ li t1, 0x00800000
+ mtc0 t1, CP0_CAUSE
+
+ /* Establish Wired (and Random) */
+ mtc0 zero, CP0_WIRED
+ nop
+
+ /* No workaround if running from ram */
+ lui t0, 0xffc0
+ lui t3, 0xbfc0
+ and t1, ra, t0
+ bne t1, t3, noCacheJump
+ nop
+
+ /*** From AMD YAMON ***/
+ /*
+ * Step 8) Initialize the caches
+ */
+ li t0, (16*1024)
+ li t1, 32
+ li t2, 0x80000000
+ addu t3, t0, t2
+cacheloop:
+ cache 0, 0(t2)
+ cache 1, 0(t2)
+ addu t2, t1
+ bne t2, t3, cacheloop
+ nop
+
+ /* Save return address */
+ move t3, ra
+
+ /* Run from cacheable space now */
+ bal cachehere
+ nop
+cachehere:
+ li t1, ~0x20000000 /* convert to KSEG0 */
+ and t0, ra, t1
+ addi t0, 5*4 /* 5 insns beyond cachehere */
+ jr t0
+ nop
+
+ /* Restore return address */
+ move ra, t3
+
+ /*
+ * Step 9) Initialize the TLB
+ */
+ li t0, 0 # index value
+ li t1, 0x00000000 # entryhi value
+ li t2, 32 # 32 entries
+
+tlbloop:
+ /* Probe TLB for matching EntryHi */
+ mtc0 t1, CP0_ENTRYHI
+ tlbp
+ nop
+
+ /* Examine Index[P], 1=no matching entry */
+ mfc0 t3, CP0_INDEX
+ li t4, 0x80000000
+ and t3, t4, t3
+ addiu t1, t1, 1 # increment t1 (asid)
+ beq zero, t3, tlbloop
+ nop
+
+ /* Initialize the TLB entry */
+ mtc0 t0, CP0_INDEX
+ mtc0 zero, CP0_ENTRYLO0
+ mtc0 zero, CP0_ENTRYLO1
+ mtc0 zero, CP0_PAGEMASK
+ tlbwi
+
+ /* Do it again */
+ addiu t0, t0, 1
+ bne t0, t2, tlbloop
+ nop
+
+ /* First setup pll:s to make serial work ok */
+ /* We have a 12.5 MHz crystal */
+ li t0, SYS_CPUPLL
+ li t1, 0x28 /* CPU clock, 500 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
+ nop
+
+ /* wait 1mS for clocks to settle */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+ /* Setup AUX PLL */
+ li t0, SYS_AUXPLL
+ li t1, 0
+ sw t1, 0(t0) /* aux pll */
+ sync
+
+ /* Static memory controller */
+ /* RCE0 - can not change while fetching, do so from icache */
+ move t2, ra /* Store return address */
+ bal getAddr
+ nop
+
+getAddr:
+ move t1, ra
+ move ra, t2 /* Move return addess back */
+
+ cache 0x14,0(t1)
+ cache 0x14,32(t1)
+ /*** /From YAMON ***/
+
+noCacheJump:
+
+ /* Static memory controller */
+
+ /* RCE0 AMD 29LV800 Flash */
+ li t0, MEM_STCFG0
+ li t1, 0x00000243
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME0
+ li t1, 0x040181D7 /* FIXME */
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR0
+ li t1, 0x11E03F80
+ sw t1, 0(t0)
+
+ /* RCE1 PCMCIA 250ns */
+ li t0, MEM_STCFG1
+ li t1, 0x00000002
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME1
+ li t1, 0x280E3E07
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR1
+ li t1, 0x10000000
+ sw t1, 0(t0)
+
+ /* RCE2 CP Altera */
+ li t0, MEM_STCFG2
+ li t1, 0x00000280 /* BE, EW */
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME2
+ li t1, 0x0303000c
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR2
+ li t1, 0x10c03f80 /* 1 MB */
+ sw t1, 0(t0)
+
+ /* RCE3 DP Altera */
+ li t0, MEM_STCFG3
+ li t1, 0x00000280 /* BE, EW */
+ sw t1, 0(t0)
+
+ li t0, MEM_STTIME3
+ li t1, 0x0303000c
+ sw t1, 0(t0)
+
+ li t0, MEM_STADDR3
+ li t1, 0x10e03f80 /* 1 MB */
+ sw t1, 0(t0)
+
+ sync
+
+ /* Set peripherals to a known state */
+ li t0, IC0_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC0_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC0_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC0_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC0_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC0_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, IC1_CFG0CLR
+ li t1, 0xFFFFFFFF
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG0CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG1CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_CFG2CLR
+ sw t1, 0(t0)
+
+ li t0, IC1_SRCSET
+ sw t1, 0(t0)
+
+ li t0, IC1_ASSIGNSET
+ sw t1, 0(t0)
+
+ li t0, IC1_WAKECLR
+ sw t1, 0(t0)
+
+ li t0, IC1_RISINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_FALLINGCLR
+ sw t1, 0(t0)
+
+ li t0, IC1_TESTBIT
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, SYS_FREQCTRL0
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_FREQCTRL1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_CLKSRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_PININPUTEN
+ li t1, 0x00000000
+ sw t1, 0(t0)
+ sync
+
+ li t0, 0xB1100100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, 0xB1400100
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+
+ li t0, SYS_WAKEMSK
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, SYS_WAKESRC
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ /* wait 1mS before setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+
+/* SDCS 0 SDRAM */
+ li t0, MEM_SDMODE0
+ li t1, 0x592CD1
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDMODE2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+/* 64 MB SDRAM at addr 0 */
+ li t0, MEM_SDADDR0
+ li t1, 0x001003F0
+ sw t1, 0(t0)
+
+
+ li t0, MEM_SDADDR1
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ li t0, MEM_SDADDR2
+ li t1, 0x00000000
+ sw t1, 0(t0)
+
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x880007A1 /* Disable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDPRECMD
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDAUTOREF
+ sw zero, 0(t0)
+ sync
+ sw zero, 0(t0)
+ sync
+
+ li t0, MEM_SDREFCFG
+ li t1, 0x8A0007A1 /* Enable */
+ sw t1, 0(t0)
+ sync
+
+ li t0, MEM_SDWRMD0
+ li t1, 0x00000023
+ sw t1, 0(t0)
+ sync
+
+ /* wait 1mS after setup */
+ li t1, MEM_1MS
+1: add t1, -1
+ bne t1, zero, 1b
+ nop
+
+ /* Setup GPIO pins */
+
+ li t0, SYS_PINFUNC
+ li t1, 0x00007025 /* 0x8080 */
+ sw t1, 0(t0)
+
+ li t0, SYS_TRIOUTCLR
+ li t1, 0xFFFFFFFF /* 0x1FFF */
+ sw t1, 0(t0)
+
+ /* Turn yellow front led on */
+ /* Release reset on CF */
+ li t0, SYS_OUTPUTCLR
+ li t1, GPIO_RJ1LG
+ sw t1, 0(t0)
+ li t0, SYS_OUTPUTSET
+ li t1, GPIO_RJ1LY|GPIO_CFRESET
+ sw t1, 0(t0)
+ sync
+ j clearmem
+ nop
+
+ .globl memtest
+memtest:
+ /* Fill memory with address */
+ li t0, 0x80000000
+ li t1, 0xFFF000 /* 64 MB */
+mt0: sw t0, 0(t0)
+ add t1, -1
+ add t0, 4
+ bne t1, zero, mt0
+ nop
+ nop
+ /* Verify addr */
+ li t0, 0x80000000
+ li t1, 0xFFF000 /* 64 MB */
+mt1: lw t2, 0(t0)
+ bne t0, t2, memhang
+ add t1, -1
+ add t0, 4
+ bne t1, zero, mt1
+ nop
+ nop
+ .globl clearmem
+clearmem:
+ /* Clear memory */
+ li t0, 0x80000000
+ li t1, 0xFFF000 /* 64 MB */
+mtc: sw zero, 0(t0)
+ add t1, -1
+ add t0, 4
+ bne t1, zero, mtc
+ nop
+ nop
+memtestend:
+ j ra
+ nop
+
+memhang:
+ b memhang
+ nop
diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds
new file mode 100644
index 0000000..8ba0b6d
--- /dev/null
+++ b/board/gth2/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .sdata : { *(.sdata) }
+
+ _gp = ALIGN(16);
+
+ __got_start = .;
+ .got : { *(.got) }
+ __got_end = .;
+
+ .sdata : { *(.sdata) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ uboot_end_data = .;
+ num_got_entries = (__got_end - __got_start) >> 2;
+
+ . = ALIGN(4);
+ .sbss : { *(.sbss) }
+ .bss : { *(.bss) }
+ uboot_end = .;
+}
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 87427e4..b9b9a71 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -28,7 +28,11 @@
#include <mpc5xxx.h>
#include <pci.h>
-#include "mt48lc8m32b2-6-7.h"
+/* Two MT48LC8M32B2 for 32 MB */
+/* #include "mt48lc8m32b2-6-7.h" */
+
+/* One MT48LC16M32S2 for 64 MB */
+#include "mt48lc16m32s2-75.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -74,6 +78,8 @@ static void sdram_start (int hi_addr)
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
+
+ udelay(10);
}
#endif
diff --git a/board/mcc200/mt48lc16m32s2-75.h b/board/mcc200/mt48lc16m32s2-75.h
new file mode 100644
index 0000000..ffdf039
--- /dev/null
+++ b/board/mcc200/mt48lc16m32s2-75.h
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR 0 /* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xD2322800
+#define SDRAM_CONFIG2 0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE 0x008D0000
+#define SDRAM_CONTROL 0x504F0000
+#define SDRAM_CONFIG1 0xC2222600
+#define SDRAM_CONFIG2 0x88B70004
+#define SDRAM_ADDRSEL 0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
diff --git a/board/ppmc7xx/Makefile b/board/ppmc7xx/Makefile
new file mode 100644
index 0000000..c378677
--- /dev/null
+++ b/board/ppmc7xx/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := ppmc7xx.o pci.o flash.o
+SOBJS := init.o
+
+$(LIB): .depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/ppmc7xx/config.mk b/board/ppmc7xx/config.mk
new file mode 100644
index 0000000..bcb6c81
--- /dev/null
+++ b/board/ppmc7xx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2005
+# Richard Danter, Wind River Systems
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+#
+#
+
+TEXT_BASE = 0xFFF00000
+TEXT_END = 0xFFF40000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
new file mode 100644
index 0000000..1cbcadc
--- /dev/null
+++ b/board/ppmc7xx/flash.c
@@ -0,0 +1,494 @@
+/*
+ * flash.c
+ * -------
+ *
+ * Flash programming routines for the Wind River PPMC 74xx/7xx
+ * based on flash.c from the TQM8260 board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <74xx_7xx.h>
+
+#define DWORD unsigned long long
+
+/* Local function prototypes */
+static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
+static void write_via_fpu (volatile DWORD* addr, DWORD* data);
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+void flash_reset (void)
+{
+ unsigned long msr;
+ DWORD cmd_reset = 0x00F000F000F000F0LL;
+
+ if (flash_info[0].flash_id != FLASH_UNKNOWN) {
+ msr = get_msr ();
+ set_msr (msr | MSR_FP);
+
+ write_via_fpu ((DWORD*)flash_info[0].start[0], &cmd_reset );
+
+ set_msr (msr);
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_get_size (ulong baseaddr, flash_info_t * info)
+{
+ int i;
+ unsigned long msr;
+ DWORD flashtest;
+ DWORD cmd_select[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x0090009000900090LL };
+
+ /* Enable FPU */
+ msr = get_msr ();
+ set_msr (msr | MSR_FP);
+
+ /* Write auto-select command sequence */
+ write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[0] );
+ write_via_fpu ((DWORD*)(baseaddr + (0x02AA << 3)), &cmd_select[1] );
+ write_via_fpu ((DWORD*)(baseaddr + (0x0555 << 3)), &cmd_select[2] );
+
+ /* Restore FPU */
+ set_msr (msr);
+
+ /* Read manufacturer ID */
+ flashtest = *(volatile DWORD*)baseaddr;
+ switch ((int)flashtest) {
+ case AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case FUJ_MANUFACT:
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ /* No, faulty or unknown flash */
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0);
+ }
+
+ /* Read device ID */
+ flashtest = *(volatile DWORD*)(baseaddr + 8);
+ switch ((long)flashtest) {
+ case AMD_ID_LV800T:
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00400000;
+ break;
+ case AMD_ID_LV800B:
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00400000;
+ break;
+ case AMD_ID_LV160T:
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00800000;
+ break;
+ case AMD_ID_LV160B:
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00800000;
+ break;
+ case AMD_ID_DL322T:
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL322B:
+ info->flash_id += FLASH_AMDL322B;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL323T:
+ info->flash_id += FLASH_AMDL323T;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_DL323B:
+ info->flash_id += FLASH_AMDL323B;
+ info->sector_count = 71;
+ info->size = 0x01000000;
+ break;
+ case AMD_ID_LV640U:
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break;
+ default:
+ /* Unknown flash type */
+ info->flash_id = FLASH_UNKNOWN;
+ return (0);
+ }
+
+ if ((long)flashtest == AMD_ID_LV640U) {
+ /* set up sector start adress table (uniform sector type) */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = baseaddr + (i * 0x00040000);
+ } else if (info->flash_id & FLASH_BTYPE) {
+ /* set up sector start adress table (bottom sector type) */
+ info->start[0] = baseaddr + 0x00000000;
+ info->start[1] = baseaddr + 0x00010000;
+ info->start[2] = baseaddr + 0x00018000;
+ info->start[3] = baseaddr + 0x00020000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000;
+ }
+ } else {
+ /* set up sector start adress table (top sector type) */
+ i = info->sector_count - 1;
+ info->start[i--] = baseaddr + info->size - 0x00010000;
+ info->start[i--] = baseaddr + info->size - 0x00018000;
+ info->start[i--] = baseaddr + info->size - 0x00020000;
+ for (; i >= 0; i--) {
+ info->start[i] = baseaddr + i * 0x00040000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
+ if (*(volatile DWORD*)(info->start[i] + 16) & 0x0001000100010001LL) {
+ info->protect[i] = 1; /* D0 = 1 if protected */
+ } else {
+ info->protect[i] = 0;
+ }
+ }
+
+ flash_reset ();
+ return (info->size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+ unsigned long size_b0 = 0;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here (only one bank) */
+ size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
+ if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size_b0, size_b0 >> 20);
+ }
+
+ /*
+ * protect monitor and environment sectors
+ */
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+ return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf ("AMD ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf ("FUJITSU ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM800T:
+ printf ("29LV800T (8 M, top sector)\n");
+ break;
+ case FLASH_AM800B:
+ printf ("29LV800T (8 M, bottom sector)\n");
+ break;
+ case FLASH_AM160T:
+ printf ("29LV160T (16 M, top sector)\n");
+ break;
+ case FLASH_AM160B:
+ printf ("29LV160B (16 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL322T:
+ printf ("29DL322T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL322B:
+ printf ("29DL322B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AMDL323T:
+ printf ("29DL323T (32 M, top sector)\n");
+ break;
+ case FLASH_AMDL323B:
+ printf ("29DL323B (32 M, bottom sector)\n");
+ break;
+ case FLASH_AM640U:
+ printf ("29LV640D (64 M, uniform sector)\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+ return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+ unsigned long msr;
+ DWORD cmd_erase[6] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x0080008000800080LL, 0x00AA00AA00AA00AALL,
+ 0x0055005500550055LL, 0x0030003000300030LL };
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect])
+ prot++;
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Enable FPU */
+ msr = get_msr();
+ set_msr ( msr | MSR_FP );
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[0] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[1] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[2] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_erase[3] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_erase[4] );
+ udelay (1000);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ write_via_fpu ((DWORD*)info->start[sect], &cmd_erase[5] );
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* Restore FPU */
+ set_msr (msr);
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
+ != 0x0080008000800080LL )
+ {
+ if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ serial_putc ('.');
+ last = now;
+ }
+ }
+
+ DONE:
+ /* reset to read mode */
+ flash_reset ();
+
+ printf (" done\n");
+ return 0;
+}
+
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong dp;
+ static unsigned char bb[8];
+ int i, l, rc, cc = cnt;
+
+ dp = (addr & ~7); /* get lower dword aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - dp) != 0) {
+ for (i = 0; i < 8; i++)
+ bb[i] = (i < l || (i - l) >= cc) ? *(char*)(dp + i) : *src++;
+ if ((rc = write_dword (info, dp, bb)) != 0) {
+ return (rc);
+ }
+ dp += 8;
+ cc -= 8 - l;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cc >= 8) {
+ if ((rc = write_dword (info, dp, src)) != 0) {
+ return (rc);
+ }
+ dp += 8;
+ src += 8;
+ cc -= 8;
+ }
+
+ if (cc <= 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ for (i = 0; i < 8; i++) {
+ bb[i] = (i < cc) ? *src++ : *(char*)(dp + i);
+ }
+ return (write_dword (info, dp, bb));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a dword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata)
+{
+ ulong start;
+ unsigned long msr;
+ int flag, i;
+ DWORD data;
+ DWORD cmd_write[3] = { 0x00AA00AA00AA00AALL, 0x0055005500550055LL,
+ 0x00A000A000A000A0LL };
+
+ for (data = 0, i = 0; i < 8; i++)
+ data = (data << 8) + *pdata++;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*(DWORD*)dest & data) != data) {
+ return (2);
+ }
+
+ /* Enable FPU */
+ msr = get_msr();
+ set_msr( msr | MSR_FP );
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[0] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x02AA << 3)), &cmd_write[1] );
+ write_via_fpu ((DWORD*)(info->start[0] + (0x0555 << 3)), &cmd_write[2] );
+ write_via_fpu ((DWORD*)dest, &data );
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts ();
+
+ /* Restore FPU */
+ set_msr(msr);
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while (*(volatile DWORD*)dest != data ) {
+ if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_via_fpu (volatile DWORD* addr, DWORD* data)
+{
+ __asm__ __volatile__ ("lfd 1, 0(%0)"::"r" (data));
+ __asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
+ __asm__ __volatile__ ("eieio");
+}
diff --git a/board/ppmc7xx/init.S b/board/ppmc7xx/init.S
new file mode 100644
index 0000000..e4ed7a6
--- /dev/null
+++ b/board/ppmc7xx/init.S
@@ -0,0 +1,336 @@
+/*
+ * init.S
+ * ------
+ *
+ * Wind River PPMC 7xx/74xx init code.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ *
+ * NOTE: The following code was generated automatically by Workbench
+ * from the ppmc7400_107.reg register file.
+ */
+
+#include <ppc_asm.tmpl>
+
+
+.globl board_asm_init
+board_asm_init:
+
+ lis r4,0xFEC0
+ ori r4,r4,0x0000
+ lis r5,0xFEE0
+ ori r5,r5,0x0000
+ lis r3,0x8000 # ADDR_00
+ ori r3,r3,0x0000
+ stwbrx r3,0,r4
+ li r3,0x1057 # VENDOR
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_02
+ ori r3,r3,0x0002
+ stwbrx r3,0,r4
+ li r3,0x0004 # ID
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_04
+ ori r3,r3,0x0004
+ stwbrx r3,0,r4
+ li r3,0x0006 # PCICMD
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_06
+ ori r3,r3,0x0006
+ stwbrx r3,0,r4
+ li r3,0x00A0 # PCISTAT
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_08
+ ori r3,r3,0x0008
+ stwbrx r3,0,r4
+ li r3,0x10 # REVID
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_09
+ ori r3,r3,0x0009
+ stwbrx r3,0,r4
+ li r3,0x00 # PROGIR
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_0A
+ ori r3,r3,0x000A
+ stwbrx r3,0,r4
+ li r3,0x00 # SUBCCODE
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_0B
+ ori r3,r3,0x000B
+ stwbrx r3,0,r4
+ li r3,0x06 # PBCCR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_0C
+ ori r3,r3,0x000C
+ stwbrx r3,0,r4
+ li r3,0x08 # PCLSR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_0D
+ ori r3,r3,0x000D
+ stwbrx r3,0,r4
+ li r3,0x00 # PLTR
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_0E
+ ori r3,r3,0x000E
+ stwbrx r3,0,r4
+ li r3,0x00 # HEADTYPE
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_0F
+ ori r3,r3,0x000F
+ stwbrx r3,0,r4
+ li r3,0x00 # BISTCTRL
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_10
+ ori r3,r3,0x0010
+ stwbrx r3,0,r4
+ lis r3,0x0000 # LMBAR
+ ori r3,r3,0x0008
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_14
+ ori r3,r3,0x0014
+ stwbrx r3,0,r4
+ lis r3,0xF000 # PCSRBAR
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_3C
+ ori r3,r3,0x003C
+ stwbrx r3,0,r4
+ li r3,0x00 # ILR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_3D
+ ori r3,r3,0x003D
+ stwbrx r3,0,r4
+ li r3,0x01 # INTPIN
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_3E
+ ori r3,r3,0x003E
+ stwbrx r3,0,r4
+ li r3,0x00 # MIN_GNT
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_3F
+ ori r3,r3,0x003F
+ stwbrx r3,0,r4
+ li r3,0x00 # MAX_LAT
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_40
+ ori r3,r3,0x0040
+ stwbrx r3,0,r4
+ li r3,0x00 # BUSNB
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_41
+ ori r3,r3,0x0041
+ stwbrx r3,0,r4
+ li r3,0x00 # SBUSNB
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_46
+ ori r3,r3,0x0046
+ stwbrx r3,0,r4
+# li r3,0xE080 # PCIARB
+ li r3,-0x1F80 # PCIARB
+ li r8, 0x2
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_70
+ ori r3,r3,0x0070
+ stwbrx r3,0,r4
+ li r3,0x0000 # PMCR1
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_72
+ ori r3,r3,0x0072
+ stwbrx r3,0,r4
+ li r3,0xC0 # PMCR2
+ stb r3,0x2(r5)
+ lis r3,0x8000 # ADDR_73
+ ori r3,r3,0x0073
+ stwbrx r3,0,r4
+ li r3,0xEF # ODCR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_74
+ ori r3,r3,0x0074
+ stwbrx r3,0,r4
+ li r3,0x7D00 # CLKDCR
+ li r8, 0x0
+ sthbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_76
+ ori r3,r3,0x0076
+ stwbrx r3,0,r4
+ li r3,0x00 # MDCR
+ stb r3,0x2(r5)
+ lis r6,0xFCE0
+ ori r6,r6,0x0000 # r6 is the EUMBAR Base Address
+ lis r3,0x8000 # ADDR_78
+ ori r3,r3,0x0078
+ stwbrx r3,0,r4
+ lis r3,0xFCE0 # EUMBBAR
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_80
+ ori r3,r3,0x0080
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # MSADDR1
+ ori r3,r3,0x4000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_84
+ ori r3,r3,0x0084
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # MSADDR2
+ ori r3,r3,0xFFFF
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_88
+ ori r3,r3,0x0088
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EMSADDR1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_8C
+ ori r3,r3,0x008C
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EMSADDR2
+ ori r3,r3,0x0303
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_90
+ ori r3,r3,0x0090
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # EMEADDR1
+ ori r3,r3,0x7F3F
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_94
+ ori r3,r3,0x0094
+ stwbrx r3,0,r4
+ lis r3,0xFFFF # EMEADDR2
+ ori r3,r3,0xFFFF
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_98
+ ori r3,r3,0x0098
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EXTEMEM1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_9C
+ ori r3,r3,0x009C
+ stwbrx r3,0,r4
+ lis r3,0x0303 # EXTEMEM2
+ ori r3,r3,0x0303
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_A0
+ ori r3,r3,0x00A0
+ stwbrx r3,0,r4
+ li r3,0x03 # MEMBNKEN
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_A3
+ ori r3,r3,0x00A3
+ stwbrx r3,0,r4
+ li r3,0x00 # MEMPMODE
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_B8
+ ori r3,r3,0x00B8
+ stwbrx r3,0,r4
+ li r3,0x00 # ECCCNT
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_B9
+ ori r3,r3,0x00B9
+ stwbrx r3,0,r4
+ li r3,0x00 # ECCTRG
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C0
+ ori r3,r3,0x00C0
+ stwbrx r3,0,r4
+ li r3,0xFF # ERRENR1
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_C1
+ ori r3,r3,0x00C1
+ stwbrx r3,0,r4
+ li r3,0x00 # ERRDR1
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C3
+ ori r3,r3,0x00C3
+ stwbrx r3,0,r4
+ li r3,0x50 # IPBESR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_C4
+ ori r3,r3,0x00C4
+ stwbrx r3,0,r4
+ li r3,0xBF # ERRENR2
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_C5
+ ori r3,r3,0x00C5
+ stwbrx r3,0,r4
+ li r3,0x00 # ERRDR2
+ stb r3,0x1(r5)
+ lis r3,0x8000 # ADDR_C7
+ ori r3,r3,0x00C7
+ stwbrx r3,0,r4
+ li r3,0x00 # PCIBESR
+ stb r3,0x3(r5)
+ lis r3,0x8000 # ADDR_C8
+ ori r3,r3,0x00C8
+ stwbrx r3,0,r4
+ lis r3,0x0000 # BERRADDR
+ ori r3,r3,0xE0FE
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_E0
+ ori r3,r3,0x00E0
+ stwbrx r3,0,r4
+ li r3,0xC0 # AMBOR
+ stb r3,0x0(r5)
+ lis r3,0x8000 # ADDR_F4
+ ori r3,r3,0x00F4
+ stwbrx r3,0,r4
+ lis r3,0x0000 # MCCR2
+ ori r3,r3,0x020C
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_F8
+ ori r3,r3,0x00F8
+ stwbrx r3,0,r4
+ lis r3,0x0230 # MCCR3
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_FC
+ ori r3,r3,0x00FC
+ stwbrx r3,0,r4
+ lis r3,0x2532 # MCCR4
+ ori r3,r3,0x2220
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_F0
+ ori r3,r3,0x00F0
+ stwbrx r3,0,r4
+ lis r3,0xFFC8 # MCCR1
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_A8
+ ori r3,r3,0x00A8
+ stwbrx r3,0,r4
+ lis r3,0xFF14 # PICR1
+ ori r3,r3,0x1CC8
+ li r8, 0x0
+ stwbrx r3,r8,r5
+ lis r3,0x8000 # ADDR_AC
+ ori r3,r3,0x00AC
+ stwbrx r3,0,r4
+ lis r3,0x0000 # PICR2
+ ori r3,r3,0x0000
+ li r8, 0x0
+ stwbrx r3,r8,r5
+
+ blr
diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c
new file mode 100644
index 0000000..5b115ea
--- /dev/null
+++ b/board/ppmc7xx/pci.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI initialisation for the MPC10x.
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <mpc106.h>
+
+#ifdef CONFIG_PCI
+
+struct pci_controller local_hose;
+
+void pci_init_board(void)
+{
+ struct pci_controller* hose = (struct pci_controller *)&local_hose;
+ u16 reg16;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI_MEM_BUS,
+ CFG_PCI_MEM_PHYS,
+ CFG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* ISA/PCI memory space */
+ pci_set_region(hose->regions + 2,
+ CFG_ISA_MEM_BUS,
+ CFG_ISA_MEM_PHYS,
+ CFG_ISA_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI I/O space */
+ pci_set_region(hose->regions + 3,
+ CFG_PCI_IO_BUS,
+ CFG_PCI_IO_PHYS,
+ CFG_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* ISA/PCI I/O space */
+ pci_set_region(hose->regions + 4,
+ CFG_ISA_IO_BUS,
+ CFG_ISA_IO_PHYS,
+ CFG_ISA_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 5;
+
+ pci_setup_indirect(hose,
+ MPC106_REG_ADDR,
+ MPC106_REG_DATA);
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ /* Initialises the MPC10x PCI Configuration regs. */
+ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /* Clear non-reserved bits in status register */
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+}
+
+#endif /* CONFIG_PCI */
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
new file mode 100644
index 0000000..0597c72
--- /dev/null
+++ b/board/ppmc7xx/ppmc7xx.c
@@ -0,0 +1,104 @@
+/*
+ * ppmc7xx.c
+ * ---------
+ *
+ * Main board-specific routines for Wind River PPMC 7xx/74xx board.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+#include <common.h>
+#include <command.h>
+
+
+/* Define some MPC107 (memory controller) registers */
+#define MPC107_EUMB_GCR 0xfce41020
+#define MPC107_EUMB_IACKR 0xfce600a0
+
+
+/* Function prototypes */
+extern void unlock_ram_in_cache( void );
+extern void _start_warm(void);
+
+
+/*
+ * initdram()
+ *
+ * This function normally initialises the (S)DRAM of the system. For this board
+ * the SDRAM was already initialised by board_asm_init (see init.S) so we just
+ * return the size of RAM.
+ */
+long initdram( int board_type )
+{
+ return CFG_SDRAM_SIZE;
+}
+
+
+/*
+ * after_reloc()
+ *
+ * This is called after U-Boot has been copied from Flash/ROM to RAM. It gives
+ * us an opportunity to do some additional setup before the rest of the system
+ * is initialised. We don't need to do anything, so we just call board_init_r()
+ * which should never return.
+ */
+void after_reloc( ulong dest_addr, gd_t* gd )
+{
+ /* Jump to the main U-Boot board init code */
+ board_init_r( gd, dest_addr );
+}
+
+
+/*
+ * checkboard()
+ *
+ * We could do some board level checks here, such as working out what version
+ * it is, but for this board we simply display it's name (on the console).
+ */
+int checkboard( void )
+{
+ puts( "Board: Wind River PPMC 7xx/74xx\n" );
+ return 0;
+}
+
+
+/*
+ * misc_init_r
+ *
+ * Used for other setup which needs to be done late in the bring-up phase.
+ */
+int misc_init_r( void )
+{
+ /* Reset the EPIC and clear pending interrupts */
+ out32r(MPC107_EUMB_GCR, 0xa0000000);
+ while( in32r( MPC107_EUMB_GCR ) & 0x80000000 );
+ out32r( MPC107_EUMB_GCR, 0x20000000 );
+ while( in32r( MPC107_EUMB_IACKR ) != 0xff );
+
+ /* Enable the I-Cache */
+ icache_enable();
+
+ return 0;
+}
+
+
+/*
+ * do_reset()
+ *
+ * Shell command to reset the board.
+ */
+void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
+{
+ printf( "Resetting...\n" );
+
+ /* Disabe and invalidate cache */
+ icache_disable();
+ dcache_disable();
+
+ /* Jump to warm start (in RAM) */
+ _start_warm();
+
+ /* Should never get here */
+ while(1);
+}
diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds
new file mode 100644
index 0000000..0dfa8c0
--- /dev/null
+++ b/board/ppmc7xx/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/74xx_7xx/start.o (.text)
+
+/* store the environment in a seperate sector in the boot flash */
+/* . = env_offset; */
+/* common/environment.o(.text) */
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/tqm5200/Makefile b/board/tqm5200/Makefile
index c234332..ab0ff1a 100644
--- a/board/tqm5200/Makefile
+++ b/board/tqm5200/Makefile
@@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-#OBJS := $(BOARD).o flash.o
OBJS := $(BOARD).o cmd_stk52xx.o
$(LIB): $(OBJS) $(SOBJS)
diff --git a/board/tqm5200/flash.c b/board/tqm5200/flash.c
deleted file mode 100644
index af4d78a..0000000
--- a/board/tqm5200/flash.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*
- * CPU to flash interface is 32-bit, so make declaration accordingly
- */
-typedef unsigned long FLASH_PORT_WIDTH;
-typedef volatile unsigned long FLASH_PORT_WIDTHV;
-
-#define FPW FLASH_PORT_WIDTH
-#define FPWV FLASH_PORT_WIDTHV
-
-#define FLASH_CYCLE1 0x0555
-#define FLASH_CYCLE2 0x02aa
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(FPWV *addr, flash_info_t *info);
-static void flash_reset(flash_info_t *info);
-static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
-static flash_info_t *flash_get_info(ulong base);
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- extern void flash_preinit(void);
- ulong flashbase = CFG_FLASH_BASE;
-
- flash_preinit();
-
- /* Init: no FLASHes known */
- memset(&flash_info[0], 0, sizeof(flash_info_t));
-
- flash_info[0].size =
- flash_get_size((FPW *)flashbase, &flash_info[0]);
-
- size = flash_info[0].size;
-
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CFG_MONITOR_BASE));
-#endif
-
-#ifdef CFG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- flash_get_info(CFG_ENV_ADDR));
-#endif
-
- return size ? size : 1;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_reset(flash_info_t *info)
-{
- FPWV *base = (FPWV *)(info->start[0]);
-
- /* Put FLASH back in read mode */
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
- *base = (FPW)0x00FF00FF; /* Intel Read Mode */
- else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
- *base = (FPW)0x00F000F0; /* AMD Read Mode */
-}
-
-/*-----------------------------------------------------------------------
- */
-
-static flash_info_t *flash_get_info(ulong base)
-{
- int i;
- flash_info_t * info;
-
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
- info = & flash_info[i];
- if (info->size && info->start[0] <= base &&
- base <= info->start[0] + info->size - 1)
- break;
- }
-
- return i == CFG_MAX_FLASH_BANKS ? 0 : info;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD: printf ("AMD "); break;
- case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
- case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
- case FLASH_MAN_SST: printf ("SST "); break;
- case FLASH_MAN_STM: printf ("STM "); break;
- case FLASH_MAN_INTEL: printf ("INTEL "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AMLV128U:
- printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
- break;
- case FLASH_AM160B:
- printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20,
- info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0) {
- printf ("\n ");
- }
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-ulong flash_get_size (FPWV *addr, flash_info_t *info)
-{
- int i;
- ulong base = (ulong)addr;
-
- /* Write auto select command: read Manufacturer ID */
- /* Write auto select command sequence and test FLASH answer */
- addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
- addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
-
- /* The manufacturer codes are only 1 byte, so just use 1 byte.
- * This works for any bus width and any FLASH device width.
- */
- udelay(100);
- switch (addr[0] & 0xff) {
-
- case (uchar)AMD_MANUFACT:
- debug ("Manufacturer: AMD (Spansion)\n");
- info->flash_id = FLASH_MAN_AMD;
- break;
-
- case (uchar)INTEL_MANUFACT:
- debug ("Manufacturer: Intel (not supported yet)\n");
- info->flash_id = FLASH_MAN_INTEL;
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
-
- /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
- if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
-
- case (FPW)AMD_ID_LV160B:
- debug ("Chip: AM29LV160MB\n");
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00400000;
- /*
- * The first 4 sectors are 16 kB, 8 kB, 8 kB and 32 kB, all
- * the other ones are 64 kB
- */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00008000;
- info->start[2] = base + 0x0000C000;
- info->start[3] = base + 0x00010000;
- for( i = 4; i < info->sector_count; i++ )
- info->start[i] =
- base + (i * 2 * (64 << 10)) - 0x00060000;
- break; /* => 4 MB */
-
- case AMD_ID_MIRROR:
- debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
- addr[14], addr[15]);
-
- switch(addr[14]) {
- case AMD_ID_LV128U_2:
- if (addr[15] != AMD_ID_LV128U_3) {
- debug ("Chip: AM29LVxxxM -> unknown\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- } else {
- debug ("Chip: AM29LV128M\n");
- info->flash_id += FLASH_AMLV128U;
- info->sector_count = 256;
- info->size = 0x02000000;
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += 0x20000;
- }
- }
- break; /* => 32 MB */
- default:
- debug ("Chip: *** unknown ***\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- break;
- }
- break;
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- }
-
- /* Put FLASH back in read mode */
- flash_reset(info);
-
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- vu_long *addr = (vu_long*)(info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
-
- debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > FLASH_AMD_COMP)) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
- addr[0x0555] = 0x00800080;
- addr[0x0555] = 0x00AA00AA;
- addr[0x02AA] = 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (vu_long*)(info->start[sect]);
- addr[0] = 0x00300030;
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (vu_long*)(info->start[l_sect]);
- while ((addr[0] & 0x00800080) != 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
-DONE:
- /* reset to read mode */
- addr = (volatile unsigned long *)info->start[0];
- addr[0] = 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- /*
- * Get lower word aligned address. Assumes 32 bit flash bus width.
- */
- wp = (addr & ~3);
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word_amd(info, (FPW *)wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash for AMD FLASH
- * A word is 16 or 32 bits, whichever the bus width of the flash bank
- * (not an individual chip) is.
- *
- * returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
-{
- ulong start;
- int flag;
- FPWV *base; /* first address in flash bank */
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest & data) != data) {
- return (2);
- }
-
- base = (FPWV *)(info->start[0]);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
- base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
- base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
-
- *dest = data; /* start programming the data */
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- start = get_timer (0);
-
- /* data polling for D7 */
- while ((*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- *dest = (FPW)0x00F000F0; /* reset bank */
- return (1);
- }
- }
- return (0);
-}
diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c
index 6aad920..310abd2 100644
--- a/board/tqm5200/tqm5200.c
+++ b/board/tqm5200/tqm5200.c
@@ -254,13 +254,7 @@ int checkboard (void)
puts ("Board: AEVFIFO\n");
return 0;
#endif
-#if defined (CONFIG_TQM5200_AA)
- puts ("Board: TQM5200-AA (TQ-Components GmbH)\n");
-#elif defined (CONFIG_TQM5200_AB)
- puts ("Board: TQM5200-AB (TQ-Components GmbH)\n");
-#elif defined (CONFIG_TQM5200_AC)
- puts ("Board: TQM5200-AC (TQ-Components GmbH)\n");
-#elif defined (CONFIG_TQM5200)
+#if defined (CONFIG_TQM5200)
puts ("Board: TQM5200 (TQ-Components GmbH)\n");
#endif
#if defined (CONFIG_STK52XX)
@@ -572,17 +566,7 @@ static const SMI_REGS init_regs [] =
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
-#if defined (CONFIG_TQM5200_AA)
- strcpy (info, " Board: TQM5200-AA (TQ-Components GmbH)");
-#elif defined (CONFIG_TQM5200_AB)
- strcpy (info, " Board: TQM5200-AB (TQ-Components GmbH)");
-#elif defined (CONFIG_TQM5200_AC)
- strcpy (info, " Board: TQM5200-AC (TQ-Components GmbH)");
-#elif defined (CONFIG_TQM5200)
- strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
-#else
-#error No supported board selected
-#endif
+ strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_STK52XX)
} else if (line_number == 2) {
strcpy (info, " on a STK52XX baseboard");
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index b5c12e3..d992aec 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -406,4 +406,28 @@ static void set_ddr_config(void) {
(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
SYNC;
+
+ /* Workaround for DDR6 Erratum
+ * see MPC8349E Device Errata Rev.8, 2/2006
+ * This workaround influences the MPC internal "input enables"
+ * dependent on CAS latency and MPC revision. According to errata
+ * sheet the internal reserved registers for this workaround are
+ * not available from revision 2.0 and up.
+ */
+
+ /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+ * (0x200)
+ */
+ if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+ /* There is a internal reserved register at IMMRBAR+0x2F00
+ * which has to be written with a certain value defined by
+ * errata sheet.
+ */
+#if defined(DDR_CASLAT_20)
+ *((u8 *)im + 0x2f00) = 0x201c0000;
+#else
+ *((u8 *)im + 0x2f00) = 0x202c0000;
+#endif
+ }
}
diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c
index 69b9101..befe8b7 100644
--- a/board/tqm85xx/tqm85xx.c
+++ b/board/tqm85xx/tqm85xx.c
@@ -27,6 +27,9 @@
* MA 02111-1307 USA
*/
+#ifdef CONFIG_PS2MULT
+void ps2mult_early_init(void);
+#endif
#include <common.h>
#include <pci.h>
@@ -410,3 +413,14 @@ void pci_init_board (void)
pci_mpc85xx_init (&hose);
#endif /* CONFIG_PCI */
}
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+#ifdef CONFIG_PS2MULT
+ ps2mult_early_init();
+#endif /* CONFIG_PS2MULT */
+ return (0);
+}
+#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c
index 00eb385..edea8f0 100644
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
@@ -729,6 +729,7 @@ static void led_blink (void)
/* blink LED. This function does not return! */
while (1) {
+ reset_timer_masked ();
led_set (1);
udelay (1000000 / LED_BLINK_FREQ / 2);
led_set (0);
diff --git a/board/trab/trab.c b/board/trab/trab.c
index 868a899..346406e 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -161,6 +161,19 @@ int misc_init_r (void)
uchar *str;
int i;
+#ifdef CONFIG_VERSION_VARIABLE
+ {
+ /* Set version variable. Please note, that this variable is
+ * also set in main_loop() later in the boot process. The
+ * version variable has to be set this early, because so it
+ * could be used in script files on an usb stick, which
+ * might be called during do_auto_update() */
+ extern char version_string[];
+
+ setenv ("ver", version_string);
+ }
+#endif /* CONFIG_VERSION_VARIABLE */
+
#ifdef CONFIG_AUTO_UPDATE
extern int do_auto_update(void);
/* this has priority over all else */
diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c
index ca68682..382a85b 100644
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -223,7 +223,7 @@ u16 tsc2000_read_channel (unsigned int channel)
u16 res;
tsc2000_set_mux(channel);
- udelay(3 * TSC2000_DELAY_BASE);
+ udelay(20 * TSC2000_DELAY_BASE);
tsc2000_write(TSC2000_REG_ADC, 0x2036);
adc_wait_conversion_done ();
diff --git a/board/trab/vfd.c b/board/trab/vfd.c
index cea8b0b..2f1e7d7 100644
--- a/board/trab/vfd.c
+++ b/board/trab/vfd.c
@@ -358,6 +358,8 @@ void transfer_pic(int display, unsigned char *adr, int height, int width)
*/
int vfd_init_clocks (void)
{
+ int i;
+
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
@@ -367,7 +369,9 @@ int vfd_init_clocks (void)
*/
gpio->PCUP = (gpio->PCUP & 0xFFF0); /* activate GPC0...GPC3 pullups */
gpio->PCCON = (gpio->PCCON & 0xFFFFFF00); /* configure GPC0...GPC3 as inputs */
- udelay (10); /* allow signals to settle */
+ /* allow signals to settle */
+ for (i=0; i<10000; i++) /* udelay isn't working yet at this point! */
+ __asm("NOP");
vfd_board_id = (~gpio->PCDAT) & 0x000F; /* read GPC0...GPC3 port pins */
VFD_DISABLE; /* activate blank for the vfd */
diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk
index c73cd27..b77c91c 100644
--- a/board/voiceblue/config.mk
+++ b/board/voiceblue/config.mk
@@ -12,5 +12,5 @@ ifeq ($(VOICEBLUE_SMALL_FLASH),y)
TEXT_BASE = 0x20012000
else
# Running in SDRAM...
-TEXT_BASE = 0x13000000
+TEXT_BASE = 0x13FD0000
endif
generated by cgit v1.1 at 2024-12-11 18:40:01 +0000