diff options
Diffstat (limited to 'board')
242 files changed, 9752 insertions, 6157 deletions
diff --git a/board/innokom/Makefile b/board/AndesTech/adp-ag101p/Makefile index 8b58b7f..03c3ff4 100644 --- a/board/innokom/Makefile +++ b/board/AndesTech/adp-ag101p/Makefile @@ -1,6 +1,7 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> # # See file CREDITS for list of people who contributed to this # project. @@ -25,12 +26,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := innokom.o flash.o +COBJS := adp-ag101p.o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS)) ######################################################################### diff --git a/board/AndesTech/adp-ag101p/adp-ag101p.c b/board/AndesTech/adp-ag101p/adp-ag101p.c new file mode 100644 index 0000000..8dd2043 --- /dev/null +++ b/board/AndesTech/adp-ag101p/adp-ag101p.c @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> + +#include <faraday/ftsdc010.h> +#include <faraday/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ + +int board_init(void) +{ + /* + * refer to BOOT_PARAMETER_PA_BASE within + * "linux/arch/nds32/include/asm/misc_spec.h" + */ + gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P; + gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; + + ftsmc020_init(); /* initialize Flash */ + return 0; +} + +int dram_init(void) +{ + unsigned long sdram_base = PHYS_SDRAM_0; + unsigned long expected_size = PHYS_SDRAM_0_SIZE; + unsigned long actual_size; + + actual_size = get_ram_size((void *)sdram_base, expected_size); + + gd->ram_size = actual_size; + + if (expected_size != actual_size) { + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + } + + return 0; +} + +int board_eth_init(bd_t *bd) +{ + return ftmac100_initialize(bd); +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else { + return 0; + } +} + +int board_mmc_init(bd_t *bis) +{ + ftsdc010_mmc_init(0); + return 0; +} diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c index 64f4b57..34ede87 100644 --- a/board/CarMediaLab/flea3/flea3.c +++ b/board/CarMediaLab/flea3/flea3.c @@ -160,7 +160,7 @@ static void board_setup_sdram(void) writel(0x2000, &esdc->esdctl0); writel(0x2000, &esdc->esdctl1); - board_setup_sdram_bank(CSD1_BASE_ADDR); + board_setup_sdram_bank(CSD0_BASE_ADDR); } static void setup_iomux_uart3(void) @@ -229,7 +229,7 @@ int board_early_init_f(void) (struct ccm_regs *)IMX_CCM_BASE; /* setup GPIO3_1 to set HighVCore signal */ - mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5); + mxc_request_iomux(MX35_PIN_ATA_DA1, MUX_CONFIG_ALT5); gpio_direction_output(65, 1); /* initialize PLL and clock configuration */ diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c new file mode 100644 index 0000000..dc5350d --- /dev/null +++ b/board/LaCie/common/common.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) + +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +void mv_phy_88e1116_init(const char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac_addr) +{ + int ret; + ushort version; + + /* I2C-0 for on-board EEPROM */ + i2c_set_bus_num(0); + + /* Check layout version for EEPROM data */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *) &version, 2); + if (ret != 0) { + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; + } + version = be16_to_cpu(version); + if (version < 1 || version > 3) { + printf("Error: unknown version %d for EEPROM data\n", + version); + return -1; + } + + /* Read Ethernet MAC address from EEPROM */ + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 2, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, mac_addr, 6); + if (ret != 0) + printf("Error: failed to read I2C EEPROM @%02x\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + return ret; +} +#endif /* CONFIG_CMD_I2C && CONFIG_SYS_I2C_EEPROM_ADDR */ diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h new file mode 100644 index 0000000..82a9522 --- /dev/null +++ b/board/LaCie/common/common.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef _LACIE_COMMON_H +#define _LACIE_COMMON_H + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +void mv_phy_88e1116_init(const char *name); +#endif +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) +int lacie_read_mac_address(uchar *mac); +#endif + +#endif /* _LACIE_COMMON_H */ diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index 00a255d..c8d45f4 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -26,10 +26,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := edminiv2.o +COBJS := edminiv2.o ../common/common.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c index ee26893..c1a01bc 100644 --- a/board/LaCie/edminiv2/edminiv2.c +++ b/board/LaCie/edminiv2/edminiv2.c @@ -27,7 +27,6 @@ #include <common.h> #include <miiphy.h> #include <asm/arch/orion5x.h> -#include "edminiv2.h" DECLARE_GLOBAL_DATA_PTR; @@ -96,33 +95,6 @@ int board_init(void) /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { - u16 reg; - u16 devadr; - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); - return; - } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, devadr); - - printf("88E1116 Initialized on %s\n", name); + mv_phy_88e1116_init("egiga0"); } #endif /* CONFIG_RESET_PHY_R */ diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile new file mode 100644 index 0000000..fbae48e --- /dev/null +++ b/board/LaCie/net2big_v2/Makefile @@ -0,0 +1,52 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/net2big_v2/kwbimage.cfg b/board/LaCie/net2big_v2/kwbimage.cfg new file mode 100644 index 0000000..8d9f153 --- /dev/null +++ b/board/LaCie/net2big_v2/kwbimage.cfg @@ -0,0 +1,162 @@ +# +# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM spi # Boot from SPI flash + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000C30 # DDR Configuration register +# bit13-0: 0xa00 (2560 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x38743000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000A32 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs2width=nonexistent +# bit7-6: 00, Cs1size =nonexistent +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000662 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000044 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 1, DDR drive strenght reduced +# bit2: 1, DDR ODT control lsd enabled +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, enabled +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 1 , D2P Latency enabled +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x07, Size (i.e. 128MB) + +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) +# bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 +# bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0 +# bit11-10:1, DQ_ODTSel. ODT select turned on + +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c new file mode 100644 index 0000000..d0b4adf --- /dev/null +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#include "net2big_v2.h" +#include "../common/common.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* GPIO configuration */ + kw_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH, + NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Request power-off */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Rear power switch (on|auto) */ + MPP14_GPIO, /* USB fuse alarm */ + MPP15_GPIO, /* Rear power switch (auto|off) */ + MPP16_GPIO, /* SATA HDD1 power */ + MPP17_GPIO, /* SATA HDD2 power */ + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP24_GPIO, /* USB mode select */ + MPP26_GPIO, /* USB device vbus */ + MPP28_GPIO, /* USB enable host vbus */ + MPP29_GPIO, /* GPIO extension ALE */ + MPP34_GPIO, /* Rear Push button 0=on 1=off */ + MPP35_GPIO, /* Inhibit switch power-off */ + MPP36_GPIO, /* SATA HDD1 presence */ + MPP37_GPIO, /* SATA HDD2 presence */ + MPP40_GPIO, /* eSATA presence */ + MPP44_GPIO, /* GPIO extension (data 0) */ + MPP45_GPIO, /* GPIO extension (data 1) */ + MPP46_GPIO, /* GPIO extension (data 2) */ + MPP47_GPIO, /* GPIO extension (addr 0) */ + MPP48_GPIO, /* GPIO extension (addr 1) */ + MPP49_GPIO, /* GPIO extension (addr 2) */ + 0 + }; + + kirkwood_mpp_conf(kwmpp_config); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + mv_phy_88e1116_init("egiga0"); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) +/* Return GPIO push button status */ +static int +do_read_push_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON); +} + +U_BOOT_CMD(button, 1, 1, do_read_push_button, + "Return GPIO push button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/net2big_v2/net2big_v2.h index 88e62b2..f9778f4 100644 --- a/board/LaCie/edminiv2/edminiv2.h +++ b/board/LaCie/net2big_v2/net2big_v2.h @@ -1,9 +1,7 @@ /* - * (C) Copyright 2009 - * Net Insight <www.netinsight.net> - * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> + * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> * - * Based on sheevaplug.h: + * Based on Kirkwood support: * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Written-by: Prafulla Wadaskar <prafulla@marvell.com> @@ -20,22 +18,18 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA */ -#ifndef __EDMINIV2_BASE_H -#define __EDMINIV2_BASE_H +#ifndef NET2BIG_V2_H +#define NET2BIG_V2_H + +/* GPIO configuration */ +#define NET2BIG_V2_OE_LOW 0x0600E000 +#define NET2BIG_V2_OE_HIGH 0x00000134 +#define NET2BIG_V2_OE_VAL_LOW 0x10030000 +#define NET2BIG_V2_OE_VAL_HIGH 0x00000000 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) +/* Buttons */ +#define NET2BIG_V2_GPIO_PUSH_BUTTON 34 -#endif /* __EDMINIV2_BASE_H */ +#endif /* NET2BIG_V2_H */ diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile index d4a613f..b43c3d3 100644 --- a/board/LaCie/netspace_v2/Makefile +++ b/board/LaCie/netspace_v2/Makefile @@ -21,10 +21,13 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).o -COBJS := netspace_v2.o +COBJS := $(BOARD).o ../common/common.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 7c4b15e..fbf020f 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -21,14 +21,14 @@ */ #include <common.h> -#include <miiphy.h> -#include <netdev.h> #include <command.h> #include <asm/arch/cpu.h> #include <asm/arch/kirkwood.h> #include <asm/arch/mpp.h> #include <asm/arch/gpio.h> + #include "netspace_v2.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; @@ -89,49 +89,29 @@ int board_init(void) return 0; } -void mv_phy_88e1116_init(char *name) +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) { - u16 reg; - u16 devadr; - - if (miiphy_set_current_dev(name)) - return; - - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { - printf("Err..(%s) could not read PHY dev address\n", __func__); - return; +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); } - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) { - printf("Err..(%s) PHY status read failed\n", __func__); - return; - } - if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) { - printf("Err..(%s) PHY reset failed\n", __func__); - return; - } - - debug("88E1116 Initialized on %s\n", name); +#endif + return 0; } +#endif +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) /* Configure and initialize PHY */ void reset_phy(void) { mv_phy_88e1116_init("egiga0"); } +#endif +#if defined(CONFIG_KIRKWOOD_GPIO) /* Return GPIO button status */ static int do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -141,3 +121,4 @@ do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD(button, 1, 1, do_read_button, "Return GPIO button status 0=off 1=on", ""); +#endif diff --git a/board/LaCie/netspace_v2/netspace_v2.h b/board/LaCie/netspace_v2/netspace_v2.h index 3f3d51c..34e492c 100644 --- a/board/LaCie/netspace_v2/netspace_v2.h +++ b/board/LaCie/netspace_v2/netspace_v2.h @@ -31,12 +31,4 @@ #define NETSPACE_V2_GPIO_BUTTON 32 -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - #endif /* NETSPACE_V2_H */ diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 35b695e..5183466 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include <net.h> #include <netdev.h> +#include <linux/compiler.h> #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index 30304b0..6340585 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -421,7 +421,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -519,7 +519,7 @@ static int mv64360_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -637,15 +637,6 @@ static int mv64360_eth_free_rx_rings (struct eth_device *dev) int mv64360_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64360_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -715,7 +706,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -724,7 +714,6 @@ int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -800,15 +789,12 @@ int mv64360_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -899,12 +885,10 @@ static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64360_eth_update_stat (dev); @@ -926,13 +910,10 @@ static void mv64360_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -955,12 +936,12 @@ static void mv64360_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1008,12 +989,10 @@ static void mv64360_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64360_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64360_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2065,13 +2044,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index d52d3f0..e62ed0c 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64360 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -276,7 +269,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +279,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +300,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -385,48 +378,46 @@ return 0; switch (i) { case 2: /* Memory type (DDR / SDRAM) */ dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; -#ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); -#endif + dimmInfo->slot); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1272,13 +1255,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1329,12 +1312,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1344,30 +1327,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64360_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1390,23 +1373,23 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf + debug ("OOOOOOOOO sdram_conf 0x1400: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ @@ -1428,18 +1411,18 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ tmp_dunit_control_low = 0x2C1107F2; else tmp_dunit_control_low = 0x3C1107d2; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1449,9 +1432,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1460,9 +1443,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1B1107d2; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1472,9 +1455,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1483,9 +1466,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x3B1107d2; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1495,9 +1478,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ @@ -1506,9 +1489,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); } else tmp_dunit_control_low = 0x1A1107d2; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1528,8 +1511,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1538,8 +1521,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1549,29 +1532,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1582,15 +1565,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x11511220)); + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); @@ -1602,42 +1585,38 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0x9)); + 0x9); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf - indent: Standard input:1450: Warning:old style assignment ambiguity in "=*". Assuming "= *" - -indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". Assuming "= *" - + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1647,8 +1626,8 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1656,17 +1635,17 @@ indent: Standard input:1451: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1712,9 +1691,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1730,9 +1709,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1747,10 +1725,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1784,7 +1762,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 14e6355..a7836ed 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -34,6 +34,7 @@ #include "../include/mv_gen_reg.h" #include <net.h> #include <netdev.h> +#include <linux/compiler.h> #include "eth.h" #include "mpsc.h" @@ -410,7 +411,7 @@ int checkboard (void) void debug_led (int led, int mode) { volatile int *addr = 0; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index cd9d5a4..4aefbaf 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -420,7 +420,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; unsigned int port_num; - u32 port_status, phy_reg_data; + u32 phy_reg_data; ethernet_private = (ETH_PORT_INFO *) dev->priv; /* ronen - when we update the MAC env params we only update dev->enetaddr @@ -518,7 +518,7 @@ static int mv64460_eth_real_open (struct eth_device *dev) */ MV_REG_WRITE (MV64460_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); - port_status = MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); + MV_REG_READ (MV64460_ETH_PORT_STATUS_REG (port_num)); /* Check Link status on phy */ eth_port_read_smi_reg (port_num, 1, &phy_reg_data); @@ -636,15 +636,6 @@ static int mv64460_eth_free_rx_rings (struct eth_device *dev) int mv64460_eth_stop (struct eth_device *dev) { - ETH_PORT_INFO *ethernet_private; - struct mv64460_eth_priv *port_private; - unsigned int port_num; - - ethernet_private = (ETH_PORT_INFO *) dev->priv; - port_private = - (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; - /* Disable all gigE address decoder */ MV_REG_WRITE (MV64460_ETH_BASE_ADDR_ENABLE_REG, 0x3f); DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); @@ -714,7 +705,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; ETH_FUNC_RET_STATUS status; struct net_device_stats *stats; @@ -723,7 +713,6 @@ int mv64460_eth_xmit (struct eth_device *dev, volatile void *dataPtr, ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; @@ -799,15 +788,12 @@ int mv64460_eth_receive (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; PKT_INFO pkt_info; struct net_device_stats *stats; - ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == @@ -898,12 +884,10 @@ static struct net_device_stats *mv64460_eth_get_stats (struct eth_device *dev) { ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; mv64460_eth_update_stat (dev); @@ -925,13 +909,10 @@ static void mv64460_eth_update_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; - volatile unsigned int dummy; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -954,12 +935,12 @@ static void mv64460_eth_update_stat (struct eth_device *dev) * But the unsigned long in PowerPC and MIPS are 32bit. So the next read * is just a dummy read for proper work of the GigE port */ - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); stats->tx_bytes += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_LOW); - dummy = eth_read_mib_counter (ethernet_private->port_num, + eth_read_mib_counter (ethernet_private->port_num, ETH_MIB_GOOD_OCTETS_SENT_HIGH); stats->rx_errors += (unsigned long) eth_read_mib_counter (ethernet_private->port_num, @@ -1007,12 +988,10 @@ static void mv64460_eth_print_stat (struct eth_device *dev) ETH_PORT_INFO *ethernet_private; struct mv64460_eth_priv *port_private; struct net_device_stats *stats; - unsigned int port_num; ethernet_private = (ETH_PORT_INFO *) dev->priv; port_private = (struct mv64460_eth_priv *) ethernet_private->port_private; - port_num = port_private->port_num; stats = port_private->stats; /* These are false updates */ @@ -2064,13 +2043,11 @@ static void eth_port_init_mac_tables (ETH_PORT eth_port_num) static void eth_clear_mib_counters (ETH_PORT eth_port_num) { int i; - unsigned int dummy; /* Perform dummy reads from MIB counters */ for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; i += 4) - dummy = MV_REG_READ ((MV64460_ETH_MIB_COUNTERS_BASE - (eth_port_num) + i)); + MV_REG_READ((MV64460_ETH_MIB_COUNTERS_BASE(eth_port_num) + i)); return; } diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index e328d8f..6297447 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -44,15 +44,8 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG #define MAP_PCI -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit (void); /* setup delay line of Mv64460 */ int mvDmaIsChannelActive (int); int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); @@ -69,14 +62,12 @@ memory_map_bank (unsigned int bankNo, #endif -#ifdef DEBUG if (bankLength > 0) { - printf ("mapping bank %d at %08x - %08x\n", + debug("mapping bank %d at %08x - %08x\n", bankNo, bankBase, bankBase + bankLength - 1); } else { - printf ("unmapping bank %d\n", bankNo); + debug("unmapping bank %d\n", bankNo); } -#endif memoryMapBank (bankNo, bankBase, bankLength); @@ -276,7 +267,7 @@ return 0; #else uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; - unsigned int i, j, density = 1, devicesForErrCheck = 0; + unsigned int i, j, density = 1; #ifdef DEBUG unsigned int k; @@ -286,17 +277,17 @@ return 0; uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 1, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); /* zero all the values */ memset (dimmInfo, 0, sizeof (*dimmInfo)); @@ -307,7 +298,7 @@ return 0; } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -387,46 +378,46 @@ return 0; dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; #ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf + debug ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf + debug ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); + dimmInfo->slot); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf + debug ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf + debug ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf + debug ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf + debug ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -434,33 +425,33 @@ return 0; switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug + ("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug + ("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug + ("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug + ("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug + ("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -479,9 +470,9 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf + debug ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -494,49 +485,49 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf ("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->clockToDataOut */ + debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ /*#ifdef CONFIG_ECC */ case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf + debug ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + dimmInfo->errorCheckType); break; /* #endif */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf + debug ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf + debug ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf + debug ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf + debug ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -552,26 +543,26 @@ return 0; dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug + ("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf + debug ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -591,34 +582,34 @@ return 0; ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug + ("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf + debug ("%d, ", - k + 1)); + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -630,8 +621,8 @@ return 0; /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -639,8 +630,8 @@ return 0; hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug + ("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -648,36 +639,36 @@ return 0; hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug + ("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug + ("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -707,8 +698,8 @@ return 0; dimmInfo-> maxClSupported_DDR >> 1; - DP (printf - ("*** Change actual Cas Latencies cause of minimumCycleTime n")); + debug + ("*** Change actual Cas Latencies cause of minimumCycleTime n"); } /* ronen - checkif the Dimm frequency compared to the Sysclock. */ if ((dimmInfo-> @@ -744,32 +735,32 @@ return 0; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf + debug ("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf + debug ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -779,7 +770,7 @@ return 0; /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -794,60 +785,60 @@ return 0; (data[i] & BIT6) >> 6; #ifdef DEBUG if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug + (" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug + (" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug + (" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug + (" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug + (" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug + (" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug + (" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug + (" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug + (" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug + (" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug + (" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug + (" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug + (" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug + (" - redundant Row Addressing: No \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -861,46 +852,46 @@ return 0; (data[i] & BIT5) >> 5; #ifdef DEBUG if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug + (" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug + (" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug + (" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug + (" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug + (" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug + (" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug + (" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug + (" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug + (" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug + (" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug + (" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug + (" - upper VCC tolerance: 10 Percent \n"); #endif break; @@ -919,7 +910,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -932,9 +923,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -951,7 +942,7 @@ return 0; leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint)); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -964,9 +955,9 @@ return 0; rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf + debug ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -983,12 +974,12 @@ return 0; trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf + tmemclk, tmemclk / 100, tmemclk % 100); + debug ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1002,12 +993,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1021,12 +1009,9 @@ return 0; rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1035,41 +1020,41 @@ return 0; tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf + debug ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf + debug ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug + ("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1095,9 +1080,9 @@ return 0; } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1122,9 +1107,9 @@ return 0; } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1149,9 +1134,9 @@ return 0; } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1176,9 +1161,9 @@ return 0; } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf + debug ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1194,8 +1179,6 @@ return 0; dimmInfo->numberOfDevices = (dimmInfo->dataWidth / dimmInfo->sdramWidth) * dimmInfo->numOfModuleBanks; - devicesForErrCheck = - (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth; if ((dimmInfo->errorCheckType == 0x1) || (dimmInfo->errorCheckType == 0x2) || (dimmInfo->errorCheckType == 0x3)) { @@ -1217,7 +1200,7 @@ return 0; tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1219,11 @@ return 0; cal_val = 2; } - DP (printf ("cal_val = %d\n", cal_val)); + debug("cal_val = %d\n", cal_val); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1271,13 +1254,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } /* SDRAM configuration */ @@ -1328,12 +1311,12 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) hang (); break; } - DP (printf ("calculated refresh interval %0x\n", sdram_config_reg)); + debug("calculated refresh interval %0x\n", sdram_config_reg); /* make sure the refresh value is only 14 bits */ if (sdram_config_reg > 0x1fff) sdram_config_reg = 0x1fff; - DP (printf ("adjusted refresh interval %0x\n", sdram_config_reg)); + debug("adjusted refresh interval %0x\n", sdram_config_reg); /* we want physical bank interleaving and */ /* virtual bank interleaving enabled so do nothing */ @@ -1343,30 +1326,30 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs == 1) { /* it's registered DRAM, so set the reg. DRAM bit */ sdram_config_reg = sdram_config_reg | BIT17; - DP (printf ("Enabling registered DRAM bit\n")); + debug("Enabling registered DRAM bit\n"); } /* turn on DRAM ECC? */ #ifdef CONFIG_MV64460_ECC if (info->errorCheckType == 0x2) { /* DRAM has ECC, so turn it on */ sdram_config_reg = sdram_config_reg | BIT18; - DP (printf ("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* set the data DQS pin configuration */ switch (info->sdramWidth) { case 0x4: /* memory is x4 */ sdram_config_reg = sdram_config_reg | BIT20 | BIT21; - DP (printf ("Data DQS pins set for 16 pins\n")); + debug("Data DQS pins set for 16 pins\n"); break; case 0x8: /* memory is x8 or x16 */ case 0x10: sdram_config_reg = sdram_config_reg | BIT21; - DP (printf ("Data DQS pins set for 8 pins\n")); + debug("Data DQS pins set for 8 pins\n"); break; case 0x20: /* memory is x32 */ /* both bits are cleared for x32 so nothing to do */ - DP (printf ("Data DQS pins set for 2 pins\n")); + debug("Data DQS pins set for 2 pins\n"); break; default: /* memory width unsupported */ printf ("DRAM chip width is unknown!\n"); @@ -1392,21 +1375,21 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* write the value into the SDRAM configuration register */ GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages control keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf + debug ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug + ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Latency according to SPD information */ switch (info->memoryType) { @@ -1419,7 +1402,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Calculate the settings for SDRAM mode and Dunit control low registers */ /* Values set according to technical bulletin TB-92 rev. c */ case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); /* ronen db64460 - change the tmp_dunit_control_low setting!!! */ switch (info->maxClSupported_DDR) { case DDR_CL_3: @@ -1429,9 +1412,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x05110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1439,9 +1422,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC5000540; else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2_5: @@ -1451,9 +1434,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x25110051; else tmp_dunit_control_low = 0x24110051; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1464,9 +1447,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* hang();1 */ } else tmp_dunit_control_low = 0xC4000540; - DP (printf + debug ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_2: @@ -1476,9 +1459,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x04110051; else tmp_dunit_control_low = 0x03110051; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1489,9 +1472,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540;; - DP (printf + debug ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; case DDR_CL_1_5: @@ -1501,9 +1484,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0x24110051; else tmp_dunit_control_low = 0x23110051; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n"); } else { /* clk sync. bypassed */ @@ -1514,9 +1497,9 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp_dunit_control_low = 0xC4000540; } else tmp_dunit_control_low = 0xC3000540; - DP (printf + debug ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1536,8 +1519,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ @@ -1546,8 +1529,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug + ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1557,29 +1540,29 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* program this with the default value */ tmp = 0x02; /* power-up default address select decoding value */ - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); /* figure out the DRAM chip size */ sdram_chip_size = (1 << (info->numOfRowAddresses + info->numOfColAddresses)); sdram_chip_size *= info->sdramWidth; sdram_chip_size *= 4; - DP (printf ("computed sdram chip size is %#lx\n", sdram_chip_size)); + debug("computed sdram chip size is %#lx\n", sdram_chip_size); /* divide sdram chip size by 64 Mbits */ sdram_chip_size = sdram_chip_size / 0x4000000; switch (sdram_chip_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: @@ -1590,15 +1573,15 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* SDRAM address control */ GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); - DP (printf + debug ("setting up sdram address control (0x1410) with: %08lx \n", - tmp)); + tmp); /* ------------------------------------------------------------------------------ */ /* same settings for registerd & non-registerd DDR SDRAM */ - DP (printf + debug ("setting up sdram_timing_control_low (0x1408) with: %08x \n", - 0x01501220)); + 0x01501220); /*ronen db64460 */ GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220); @@ -1611,10 +1594,10 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf + debug ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU @@ -1624,29 +1607,29 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As 4460 */ tmp |= (1 << 26); - DP (printf + debug ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf + GTREGREAD (SDRAM_CONFIG)); + debug ("After Buffer assignment - sdram_conf (0x1400): %08x\n", - GTREGREAD (SDRAM_CONFIG))); + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ /* ------------------------------------------------------------------------------ */ /* ronen db64460 */ - DP (printf + debug ("setting up sdram_timing_control_high (0x140c) with: %08x \n", - 0xc)); + 0xc); GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc); - DP (printf + debug ("setting up sdram address pads control (0x14c0) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); - DP (printf + debug ("setting up sdram data pads control (0x14c4) with: %08x \n", - 0x7d5014a)); + 0x7d5014a); GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); /* ------------------------------------------------------------------------------ */ @@ -1656,8 +1639,8 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug + ("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1665,17 +1648,17 @@ indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". As /* set SDRAM mode */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0); check = GTREGREAD (SDRAM_OPERATION); - DP (printf + debug ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + check); /* unmap the bank */ memory_map_bank (i, 0, 0); @@ -1721,9 +1704,9 @@ long int dram_size (long int *base, long int maxsize) *b = save2; if (val != cnt) { - DP (printf + debug ("Found %08x at Address %08x (failure)\n", - (unsigned int) val, (unsigned int) addr)); + (unsigned int) val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if (cnt == STARTVAL / sizeof (long)) cnt = 0; @@ -1739,9 +1722,8 @@ long int dram_size (long int *base, long int maxsize) * controlling logic happens */ phys_size_t initdram (int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = {[0 ... 3] = 0 }; - ulong realsize, total, check; + ulong realsize, total; AUX_MEM_DIMM_INFO dimmInfo1; AUX_MEM_DIMM_INFO dimmInfo2; int nhr, bank_no; @@ -1756,10 +1738,10 @@ phys_size_t initdram (int board_type) printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm (0, &dimmInfo1); + check_dimm (0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm (1, &dimmInfo2); + check_dimm (1, &dimmInfo2); memory_map_bank (0, 0, 0); memory_map_bank (1, 0, 0); @@ -1793,7 +1775,6 @@ phys_size_t initdram (int board_type) /* next, size the SDRAM banks */ realsize = total = 0; - check = GB / 4; if (dimmInfo1.numOfModuleBanks > 0) { checkbank[0] = 1; } diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile index 9134856..c56bcf8 100644 --- a/board/afeb9260/Makefile +++ b/board/afeb9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index f0e2e80..dda69e0 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org> * diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 1351358..f438c15 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -36,21 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - static struct davinci_timer *timer = (struct davinci_timer *)DAVINCI_TIMER3_BASE; diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index 359f590..59fd465 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -32,7 +32,6 @@ LIB = $(obj)lib$(BOARD).o COBJS-y := $(BOARD).o COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o COBJS-$(CONFIG_EPLED) += ../common/epled.o -COBJS-$(CONFIG_GPIO) += gpio.o COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o SOBJS-y := text_base.o diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index f7f3853..fd3ec9a 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -51,6 +51,7 @@ /* led_pio.s1 is a altera_avalon_pio */ #define LED_PIO_BASE 0x82120870 #define LED_PIO_WIDTH 8 +#define LED_PIO_RSTVAL 0x0 /* high_res_timer.s1 is a altera_avalon_timer */ #define CONFIG_SYS_TIMER_BASE 0x82120820 diff --git a/board/altera/nios2-generic/gpio.c b/board/altera/nios2-generic/gpio.c deleted file mode 100644 index 4a30564..0000000 --- a/board/altera/nios2-generic/gpio.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * board gpio driver - * - * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> - * Licensed under the GPL-2 or later. - */ -#include <common.h> -#include <asm/io.h> - -#ifndef CONFIG_SYS_GPIO_BASE - -#define ALTERA_PIO_BASE LED_PIO_BASE -#define ALTERA_PIO_WIDTH LED_PIO_WIDTH -#define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0) -#define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4) -static u32 pio_data_reg; -static u32 pio_dir_reg; - -int gpio_request(unsigned gpio, const char *label) -{ - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - u32 mask = 1 << gpio; - writel(pio_dir_reg &= ~mask, ALTERA_PIO_DIR); - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - u32 mask = 1 << gpio; - if (value) - pio_data_reg |= mask; - else - pio_data_reg &= ~mask; - writel(pio_data_reg, ALTERA_PIO_DATA); - writel(pio_dir_reg |= mask, ALTERA_PIO_DIR); - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - u32 mask = 1 << gpio; - if (pio_dir_reg & mask) - return (pio_data_reg & mask) ? 1 : 0; - else - return (readl(ALTERA_PIO_DATA) & mask) ? 1 : 0; -} - -void gpio_set_value(unsigned gpio, int value) -{ - u32 mask = 1 << gpio; - if (value) - pio_data_reg |= mask; - else - pio_data_reg &= ~mask; - writel(pio_data_reg, ALTERA_PIO_DATA); -} - -int gpio_is_valid(int number) -{ - return ((unsigned)number) < ALTERA_PIO_WIDTH; -} -#endif diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c index 49ef80d..0f88275 100644 --- a/board/altera/nios2-generic/nios2-generic.c +++ b/board/altera/nios2-generic/nios2-generic.c @@ -26,6 +26,7 @@ #include <netdev.h> #include <mtd/cfi_flash.h> #include <asm/io.h> +#include <asm/gpio.h> void text_base_hook(void); /* nop hook for text_base.S */ @@ -43,6 +44,13 @@ void early_flash_cmd_reset(void) int board_early_init_f(void) { text_base_hook(); +#ifdef CONFIG_ALTERA_PIO +#ifdef LED_PIO_BASE + altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o', + LED_PIO_RSTVAL, (1 << LED_PIO_WIDTH) - 1, + "led"); +#endif +#endif #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) early_flash_cmd_reset(); #endif diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index 8f23375..1960fc1 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -396,7 +396,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -427,8 +427,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -454,7 +452,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -825,7 +822,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -856,8 +853,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) printf("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -883,7 +878,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c index e9fbbb1..63968a4 100644 --- a/board/amcc/taihu/flash.c +++ b/board/amcc/taihu/flash.c @@ -511,7 +511,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -542,8 +542,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -569,7 +567,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -953,7 +950,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -984,8 +981,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) printf("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -1011,7 +1006,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index e9cd333..f45325e 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -51,7 +51,6 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, uchar chip; ulong data; int nbytes; - extern char console_buffer[]; char sysClock[4]; char cpuClock[4]; diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index 20b6af9..ab513f9 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -422,7 +422,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -449,8 +449,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -476,7 +474,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must @@ -831,7 +828,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -858,8 +855,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) printf("\n"); - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -885,7 +880,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c index 1e742e5..bf8877e 100644 --- a/board/amirix/ap1000/flash.c +++ b/board/amirix/ap1000/flash.c @@ -774,12 +774,9 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword) { - - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr (info, 0, 0); cptr.cp = (uchar *) dest; /* Check if Flash is (sufficiently) erased */ diff --git a/board/armltd/integrator/arm-ebi.h b/board/armltd/integrator/arm-ebi.h new file mode 100644 index 0000000..2d85e3f --- /dev/null +++ b/board/armltd/integrator/arm-ebi.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Register definitions for the External Bus Interface (EBI) + * found in the ARM Integrator AP and CP reference designs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARM_EBI_H +#define __ARM_EBI_H + +#define EBI_BASE 0x12000000 + +#define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ +#define EBI_CSR1_REG 0x04 /* CS1 = Flash */ +#define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ +#define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ +/* + * The four upper bits are the waitstates for each chip select + * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles + */ +#define EBI_CSR_WAIT_MASK 0xF0 +/* Whether memory is synchronous or asynchronous */ +#define EBI_CSR_SYNC_MASK 0xF7 +#define EBI_CSR_ASYNC 0x00 +#define EBI_CSR_SYNC 0x08 +/* Whether memory is write enabled or not */ +#define EBI_CSR_WREN_MASK 0xFB +#define EBI_CSR_WREN_DISABLE 0x00 +#define EBI_CSR_WREN_ENABLE 0x04 +/* Memory bit width for each chip select */ +#define EBI_CSR_MEMSIZE_MASK 0xFC +#define EBI_CSR_MEMSIZE_8BIT 0x00 +#define EBI_CSR_MEMSIZE_16BIT 0x01 +#define EBI_CSR_MEMSIZE_32BIT 0x02 + +/* + * The lock register need to be written with 0xa05f before anything in the + * EBI can be changed. + */ +#define EBI_LOCK_REG 0x20 +#define EBI_UNLOCK_MAGIC 0xA05F + +#endif diff --git a/board/armltd/integrator/config.mk b/board/armltd/integrator/config.mk deleted file mode 100644 index 8b57af1..0000000 --- a/board/armltd/integrator/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# image should be loaded at 0x01000000 -# - -CONFIG_SYS_TEXT_BASE = 0x01000000 diff --git a/board/armltd/integrator/integrator-sc.h b/board/armltd/integrator/integrator-sc.h new file mode 100644 index 0000000..279dc55 --- /dev/null +++ b/board/armltd/integrator/integrator-sc.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2011 + * Linaro + * Linus Walleij <linus.walleij@linaro.org> + * Register definitions for the System Controller (SC) and + * the similar "CP Controller" found in the ARM Integrator/AP and + * Integrator/CP reference designs + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARM_SC_H +#define __ARM_SC_H + +#define SC_BASE 0x11000000 + +/* + * The system controller registers + */ +#define SC_ID_OFFSET 0x00 +#define SC_OSC_OFFSET 0x04 +/* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ +#define SC_OSC_DIVXY (1 << 8) +#define SC_CTRLS_OFFSET 0x08 +#define SC_CTRLC_OFFSET 0x0C +/* Set bits by writing CTRLS, clear bits by writing CTRLC */ +#define SC_CTRL_SOFTRESET (1 << 0) +#define SC_CTRL_FLASHVPP (1 << 1) +#define SC_CTRL_FLASHWP (1 << 2) +#define SC_CTRL_UART1DTR (1 << 4) +#define SC_CTRL_UART1RTS (1 << 5) +#define SC_CTRL_UART0DTR (1 << 6) +#define SC_CTRL_UART0RTS (1 << 7) +#define SC_DEC_OFFSET 0x10 +#define SC_ARB_OFFSET 0x14 +#define SC_PCI_OFFSET 0x18 +#define SC_PCI_PCIEN (1 << 0) +#define SC_PCI_PCIBINT_CLR (1 << 1) +#define SC_LOCK_OFFSET 0x1C +#define SC_LBFADDR_OFFSET 0x20 +#define SC_LBFCODE_OFFSET 0x24 + +#define SC_ID (SC_BASE + SC_ID_OFFSET) +#define SC_OSC (SC_BASE + SC_OSC_OFFSET) +#define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET) +#define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET) +#define SC_DEC (SC_BASE + SC_DEC_OFFSET) +#define SC_ARB (SC_BASE + SC_ARB_OFFSET) +#define SC_PCI (SC_BASE + SC_PCI_OFFSET) +#define SC_LOCK (SC_BASE + SC_LOCK_OFFSET) +#define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET) +#define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET) + +/* + * The Integrator/CP as a smaller set of registers, at a different + * offset - probably not to disturb old software. + */ + +#define CP_BASE 0xCB000000 + +#define CP_IDFIELD_OFFSET 0x00 +#define CP_FLASHPROG_OFFSET 0x04 +#define CP_FLASHPROG_FLVPPEN (1 << 0) +#define CP_FLASHPROG_FLWREN (1 << 1) +#define CP_FLASHPROG_FLASHSIZE (1 << 2) +#define CP_FLASHPROG_EXTRABANK (1 << 3) +#define CP_INTREG_OFFSET 0x08 +#define CP_DECODE_OFFSET 0x0C + +#define CP_IDFIELD (CP_BASE + CP_ID_OFFSET) +#define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET) +#define CP_INTREG (CP_BASE + CP_INTREG_OFFSET) +#define CP_DECODE (CP_BASE + CP_DECODE_OFFSET) + +#endif diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index c8d2bc7..a507c09 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -35,6 +35,9 @@ #include <common.h> #include <netdev.h> +#include <asm/io.h> +#include "arm-ebi.h" +#include "integrator-sc.h" DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +58,8 @@ void show_boot_progress(int progress) int board_init (void) { + u32 val; + /* arch number of Integrator Board */ #ifdef CONFIG_ARCH_CINTEGRATOR gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; @@ -72,6 +77,37 @@ extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif +#ifdef CONFIG_ARCH_CINTEGRATOR + /* + * Flash protection on the Integrator/CP is in a simple register + */ + val = readl(CP_FLASHPROG); + val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); + writel(val, CP_FLASHPROG); +#else + /* + * The Integrator/AP has some special protection mechanisms + * for the external memories, first the External Bus Interface (EBI) + * then the system controller (SC). + * + * The system comes up with the flash memory non-writable and + * configuration locked. If we want U-Boot to be used for flash + * access we cannot have the flash memory locked. + */ + writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); + val = readl(EBI_BASE + EBI_CSR1_REG); + val &= EBI_CSR_WREN_MASK; + val |= EBI_CSR_WREN_ENABLE; + writel(val, EBI_BASE + EBI_CSR1_REG); + writel(0, EBI_BASE + EBI_LOCK_REG); + + /* + * Set up the system controller to remove write protection from + * the flash memory and enable Vpp + */ + writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); +#endif + icache_enable (); return 0; @@ -86,21 +122,30 @@ int misc_init_r (void) return (0); } +/* + * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot + * from there, which means we cannot test the RAM underneath the ROM at this + * point. It will be unmapped later on, when we are executing from the + * relocated in RAM U-Boot. We simply assume that this RAM is usable if the + * RAM on higher addresses works fine. + */ +#define REMAPPED_FLASH_SZ 0x40000 + int dram_init (void) { gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); - unsigned long cm_reg_sdram; - unsigned long sdram_shift; + u32 cm_reg_sdram; + u32 sdram_shift; dram_query(); /* Assembler accesses to CM registers */ /* Queries the SPD values */ /* Obtain the SDRAM size from the CM SDRAM register */ - cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); + cm_reg_sdram = readl(CM_BASE + OS_SDRAM); /* Register SDRAM size * * 0xXXXXXXbbb000bb 16 MB @@ -110,16 +155,18 @@ extern void dram_query(void); * 0xXXXXXXbbb100bb 256 MB * */ - sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + REMAPPED_FLASH_SZ, 0x01000000 << sdram_shift); } #else - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + + REMAPPED_FLASH_SZ, PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ + /* We only have one bank of RAM, set it to whatever was detected */ + gd->bd->bi_dram[0].size = gd->ram_size; return 0; } diff --git a/board/atmel/at91sam9260ek/Makefile b/board/atmel/at91sam9260ek/Makefile index b9ecc88..66706eb 100644 --- a/board/atmel/at91sam9260ek/Makefile +++ b/board/atmel/at91sam9260ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index b3ed91d..2555672 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index daf81e8..9bdd385 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/Makefile b/board/atmel/at91sam9261ek/Makefile index 080f289..f44dcdb 100644 --- a/board/atmel/at91sam9261ek/Makefile +++ b/board/atmel/at91sam9261ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index b6c7d9e..47ab839 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9261ek/led.c b/board/atmel/at91sam9261ek/led.c index 0c2f522..7fa6136 100644 --- a/board/atmel/at91sam9261ek/led.c +++ b/board/atmel/at91sam9261ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 8493043..af8726d 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 4d2937d..41ec752 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9263ek/led.c b/board/atmel/at91sam9263ek/led.c index c44455e..ce3cf09 100644 --- a/board/atmel/at91sam9263ek/led.c +++ b/board/atmel/at91sam9263ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/Makefile b/board/atmel/at91sam9m10g45ek/Makefile index 6c37827..1915111 100644 --- a/board/atmel/at91sam9m10g45ek/Makefile +++ b/board/atmel/at91sam9m10g45ek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 24a8606..5a04274 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index dadbd6a..0fd38f6 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/Makefile b/board/atmel/at91sam9rlek/Makefile index 7de8897..36df7af 100644 --- a/board/atmel/at91sam9rlek/Makefile +++ b/board/atmel/at91sam9rlek/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index e559084..ef0ddd7 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/atmel/at91sam9rlek/led.c b/board/atmel/at91sam9rlek/led.c index 987e8c0..4a1e8d7 100644 --- a/board/atmel/at91sam9rlek/led.c +++ b/board/atmel/at91sam9rlek/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 26e34e9..f360323 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/pxa.h> #include <serial.h> #include <asm/io.h> #include <spartan3.h> @@ -57,10 +58,9 @@ struct serial_device *default_serial_console(void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/calao/sbc35_a9g20/Makefile b/board/calao/sbc35_a9g20/Makefile index 7b7cc29..8a0618e 100644 --- a/board/calao/sbc35_a9g20/Makefile +++ b/board/calao/sbc35_a9g20/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index 5f448d9..4f5cff6 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * Copyright (C) 2009 diff --git a/board/calao/tny_a9260/Makefile b/board/calao/tny_a9260/Makefile index 1bf21e1..5a6c6b8 100644 --- a/board/calao/tny_a9260/Makefile +++ b/board/calao/tny_a9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index ab51a33..24de177 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * Copyright (C) 2009 diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c deleted file mode 100644 index 043afea..0000000 --- a/board/cerf250/cerf250.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of cerf PXA Board */ - gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c deleted file mode 100644 index e1e7807..0000000 --- a/board/cerf250/flash.c +++ /dev/null @@ -1,429 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 2e1356f..5522bf0 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -206,7 +206,7 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type; int rcode = 0; ulong start; @@ -240,7 +240,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -370,7 +370,6 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) { volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -380,7 +379,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = 0x40; /* write setup */ *addr = data; diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 2e1356f..5522bf0 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -206,7 +206,7 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type; int rcode = 0; ulong start; @@ -240,7 +240,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) printf ("\n"); /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -370,7 +370,6 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) { volatile unsigned char *addr = (volatile unsigned char *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -380,7 +379,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = 0x40; /* write setup */ *addr = data; diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c deleted file mode 100644 index 2bbf2d5..0000000 --- a/board/cradle/cradle.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/pxa-regs.h> -#include <common.h> -#include <netdev.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* local prototypes */ -void set_led (int led, int color); -void error_code_halt (int code); -int init_sio (int led, unsigned long base); -inline void cradle_outb (unsigned short val, unsigned long base, - unsigned long reg); -inline unsigned char cradle_inb (unsigned long base, unsigned long reg); -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -void -/**********************************************************/ -error_code_halt (int code) -/**********************************************************/ -{ - while (1) { - led_code (code, RED); - sleep (1); - led_code (0, OFF); - sleep (1); - } -} - -void -/**********************************************************/ -led_code (int code, int color) -/**********************************************************/ -{ - int i; - - code &= 0xf; /* only 4 leds */ - - for (i = 0; i < 4; i++) { - if (code & (1 << i)) { - set_led (i, color); - } else { - set_led (i, OFF); - } - } -} - -void -/**********************************************************/ -set_led (int led, int color) -/**********************************************************/ -{ - int shift = led * 2; - unsigned long mask = 0x3 << shift; - - writel(mask, GPCR2); /* clear bits */ - writel((color << shift), GPSR2); /* set bits */ - udelay (5000); -} - -inline void -/**********************************************************/ -cradle_outb (unsigned short val, unsigned long base, unsigned long reg) -/**********************************************************/ -{ - *(volatile unsigned short *) (base + (reg * 2)) = val; -} - -inline unsigned char -/**********************************************************/ -cradle_inb (unsigned long base, unsigned long reg) -/**********************************************************/ -{ - unsigned short val; - - val = *(volatile unsigned short *) (base + (reg * 2)); - return (val & 0xff); -} - -int -/**********************************************************/ -init_sio (int led, unsigned long base) -/**********************************************************/ -{ - unsigned char val; - - set_led (led, YELLOW); - val = cradle_inb (base, CRADLE_SIO_INDEX); - val = cradle_inb (base, CRADLE_SIO_INDEX); - if (val != 0) { - set_led (led, RED); - return -1; - } - - /* map SCC2 to COM1 */ - cradle_outb (0x01, base, CRADLE_SIO_INDEX); - cradle_outb (0x00, base, CRADLE_SIO_DATA); - - /* enable SCC2 extended regs */ - cradle_outb (0x40, base, CRADLE_SIO_INDEX); - cradle_outb (0xa0, base, CRADLE_SIO_DATA); - - /* enable SCC2 clock multiplier */ - cradle_outb (0x51, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* enable SCC2 */ - cradle_outb (0x00, base, CRADLE_SIO_INDEX); - cradle_outb (0x04, base, CRADLE_SIO_DATA); - - /* map SCC2 DMA to channel 0 */ - cradle_outb (0x4f, base, CRADLE_SIO_INDEX); - cradle_outb (0x09, base, CRADLE_SIO_DATA); - - /* read ID from SIO to check operation */ - cradle_outb (0xe4, base, 0x3f8 + 0x3); - val = cradle_inb (base, 0x3f8 + 0x0); - if ((val & 0xf0) != 0x20) { - set_led (led, RED); - /* disable SCC2 */ - cradle_outb (0, base, CRADLE_SIO_INDEX); - cradle_outb (0, base, CRADLE_SIO_DATA); - return -1; - } - /* set back to bank 0 */ - cradle_outb (0, base, 0x3f8 + 0x3); - set_led (led, GREEN); - return 0; -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_late_init (void) -/**********************************************************/ -{ - return (0); -} - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - led_code (0xf, YELLOW); - - /* arch number of HHP Cradle */ - gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - /* Init SIOs to enable SCC2 */ - udelay (100000); /* delay makes it look neat */ - init_sio (0, CRADLE_SIO1_PHYS); - udelay (100000); - init_sio (1, CRADLE_SIO2_PHYS); - udelay (100000); - init_sio (2, CRADLE_SIO3_PHYS); - udelay (100000); - set_led (3, GREEN); - - return 1; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/cradle/flash.c b/board/cradle/flash.c deleted file mode 100644 index 1601782..0000000 --- a/board/cradle/flash.c +++ /dev/null @@ -1,361 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define FLASH_BANK_SIZE 0x400000 -#define MAIN_SECT_SIZE 0x20000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i, j; - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F320J3A & FLASH_TYPEMASK): - printf ("28F320J3A (32Mbit)\n"); - break; - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while ((*addr & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - /* clear status register command */ - *addr = 0x50; - /* reset to read mode */ - *addr = 0xFF; - } - printf ("ok.\n"); - } - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((*addr & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((val = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0xB0; - goto outahere; - } - } - - if (val & 0x1A) { /* check for error */ - printf ("\nFlash write error %02x at address %08lx\n", - (int) val, (unsigned long) dest); - if (val & (1 << 3)) { - printf ("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if (val & (1 << 1)) { - printf ("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if (val & (1 << 4)) { - printf ("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0xFF; - - if (flag) - enable_interrupts (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c index a3d893e..77a2100 100644 --- a/board/cray/L1/flash.c +++ b/board/cray/L1/flash.c @@ -273,7 +273,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; if ((s_first < 0) || (s_first > s_last)) { if (info->flash_id == FLASH_UNKNOWN) { @@ -303,16 +303,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); - printf("Erasing sector %p\n", addr2); + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; @@ -320,15 +318,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ - l_sect = sect; - /* - * Wait for each sector to complete, it's more - * reliable. According to AMD Spec, you must - * issue all erase commands within a specified - * timeout. This has been seen to fail, especially - * if printf()s are included (for debug)!! - */ - wait_for_DQ7(info, sect); + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); } } diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c deleted file mode 100644 index dd29e62..0000000 --- a/board/csb226/csb226.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa-regs.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ -#if 0 - uchar *str; - - /* determine if the software update key is pressed during startup */ - /* not ported yet... */ - if (GPLR0 & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); -#endif - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of CSB226 board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB226; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/** - * csb226_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void csb226_set_led(int led, int state) -{ - switch(led) { - - case 0: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0); - } - break; - - case 1: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0); - } - break; - - case 2: if (state==1) { - writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0); - } else if (state==0) { - writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0); - } - break; - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; - } - - return; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/csb226/flash.c b/board/csb226/flash.c deleted file mode 100644 index e103470..0000000 --- a/board/csb226/flash.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> - * - * (C) Copyright 2003 (2 x 16 bit Flash bank patches) - * Rolf Peukert, IMMS gGmbH, <rolf.peukert@imms.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/pxa-regs.h> - -#define FLASH_BANK_SIZE 0x02000000 -#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - u32 * volatile addr = (u32 * volatile)(info->start[sect]); - - /* erase sector: */ - /* The strata flashs are aligned side by side on */ - /* the data bus, so we have to write the commands */ - /* to both chips here: */ - - *addr = 0x00200020; /* erase setup */ - *addr = 0x00D000D0; /* erase confirm */ - - while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x00B000B0; /* suspend erase*/ - *addr = 0x00FF00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* reset to read mode */ - } - printf("ok.\n"); - } - if (ctrlc()) printf("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - -/** - * write_long: - copy memory to flash, assume a bank of 2 devices with 16bit each - */ - -static int write_long (flash_info_t *info, ulong dest, ulong data) -{ - u32 * volatile addr = (u32 * volatile)dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* read array command - just for the case... */ - *addr = 0x00FF00FF; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x00500050; - - /* program set-up command */ - *addr = 0x00400040; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - /* suspend program command */ - *addr = 0x00B000B0; - goto outahere; - } - } - - /* check for errors */ - if(val & 0x001A001A) { - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & 0x00080008) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & 0x00020002) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & 0x00100010) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - -outahere: - /* read array command */ - *addr = 0x00FF00FF; - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -/* "long" version, uses 32bit words */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ulong data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - for (; i<4 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((ulong*)src); - if ((rc = write_long(info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 24); - } - - return write_long(info, wp, data); -} diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 665aedf..c41f11d 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -231,7 +231,7 @@ static void board_nand_setup(void) mxc_setup_weimcs(3, &cs3); - __REG(IOMUXC_GPR) |= 1 << 13; + mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO)); diff --git a/board/davinci/common/davinci_pinmux.c b/board/davinci/common/davinci_pinmux.c deleted file mode 100644 index ce58f71..0000000 --- a/board/davinci/common/davinci_pinmux.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * DaVinci pinmux functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <common.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> - -/* - * Change the setting of a pin multiplexer field. - * - * Takes an array of pinmux settings similar to: - * - * struct pinmux_config uart_pins[] = { - * { &davinci_syscfg_regs->pinmux[8], 2, 7 }, - * { &davinci_syscfg_regs->pinmux[9], 2, 0 } - * }; - * - * Stepping through the array, each pinmux[n] register has the given value - * set in the pin mux field specified. - * - * The number of pins in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Returns 0 if all field numbers and values are in the correct range, - * else returns -1. - */ -int davinci_configure_pin_mux(const struct pinmux_config *pins, - const int n_pins) -{ - int i; - - /* check for invalid pinmux values */ - for (i = 0; i < n_pins; i++) { - if (pins[i].field >= PIN_MUX_NUM_FIELDS || - (pins[i].value & ~PIN_MUX_FIELD_MASK) != 0) - return -1; - } - - /* configure the pinmuxes */ - for (i = 0; i < n_pins; i++) { - const int offset = pins[i].field * PIN_MUX_FIELD_SIZE; - const unsigned int value = pins[i].value << offset; - const unsigned int mask = PIN_MUX_FIELD_MASK << offset; - const dv_reg *mux = pins[i].mux; - - writel(value | (readl(mux) & (~mask)), mux); - } - - return 0; -} - -/* - * Configure multiple pinmux resources. - * - * Takes an pinmux_resource array of pinmux_config and pin counts: - * - * const struct pinmux_resource pinmuxes[] = { - * PINMUX_ITEM(uart_pins), - * PINMUX_ITEM(i2c_pins), - * }; - * - * The number of items in the array must be passed (ARRAY_SIZE can provide - * this value conveniently). - * - * Each item entry is configured in the defined order. If configuration - * of any item fails, -1 is returned and none of the following items are - * configured. On success, 0 is returned. - */ -int davinci_configure_pin_mux_items(const struct pinmux_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) { - if (davinci_configure_pin_mux(item[i].pins, - item[i].n_pins) != 0) - return -1; - } - - return 0; -} diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c deleted file mode 100644 index 5aa7605..0000000 --- a/board/davinci/common/misc.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Miscelaneous DaVinci functions. - * - * Copyright (C) 2009 Nick Thompson, GE Fanuc Ltd, <nick.thompson@gefanuc.com> - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <common.h> -#include <i2c.h> -#include <net.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <asm/arch/davinci_misc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_SPL_BUILD -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} -#endif - -#ifdef CONFIG_DRIVER_TI_EMAC - -/* Read ethernet MAC address from EEPROM for DVEVM compatible boards. - * Returns 1 if found, 0 otherwise. - */ -int dvevm_read_mac_address(uint8_t *buf) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - (uint8_t *) &buf[0], 6)) - goto i2cerr; - - /* Check that MAC address is valid. */ - if (!is_valid_ether_addr(buf)) - goto err; - - return 1; /* Found */ - -i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); -err: -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ - - return 0; -} - -/* - * Set the mii mode as MII or RMII - */ -#if defined(CONFIG_SOC_DA8XX) -void davinci_emac_mii_mode_sel(int mode_sel) -{ - int val; - - val = readl(&davinci_syscfg_regs->cfgchip3); - if (mode_sel == 0) - val &= ~(1 << 8); - else - val |= (1 << 8); - writel(val, &davinci_syscfg_regs->cfgchip3); -} -#endif -/* - * If there is no MAC address in the environment, then it will be initialized - * (silently) from the value in the EEPROM. - */ -void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) -{ - uint8_t env_enetaddr[6]; - - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { - /* There is no MAC address in the environment, so we initialize - * it from the value in the EEPROM. */ - debug("### Setting environment from EEPROM MAC address = " - "\"%pM\"\n", - env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); - } -} - -#endif /* CONFIG_DRIVER_TI_EMAC */ - -#if defined(CONFIG_SOC_DA8XX) -#ifndef CONFIG_USE_IRQ -void irq_init(void) -{ - /* - * Mask all IRQs by clearing the global enable and setting - * the enable clear for all the 90 interrupts. - */ - - writel(0, &davinci_aintc_regs->ger); - - writel(0, &davinci_aintc_regs->hier); - - writel(0xffffffff, &davinci_aintc_regs->ecr1); - writel(0xffffffff, &davinci_aintc_regs->ecr2); - writel(0xffffffff, &davinci_aintc_regs->ecr3); -} -#endif - -/* - * Enable PSC for various peripherals. - */ -int da8xx_configure_lpsc_items(const struct lpsc_resource *item, - const int n_items) -{ - int i; - - for (i = 0; i < n_items; i++) - lpsc_on(item[i].lpsc_no); - - return 0; -} -#endif diff --git a/board/davinci/da8xxevm/da830evm.c b/board/davinci/da8xxevm/da830evm.c index 2021e73..c45c94b 100644 --- a/board/davinci/da8xxevm/da830evm.c +++ b/board/davinci/da8xxevm/da830evm.c @@ -46,8 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - /* SPI0 pin muxer settings */ static const struct pinmux_config spi0_pins[] = { { pinmux(7), 1, 3 }, diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index e0a3bbe..9c0eade 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -28,137 +28,14 @@ #include <asm/arch/hardware.h> #include <asm/arch/emif_defs.h> #include <asm/arch/emac_defs.h> +#include <asm/arch/pinmux_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> #include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - -/* SPI0 pin muxer settings */ -static const struct pinmux_config spi1_pins[] = { - { pinmux(5), 1, 1 }, - { pinmux(5), 1, 2 }, - { pinmux(5), 1, 4 }, - { pinmux(5), 1, 5 } -}; - -/* UART pin muxer settings */ -static const struct pinmux_config uart_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - #ifdef CONFIG_DRIVER_TI_EMAC -static const struct pinmux_config emac_pins[] = { -#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII - { pinmux(14), 8, 2 }, - { pinmux(14), 8, 3 }, - { pinmux(14), 8, 4 }, - { pinmux(14), 8, 5 }, - { pinmux(14), 8, 6 }, - { pinmux(14), 8, 7 }, - { pinmux(15), 8, 1 }, -#else /* ! CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 }, - { pinmux(3), 8, 0 }, - { pinmux(3), 8, 1 }, - { pinmux(3), 8, 2 }, - { pinmux(3), 8, 3 }, - { pinmux(3), 8, 4 }, - { pinmux(3), 8, 5 }, - { pinmux(3), 8, 6 }, - { pinmux(3), 8, 7 }, -#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */ - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -/* I2C pin muxer settings */ -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 2 }, - { pinmux(4), 2, 3 } -}; - -#ifdef CONFIG_NAND_DAVINCI -const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; -#elif defined(CONFIG_USE_NOR) -/* NOR pin muxer settings */ -const struct pinmux_config nor_pins[] = { - /* GP0[11] is required for NOR to work on Rev 3 EVMs */ - { pinmux(0), 8, 4 }, /* GP0[11] */ - { pinmux(5), 1, 6 }, - { pinmux(6), 1, 6 }, - { pinmux(7), 1, 0 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(8), 1, 0 }, - { pinmux(8), 1, 1 }, - { pinmux(8), 1, 2 }, - { pinmux(8), 1, 3 }, - { pinmux(8), 1, 4 }, - { pinmux(8), 1, 5 }, - { pinmux(8), 1, 6 }, - { pinmux(8), 1, 7 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(10), 1, 0 }, - { pinmux(10), 1, 1 }, - { pinmux(10), 1, 2 }, - { pinmux(10), 1, 3 }, - { pinmux(10), 1, 4 }, - { pinmux(10), 1, 5 }, - { pinmux(10), 1, 6 }, - { pinmux(10), 1, 7 }, - { pinmux(11), 1, 0 }, - { pinmux(11), 1, 1 }, - { pinmux(11), 1, 2 }, - { pinmux(11), 1, 3 }, - { pinmux(11), 1, 4 }, - { pinmux(11), 1, 5 }, - { pinmux(11), 1, 6 }, - { pinmux(11), 1, 7 }, - { pinmux(12), 1, 0 }, - { pinmux(12), 1, 1 }, - { pinmux(12), 1, 2 }, - { pinmux(12), 1, 3 }, - { pinmux(12), 1, 4 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 }, - { pinmux(12), 1, 7 } -}; -#endif - #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII #define HAS_RMII 1 #else @@ -224,17 +101,38 @@ int misc_init_r(void) return 0; } +static const struct pinmux_config gpio_pins[] = { +#ifdef CONFIG_USE_NOR + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif +}; + static const struct pinmux_resource pinmuxes[] = { +#ifdef CONFIG_DRIVER_TI_EMAC + PINMUX_ITEM(emac_pins_mdio), +#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII + PINMUX_ITEM(emac_pins_rmii), +#else + PINMUX_ITEM(emac_pins_mii), +#endif +#endif #ifdef CONFIG_SPI_FLASH - PINMUX_ITEM(spi1_pins), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), #endif - PINMUX_ITEM(uart_pins), - PINMUX_ITEM(i2c_pins), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(i2c0_pins), #ifdef CONFIG_NAND_DAVINCI - PINMUX_ITEM(nand_pins), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), #elif defined(CONFIG_USE_NOR) - PINMUX_ITEM(nor_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_nor), #endif + PINMUX_ITEM(gpio_pins), }; static const struct lpsc_resource lpsc[] = { @@ -249,6 +147,8 @@ static const struct lpsc_resource lpsc[] = { #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 #endif +#define REV_AM18X_EVM 0x100 + /* * get_board_rev() - setup to pass kernel board revision information * Returns: @@ -274,7 +174,9 @@ u32 get_board_rev(void) rev = 2; else if (maxcpuclk >= 372000000) rev = 1; - +#ifdef CONFIG_DA850_AM18X_EVM + rev |= REV_AM18X_EVM; +#endif return rev; } @@ -346,9 +248,6 @@ int board_init(void) #endif #ifdef CONFIG_DRIVER_TI_EMAC - if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) - return 1; - davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index f34830e..9d4e238 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -47,8 +47,8 @@ int board_early_init_f(void) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* set cfgchip3 to select mii */ writel(readl(&davinci_syscfg_regs->cfgchip3) & diff --git a/board/davinci/da8xxevm/hawkboard_nand_spl.c b/board/davinci/da8xxevm/hawkboard_nand_spl.c index e5e65e5..df97963 100644 --- a/board/davinci/da8xxevm/hawkboard_nand_spl.c +++ b/board/davinci/da8xxevm/hawkboard_nand_spl.c @@ -27,63 +27,20 @@ #include <asm/arch/hardware.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <asm/arch/pinmux_defs.h> #include <ns16550.h> #include <nand.h> DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - -static const struct pinmux_config mii_pins[] = { - { pinmux(2), 8, 1 }, - { pinmux(2), 8, 2 }, - { pinmux(2), 8, 3 }, - { pinmux(2), 8, 4 }, - { pinmux(2), 8, 5 }, - { pinmux(2), 8, 6 }, - { pinmux(2), 8, 7 } -}; - -static const struct pinmux_config mdio_pins[] = { - { pinmux(4), 8, 0 }, - { pinmux(4), 8, 1 } -}; - -static const struct pinmux_config nand_pins[] = { - { pinmux(7), 1, 1 }, - { pinmux(7), 1, 2 }, - { pinmux(7), 1, 4 }, - { pinmux(7), 1, 5 }, - { pinmux(9), 1, 0 }, - { pinmux(9), 1, 1 }, - { pinmux(9), 1, 2 }, - { pinmux(9), 1, 3 }, - { pinmux(9), 1, 4 }, - { pinmux(9), 1, 5 }, - { pinmux(9), 1, 6 }, - { pinmux(9), 1, 7 }, - { pinmux(12), 1, 5 }, - { pinmux(12), 1, 6 } -}; - -static const struct pinmux_config uart2_pins[] = { - { pinmux(0), 4, 6 }, - { pinmux(0), 4, 7 }, - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - -static const struct pinmux_config i2c_pins[] = { - { pinmux(4), 2, 4 }, - { pinmux(4), 2, 5 } -}; - static const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(mii_pins), - PINMUX_ITEM(mdio_pins), - PINMUX_ITEM(i2c_pins), - PINMUX_ITEM(nand_pins), - PINMUX_ITEM(uart2_pins), + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), }; static const struct lpsc_resource lpsc[] = { @@ -99,8 +56,8 @@ void board_init_f(ulong bootflag) /* * Kick Registers need to be set to allow access to Pin Mux registers */ - writel(HAWKBOARD_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(HAWKBOARD_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); + writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); + writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); /* setup the SUSPSRC for ARM to control emulation suspend */ writel(readl(&davinci_syscfg_regs->suspsrc) & diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c index 1a01c3c..ac82d5c 100644 --- a/board/davinci/dm6467evm/dm6467evm.c +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -24,6 +24,26 @@ DECLARE_GLOBAL_DATA_PTR; +#define REV_DM6467EVM 0 +#define REV_DM6467TEVM 1 +/* + * get_board_rev() - setup to pass kernel board revision information + * Returns: + * bit[0-3] System clock frequency + * 0000b - 27 MHz + * 0001b - 33 MHz + */ +u32 get_board_rev(void) +{ + +#ifdef DAVINCI_DM6467TEVM + return REV_DM6467TEVM; +#else + return REV_DM6467EVM; +#endif + +} + int board_init(void) { gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM; diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 720a360..9b6c4c0 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -40,8 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define pinmux(x) (&davinci_syscfg_regs->pinmux[x]) - static const struct da8xx_panel lcd_panel = { /* Casio COM57H531x */ .name = "Casio_COM57H531x", diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 8b615a9..52d00e4 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index c194290..55110fb 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -34,9 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_SONATA; - /* address of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; diff --git a/board/cradle/Makefile b/board/denx/m28evk/Makefile index bdc91d8..b6f002f 100644 --- a/board/cradle/Makefile +++ b/board/denx/m28evk/Makefile @@ -25,7 +25,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cradle.o flash.o +ifndef CONFIG_SPL_BUILD +COBJS := m28evk.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS := mem_init.o mmc_boot.o power_init.o memsize.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -33,6 +39,13 @@ OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +all: $(ALL) + +ifdef CONFIG_SPL_BUILD +memsize.c: + ln -sf $(TOPDIR)/common/memsize.c $@ +endif + ######################################################################### # defines $(obj).depend target diff --git a/board/denx/m28evk/m28_init.h b/board/denx/m28evk/m28_init.h new file mode 100644 index 0000000..98d3631 --- /dev/null +++ b/board/denx/m28evk/m28_init.h @@ -0,0 +1,41 @@ +/* + * Freescale i.MX28 SPL functions + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __M28_INIT_H__ +#define __M28_INIT_H__ + +void early_delay(int delay); + +void mx28_power_init(void); + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void); +#else +static inline void mx28_power_wait_pswitch(void) { } +#endif + +void mx28_mem_init(void); + +#endif /* __M28_INIT_H__ */ diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c new file mode 100644 index 0000000..8cf3dc9 --- /dev/null +++ b/board/denx/m28evk/m28evk.c @@ -0,0 +1,216 @@ +/* + * DENX M28 module + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mx28_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mx28_set_sspclk(MXC_SSPCLK2, 96000, 0); + +#ifdef CONFIG_CMD_USB + mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT); + mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 | + MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP); + gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0); +#endif + + return 0; +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +int dram_init(void) +{ + uint32_t sz[2]; + + sz[0] = readl(HW_DIGCTRL_SCRATCH0); + sz[1] = readl(HW_DIGCTRL_SCRATCH1); + + if (sz[0] != sz[1]) { + printf("MX28:\n" + "Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n" + "HW_DIGCTRL_SCRATCH1 is not the same. Please\n" + "verify these two registers contain valid RAM size!\n"); + hang(); + } + + gd->ram_size = sz[0]; + return 0; +} + +#ifdef CONFIG_CMD_MMC +static int m28_mmc_wp(int id) +{ + if (id != 0) { + printf("MXS MMC: Invalid card selected (card id = %d)\n", id); + return 1; + } + + return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10); +} + +int board_mmc_init(bd_t *bis) +{ + /* Configure WP as output */ + gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); + + return mxsmmc_initialize(bis, 0, m28_mmc_wp); +} +#endif + +#ifdef CONFIG_CMD_NET + +#define MII_OPMODE_STRAP_OVERRIDE 0x16 +#define MII_PHY_CTRL1 0x1e +#define MII_PHY_CTRL2 0x1f + +int fecmxc_mii_postcall(int phy) +{ + miiphy_write("FEC1", phy, MII_BMCR, 0x9000); + miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); + if (phy == 3) + miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, + CLKCTRL_ENET_TIME_SEL_RMII_CLK); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC1\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + printf("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXS: Unable to register FEC0 mii postcall\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC1"); + if (!dev) { + printf("FEC MXS: Unable to get FEC1 device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXS: Unable to register FEC1 mii postcall\n"); + return ret; + } + + return ret; +} + +#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP + +#define MXS_OCOTP_MAX_TIMEOUT 1000000 +void imx_get_mac_from_fuse(char *mac) +{ + struct mx28_ocotp_regs *ocotp_regs = + (struct mx28_ocotp_regs *)MXS_OCOTP_BASE; + uint32_t data; + + memset(mac, 0, 6); + + writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set); + + if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY, + MXS_OCOTP_MAX_TIMEOUT)) { + printf("MXS FEC: Can't get MAC from OCOTP\n"); + return; + } + + data = readl(&ocotp_regs->hw_ocotp_cust0); + + mac[0] = 0x00; + mac[1] = 0x04; + mac[2] = (data >> 24) & 0xff; + mac[3] = (data >> 16) & 0xff; + mac[4] = (data >> 8) & 0xff; + mac[5] = data & 0xff; +} +#else +void imx_get_mac_from_fuse(char *mac) +{ + memset(mac, 0, 6); +} +#endif + +#endif diff --git a/board/denx/m28evk/mem_init.c b/board/denx/m28evk/mem_init.c new file mode 100644 index 0000000..17d1f9b --- /dev/null +++ b/board/denx/m28evk/mem_init.c @@ -0,0 +1,240 @@ +/* + * Freescale i.MX28 RAM init + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> + +#include "m28_init.h" + +uint32_t dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, + 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, + 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, + 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, + 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, + 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, + 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, + 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, + 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 +}; + +void init_m28_200mhz_ddr2(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} + +void mx28_mem_init_clock(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Gate EMI clock */ + writel(CLKCTRL_FRAC0_CLKGATEEMI, + &clkctrl_regs->hw_clkctrl_frac0_set); + + /* EMI = 205MHz */ + writel(CLKCTRL_FRAC0_EMIFRAC_MASK, + &clkctrl_regs->hw_clkctrl_frac0_set); + writel((0x2a << CLKCTRL_FRAC0_EMIFRAC_OFFSET) & + CLKCTRL_FRAC0_EMIFRAC_MASK, + &clkctrl_regs->hw_clkctrl_frac0_clr); + + /* Ungate EMI clock */ + writel(CLKCTRL_FRAC0_CLKGATEEMI, + &clkctrl_regs->hw_clkctrl_frac0_clr); + + early_delay(11000); + + writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | + (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), + &clkctrl_regs->hw_clkctrl_emi); + + /* Unbypass EMI */ + writel(CLKCTRL_CLKSEQ_BYPASS_EMI, + &clkctrl_regs->hw_clkctrl_clkseq_clr); + + early_delay(10000); +} + +void mx28_mem_setup_cpu_and_hbus(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* CPU = 454MHz and ungate CPU clock */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0, + CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU, + 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET); + + /* Set CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); + + /* HBUS = 151MHz */ + writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); + writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, + &clkctrl_regs->hw_clkctrl_hbus_clr); + + early_delay(10000); + + /* CPU clock divider = 1 */ + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, + CLKCTRL_CPU_DIV_CPU_MASK, 1); + + /* Disable CPU bypass */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +void mx28_mem_setup_vdda(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | + (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vddactrl); +} + +void mx28_mem_setup_vddd(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) | + (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) | + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW, + &power_regs->hw_power_vdddctrl); +} + +#define HW_DIGCTRL_SCRATCH0 0x8001c280 +#define HW_DIGCTRL_SCRATCH1 0x8001c290 +void data_abort_memdetect_handler(void) __attribute__((naked)); +void data_abort_memdetect_handler(void) +{ + asm volatile("subs pc, r14, #4"); +} + +void mx28_mem_get_size(void) +{ + uint32_t sz, da; + uint32_t *vt = (uint32_t *)0x20; + + /* Replace the DABT handler. */ + da = vt[4]; + vt[4] = (uint32_t)&data_abort_memdetect_handler; + + sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + writel(sz, HW_DIGCTRL_SCRATCH0); + writel(sz, HW_DIGCTRL_SCRATCH1); + + /* Restore the old DABT handler. */ + vt[4] = da; +} + +void mx28_mem_init(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct mx28_pinctrl_regs *pinctrl_regs = + (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set DDR2 mode */ + writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + /* Power up PLL0 */ + writel(CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + + early_delay(11000); + + mx28_mem_init_clock(); + + mx28_mem_setup_vdda(); + + /* + * Configure the DRAM registers + */ + + /* Clear START bit from DRAM_CTL16 */ + clrbits_le32(MXS_DRAM_BASE + 0x40, 1); + + init_m28_200mhz_ddr2(); + + /* Clear SREFRESH bit from DRAM_CTL17 */ + clrbits_le32(MXS_DRAM_BASE + 0x44, 1); + + /* Set START bit in DRAM_CTL16 */ + setbits_le32(MXS_DRAM_BASE + 0x40, 1); + + /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */ + while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20))) + ; + + mx28_mem_setup_vddd(); + + early_delay(10000); + + mx28_mem_setup_cpu_and_hbus(); + + mx28_mem_get_size(); +} diff --git a/board/denx/m28evk/mmc_boot.c b/board/denx/m28evk/mmc_boot.c new file mode 100644 index 0000000..86d3ab5 --- /dev/null +++ b/board/denx/m28evk/mmc_boot.c @@ -0,0 +1,273 @@ +/* + * Freescale i.MX28 Boot setup + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> + +#include "m28_init.h" + +/* + * This delay function is intended to be used only in early stage of boot, where + * clock are not set up yet. The timer used here is reset on every boot and + * takes a few seconds to roll. The boot doesn't take that long, so to keep the + * code simple, it doesn't take rolling into consideration. + */ +#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0 +void early_delay(int delay) +{ + uint32_t st = readl(HW_DIGCTRL_MICROSECONDS); + st += delay; + while (st > readl(HW_DIGCTRL_MICROSECONDS)) + ; +} + +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* LED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, + + /* framebuffer */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, + + /* UART1 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_RX__DUART_CTS, + + /* UART2 */ + MX28_PAD_AUART1_RX__AUART1_RX, + MX28_PAD_AUART1_TX__AUART1_TX, + MX28_PAD_AUART1_RTS__AUART1_RTS, + MX28_PAD_AUART1_CTS__AUART1_CTS, + + /* CAN */ + MX28_PAD_GPMI_RDY2__CAN0_TX, + MX28_PAD_GPMI_RDY3__CAN0_RX, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* TSC2007 */ + MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), + MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */ + MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */ + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC Ethernet */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +}; + +void board_init_ll(void) +{ + mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup)); + mx28_power_init(); + mx28_mem_init(); + mx28_power_wait_pswitch(); +} + +/* Support aparatus */ +inline void board_init_f(unsigned long bootflag) +{ + for (;;) + ; +} + +inline void board_init_r(gd_t *id, ulong dest_addr) +{ + for (;;) + ; +} + +inline int printf(const char *fmt, ...) +{ + return 0; +} + +inline void __coloured_LED_init(void) {} +inline void __red_LED_on(void) {} +void coloured_LED_init(void) + __attribute__((weak, alias("__coloured_LED_init"))); +void red_LED_on(void) + __attribute__((weak, alias("__red_LED_on"))); +void hang(void) __attribute__ ((noreturn)); +void hang(void) +{ + for (;;) + ; +} diff --git a/board/denx/m28evk/power_init.c b/board/denx/m28evk/power_init.c new file mode 100644 index 0000000..27322b4 --- /dev/null +++ b/board/denx/m28evk/power_init.c @@ -0,0 +1,913 @@ +/* + * Freescale i.MX28 Boot PMIC init + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> + +#include "m28_init.h" + +void mx28_power_clock2xtal(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + /* Set XTAL as CPU reference clock */ + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_set); +} + +void mx28_power_clock2pll(void) +{ + struct mx28_clkctrl_regs *clkctrl_regs = + (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; + + writel(CLKCTRL_PLL0CTRL0_POWER, + &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); + early_delay(100); + writel(CLKCTRL_CLKSEQ_BYPASS_CPU, + &clkctrl_regs->hw_clkctrl_clkseq_clr); +} + +void mx28_power_clear_auto_restart(void) +{ + struct mx28_rtc_regs *rtc_regs = + (struct mx28_rtc_regs *)MXS_RTC_BASE; + + writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) + ; + + writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) + ; + + /* + * Due to the hardware design bug of mx28 EVK-A + * we need to set the AUTO_RESTART bit. + */ + if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) + return; + + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + + setbits_le32(&rtc_regs->hw_rtc_persistent0, + RTC_PERSISTENT0_AUTO_RESTART); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); + writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) + ; + while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) + ; +} + +void mx28_power_set_linreg(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Set linear regulator 25mV below switching converter */ + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_LINREG_OFFSET_MASK, + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_LINREG_OFFSET_MASK, + POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW); +} + +void mx28_power_setup_5v_detect(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Start 5V detection */ + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, + POWER_5VCTRL_VBUSVALID_TRSH_4V4 | + POWER_5VCTRL_PWRUP_VBUS_CMPS); +} + +void mx28_src_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Improve efficieny and reduce transient ripple */ + writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | + POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); + + clrsetbits_le32(&power_regs->hw_power_dclimits, + POWER_DCLIMITS_POSLIMIT_BUCK_MASK, + 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); + + setbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_EN_BATADJ); + + /* Increase the RCSCALE level for quick DCDC response to dynamic load */ + clrsetbits_le32(&power_regs->hw_power_loopctrl, + POWER_LOOPCTRL_EN_RCSCALE_MASK, + POWER_LOOPCTRL_RCSCALE_THRESH | + POWER_LOOPCTRL_EN_RCSCALE_8X); + + clrsetbits_le32(&power_regs->hw_power_minpwr, + POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); + + /* 5V to battery handoff ... FIXME */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); +} + +void mx28_power_init_4p2_params(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Setup 4P2 parameters */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, + POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET)); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_HEADROOM_ADJ_MASK, + 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET); + + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_DROPOUT_CTRL_MASK, + POWER_DCDC4P2_DROPOUT_CTRL_100MV | + POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); +} + +void mx28_enable_4p2_dcdc_input(int xfer) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; + uint32_t prev_5v_brnout, prev_5v_droop; + + prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_PWDN_5VBRNOUT; + prev_5v_droop = readl(&power_regs->hw_power_ctrl) & + POWER_CTRL_ENIRQ_VDD5V_DROOP; + + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + + clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); + + if (xfer && (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return; + } + + /* + * Recording orignal values that will be modified temporarlily + * to handle a chip bug. See chip errata for CQ ENGR00115837 + */ + tmp = readl(&power_regs->hw_power_5vctrl); + vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; + vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; + + pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; + + /* + * Disable mechanisms that get erroneously tripped by when setting + * the DCDC4P2 EN_DCDC + */ + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_5VDETECT | + POWER_5VCTRL_VBUSVALID_TRSH_MASK); + + writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); + + if (xfer) { + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + early_delay(20); + clrbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_DCDC_XFER); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_ENABLE_DCDC); + } else { + setbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + } + + early_delay(25); + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); + + if (vbus_5vdetect) + writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); + + if (!pwd_bo) + clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_VBUS_VALID_IRQ); + + if (prev_5v_brnout) { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_set); + writel(POWER_RESET_UNLOCK_KEY, + &power_regs->hw_power_reset); + } else { + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); + } + + while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_VDD5V_DROOP_IRQ); + + if (prev_5v_droop) + clrbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); + else + setbits_le32(&power_regs->hw_power_ctrl, + POWER_CTRL_ENIRQ_VDD5V_DROOP); +} + +void mx28_power_init_4p2_regulator(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp, tmp2; + + setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); + + writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); + + writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + &power_regs->hw_power_5vctrl_clr); + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); + + /* Power up the 4p2 rail and logic/control */ + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + /* + * Start charging up the 4p2 capacitor. We ramp of this charge + * gradually to avoid large inrush current from the 5V cable which can + * cause transients/problems + */ + mx28_enable_4p2_dcdc_input(0); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + /* + * If we arrived here, we were unable to recover from mx23 chip + * errata 5837. 4P2 is disabled and sufficient battery power is + * not present. Exiting to not enable DCDC power during 5V + * connected state. + */ + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + hang(); + } + + /* + * Here we set the 4p2 brownout level to something very close to 4.2V. + * We then check the brownout status. If the brownout status is false, + * the voltage is already close to the target voltage of 4.2V so we + * can go ahead and set the 4P2 current limit to our max target limit. + * If the brownout status is true, we need to ramp us the current limit + * so that we don't cause large inrush current issues. We step up the + * current limit until the brownout status is false or until we've + * reached our maximum defined 4p2 current limit. + */ + clrsetbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_BO_MASK, + 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ + + if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { + setbits_le32(&power_regs->hw_power_5vctrl, + 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + } else { + tmp = (readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + while (tmp < 0x3f) { + if (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DCDC_4P2_BO)) { + tmp = readl(&power_regs->hw_power_5vctrl); + tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + early_delay(100); + writel(tmp, &power_regs->hw_power_5vctrl); + break; + } else { + tmp++; + tmp2 = readl(&power_regs->hw_power_5vctrl); + tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; + tmp2 |= tmp << + POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; + writel(tmp2, &power_regs->hw_power_5vctrl); + early_delay(100); + } + } + } + + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); +} + +void mx28_power_init_dcdc_4p2_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + if (!(readl(&power_regs->hw_power_dcdc4p2) & + POWER_DCDC4P2_ENABLE_DCDC)) { + hang(); + } + + mx28_enable_4p2_dcdc_input(1); + + if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { + clrbits_le32(&power_regs->hw_power_dcdc4p2, + POWER_DCDC4P2_ENABLE_DCDC); + writel(POWER_5VCTRL_ENABLE_DCDC, + &power_regs->hw_power_5vctrl_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_set); + } +} + +void mx28_power_enable_4p2(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t vdddctrl, vddactrl, vddioctrl; + uint32_t tmp; + + vdddctrl = readl(&power_regs->hw_power_vdddctrl); + vddactrl = readl(&power_regs->hw_power_vddactrl); + vddioctrl = readl(&power_regs->hw_power_vddioctrl); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT); + + mx28_power_init_4p2_params(); + mx28_power_init_4p2_regulator(); + + /* Shutdown battery (none present) */ + clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); + writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr); + + mx28_power_init_dcdc_4p2_source(); + + writel(vdddctrl, &power_regs->hw_power_vdddctrl); + early_delay(20); + writel(vddactrl, &power_regs->hw_power_vddactrl); + early_delay(20); + writel(vddioctrl, &power_regs->hw_power_vddioctrl); + + /* + * Check if FET is enabled on either powerout and if so, + * disable load. + */ + tmp = 0; + tmp |= !(readl(&power_regs->hw_power_vdddctrl) & + POWER_VDDDCTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddactrl) & + POWER_VDDACTRL_DISABLE_FET); + tmp |= !(readl(&power_regs->hw_power_vddioctrl) & + POWER_VDDIOCTRL_DISABLE_FET); + if (tmp) + writel(POWER_CHARGE_ENABLE_LOAD, + &power_regs->hw_power_charge_clr); +} + +void mx28_boot_valid_5v(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V + * disconnect event. FIXME + */ + writel(POWER_5VCTRL_VBUSVALID_5VDETECT, + &power_regs->hw_power_5vctrl_set); + + /* Configure polarity to check for 5V disconnection. */ + writel(POWER_CTRL_POLARITY_VBUSVALID | + POWER_CTRL_POLARITY_VDD5V_GT_VDDIO, + &power_regs->hw_power_ctrl_clr); + + writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ, + &power_regs->hw_power_ctrl_clr); + + mx28_power_enable_4p2(); +} + +void mx28_powerdown(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); + writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, + &power_regs->hw_power_reset); +} + +void mx28_handle_5v_conflict(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + + for (;;) { + tmp = readl(&power_regs->hw_power_sts); + + if (tmp & POWER_STS_VDDIO_BO) { + mx28_powerdown(); + break; + } + + if (tmp & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + break; + } else { + mx28_powerdown(); + break; + } + } +} + +int mx28_get_batt_volt(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + return volt; +} + +int mx28_is_batt_ready(void) +{ + return (mx28_get_batt_volt() >= 3600); +} + +void mx28_5v_boot(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* + * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, + * but their implementation always returns 1 so we omit it here. + */ + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + early_delay(1000); + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + mx28_boot_valid_5v(); + return; + } + + mx28_handle_5v_conflict(); +} + +void mx28_init_batt_bo(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + /* Brownout at 3V */ + clrsetbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BRWNOUT_LVL_MASK, + 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); + + writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); + writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); +} + +void mx28_switch_vddd_to_dcdc_source(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_LINREG_OFFSET_MASK, + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_DISABLE_STEPPING); +} + +int mx28_is_batt_good(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t volt; + + volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + + if ((volt >= 2400) && (volt <= 4300)) + return 1; + + clrsetbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, + 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + clrsetbits_le32(&power_regs->hw_power_charge, + POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + POWER_CHARGE_STOP_ILIMIT_10MA | 0x3); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr); + writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, + &power_regs->hw_power_5vctrl_clr); + + early_delay(500000); + + volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; + volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; + volt *= 8; + + if (volt >= 3500) + return 0; + + if (volt >= 2400) + return 1; + + writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK, + &power_regs->hw_power_charge_clr); + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + return 0; +} + +void mx28_power_configure_power_source(void) +{ + mx28_src_power_init(); + + mx28_5v_boot(); + mx28_power_clock2pll(); + + mx28_init_batt_bo(); + mx28_switch_vddd_to_dcdc_source(); +} + +void mx28_enable_output_rail_protection(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_PWDN_BRNOUT); + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_PWDN_BRNOUT); +} + +int mx28_get_vddio_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + tmp = readl(&power_regs->hw_power_vddioctrl); + if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + } + + return 0; + +} + +int mx28_get_vddd_power_source_off(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t tmp; + + tmp = readl(&power_regs->hw_power_vdddctrl); + if (tmp & POWER_VDDDCTRL_DISABLE_FET) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return 1; + } + } + + if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) { + if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) == + POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) { + return 1; + } + } + + return 0; +} + +void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + + powered_by_linreg = mx28_get_vddio_power_source_off(); + if (new_target > cur_target) { + + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vddioctrl); + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_BO_OFFSET_MASK); + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDIO_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO) + setbits_le32(&power_regs->hw_power_vddioctrl, + POWER_CTRL_ENIRQ_VDDIO_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 2800; + diff /= 50; + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vddioctrl); + cur_target &= POWER_VDDIOCTRL_TRG_MASK; + cur_target *= 50; /* 50 mV step*/ + cur_target += 2800; /* 2800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + uint32_t cur_target, diff, bo_int = 0; + uint32_t powered_by_linreg = 0; + + new_brownout = new_target - new_brownout; + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + + powered_by_linreg = mx28_get_vddd_power_source_off(); + if (new_target > cur_target) { + if (powered_by_linreg) { + bo_int = readl(&power_regs->hw_power_vdddctrl); + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK); + + do { + if (new_target - cur_target > 100) + diff = cur_target + 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target > cur_target); + + if (powered_by_linreg) { + writel(POWER_CTRL_VDDD_BO_IRQ, + &power_regs->hw_power_ctrl_clr); + if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) + setbits_le32(&power_regs->hw_power_vdddctrl, + POWER_CTRL_ENIRQ_VDDD_BO); + } + } else { + do { + if (cur_target - new_target > 100) + diff = cur_target - 100; + else + diff = new_target; + + diff -= 800; + diff /= 25; + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_TRG_MASK, diff); + + if (powered_by_linreg) + early_delay(1500); + else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) + ; + + } + + cur_target = readl(&power_regs->hw_power_vdddctrl); + cur_target &= POWER_VDDDCTRL_TRG_MASK; + cur_target *= 25; /* 25 mV step*/ + cur_target += 800; /* 800 mV lowest */ + } while (new_target < cur_target); + } + + clrsetbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_BO_OFFSET_MASK, + new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); +} + +void mx28_power_init(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + mx28_power_clock2xtal(); + mx28_power_clear_auto_restart(); + mx28_power_set_linreg(); + mx28_power_setup_5v_detect(); + mx28_power_configure_power_source(); + mx28_enable_output_rail_protection(); + + mx28_power_set_vddio(3300, 3150); + + mx28_power_set_vddd(1350, 1200); + + writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | + POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | + POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | + POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); + + writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); + + early_delay(1000); +} + +#ifdef CONFIG_SPL_MX28_PSWITCH_WAIT +void mx28_power_wait_pswitch(void) +{ + struct mx28_power_regs *power_regs = + (struct mx28_power_regs *)MXS_POWER_BASE; + + while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) + ; +} +#endif diff --git a/board/denx/m28evk/start.S b/board/denx/m28evk/start.S new file mode 100644 index 0000000..94696d6 --- /dev/null +++ b/board/denx/m28evk/start.S @@ -0,0 +1,234 @@ +/* + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Groger <mag@sysgo.de> + * Copyright (c) 2002 Alex Zupke <azu@sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> + * Copyright (c) 2003 Kshitij <kshitij@ti.com> + * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> + * + * Change to support call back into iMX28 bootrom + * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <common.h> +#include <version.h> + +#if defined(CONFIG_OMAP1610) +#include <./configs/omap1510.h> +#elif defined(CONFIG_OMAP730) +#include <./configs/omap730.h> +#endif + +/* + ************************************************************************* + * + * Jump vector table as in table 3.1 in [1] + * + ************************************************************************* + */ + + +.globl _start +_start: + b reset + b undefined_instruction + b software_interrupt + b prefetch_abort + b data_abort + b not_used + b irq + b fiq + +/* + * Vector table, located at address 0x20. + * This table allows the code running AFTER SPL, the U-Boot, to install it's + * interrupt handlers here. The problem is that the U-Boot is loaded into RAM, + * including it's interrupt vectoring table and the table at 0x0 is still the + * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table + * is still used. + */ +_vt_reset: + .word _reset +_vt_undefined_instruction: + .word _hang +_vt_software_interrupt: + .word _hang +_vt_prefetch_abort: + .word _hang +_vt_data_abort: + .word _hang +_vt_not_used: + .word _reset +_vt_irq: + .word _hang +_vt_fiq: + .word _hang + +reset: + ldr pc, _vt_reset +undefined_instruction: + ldr pc, _vt_undefined_instruction +software_interrupt: + ldr pc, _vt_software_interrupt +prefetch_abort: + ldr pc, _vt_prefetch_abort +data_abort: + ldr pc, _vt_data_abort +not_used: + ldr pc, _vt_not_used +irq: + ldr pc, _vt_irq +fiq: + ldr pc, _vt_fiq + + .balignl 16,0xdeadbeef + +/* + ************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + ************************************************************************* + */ + +.globl _TEXT_BASE +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + +/* + * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. + */ +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start + +.globl _bss_end_ofs +_bss_end_ofs: + .word __bss_end__ - _start + +.globl _end_ofs +_end_ofs: + .word _end - _start + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +/* + * the actual reset code + */ + +_reset: + /* + * Store all registers on old stack pointer, this will allow us later to + * return to the BootROM and let the BootROM load U-Boot into RAM. + */ + push {r0-r12,r14} + + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + + bl board_init_ll + + pop {r0-r12,r14} + bx lr + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ + orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + mov pc, lr /* back to my caller */ + + .align 5 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ + +_hang: + ldr sp, _TEXT_BASE /* switch to abort stack */ +1: + bl 1b /* hang and never return */ diff --git a/board/denx/m28evk/u-boot-spl.lds b/board/denx/m28evk/u-boot-spl.lds new file mode 100644 index 0000000..e296a92 --- /dev/null +++ b/board/denx/m28evk/u-boot-spl.lds @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + board/denx/m28evk/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/denx/m28evk/u-boot.bd b/board/denx/m28evk/u-boot.bd new file mode 100644 index 0000000..3ce7f92 --- /dev/null +++ b/board/denx/m28evk/u-boot.bd @@ -0,0 +1,14 @@ +sources { + u_boot_spl="spl/u-boot-spl.bin"; + u_boot="u-boot.bin"; +} + +section (0) { + load u_boot_spl > 0x0000; + load ivt (entry = 0x0014) > 0x8000; + hab call 0x8000; + + load u_boot > 0x40000100; + load ivt (entry = 0x40000100) > 0x8000; + hab call 0x8000; +} diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index c4ed820..429fe1b 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -223,7 +223,7 @@ void setup_pcat_compatibility() * active low polarity on PIC interrupt pins, * active high polarity on all other irq pins */ - writew(0x0000,&sc520_mmcr->intpinpol); + writew(0x0000, &sc520_mmcr->intpinpol); /* * PIT 0 -> IRQ0 @@ -252,7 +252,7 @@ void setup_pcat_compatibility() void enet_timer_isr(void) { - static long enet_ticks = 0; + static long enet_ticks; enet_ticks++; @@ -281,9 +281,9 @@ void hw_watchdog_reset(void) void enet_toggle_run_led(void) { - unsigned char leds_state= inb(LED_LATCH_ADDRESS); + unsigned char leds_state = inb(LED_LATCH_ADDRESS); if (leds_state & LED_RUN_BITMASK) - outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS); + outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS); else outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS); } diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c index 29d13d2..5af4ef7 100644 --- a/board/eNET/eNET_pci.c +++ b/board/eNET/eNET_pci.c @@ -38,7 +38,7 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) CONFIG_SYS_THIRD_PCI_IRQ, CONFIG_SYS_FORTH_PCI_IRQ }; - static int next_irq_index=0; + static int next_irq_index; uchar tmp_pin; int pin; @@ -47,9 +47,8 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) pin = tmp_pin; pin -= 1; /* PCI config space use 1-based numbering */ - if (pin == -1) { + if (pin == -1) return; /* device use no irq */ - } /* map device number + pin to a pin on the sc520 */ switch (PCI_DEV(dev)) { @@ -69,19 +68,19 @@ static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev) if (sc520_pci_ints[pin] == -1) { /* re-route one interrupt for us */ - if (next_irq_index > 3) { + if (next_irq_index > 3) return; - } - if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) { + + if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) return; - } + next_irq_index++; } - if (-1 != sc520_pci_ints[pin]) { - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, + if (-1 != sc520_pci_ints[pin]) + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, sc520_pci_ints[pin]); - } + printf("fixup_irq: device %d pin %c irq %d\n", PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]); } diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S index 4241f6e..5e3f44c 100644 --- a/board/eNET/eNET_start16.S +++ b/board/eNET/eNET_start16.S @@ -30,6 +30,7 @@ #include "config.h" #include "hardware.h" #include <asm/arch/sc520.h> +#include <generated/asm-offsets.h> .text .section .start16, "ax" @@ -46,12 +47,12 @@ board_init16: movw %ax, %ds /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */ - movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR14, %edi movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax movl %eax, (%di) /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */ - movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi + movl $GENERATED_SC520_PAR15, %edi movl $CONFIG_SYS_SC520_LLIO_PAR, %eax movl %eax, (%di) diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index b78bf6c..3d2cc1a 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -226,7 +226,7 @@ static void power_init(void) /* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; pmic_reg_write(p, REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ @@ -260,18 +260,23 @@ static void power_init(void) (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); pmic_reg_write(p, REG_SW_5, val); - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; pmic_reg_write(p, REG_SETTING_1, val); + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; pmic_reg_write(p, REG_MODE_1, val); @@ -279,7 +284,7 @@ static void power_init(void) /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; + VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); pmic_reg_read(p, REG_POWER_CTL2, &val); diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile new file mode 100644 index 0000000..8dc85d2 --- /dev/null +++ b/board/egnite/ethernut5/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2010 +# egnite GmbH +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += $(BOARD)_pwrman.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c new file mode 100644 index 0000000..e42e91e --- /dev/null +++ b/board/egnite/ethernut5/ethernut5.c @@ -0,0 +1,270 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * (C) Copyright 2010 + * Ole Reinhardt <ole.reinhardt@thermotemp.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 general board support + * + * Ethernut is an open source hardware and software project for + * embedded Ethernet devices. Hardware layouts and CAD files are + * freely available under BSD-like license. + * + * Ethernut 5 is the first member of the Ethernut board family + * with U-Boot and Linux support. This implementation is based + * on the original work done by Ole Reinhardt, but heavily modified + * to support additional features and the latest board revision 5.0F. + * + * Main board components are by default: + * + * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash + * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM + * 512 MBytes Micron MT29F4G08ABADA NAND Flash + * 4 MBytes Atmel AT45DB321D DataFlash + * SMSC LAN8710 Ethernet PHY + * Atmel ATmega168 MCU used for power management + * Linear Technology LTC4411 PoE controller + * + * U-Boot relevant board interfaces are: + * + * 100 Mbit Ethernet with IEEE 802.3af PoE + * RS-232 serial port + * USB host and device + * MMC/SD-Card slot + * Expansion port with I2C, SPI and more... + * + * Typically the U-Boot image is loaded from serial DataFlash into + * SDRAM by the samboot boot loader, which is located in internal + * NOR Flash and provides all essential initializations like CPU + * and peripheral clocks and, of course, the SDRAM configuration. + * + * For testing purposes it is also possibly to directly transfer + * the image into SDRAM via JTAG. A tested configuration exists + * for the Turtelizer 2 hardware dongle and the OpenOCD software. + * In this case the latter will do the basic hardware configuration + * via its reset-init script. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <spi.h> +#include <dataflash.h> +#include <mmc.h> + +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +#include "ethernut5_pwrman.h" + +DECLARE_GLOBAL_DATA_PTR; + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0} +}; + +/* + * In fact we have 7 partitions, but u-boot supports 5 only. This is + * no big deal, because the first partition is reserved for applications + * and the last one is used by Nut/OS. Both need not to be visible here. + */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" }, + { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" }, + { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" }, + { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" }, + { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" } +}; + +/* + * This is called last during early initialization. Most of the basic + * hardware interfaces are up and running. + * + * The SDRAM hardware has been configured by the first stage boot loader. + * We only need to announce its size, using u-boot's memory check. + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_CMD_NAND +static void ethernut5_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + +#ifdef CONFIG_SYS_NAND_READY_PIN + /* Ready pin is optional. */ + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +/* + * This is called first during late initialization. + */ +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + /* Set adress of boot parameters. */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Initialize UARTs and power management. */ + at91_seriald_hw_init(); + ethernut5_power_init(); +#ifdef CONFIG_CMD_NAND + ethernut5_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif + return 0; +} + +#ifdef CONFIG_MACB +/* + * This is optionally called last during late initialization. + */ +int board_eth_init(bd_t *bis) +{ + const char *devname; + unsigned short mode; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable on-chip EMAC clock. */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + /* Need to reset PHY via power management. */ + ethernut5_phy_reset(); + /* Set peripheral pins. */ + at91_macb_hw_init(); + /* Basic EMAC initialization. */ + if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID)) + return -1; + /* + * Early board revisions have a pull-down at the PHY's MODE0 + * strap pin, which forces the PHY into power down. Here we + * switch to all-capable mode. + */ + devname = miiphy_get_current_dev(); + if (miiphy_read(devname, 0, 18, &mode) == 0) { + /* Set mode[2:0] to 0b111. */ + mode |= 0x00E0; + miiphy_write(devname, 0, 18, mode); + /* Soft reset overrides strap pins. */ + miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); + } + /* Sync environment with network devices, needed for nfsroot. */ + return eth_init(gd->bd); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable MCI clock. */ + writel(1 << ATMEL_ID_MCI, &pmc->pcer); + /* Initialize MCI hardware. */ + at91_mci_hw_init(); + /* Register the device. */ + return atmel_mci_init((void *)ATMEL_BASE_MCI); +} + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + *cd = at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; + return 0; +} +#endif + +#ifdef CONFIG_ATMEL_SPI +/* + * Note, that u-boot uses different code for SPI bus access. While + * memory routines use automatic chip select control, the serial + * flash support requires 'manual' GPIO control. Thus, we switch + * modes. + */ +void spi_cs_activate(struct spi_slave *slave) +{ + /* Enable NPCS0 in GPIO mode. This disables peripheral control. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Disable NPCS0 in GPIO mode. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + /* Switch back to peripheral chip select control. */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} +#endif diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c new file mode 100644 index 0000000..4b00038 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -0,0 +1,338 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * This board may be supplied via USB, IEEE 802.3af PoE or an + * auxiliary DC input. An on-board ATmega168 microcontroller, + * the so called power management controller or PMC, is used + * to select the supply source and to switch on and off certain + * energy consuming board components. This allows to reduce the + * total stand-by consumption to less than 70mW. + * + * The main CPU communicates with the PMC via I2C. When + * CONFIG_CMD_BSP is defined in the board configuration file, + * then the board specific command 'pwrman' becomes available, + * which allows to manually deal with the PMC. + * + * Two distinct registers are provided by the PMC for enabling + * and disabling specific features. This avoids the often seen + * read-modify-write cycle or shadow register requirement. + * Additional registers are available to query the board + * status and temperature, the auxiliary voltage and to control + * the green user LED that is integrated in the reset switch. + * + * Note, that the AVR firmware of the PMC is released under BSDL. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <i2c.h> + +#include "ethernut5_pwrman.h" + +/* PMC firmware version */ +static int pwrman_major; +static int pwrman_minor; + +/* + * Enable Ethernut 5 power management. + * + * This function must be called during board initialization. + * While we are using u-boot's I2C subsystem, it may be required + * to enable the serial port before calling this function, + * in particular when debugging is enabled. + * + * If board specific commands are not available, we will activate + * all board components. + */ +void ethernut5_power_init(void) +{ + pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS); + pwrman_major = pwrman_minor >> 4; + pwrman_minor &= 15; + +#ifndef CONFIG_CMD_BSP + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major == 2) { + /* Without board specific commands we enable all features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + } +#endif +} + +/* + * Reset Ethernet PHY. + * + * This function allows the re-configure the PHY after + * changing its strap pins. + */ +void ethernut5_phy_reset(void) +{ + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major != 2) + return; + + /* + * Make sure that the Ethernet clock is enabled and the PHY reset + * is disabled for at least 100 us. + */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + udelay(100); + + /* + * LAN8710 strap pins are + * PA14 => PHY MODE0 + * PA15 => PHY MODE1 + * PA17 => PHY MODE2 => 111b all capable + * PA18 => PHY ADDR0 => 0b + */ + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); + at91_set_pio_input(AT91_PIO_PORTA, 15, 1); + at91_set_pio_input(AT91_PIO_PORTA, 17, 1); + at91_set_pio_input(AT91_PIO_PORTA, 18, 0); + + /* Activate PHY reset for 100 us. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST); + udelay(100); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); +} + +/* + * Output the firmware version we got during initialization. + */ +void ethernut5_print_version(void) +{ + printf("%u.%u\n", pwrman_major, pwrman_minor); +} + +/* + * All code below this point is optional and implements + * the 'pwrman' command. + */ +#ifdef CONFIG_CMD_BSP + +/* Human readable names of PMC features */ +char *pwrman_feat[8] = { + "board", "vbin", "vbout", "mmc", + "rs232", "ethclk", "ethrst", "wakeup" +}; + +/* + * Print all feature names, that have its related flags enabled. + */ +static void print_flagged_features(u8 flags) +{ + int i; + + for (i = 0; i < 8; i++) { + if (flags & (1 << i)) + printf("%s ", pwrman_feat[i]); + } +} + +/* + * Return flags of a given list of feature names. + * + * The function stops at the first unknown list entry and + * returns the number of detected names as a function result. + */ +static int feature_flags(char * const names[], int num, u8 *flags) +{ + int i, j; + + *flags = 0; + for (i = 0; i < num; i++) { + for (j = 0; j < 8; j++) { + if (strcmp(pwrman_feat[j], names[i]) == 0) { + *flags |= 1 << j; + break; + } + } + if (j > 7) + break; + } + return i; +} + +void ethernut5_print_power(void) +{ + u8 flags; + int i; + + flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA); + for (i = 0; i < 2; i++) { + if (flags) { + print_flagged_features(flags); + printf("%s\n", i ? "off" : "on"); + } + flags = ~flags; + } +} + +void ethernut5_print_celsius(void) +{ + int val; + + /* Read ADC value from LM50 and return Celsius degrees. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); + val *= 5000; /* 100mV/degree with 5V reference */ + val += 128; /* 8 bit resolution */ + val /= 256; + val -= 450; /* Celsius offset, still x10 */ + /* Output full degrees. */ + printf("%d\n", (val + 5) / 10); +} + +void ethernut5_print_voltage(void) +{ + int val; + + /* Read ADC value from divider and return voltage. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); + /* Resistors are 100k and 12.1k */ + val += 5; + val *= 180948; + val /= 100000; + val++; + /* Calculation was done in 0.1V units. */ + printf("%d\n", (val + 5) / 10); +} + +/* + * Process the board specific 'pwrman' command. + */ +int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 val; + int i; + + if (argc == 1) { + ethernut5_print_power(); + } else if (argc == 2 && strcmp(argv[1], "reset") == 0) { + at91_set_pio_output(AT91_PIO_PORTB, 8, 1); + udelay(100); + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); + udelay(100000); + } else if (argc == 2 && strcmp(argv[1], "temp") == 0) { + ethernut5_print_celsius(); + } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) { + ethernut5_print_voltage(); + } else if (argc == 2 && strcmp(argv[1], "version") == 0) { + ethernut5_print_version(); + } else if (strcmp(argv[1], "led") == 0) { + /* Control the green status LED. Blink frequency unit + ** is 0.1s, very roughly. */ + if (argc == 2) { + /* No more arguments, output current settings. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL); + printf("led %u %u\n", val >> 4, val & 15); + } else { + /* First argument specifies the on-time. */ + val = (u8) simple_strtoul(argv[2], NULL, 0); + val <<= 4; + if (argc > 3) { + /* Second argument specifies the off-time. */ + val |= (u8) (simple_strtoul(argv[3], NULL, 0) + & 15); + } + /* Update the LED control register. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val); + } + } else { + /* We expect a list of features followed an optional status. */ + argc--; + i = feature_flags(&argv[1], argc, &val); + if (argc == i) { + /* We got a list only, print status. */ + val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA); + if (val) { + if (i > 1) + print_flagged_features(val); + printf("active\n"); + } else { + printf("inactive\n"); + } + } else { + /* More arguments. */ + if (i == 0) { + /* No given feature, use despensibles. */ + val = PWRMAN_DISPENSIBLE; + } + if (strcmp(argv[i + 1], "on") == 0) { + /* Enable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, + val); + } else if (strcmp(argv[i + 1], "off") == 0) { + /* Disable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, + val); + } else { + printf("Bad parameter %s\n", argv[i + 1]); + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD( + pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman, + "power management", + "- print settings\n" + "pwrman feature ...\n" + " - print status\n" + "pwrman [feature ...] on|off\n" + " - enable/disable specified or all dispensible features\n" + "pwrman led [on-time [off-time]]\n" + " - print or set led blink timer\n" + "pwrman temp\n" + " - print board temperature (Celsius)\n" + "pwrman vaux\n" + " - print auxiliary input voltage\n" + "pwrman reset\n" + " - reset power management controller\n" + "pwrman version\n" + " - print firmware version\n" + "\n" + " features, (*)=dispensible:\n" + " board - 1.8V and 3.3V supply\n" + " vbin - supply via USB device connector\n" + " vbout - USB host connector supply(*)\n" + " mmc - MMC slot supply(*)\n" + " rs232 - RS232 driver\n" + " ethclk - Ethernet PHY clock(*)\n" + " ethrst - Ethernet PHY reset\n" + " wakeup - RTC alarm" +); +#endif /* CONFIG_CMD_BSP */ diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h new file mode 100644 index 0000000..0541884 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info@egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +/* I2C address of the PMC */ +#define PWRMAN_I2C_ADDR 0x22 + +/* PMC registers */ +#define PWRMAN_REG_VERS 0 /* Version register */ +#define PWRMAN_REG_STA 1 /* Feature status register */ +#define PWRMAN_REG_ENA 2 /* Feature enable register */ +#define PWRMAN_REG_DIS 3 /* Feature disable register */ +#define PWRMAN_REG_TEMP 4 /* Board temperature */ +#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */ +#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */ + +/* Feature flags used in status, enable and disable registers */ +#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */ +#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */ +#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */ +#define PWRMAN_MMC 0x08 /* Memory card supply */ +#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */ +#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */ +#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */ +#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */ + +/* Features, which are not essential to keep u-boot alive */ +#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK) + +/* Enable Ethernut 5 power management. */ +extern void ethernut5_power_init(void); + +/* Reset Ethernet PHY. */ +extern void ethernut5_phy_reset(void); + +extern void ethernut5_print_version(void); + +#ifdef CONFIG_CMD_BSP +extern void ethernut5_print_power(void); +extern void ethernut5_print_celsius(void); +extern void ethernut5_print_voltage(void); +#endif diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c index bc6eb40..d05e226 100644 --- a/board/eltec/bab7xx/misc.c +++ b/board/eltec/bab7xx/misc.c @@ -31,7 +31,6 @@ #include "srom.h" /* imports */ -extern char console_buffer[CONFIG_SYS_CBSIZE]; extern int l2_cache_enable (int l2control); extern void *nvram_read (void *dest, const short src, size_t count); extern void nvram_write (short dest, const void *src, size_t count); diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index cbaf10b..d476cd5 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -29,7 +29,6 @@ #include "srom.h" /* imports */ -extern char console_buffer[CONFIG_SYS_CBSIZE]; extern int l2_cache_enable (int l2control); extern int eepro100_write_eeprom (struct eth_device *dev, int location, int addr_len, unsigned short data); diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index 7cca6b2..e806b3e 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -35,9 +35,6 @@ #include "mpc8xx.h" #include <video_fb.h> -/* imports from common/main.c */ -extern char console_buffer[CONFIG_SYS_CBSIZE]; - extern void eeprom_init (void); extern int eeprom_read (unsigned dev_addr, unsigned offset, unsigned char *buffer, unsigned cnt); diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index 76f7a0c..4df7f0e 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -34,6 +34,7 @@ #include <common.h> #include <commproc.h> #include <mpc8xx.h> +#include <asm/io.h> /***************************************************************************** * UPM table for 60ns EDO RAM at 25 MHz bus/external clock @@ -87,7 +88,7 @@ phys_size_t initdram (int board_type) */ if ((ulong) initdram & 0xff000000) { volatile uint *addr1, *addr2; - uint i, j; + uint i; upmconfig (UPMA, (uint *) edo_60ns_25MHz_tbl, sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); @@ -100,8 +101,8 @@ phys_size_t initdram (int board_type) */ addr1 = (volatile uint *) 0; addr2 = (volatile uint *) 0x00400000; - for (i = 0, j = 0; i < 8; i++) - j = addr1[0]; + for (i = 0; i < 8; i++) + in_be32(addr1); /* * Now check whether we got 4MB or 16MB populated diff --git a/board/emk/top9000/top9000.c b/board/emk/top9000/top9000.c index 61dee62..6f5662a 100644 --- a/board/emk/top9000/top9000.c +++ b/board/emk/top9000/top9000.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * (C) Copyright 2010 diff --git a/board/davinci/common/Makefile b/board/enbw/enbw_cmc/Makefile index 9d7b164..cd1f0d4 100644 --- a/board/davinci/common/Makefile +++ b/board/enbw/enbw_cmc/Makefile @@ -1,7 +1,9 @@ # -# (C) Copyright 2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # +# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> +# # See file CREDITS for list of people who contributed to this # project. # @@ -23,13 +25,9 @@ include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)board/$(VENDOR)/common) -endif - -LIB = $(obj)lib$(VENDOR).o +LIB = $(obj)lib$(BOARD).o -COBJS := misc.o davinci_pinmux.o +COBJS := $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c new file mode 100644 index 0000000..5cd5357 --- /dev/null +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -0,0 +1,607 @@ +/* + * (C) Copyright 2011 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on da830evm.c. Original Copyrights follow: + * + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <hwconfig.h> +#include <i2c.h> +#include <malloc.h> +#include <miiphy.h> +#include <mmc.h> +#include <net.h> +#include <netdev.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/da850_lowlevel.h> +#include <asm/arch/davinci_misc.h> +#include <asm/arch/emif_defs.h> +#include <asm/arch/emac_defs.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux_defs.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdmmc_defs.h> +#include <asm/arch/timer_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct lpsc_resource lpsc[] = { + { DAVINCI_LPSC_AEMIF }, + { DAVINCI_LPSC_SPI1 }, + { DAVINCI_LPSC_ARM_RAM_ROM }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_EMAC }, + { DAVINCI_LPSC_UART0 }, + { DAVINCI_LPSC_GPIO }, + { DAVINCI_LPSC_DDR_EMIF }, + { DAVINCI_LPSC_UART1 }, + { DAVINCI_LPSC_UART2 }, + { DAVINCI_LPSC_MMC_SD1 }, + { DAVINCI_LPSC_USB20 }, + { DAVINCI_LPSC_USB11 }, +}; + +static const struct pinmux_config enbw_pins[] = { + { pinmux(0), 8, 0 }, + { pinmux(0), 8, 1 }, + { pinmux(0), 8, 2 }, + { pinmux(0), 8, 3 }, + { pinmux(0), 8, 4 }, + { pinmux(0), 8, 5 }, + { pinmux(1), 4, 0 }, + { pinmux(1), 8, 1 }, + { pinmux(1), 8, 2 }, + { pinmux(1), 8, 3 }, + { pinmux(1), 8, 4 }, + { pinmux(1), 8, 5 }, + { pinmux(1), 8, 6 }, + { pinmux(1), 4, 7 }, + { pinmux(2), 8, 0 }, + { pinmux(5), 1, 0 }, + { pinmux(5), 1, 3 }, + { pinmux(5), 1, 7 }, + { pinmux(6), 1, 0 }, + { pinmux(6), 1, 1 }, + { pinmux(6), 8, 2 }, + { pinmux(6), 8, 3 }, + { pinmux(6), 1, 4 }, + { pinmux(6), 8, 5 }, + { pinmux(6), 1, 7 }, + { pinmux(7), 8, 2 }, + { pinmux(7), 1, 3 }, + { pinmux(7), 1, 6 }, + { pinmux(7), 1, 7 }, + { pinmux(13), 8, 2 }, + { pinmux(13), 8, 3 }, + { pinmux(13), 8, 4 }, + { pinmux(13), 8, 5 }, + { pinmux(13), 8, 6 }, + { pinmux(13), 8, 7 }, + { pinmux(14), 8, 0 }, + { pinmux(14), 8, 1 }, + { pinmux(16), 8, 1 }, + { pinmux(16), 8, 2 }, + { pinmux(16), 8, 3 }, + { pinmux(16), 8, 4 }, + { pinmux(16), 8, 5 }, + { pinmux(16), 8, 6 }, + { pinmux(16), 8, 7 }, + { pinmux(17), 1, 0 }, + { pinmux(17), 1, 1 }, + { pinmux(17), 1, 2 }, + { pinmux(17), 8, 3 }, + { pinmux(17), 8, 4 }, + { pinmux(17), 8, 5 }, + { pinmux(17), 8, 6 }, + { pinmux(17), 8, 7 }, + { pinmux(18), 8, 0 }, + { pinmux(18), 8, 1 }, + { pinmux(18), 2, 2 }, + { pinmux(18), 2, 3 }, + { pinmux(18), 2, 4 }, + { pinmux(18), 8, 6 }, + { pinmux(18), 8, 7 }, + { pinmux(19), 8, 0 }, + { pinmux(19), 2, 1 }, + { pinmux(19), 2, 2 }, + { pinmux(19), 2, 3 }, + { pinmux(19), 2, 4 }, + { pinmux(19), 8, 5 }, + { pinmux(19), 8, 6 }, +}; + +const struct pinmux_resource pinmuxes[] = { + PINMUX_ITEM(emac_pins_mii), + PINMUX_ITEM(emac_pins_mdio), + PINMUX_ITEM(i2c0_pins), + PINMUX_ITEM(emifa_pins_cs2), + PINMUX_ITEM(emifa_pins_cs3), + PINMUX_ITEM(emifa_pins_cs4), + PINMUX_ITEM(emifa_pins_nand), + PINMUX_ITEM(emifa_pins_nor), + PINMUX_ITEM(spi1_pins_base), + PINMUX_ITEM(spi1_pins_scs0), + PINMUX_ITEM(uart1_pins_txrx), + PINMUX_ITEM(uart2_pins_txrx), + PINMUX_ITEM(uart2_pins_rtscts), + PINMUX_ITEM(enbw_pins), +}; + +const int pinmuxes_size = ARRAY_SIZE(pinmuxes); + +struct gpio_config { + char name[GPIO_NAME_SIZE]; + unsigned char bank; + unsigned char gpio; + unsigned char out; + unsigned char value; +}; + +static const struct gpio_config enbw_gpio_config[] = { + { "RS485 enable", 8, 11, 1, 0 }, + { "RS485 iso", 8, 10, 1, 0 }, + { "W2HUT RS485 Rx ena", 8, 9, 1, 0 }, + { "W2HUT RS485 iso", 8, 8, 1, 0 }, + { "LAN reset", 7, 15, 1, 1 }, + { "ena 11V PLC", 7, 14, 1, 0 }, + { "ena 1.5V PLC", 7, 13, 1, 0 }, + { "disable VBUS", 7, 12, 1, 1 }, + { "PLC reset", 6, 13, 1, 1 }, + { "LCM RS", 6, 12, 1, 0 }, + { "LCM R/W", 6, 11, 1, 0 }, + { "PLC pairing", 6, 10, 1, 1 }, + { "PLC MDIO CLK", 6, 9, 1, 0 }, + { "HK218", 6, 8, 1, 0 }, + { "HK218 Rx", 6, 1, 1, 1 }, + { "TPM reset", 6, 0, 1, 1 }, + { "LCM E", 2, 2, 1, 1 }, + { "PV-IF RxD ena", 0, 15, 1, 1 }, + { "LED1", 1, 15, 1, 1 }, + { "LED2", 0, 1, 1, 1 }, + { "LED3", 0, 2, 1, 1 }, + { "LED4", 0, 3, 1, 1 }, + { "LED5", 0, 4, 1, 1 }, + { "LED6", 0, 5, 1, 0 }, + { "LED7", 0, 6, 1, 0 }, + { "LED8", 0, 14, 1, 0 }, + { "USER1", 0, 12, 0, 0 }, + { "USER2", 0, 13, 0, 0 }, +}; + +#define PHY_POWER 0x0800 + +static void enbw_cmc_switch(int port, int on) +{ + const char *devname; + unsigned char phyaddr = 3; + unsigned char reg = 0; + unsigned short data; + + if (port == 1) + phyaddr = 2; + + devname = miiphy_get_current_dev(); + if (!devname) { + printf("Error: no mii device\n"); + return; + } + if (miiphy_read(devname, phyaddr, reg, &data) != 0) { + printf("Error reading from the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } + + if (on) + data &= ~PHY_POWER; + else + data |= PHY_POWER; + + if (miiphy_write(devname, phyaddr, reg, data) != 0) { + printf("Error writing to the PHY addr=%02x reg=%02x\n", + phyaddr, reg); + return; + } +} + +int board_init(void) +{ + int i, ret; + +#ifndef CONFIG_USE_IRQ + irq_init(); +#endif + /* address of boot parameters, not used as booting with DTT */ + gd->bd->bi_boot_params = 0; + + for (i = 0; i < ARRAY_SIZE(enbw_gpio_config); i++) { + int gpio = enbw_gpio_config[i].bank * 16 + + enbw_gpio_config[i].gpio; + + ret = gpio_request(gpio, enbw_gpio_config[i].name); + if (ret) { + printf("%s: Could not get %s gpio\n", __func__, + enbw_gpio_config[i].name); + return -1; + } + + if (enbw_gpio_config[i].out) + gpio_direction_output(gpio, + enbw_gpio_config[i].value); + else + gpio_direction_input(gpio); + } + + /* setup the SUSPSRC for ARM to control emulation suspend */ + clrbits_le32(&davinci_syscfg_regs->suspsrc, + (DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | + DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | + DAVINCI_SYSCFG_SUSPSRC_UART2)); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +/* + * Initializes on-board ethernet controllers. + */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_DRIVER_TI_EMAC + davinci_emac_mii_mode_sel(0); +#endif /* CONFIG_DRIVER_TI_EMAC */ + + if (!davinci_emac_initialize()) { + printf("Error: Ethernet init failed!\n"); + return -1; + } + + if (hwconfig_subarg_cmp("switch", "lan", "on")) + /* Switch port lan on */ + enbw_cmc_switch(1, 1); + else + enbw_cmc_switch(1, 0); + + if (hwconfig_subarg_cmp("switch", "pwl", "on")) + /* Switch port pwl on */ + enbw_cmc_switch(2, 1); + else + enbw_cmc_switch(2, 0); + + return 0; +} +#endif /* CONFIG_DRIVER_TI_EMAC */ + +#ifdef CONFIG_PREBOOT +static uchar kbd_magic_prefix[] = "key_magic_"; +static uchar kbd_command_prefix[] = "key_cmd_"; + +struct kbd_data_t { + char s1; +}; + +struct kbd_data_t *get_keys(struct kbd_data_t *kbd_data) +{ + /* read SW1 + SW2 */ + kbd_data->s1 = gpio_get_value(12) + + (gpio_get_value(13) << 1); + return kbd_data; +} + +static int compare_magic(const struct kbd_data_t *kbd_data, char *str) +{ + char s1 = str[0]; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s1) + return -1; + + return 0; +} + +static char *key_match(const struct kbd_data_t *kbd_data) +{ + char magic[sizeof(kbd_magic_prefix) + 1]; + char *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + kbd_magic_keys = getenv("magic_keys"); + if (kbd_magic_keys == NULL) + kbd_magic_keys = ""; + + /* + * loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + + if (compare_magic(kbd_data, getenv(magic)) == 0) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + + return cmd; + } + } + + return NULL; +} +#endif /* CONFIG_PREBOOT */ + +int misc_init_r(void) +{ + char *s, buf[32]; +#ifdef CONFIG_PREBOOT + struct kbd_data_t kbd_data; + /* Decode keys */ + char *str = strdup(key_match(get_keys(&kbd_data))); + /* Set or delete definition */ + setenv("preboot", str); + free(str); +#endif /* CONFIG_PREBOOT */ + + /* count all restarts, and save this in an environment var */ + s = getenv("restartcount"); + + if (s) + sprintf(buf, "%ld", simple_strtoul(s, NULL, 10) + 1); + else + strcpy(buf, "1"); + + setenv("restartcount", buf); + saveenv(); + +#ifdef CONFIG_HW_WATCHDOG + davinci_hw_watchdog_enable(); +#endif + + return 0; +} + +struct cmc_led { + char name[20]; + unsigned char bank; + unsigned char gpio; +}; + +struct cmc_led led_table[] = { + {"led1", 1, 15}, + {"led2", 0, 1}, + {"led3", 0, 2}, + {"led4", 0, 3}, + {"led5", 0, 4}, + {"led6", 0, 5}, + {"led7", 0, 6}, + {"led8", 0, 14}, +}; + +static int cmc_get_led_state(struct cmc_led *led) +{ + int value; + int gpio = led->bank * 16 + led->gpio; + + value = gpio_get_value(gpio); + + return value; +} + +static int cmc_set_led_state(struct cmc_led *led, int state) +{ + int gpio = led->bank * 16 + led->gpio; + + gpio_set_value(gpio, state); + return 0; +} + +static int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + struct cmc_led *led; + int found = 0; + int i = 0; + int only_print = 0; + int len = ARRAY_SIZE(led_table); + + if (argc < 2) + return cmd_usage(cmdtp); + + if (argc < 3) + only_print = 1; + + led = led_table; + while ((!found) && (i < len)) { + if (strcmp(argv[1], led->name) == 0) { + found = 1; + } else { + led++; + i++; + } + } + if (!found) + return cmd_usage(cmdtp); + + if (only_print) { + if (cmc_get_led_state(led)) + printf("on\n"); + else + printf("off\n"); + + return 0; + } + if (strcmp(argv[2], "on") == 0) + cmc_set_led_state(led, 1); + else + cmc_set_led_state(led, 0); + + return 0; +} + +U_BOOT_CMD(led, 3, 1, do_led, + "switch on/off board led", + "[name] [on/off]" +); + +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + davinci_hw_watchdog_reset(); +} +#endif + +#if defined(CONFIG_POST) +void arch_memory_failure_handle(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + int state = 1; + + /* + * if memor< failure blink with the LED 1,2 and 3 + * as we running from flash, we cannot use the gpio + * api here, so access the gpio pin direct through + * the gpio register. + */ + while (1) { + if (state) { + clrbits_le32(&gpio->out_data, 0x80000006); + state = 0; + } else { + setbits_le32(&gpio->out_data, 0x80000006); + state = 1; + } + udelay(500); + } +} +#endif + +#if defined(CONFIG_BOOTCOUNT_LIMIT) +void bootcount_store(ulong a) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + /* + * write RTC kick register to enable write + * for RTC Scratch registers. Cratch0 and 1 are + * used for bootcount values. + */ + out_be32(®->kick0r, RTC_KICK0R_WE); + out_be32(®->kick1r, RTC_KICK1R_WE); + out_be32(®->scratch0, a); + out_be32(®->scratch1, BOOTCOUNT_MAGIC); +} + +ulong bootcount_load(void) +{ + struct davinci_rtc *reg = + (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; + + if (in_be32(®->scratch1) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32(®->scratch0); +} +#endif + +void board_gpio_init(void) +{ + struct davinci_gpio *gpio = davinci_gpio_bank01; + + /* + * Power on required peripherals + * ARM does not have access by default to PSC0 and PSC1 + * assuming here that the DSP bootloader has set the IOPU + * such that PSC access is available to ARM + */ + if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) + return; + + /* + * set LED (gpio Interface not usable here) + * set LED pins to output and state 0 + */ + clrbits_le32(&gpio->dir, 0x8000407e); + clrbits_le32(&gpio->out_data, 0x8000407e); + /* set LED 1 - 5 to state on */ + setbits_le32(&gpio->out_data, 0x8000001e); +} + +int board_late_init(void) +{ + cmc_set_led_state(&led_table[4], 0); + + return 0; +} + +void show_boot_progress(int val) +{ + switch (val) { + case 1: + cmc_set_led_state(&led_table[4], 1); + break; + case 4: + cmc_set_led_state(&led_table[4], 0); + break; + case 15: + cmc_set_led_state(&led_table[4], 1); + break; + } +} + +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd1 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD1_BASE, + .input_clk = 228000000, + .host_caps = MMC_MODE_4BIT, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd1.input_clk = clk_get(DAVINCI_MMC_CLKID); + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd1); +} +#endif diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 4dfea71..fc60545 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -91,7 +91,6 @@ int au_check_cksum_valid(int i, long nbytes) int au_check_header_valid(int i, long nbytes) { image_header_t *hdr; - unsigned long checksum; hdr = (image_header_t *)LOAD_ADDR; #if defined(CONFIG_FIT) @@ -127,9 +126,6 @@ int au_check_header_valid(int i, long nbytes) return -1; } - /* recycle checksum */ - checksum = image_get_data_size (hdr); - return 0; } @@ -397,7 +393,7 @@ int do_auto_update(void) { block_dev_desc_t *stor_dev = NULL; long sz; - int i, res, cnt, old_ctrlc, got_ctrlc; + int i, res, cnt, old_ctrlc; char buffer[32]; char str[80]; int n; @@ -473,8 +469,6 @@ int do_auto_update(void) /* let the user break out of the loop */ if (ctrlc() || had_ctrlc ()) { clear_ctrlc (); - if (res < 0) - got_ctrlc = 1; break; } cnt++; diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c index 9823e5e..cba33b8 100644 --- a/board/esd/common/xilinx_jtag/micro.c +++ b/board/esd/common/xilinx_jtag/micro.c @@ -1831,7 +1831,6 @@ int xsvfExecute(void) int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int iErrorCode; - char* pzXsvfFileName; unsigned long duration; unsigned long long startClock, endClock; @@ -1847,7 +1846,6 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); - pzXsvfFileName = 0; xsvf_iDebugLevel = 0; printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 98a8584..41b5ba0 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -656,7 +656,6 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int i; unsigned char ow_id[6]; char str[32]; - unsigned char ow_crc; /* * Clear 1-wire bit (open drain with pull-up) @@ -675,11 +674,10 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) OWReadByte(); /* skip family code ( == 0x01) */ for (i = 0; i < 6; i++) ow_id[i] = OWReadByte(); - ow_crc = OWReadByte(); /* read crc */ + OWReadByte(); /* read crc */ - sprintf(str, "%08X%04X", - *(unsigned int *)&ow_id[0], - *(unsigned short *)&ow_id[4]); + sprintf(str, "%02X%02X%02X%02X%02X%02X", + ow_id[0], ow_id[1], ow_id[2], ow_id[3], ow_id[4], ow_id[5]); printf("Setting environment variable 'ow_id' to %s\n", str); setenv("ow_id", str); diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index f27d65e..08311c9 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -566,7 +566,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) volatile unsigned int *ptr; int count = 0; int count2 = 0; - int status; + int status = 0; char addr[16]; char str[] = "\\|/-"; char *local_args[2]; @@ -622,7 +622,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; } - return 0; + return status; } U_BOOT_CMD( diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 615e32a..9767cf2 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -47,18 +47,6 @@ DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG -/* #define DEBUG */ -#ifdef CONFIG_PCI -#define MAP_PCI -#endif /* of CONFIG_PCI */ - -#ifdef DEBUG -#define DP(x) x -#else -#define DP(x) -#endif - int set_dfcdlInit(void); /* setup delay line of Mv64360 */ /* ------------------------------------------------------------------------- */ @@ -250,8 +238,6 @@ NSto10PS(unsigned char spd_byte) /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) { - unsigned long spd_checksum; - uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; int ret; unsigned int i, j, density = 1, devicesForErrCheck = 0; @@ -264,7 +250,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) uchar supp_cal, cal_val; ulong memclk, tmemclk; ulong tmp; - uchar trp_clocks = 0, trcd_clocks, tras_clocks, trrd_clocks; + uchar trp_clocks = 0, tras_clocks; uchar data[128]; memclk = gd->bus_clk; @@ -275,11 +261,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) ret = 0; - DP (puts ("before i2c read\n")); + debug("before i2c read\n"); ret = i2c_read (addr, 0, 2, data, 128); - DP (puts ("after i2c read\n")); + debug("after i2c read\n"); if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd') || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm') @@ -345,7 +331,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } if (ret) { - DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret)); + debug("No DIMM in slot %d [err = %x]\n", slot, ret); return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ @@ -402,8 +388,9 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /*------------------------------------------------------------------------------------------------------------------------------*/ /* calculate SPD checksum */ /*------------------------------------------------------------------------------------------------------------------------------*/ - spd_checksum = 0; #if 0 /* test-only */ + spd_checksum = 0; + for (i = 0; i <= 62; i++) { spd_checksum += data[i]; } @@ -424,46 +411,40 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; #ifdef DEBUG if (dimmInfo->memoryType == 0) - DP (printf - ("Dram_type in slot %d is: SDRAM\n", - dimmInfo->slot)); + debug("Dram_type in slot %d is: SDRAM\n", + dimmInfo->slot); if (dimmInfo->memoryType == 1) - DP (printf - ("Dram_type in slot %d is: DDRAM\n", - dimmInfo->slot)); + debug("Dram_type in slot %d is: DDRAM\n", + dimmInfo->slot); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 3: /* Number Of Row Addresses */ dimmInfo->numOfRowAddresses = data[i]; - DP (printf - ("Module Number of row addresses: %d\n", - dimmInfo->numOfRowAddresses)); + debug("Module Number of row addresses: %d\n", + dimmInfo->numOfRowAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 4: /* Number Of Column Addresses */ dimmInfo->numOfColAddresses = data[i]; - DP (printf - ("Module Number of col addresses: %d\n", - dimmInfo->numOfColAddresses)); + debug("Module Number of col addresses: %d\n", + dimmInfo->numOfColAddresses); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 5: /* Number Of Module Banks */ dimmInfo->numOfModuleBanks = data[i]; - DP (printf - ("Number of Banks on Mod. : %d\n", - dimmInfo->numOfModuleBanks)); + debug("Number of Banks on Mod. : %d\n", + dimmInfo->numOfModuleBanks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 6: /* Data Width */ dimmInfo->dataWidth = data[i]; - DP (printf - ("Module Data Width: %d\n", - dimmInfo->dataWidth)); + debug("Module Data Width: %d\n", + dimmInfo->dataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -471,33 +452,27 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) switch (data[i]) { case 0x0: dimmInfo->voltageInterface = TTL_5V_TOLERANT; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug("Module is TTL_5V_TOLERANT\n"); break; case 0x1: dimmInfo->voltageInterface = LVTTL; - DP (printf - ("Module is LVTTL\n")); + debug("Module is LVTTL\n"); break; case 0x2: dimmInfo->voltageInterface = HSTL_1_5V; - DP (printf - ("Module is TTL_5V_TOLERANT\n")); + debug("Module is TTL_5V_TOLERANT\n"); break; case 0x3: dimmInfo->voltageInterface = SSTL_3_3V; - DP (printf - ("Module is HSTL_1_5V\n")); + debug("Module is HSTL_1_5V\n"); break; case 0x4: dimmInfo->voltageInterface = SSTL_2_5V; - DP (printf - ("Module is SSTL_2_5V\n")); + debug("Module is SSTL_2_5V\n"); break; default: dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; - DP (printf - ("Module is VOLTAGE_UNKNOWN\n")); + debug("Module is VOLTAGE_UNKNOWN\n"); break; } break; @@ -516,9 +491,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -531,9 +505,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOut_LoP = leftOfPoint; dimmInfo->clockToDataOut_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out: %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out: %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -541,42 +514,37 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) #ifdef CONFIG_MV64360_ECC case 11: /* Error Check Type */ dimmInfo->errorCheckType = data[i]; - DP (printf - ("Error Check Type (0=NONE): %d\n", - dimmInfo->errorCheckType)); + debug("Error Check Type (0=NONE): %d\n", + dimmInfo->errorCheckType); break; #endif /* of ifdef CONFIG_MV64360_ECC */ /*------------------------------------------------------------------------------------------------------------------------------*/ case 12: /* Refresh Interval */ dimmInfo->RefreshInterval = data[i]; - DP (printf - ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", - dimmInfo->RefreshInterval)); + debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", + dimmInfo->RefreshInterval); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 13: /* Sdram Width */ dimmInfo->sdramWidth = data[i]; - DP (printf - ("Sdram Width: %d\n", - dimmInfo->sdramWidth)); + debug("Sdram Width: %d\n", + dimmInfo->sdramWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 14: /* Error Check Data Width */ dimmInfo->errorCheckDataWidth = data[i]; - DP (printf - ("Error Check Data Width: %d\n", - dimmInfo->errorCheckDataWidth)); + debug("Error Check Data Width: %d\n", + dimmInfo->errorCheckDataWidth); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 15: /* Minimum Clock Delay */ dimmInfo->minClkDelay = data[i]; - DP (printf - ("Minimum Clock Delay: %d\n", - dimmInfo->minClkDelay)); + debug("Minimum Clock Delay: %d\n", + dimmInfo->minClkDelay); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -592,26 +560,24 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo->burstLengthSupported = data[i]; #ifdef DEBUG - DP (printf - ("Burst Length Supported: ")); + debug("Burst Length Supported: "); if (dimmInfo->burstLengthSupported & 0x01) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->burstLengthSupported & 0x02) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->burstLengthSupported & 0x04) - DP (printf ("4, ")); + debug("4, "); if (dimmInfo->burstLengthSupported & 0x08) - DP (printf ("8, ")); - DP (printf (" Bit \n")); + debug("8, "); + debug(" Bit \n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 17: /* Number Of Banks On Each Device */ dimmInfo->numOfBanksOnEachDevice = data[i]; - DP (printf - ("Number Of Banks On Each Chip: %d\n", - dimmInfo->numOfBanksOnEachDevice)); + debug("Number Of Banks On Each Chip: %d\n", + dimmInfo->numOfBanksOnEachDevice); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -631,34 +597,32 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) ********************************************************/ dimmInfo->suportedCasLatencies = data[i]; #ifdef DEBUG - DP (printf - ("Suported Cas Latencies: (CL) ")); + debug("Suported Cas Latencies: (CL) "); if (dimmInfo->memoryType == 0) { /* SDRAM */ for (k = 0; k <= 7; k++) { if (dimmInfo-> suportedCasLatencies & (1 << k)) - DP (printf - ("%d, ", - k + 1)); + debug("%d, ", + k + 1); } } else { /* DDR-RAM */ if (dimmInfo->suportedCasLatencies & 1) - DP (printf ("1, ")); + debug("1, "); if (dimmInfo->suportedCasLatencies & 2) - DP (printf ("1.5, ")); + debug("1.5, "); if (dimmInfo->suportedCasLatencies & 4) - DP (printf ("2, ")); + debug("2, "); if (dimmInfo->suportedCasLatencies & 8) - DP (printf ("2.5, ")); + debug("2.5, "); if (dimmInfo->suportedCasLatencies & 16) - DP (printf ("3, ")); + debug("3, "); if (dimmInfo->suportedCasLatencies & 32) - DP (printf ("3.5, ")); + debug("3.5, "); } - DP (printf ("\n")); + debug("\n"); #endif /* Calculating MAX CAS latency */ for (j = 7; j > 0; j--) { @@ -670,8 +634,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ switch (j) { case 7: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -679,8 +642,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) hang (); break; case 6: - DP (printf - ("Max. Cas Latencies (DDR): ERROR !!!\n")); + debug("Max. Cas Latencies (DDR): ERROR !!!\n"); dimmInfo-> maxClSupported_DDR = @@ -688,36 +650,31 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) hang (); break; case 5: - DP (printf - ("Max. Cas Latencies (DDR): 3.5 clk's\n")); + debug("Max. Cas Latencies (DDR): 3.5 clk's\n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3_5; break; case 4: - DP (printf - ("Max. Cas Latencies (DDR): 3 clk's \n")); + debug("Max. Cas Latencies (DDR): 3 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_3; break; case 3: - DP (printf - ("Max. Cas Latencies (DDR): 2.5 clk's \n")); + debug("Max. Cas Latencies (DDR): 2.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2_5; break; case 2: - DP (printf - ("Max. Cas Latencies (DDR): 2 clk's \n")); + debug("Max. Cas Latencies (DDR): 2 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_2; break; case 1: - DP (printf - ("Max. Cas Latencies (DDR): 1.5 clk's \n")); + debug("Max. Cas Latencies (DDR): 1.5 clk's \n"); dimmInfo-> maxClSupported_DDR = DDR_CL_1_5; @@ -736,32 +693,29 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; case SDRAM: /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ - DP (printf - ("Max. Cas Latencies (SD): %d\n", + debug("Max. Cas Latencies (SD): %d\n", dimmInfo-> - maxClSupported_SD)); + maxClSupported_SD); dimmInfo-> maxCASlatencySupported_LoP = j; dimmInfo-> maxCASlatencySupported_RoP = 0; - DP (printf - ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", + debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", dimmInfo-> maxCASlatencySupported_LoP, dimmInfo-> - maxCASlatencySupported_RoP)); + maxCASlatencySupported_RoP); break; } break; @@ -771,7 +725,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /*------------------------------------------------------------------------------------------------------------------------------*/ case 21: /* Buffered Address And Control Inputs */ - DP (printf ("\nModul Attributes (SPD Byte 21): \n")); + debug("\nModul Attributes (SPD Byte 21): \n"); dimmInfo->bufferedAddrAndControlInputs = data[i] & BIT0; dimmInfo->registeredAddrAndControlInputs = @@ -784,62 +738,47 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (data[i] & BIT5) >> 5; dimmInfo->redundantRowAddressing = (data[i] & BIT6) >> 6; -#ifdef DEBUG + if (dimmInfo->bufferedAddrAndControlInputs == 1) - DP (printf - (" - Buffered Address/Control Input: Yes \n")); + debug(" - Buffered Address/Control Input: Yes \n"); else - DP (printf - (" - Buffered Address/Control Input: No \n")); + debug(" - Buffered Address/Control Input: No \n"); if (dimmInfo->registeredAddrAndControlInputs == 1) - DP (printf - (" - Registered Address/Control Input: Yes \n")); + debug(" - Registered Address/Control Input: Yes \n"); else - DP (printf - (" - Registered Address/Control Input: No \n")); + debug(" - Registered Address/Control Input: No \n"); if (dimmInfo->onCardPLL == 1) - DP (printf - (" - On-Card PLL (clock): Yes \n")); + debug(" - On-Card PLL (clock): Yes \n"); else - DP (printf - (" - On-Card PLL (clock): No \n")); + debug(" - On-Card PLL (clock): No \n"); if (dimmInfo->bufferedDQMBinputs == 1) - DP (printf - (" - Bufferd DQMB Inputs: Yes \n")); + debug(" - Bufferd DQMB Inputs: Yes \n"); else - DP (printf - (" - Bufferd DQMB Inputs: No \n")); + debug(" - Bufferd DQMB Inputs: No \n"); if (dimmInfo->registeredDQMBinputs == 1) - DP (printf - (" - Registered DQMB Inputs: Yes \n")); + debug(" - Registered DQMB Inputs: Yes \n"); else - DP (printf - (" - Registered DQMB Inputs: No \n")); + debug(" - Registered DQMB Inputs: No \n"); if (dimmInfo->differentialClockInput == 1) - DP (printf - (" - Differential Clock Input: Yes \n")); + debug(" - Differential Clock Input: Yes \n"); else - DP (printf - (" - Differential Clock Input: No \n")); + debug(" - Differential Clock Input: No \n"); if (dimmInfo->redundantRowAddressing == 1) - DP (printf - (" - redundant Row Addressing: Yes \n")); + debug(" - redundant Row Addressing: Yes \n"); else - DP (printf - (" - redundant Row Addressing: No \n")); + debug(" - redundant Row Addressing: No \n"); -#endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 22: /* Suported AutoPreCharge */ - DP (printf ("\nModul Attributes (SPD Byte 22): \n")); + debug("\nModul Attributes (SPD Byte 22): \n"); dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; dimmInfo->suportedAutoPreCharge = (data[i] & BIT1) >> 1; @@ -851,50 +790,37 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) (data[i] & BIT4) >> 4; dimmInfo->suported5PercentUpperVCC = (data[i] & BIT5) >> 5; -#ifdef DEBUG + if (dimmInfo->suportedEarlyRasPreCharge == 1) - DP (printf - (" - Early Ras Precharge: Yes \n")); + debug(" - Early Ras Precharge: Yes \n"); else - DP (printf - (" - Early Ras Precharge: No \n")); + debug(" - Early Ras Precharge: No \n"); if (dimmInfo->suportedAutoPreCharge == 1) - DP (printf - (" - AutoPreCharge: Yes \n")); + debug(" - AutoPreCharge: Yes \n"); else - DP (printf - (" - AutoPreCharge: No \n")); + debug(" - AutoPreCharge: No \n"); if (dimmInfo->suportedPreChargeAll == 1) - DP (printf - (" - Precharge All: Yes \n")); + debug(" - Precharge All: Yes \n"); else - DP (printf - (" - Precharge All: No \n")); + debug(" - Precharge All: No \n"); if (dimmInfo->suportedWrite1ReadBurst == 1) - DP (printf - (" - Write 1/ReadBurst: Yes \n")); + debug(" - Write 1/ReadBurst: Yes \n"); else - DP (printf - (" - Write 1/ReadBurst: No \n")); + debug(" - Write 1/ReadBurst: No \n"); if (dimmInfo->suported5PercentLowVCC == 1) - DP (printf - (" - lower VCC tolerance: 5 Percent \n")); + debug(" - lower VCC tolerance: 5 Percent \n"); else - DP (printf - (" - lower VCC tolerance: 10 Percent \n")); + debug(" - lower VCC tolerance: 10 Percent \n"); if (dimmInfo->suported5PercentUpperVCC == 1) - DP (printf - (" - upper VCC tolerance: 5 Percent \n")); + debug(" - upper VCC tolerance: 5 Percent \n"); else - DP (printf - (" - upper VCC tolerance: 10 Percent \n")); + debug(" - upper VCC tolerance: 10 Percent \n"); -#endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -911,9 +837,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -927,9 +852,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -946,9 +870,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) leftOfPoint; dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = rightOfPoint; - DP (printf - ("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", + leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -962,9 +885,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = time_tmp % div; dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; - DP (printf - ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", - leftOfPoint, rightOfPoint)); + debug("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", + leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -981,12 +903,10 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) trp_clocks = (dimmInfo->minRowPrechargeTime + (tmemclk - 1)) / tmemclk; - DP (printf - ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", - tmemclk, tmemclk / 100, tmemclk % 100)); - DP (printf - ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", + tmemclk, tmemclk / 100, tmemclk % 100); + debug("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1000,12 +920,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trrd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1019,12 +935,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) rightOfPoint = (data[i] & maskRightOfPoint) * 25; dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ - trcd_clocks = - (dimmInfo->minRowActiveRowActiveDelay + - (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", - leftOfPoint, rightOfPoint, trp_clocks)); + debug("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", + leftOfPoint, rightOfPoint, trp_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1033,41 +945,38 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) tras_clocks = (NSto10PS (data[i]) + (tmemclk - 1)) / tmemclk; - DP (printf - ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", - dimmInfo->minRasPulseWidth, tras_clocks)); + debug("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", + dimmInfo->minRasPulseWidth, tras_clocks); break; /*------------------------------------------------------------------------------------------------------------------------------*/ case 31: /* Module Bank Density */ dimmInfo->moduleBankDensity = data[i]; - DP (printf - ("Module Bank Density: %d\n", - dimmInfo->moduleBankDensity)); + debug("Module Bank Density: %d\n", + dimmInfo->moduleBankDensity); #ifdef DEBUG - DP (printf - ("*** Offered Densities (more than 1 = Multisize-Module): ")); + debug("*** Offered Densities (more than 1 = Multisize-Module): "); { if (dimmInfo->moduleBankDensity & 1) - DP (printf ("4MB, ")); + debug("4MB, "); if (dimmInfo->moduleBankDensity & 2) - DP (printf ("8MB, ")); + debug("8MB, "); if (dimmInfo->moduleBankDensity & 4) - DP (printf ("16MB, ")); + debug("16MB, "); if (dimmInfo->moduleBankDensity & 8) - DP (printf ("32MB, ")); + debug("32MB, "); if (dimmInfo->moduleBankDensity & 16) - DP (printf ("64MB, ")); + debug("64MB, "); if (dimmInfo->moduleBankDensity & 32) - DP (printf ("128MB, ")); + debug("128MB, "); if ((dimmInfo->moduleBankDensity & 64) || (dimmInfo->moduleBankDensity & 128)) { - DP (printf ("ERROR, ")); + debug("ERROR, "); hang (); } } - DP (printf ("\n")); + debug("\n"); #endif break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1093,9 +1002,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->addrAndCommandSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Address And Command Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1120,9 +1028,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->addrAndCommandHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Address And Command Hold Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Address And Command Hold Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1147,9 +1054,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->dataInputSetupTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Setup Time [ns]: %d.%d\n", - sign * leftOfPoint, rightOfPoint)); + debug("Data Input Setup Time [ns]: %d.%d\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ @@ -1174,9 +1080,8 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } dimmInfo->dataInputHoldTime = (leftOfPoint * 100 + rightOfPoint) * sign; - DP (printf - ("Data Input Hold Time [ns]: %d.%d\n\n", - sign * leftOfPoint, rightOfPoint)); + debug("Data Input Hold Time [ns]: %d.%d\n\n", + sign * leftOfPoint, rightOfPoint); break; /*------------------------------------------------------------------------------------------------------------------------------*/ } @@ -1213,7 +1118,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) tmp *= dimmInfo->sdramWidth; tmp = tmp >> 24; /* div by 0x4000000 (64M) */ dimmInfo->drb_size = (uchar) tmp; - DP (printf ("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size)); + debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); /* try a CAS latency of 3 first... */ @@ -1236,11 +1141,11 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) cal_val = 4; } - DP (printf ("cal_val = %d\n", cal_val * 5)); + debug("cal_val = %d\n", cal_val * 5); /* bummer, did't work... */ if (cal_val == 0) { - DP (printf ("Couldn't find a good CAS latency\n")); + debug("Couldn't find a good CAS latency\n"); hang (); return 0; } @@ -1267,81 +1172,74 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* Program the GT with the discovered data */ if (info->registeredAddrAndControlInputs == true) - DP (printf - ("Module is registered, but we do not support registered Modules !!!\n")); + debug("Module is registered, but we do not support registered Modules !!!\n"); /* delay line */ set_dfcdlInit (); /* may be its not needed */ - DP (printf ("Delay line set done\n")); + debug("Delay line set done\n"); /* set SDRAM mode NOP */ /* To_do check it */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); } #ifdef CONFIG_MV64360_ECC if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) { /* DRAM has ECC, so turn it on */ sdram_config_reg |= BIT18; - DP(printf("Enabling ECC\n")); + debug("Enabling ECC\n"); } #endif /* of ifdef CONFIG_MV64360_ECC */ /* SDRAM configuration */ GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg); - DP (printf ("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG))); + debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG)); /* SDRAM open pages controll keep open as much as I can */ GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); - DP (printf - ("sdram_open_pages_controll 0x1414: %08x\n", - GTREGREAD (SDRAM_OPEN_PAGES_CONTROL))); + debug("sdram_open_pages_controll 0x1414: %08x\n", + GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ if (tmp == 0) - DP (printf ("Core Signals are sync (by HW-Setting)!!!\n")); + debug("Core Signals are sync (by HW-Setting)!!!\n"); else - DP (printf - ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n")); + debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); /* SDRAM set CAS Lentency according to SPD information */ switch (info->memoryType) { case SDRAM: - DP (printf ("### SD-RAM not supported yet !!!\n")); + debug("### SD-RAM not supported yet !!!\n"); hang (); /* ToDo fill SD-RAM if needed !!!!! */ break; case DDR: - DP (printf ("### SET-CL for DDR-RAM\n")); + debug("### SET-CL for DDR-RAM\n"); switch (info->maxClSupported_DDR) { case DDR_CL_3: tmp_dunit_control_low = 0x3c000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ - DP (printf - ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); break; case DDR_CL_2_5: if (tmp == 1) { /* clocks sync */ tmp_dunit_control_low = 0x24000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* clk sync. bypassed */ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x62; /* CL=2,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1349,16 +1247,14 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (tmp == 1) { /* Sync */ tmp_dunit_control_low = 0x03000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* Not sync. */ tmp_dunit_control_low = 0x3b000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ - DP (printf - ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1366,16 +1262,14 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (tmp == 1) { /* Sync */ tmp_dunit_control_low = 0x23000000; /* Read-Data sampled on falling edge of Clk */ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } else { /* not sync */ tmp_dunit_control_low = 0x1a000000; /* Read-Data sampled on rising edge of Clk */ tmp_sdram_mode = 0x52; /* CL=1,5 Burstlength = 4 */ - DP (printf - ("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", - tmp_sdram_mode, tmp_dunit_control_low)); + debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", + tmp_sdram_mode, tmp_dunit_control_low); } break; @@ -1393,8 +1287,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } @@ -1415,8 +1308,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* set SDRAM mode SetCommand 0x1418 */ GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); } /*------------------------------------------------------------------------------ */ @@ -1428,41 +1320,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) tmp = 0x02; - DP (printf ("drb_size (n*64Mbit): %d\n", info->drb_size)); + debug("drb_size (n*64Mbit): %d\n", info->drb_size); switch (info->drb_size) { case 1: /* 64 Mbit */ case 2: /* 128 Mbit */ - DP (printf ("RAM-Device_size 64Mbit or 128Mbit)\n")); + debug("RAM-Device_size 64Mbit or 128Mbit)\n"); tmp |= (0x00 << 4); break; case 4: /* 256 Mbit */ case 8: /* 512 Mbit */ - DP (printf ("RAM-Device_size 256Mbit or 512Mbit)\n")); + debug("RAM-Device_size 256Mbit or 512Mbit)\n"); tmp |= (0x01 << 4); break; case 16: /* 1 Gbit */ case 32: /* 2 Gbit */ - DP (printf ("RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); break; default: printf ("Error in dram size calculation\n"); - DP (printf ("Assume: RAM-Device_size 1Gbit or 2Gbit)\n")); + debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n"); tmp |= (0x02 << 4); return 1; } /* SDRAM bank parameters */ /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */ - DP (printf - ("setting up slot %d config with: %08lx \n", info->slot, tmp)); + debug("setting up slot %d config with: %08lx \n", info->slot, tmp); GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); /* ------------------------------------------------------------------------------ */ - DP (printf - ("setting up sdram_timing_control_low with: %08x \n", - 0x11511220)); + debug("setting up sdram_timing_control_low with: %08x \n", + 0x11511220); GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); @@ -1474,38 +1364,33 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) if (info->registeredAddrAndControlInputs || info->registeredDQMBinputs) { tmp |= (1 << 17); - DP (printf - ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", + debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", info->registeredAddrAndControlInputs, - info->registeredDQMBinputs)); + info->registeredDQMBinputs); } /* Use buffer 1 to return read data to the CPU * Page 426 MV64360 */ tmp |= (1 << 26); - DP (printf - ("Before Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); - DP (printf - ("After Buffer assignment - sdram_conf: %08x\n", - GTREGREAD (SDRAM_CONFIG))); + debug("Before Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG)); + debug("After Buffer assignment - sdram_conf: %08x\n", + GTREGREAD (SDRAM_CONFIG)); /* SDRAM timing To_do: */ tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH); - DP (printf ("# sdram_timing_control_high is : %08lx \n", tmp)); + debug("# sdram_timing_control_high is : %08lx \n", tmp); /* SDRAM address decode register */ /* program this with the default value */ tmp = GTREGREAD (SDRAM_ADDR_CONTROL); - DP (printf - ("SDRAM address control (before: decode): %08x ", - GTREGREAD (SDRAM_ADDR_CONTROL))); + debug("SDRAM address control (before: decode): %08x ", + GTREGREAD (SDRAM_ADDR_CONTROL)); GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2)); - DP (printf - ("SDRAM address control (after: decode): %08x\n", - GTREGREAD (SDRAM_ADDR_CONTROL))); + debug("SDRAM address control (after: decode): %08x\n", + GTREGREAD (SDRAM_ADDR_CONTROL)); /* set the SDRAM configuration for each bank */ @@ -1514,8 +1399,7 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) int l, l1; i = info->slot; - DP (printf - ("\n*** Running a MRS cycle for bank %d ***\n", i)); + debug("\n*** Running a MRS cycle for bank %d ***\n", i); /* map the bank */ memory_map_bank (i, 0, GB / 4); @@ -1525,15 +1409,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); GT_REG_WRITE (SDRAM_OPERATION, 0x4); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } l1 = 0; for (l=0;l<200;l++) @@ -1542,15 +1424,13 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) GT_REG_WRITE (SDRAM_MODE, tmp); GT_REG_WRITE (SDRAM_OPERATION, 0x3); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } /* switch back to normal operation mode */ GT_REG_WRITE (SDRAM_OPERATION, 0x5); while (GTREGREAD (SDRAM_OPERATION) != 0) { - DP (printf - ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); } #endif /* test only */ @@ -1597,7 +1477,7 @@ dram_size(long int *base, long int maxsize) *b=save2; if (val != cnt) { - DP(printf("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr)); + debug("Found %08x at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr); /* fix boundary condition.. STARTVAL means zero */ if(cnt==STARTVAL/sizeof(long)) cnt=0; return (cnt * sizeof(long)); @@ -1690,7 +1570,6 @@ int mv_dma_transfer(int engine, ulong source_addr, phys_size_t initdram(int board_type) { - int s0 = 0, s1 = 0; int checkbank[4] = { [0 ... 3] = 0 }; ulong realsize, total, check; AUX_MEM_DIMM_INFO dimmInfo1; @@ -1709,10 +1588,10 @@ initdram(int board_type) printf("Skipping SD- DDRRAM setup due to NHR bit being set\n"); } else { /* DIMM0 */ - s0 = check_dimm(0, &dimmInfo1); + (void)check_dimm(0, &dimmInfo1); /* DIMM1 */ - s1 = check_dimm(1, &dimmInfo2); + (void)check_dimm(1, &dimmInfo2); memory_map_bank(0, 0, 0); memory_map_bank(1, 0, 0); diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 4946538..0014808 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -132,8 +132,6 @@ static void showPci9054 (void) static void updatePci9054 (void) { - int val; - /* * Set EEPROM write-protect register to 0 */ @@ -141,44 +139,44 @@ static void updatePci9054 (void) in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0x905410b5); - val = PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ - val = PciEepromWriteLongVPD (0x08, 0x28140100); + PciEepromWriteLongVPD (0x00, 0x905410b5); + PciEepromWriteLongVPD (0x04, 0x09800001); /* other input controller */ + PciEepromWriteLongVPD (0x08, 0x28140100); - val = PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ - val = PciEepromWriteLongVPD (0x10, 0x00000000); + PciEepromWriteLongVPD (0x0c, 0x00000000); /* MBOX0... */ + PciEepromWriteLongVPD (0x10, 0x00000000); /* las0: fpga access (0x0000.0000 ... 0x0003.ffff) */ - val = PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ - val = PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ + PciEepromWriteLongVPD (0x14, 0xfffc0000); /* LAS0RR... */ + PciEepromWriteLongVPD (0x18, 0x00000001); /* LAS0BA */ - val = PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ - val = PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ + PciEepromWriteLongVPD (0x1c, 0x00200000); /* MARBR... */ + PciEepromWriteLongVPD (0x20, 0x00300500); /* LMISC/BIGEND */ - val = PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ - val = PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ + PciEepromWriteLongVPD (0x24, 0x00000000); /* EROMRR... */ + PciEepromWriteLongVPD (0x28, 0x00000000); /* EROMBA */ - val = PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ + PciEepromWriteLongVPD (0x2c, 0x43030000); /* LBRD0... */ - val = PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ - val = PciEepromWriteLongVPD (0x34, 0x00000000); - val = PciEepromWriteLongVPD (0x38, 0x00000000); + PciEepromWriteLongVPD (0x30, 0x00000000); /* DMRR... */ + PciEepromWriteLongVPD (0x34, 0x00000000); + PciEepromWriteLongVPD (0x38, 0x00000000); - val = PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ - val = PciEepromWriteLongVPD (0x40, 0x00000000); + PciEepromWriteLongVPD (0x3c, 0x00000000); /* DMPBAM... */ + PciEepromWriteLongVPD (0x40, 0x00000000); /* Extra Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ + PciEepromWriteLongVPD (0x44, 0x010212fe); /* PCISID... */ /* las1: 505-sram access (0x0004.0000 ... 0x001f.ffff) */ /* Offset to LAS1: Group 1: 0x00040000 */ /* Group 2: 0x00080000 */ /* Group 3: 0x000c0000 */ - val = PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ - val = PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ - val = PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ + PciEepromWriteLongVPD (0x48, 0xffe00000); /* LAS1RR */ + PciEepromWriteLongVPD (0x4c, 0x00040001); /* LAS1BA */ + PciEepromWriteLongVPD (0x50, 0x00000208); /* LBRD1 */ /* so wars bisher */ - val = PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ + PciEepromWriteLongVPD (0x54, 0x00004c06); /* HotSwap... */ printf ("Finished writing defaults into PLX PCI9054 EEPROM!\n"); } @@ -186,8 +184,6 @@ static void updatePci9054 (void) static void clearPci9054 (void) { - int val; - /* * Set EEPROM write-protect register to 0 */ @@ -195,8 +191,8 @@ static void clearPci9054 (void) in_be32 ((void *)(pci9054_iobase + 0x0c)) & 0xffff00ff); /* Long Serial EEPROM Load Registers... */ - val = PciEepromWriteLongVPD (0x00, 0xffffffff); - val = PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ + PciEepromWriteLongVPD (0x00, 0xffffffff); + PciEepromWriteLongVPD (0x04, 0xffffffff); /* other input controller */ printf ("Finished clearing PLX PCI9054 EEPROM!\n"); } diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c index d6a7737..e2f2aac 100644 --- a/board/esd/dasa_sim/flash.c +++ b/board/esd/dasa_sim/flash.c @@ -44,7 +44,6 @@ unsigned long flash_init (void) { unsigned long size_b0; int i; - unsigned long base_b0; /* Init: no FLASHes known */ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { @@ -63,8 +62,6 @@ unsigned long flash_init (void) /* Setup offsets */ flash_get_offsets (-size_b0, &flash_info[0]); - base_b0 = -size_b0; - /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, -monitor_flash_len, diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile index 74cfce9..2c95ced 100644 --- a/board/esd/meesc/Makefile +++ b/board/esd/meesc/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index ad43531..4882ffc 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * (C) Copyright 2009-2011 diff --git a/board/esd/otc570/Makefile b/board/esd/otc570/Makefile index 1819292..3e94d19 100644 --- a/board/esd/otc570/Makefile +++ b/board/esd/otc570/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c index 15faa16..5dded41 100644 --- a/board/esd/otc570/otc570.c +++ b/board/esd/otc570/otc570.c @@ -4,7 +4,7 @@ * esd electronic system design gmbh <www.esd.eu> * * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 13f9019..f570ef3 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -42,7 +42,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned int *ptr = 0; int count = 0; int count2 = 0; - int status; int i; char addr[16]; char str[] = "\\|/-"; @@ -99,7 +98,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) local_args[0] = argv[0]; local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); + do_bootm (cmdtp, 0, 1, local_args); } return 0; diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 0202876..f1ffb7b 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -342,7 +342,8 @@ U_BOOT_CMD( #if defined(CONFIG_PRAM) #include <environment.h> -extern env_t *env_ptr; +#include <search.h> +#include <errno.h> int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -351,6 +352,10 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) u32 param; ulong *lptr; + env_t *envp; + char *res; + int len; + v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -384,7 +389,15 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* env is first (4k aligned) */ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); - memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + envp = (env_t *)nextbase; + res = (char *)envp->data; + len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + envp->crc = crc32(0, envp->data, ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ *(--lptr) = base - nextbase; /* offset | type=0 */ diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 5236f44..3713e37 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -574,8 +574,6 @@ void pci_target_init(struct pci_controller *hose) /* No error reporting */ pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); - pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); - if (!is_monarch()) { /* Program the board's subsystem id/classcode */ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, @@ -617,21 +615,6 @@ void pci_master_init(struct pci_controller *hose) static void wait_for_pci_ready(void) { - int i; - char *s = getenv("pcidelay"); - /* - * We have our own handling of the pcidelay variable. - * Using CONFIG_PCI_BOOTDELAY enables pausing for host - * and adapter devices. For adapter devices we do not - * want this. - */ - if (s) { - int ms = simple_strtoul(s, NULL, 10); - printf("PCI: Waiting for %d ms\n", ms); - for (i=0; i<ms; i++) - udelay(1000); - } - if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) { printf("PCI: Waiting for EREADY (CTRL-C to skip) ... "); while (1) { diff --git a/board/eukrea/cpu9260/Makefile b/board/eukrea/cpu9260/Makefile index 897fe3e..2ec6338 100644 --- a/board/eukrea/cpu9260/Makefile +++ b/board/eukrea/cpu9260/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com +# Stelian Pop <stelian@popies.net # Lead Tech Design <www.leadtechdesign.com> # Ilko Iliev <www.ronetix.at> # diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 402f19f..ecb0796 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Ilko Iliev <www.ronetix.at> * diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index 1492ffc..c02a9cd 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -127,31 +127,32 @@ static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr) #endif if(icr&0x10000000) { +#ifdef DEBUG unsigned int psr; + psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base); -#ifdef DEBUG printf("PHY state change:\n" " GT:%s:%s:%s:%s\n", - psr&1?"100":" 10", - psr&8?" Link":"nLink", - psr&2?"FD":"HD", - psr&4?" FC":"nFC"); + psr & 1 ? "100" : " 10", + psr & 8 ? " Link" : "nLink", + psr & 2 ? "FD" : "HD", + psr & 4 ? " FC" : "nFC"); #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */ { - unsigned short mii_11; - mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11); - - printf(" mii:%s:%s:%s:%s %s:%s %s\n", - mii_11&(1<<14)?"100":" 10", - mii_11&(1<<10)?" Link":"nLink", - mii_11&(1<<9)?"FD":"HD", - mii_11&(1<<4)?" FC":"nFC", - - mii_11&(1<<7)?"ANc":"ANnc", - mii_11&(1<<8)?"AN":"Manual", - "" - ); + unsigned short mii_11; + mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11); + + printf(" mii:%s:%s:%s:%s %s:%s %s\n", + mii_11 & (1 << 14) ? "100" : " 10", + mii_11 & (1 << 10) ? " Link" : "nLink", + mii_11 & (1 << 9) ? "FD" : "HD", + mii_11 & (1 << 4) ? " FC" : "nFC", + + mii_11 & (1 << 7) ? "ANc" : "ANnc", + mii_11 & (1 << 8) ? "AN" : "Manual", + "" + ); } #endif /* CONFIG_INTEL_LXT97X */ #endif /* DEBUG */ diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index 80756a5..393320a 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -32,6 +32,7 @@ #include <galileo/gt64260R.h> #include <net.h> #include <netdev.h> +#include <linux/compiler.h> #include <asm/io.h> #include "eth.h" @@ -360,7 +361,7 @@ debug_led(int led, int mode) { #if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4) volatile int *addr = NULL; - int dummy; + __maybe_unused int dummy; if (mode == 1) { switch (led) { diff --git a/board/evb64260/i2c.c b/board/evb64260/i2c.c index 88d0dac..8119fce 100644 --- a/board/evb64260/i2c.c +++ b/board/evb64260/i2c.c @@ -20,29 +20,25 @@ static void i2c_init(int speed, int slaveaddr) { unsigned int n, m, freq, margin, power; - unsigned int actualFreq, actualN=0, actualM=0; + unsigned int actualn = 0, actualm = 0; unsigned int control, status; - unsigned int minMargin = 0xffffffff; + unsigned int minmargin = 0xffffffff; unsigned int tclk = 125000000; DP(puts("i2c_init\n")); - for(n = 0 ; n < 8 ; n++) - { - for(m = 0 ; m < 16 ; m++) - { - power = 2<<n; /* power = 2^(n+1) */ - freq = tclk/(10*(m+1)*power); + for (n = 0 ; n < 8 ; n++) { + for (m = 0 ; m < 16 ; m++) { + power = 2 << n; /* power = 2^(n+1) */ + freq = tclk / (10 * (m + 1) * power); if (speed > freq) margin = speed - freq; else margin = freq - speed; - if(margin < minMargin) - { - minMargin = margin; - actualFreq = freq; - actualN = n; - actualM = m; + if (margin < minmargin) { + minmargin = margin; + actualn = n; + actualm = m; } } } @@ -59,7 +55,7 @@ i2c_init(int speed, int slaveaddr) DP(puts("set baudrate\n")); - GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualM << 3) | actualN); + GT_REG_WRITE(I2C_STATUS_BAUDE_RATE, (actualm << 3) | actualn); GT_REG_WRITE(I2C_CONTROL, (0x1 << 2) | (0x1 << 6)); udelay(I2C_DELAY * 10); @@ -91,13 +87,13 @@ i2c_start(void) udelay(I2C_DELAY); if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; } - return (0); + return 0; } static uchar @@ -110,9 +106,8 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) /* Output slave address */ - if (ten_bit) { + if (ten_bit) bits = 10; - } data = (dev_addr << 1); /* set the read bit */ @@ -129,7 +124,7 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) udelay(I2C_DELAY); if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return(status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; @@ -137,14 +132,14 @@ i2c_select_device(uchar dev_addr, uchar read, int ten_bit) if (bits == 10) { printf("10 bit I2C addressing not yet implemented\n"); - return (0xff); + return 0xff; } - return (0); + return 0; } static uchar -i2c_get_data(uchar* return_data, int len) { +i2c_get_data(uchar *return_data, int len) { unsigned int data, status = 0; int count = 0; @@ -163,7 +158,7 @@ i2c_get_data(uchar* return_data, int len) { count++; while ((status & 0xff) != 0x50) { udelay(I2C_DELAY); - if(count > 2) { + if (count > 2) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ return 0; } @@ -178,16 +173,16 @@ i2c_get_data(uchar* return_data, int len) { RESET_REG_BITS(I2C_CONTROL, BIT2|BIT3); while ((status & 0xff) != 0x58) { udelay(I2C_DELAY); - if(count > 200) { + if (count > 200) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; } GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /* stop */ - return (0); + return 0; } static uchar @@ -213,9 +208,9 @@ i2c_write_data(unsigned int data, int len) count++; while ((status & 0xff) != 0x28) { udelay(I2C_DELAY); - if(count > 20) { + if (count > 20) { GT_REG_WRITE(I2C_CONTROL, (0x1 << 4)); /*stop*/ - return (status); + return status; } GT_REG_READ(I2C_STATUS_BAUDE_RATE, &status); count++; @@ -227,7 +222,7 @@ i2c_write_data(unsigned int data, int len) udelay(I2C_DELAY * 10); - return (0); + return 0; } static uchar @@ -254,19 +249,19 @@ i2c_set_dev_offset(uchar dev_addr, unsigned int offset, int ten_bit) return status; } - return (0); + return 0; } uchar -i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, +i2c_read(uchar dev_addr, unsigned int offset, int len, uchar *data, int ten_bit) { uchar status = 0; - unsigned int i2cFreq = 400000; + unsigned int i2cfreq = 400000; DP(puts("i2c_read\n")); - i2c_init(i2cFreq,0); + i2c_init(i2cfreq, 0); status = i2c_start(); @@ -285,7 +280,7 @@ i2c_read(uchar dev_addr, unsigned int offset, int len, uchar* data, return status; } - i2c_init(i2cFreq,0); + i2c_init(i2cfreq, 0); status = i2c_start(); if (status) { diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index e2f0769..6f725f6 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -29,6 +29,7 @@ #include <galileo/pci.h> #include <galileo/gt64260R.h> #include <net.h> +#include <linux/compiler.h> #include "eth.h" #include "mpsc.h" @@ -330,7 +331,8 @@ static int check_dimm (uchar slot, sdram_info_t * info) static int setup_sdram_common (sdram_info_t info[2]) { ulong tmp; - int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2; + int tpar = 2, tras_clocks = 5, registered = 1; + __maybe_unused int ecc = 2; if (!info[0].banks && !info[1].banks) return 0; @@ -407,8 +409,9 @@ static int setup_sdram_common (sdram_info_t info[2]) /* sets up the GT properly with information passed in */ static int setup_sdram (sdram_info_t * info) { - ulong tmp, check; + ulong tmp; ulong *addr = 0; + __maybe_unused ulong check; int i; /* sanity checking */ diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c index 8e38102..621c64c 100644 --- a/board/evb64260/zuma_pbb_mbox.c +++ b/board/evb64260/zuma_pbb_mbox.c @@ -12,57 +12,62 @@ struct _zuma_mbox_dev zuma_mbox_dev; static int zuma_mbox_write(struct _zuma_mbox_dev *dev, unsigned int data) { - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while((status & OUT_PENDING) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - /* printf("mbox real write %08x\n",data); */ - dev->sip->mbox_out = cpu_to_le32(data); - return 4; - } - - printf("mbox tx timeout\n"); - return 0; + unsigned int status, count = 0, i; + + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + + while ((status & OUT_PENDING) && count < 1000) { + count++; + for (i = 0; i < 1000; i++) + ; + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + } + if (count < 1000) { + /* if SET it means msg pending */ + /* printf("mbox real write %08x\n",data); */ + dev->sip->mbox_out = cpu_to_le32(data); + return 4; + } + + printf("mbox tx timeout\n"); + return 0; } static int zuma_mbox_read(struct _zuma_mbox_dev *dev, unsigned int *data) { - unsigned int status, count = 0, i; - - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - - while(!(status & IN_VALID) && count < 1000) { - count++; - for(i=0;i<1000;i++); - status = (volatile int)le32_to_cpu(dev->sip->mbox_status); - } - if(count < 1000) { - /* if SET it means msg pending */ - *data=le32_to_cpu(dev->sip->mbox_in); - /*printf("mbox real read %08x\n", *data); */ - return 4; - } - printf("mbox rx timeout\n"); - return 0; + unsigned int status, count = 0, i; + + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + + while (!(status & IN_VALID) && count < 1000) { + count++; + for (i = 0; i < 1000; i++) + ; + status = (volatile int) le32_to_cpu(dev->sip->mbox_status); + } + if (count < 1000) { + /* if SET it means msg pending */ + *data = le32_to_cpu(dev->sip->mbox_in); + /*printf("mbox real read %08x\n", *data); */ + return 4; + } + printf("mbox rx timeout\n"); + return 0; } static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) { - int ret; - ret=zuma_mbox_write(&zuma_mbox_dev,out); - /*printf("write 0x%08x (%d bytes)\n", out, ret); */ - if(ret!=4) return -1; - ret=zuma_mbox_read(&zuma_mbox_dev,in); - /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ - if(ret!=4) return -1; - return 0; + int ret; + + ret = zuma_mbox_write(&zuma_mbox_dev, out); + /*printf("write 0x%08x (%d bytes)\n", out, ret); */ + if (ret != 4) + return -1; + ret = zuma_mbox_read(&zuma_mbox_dev, in); + /*printf("read 0x%08x (%d bytes)\n", *in, ret); */ + if (ret != 4) + return -1; + return 0; } @@ -70,81 +75,93 @@ static int zuma_mbox_do_one_mailbox(unsigned int out, unsigned int *in) static int zuma_mbox_do_all_mailbox(void) { - unsigned int data_in; - unsigned short sdata_in; + unsigned int data_in; + unsigned short sdata_in; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_START, &data_in)); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); - memcpy(zuma_acc_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_acc_mac,&sdata_in,2); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACL, &data_in)); + memcpy(zuma_acc_mac + 2, &data_in, 4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_MACH, &data_in)); + sdata_in = data_in & 0xffff; + memcpy(zuma_acc_mac, &sdata_in, 2); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); - zuma_ip=data_in; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_IP, &data_in)); + zuma_ip = data_in; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); - zuma_slot_bac=data_in>>3; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_SLOT, &data_in)); + zuma_slot_bac = data_in >> 3; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); - zuma_console_baud = data_in & 0xffff; - zuma_debug_baud = data_in >> 16; + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_BAUD, &data_in)); + zuma_console_baud = data_in & 0xffff; + zuma_debug_baud = data_in >> 16; - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); - memcpy(zuma_prv_mac+2,&data_in,4); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); - sdata_in=data_in&0xffff; - memcpy(zuma_prv_mac,&sdata_in,2); + RET_IF_FAILED(zuma_mbox_do_one_mailbox + (ZUMA_MBOXMSG_ENG_PRV_MACL, &data_in)); + memcpy(zuma_prv_mac + 2, &data_in, 4); + RET_IF_FAILED(zuma_mbox_do_one_mailbox + (ZUMA_MBOXMSG_ENG_PRV_MACH, &data_in)); + sdata_in = data_in & 0xffff; + memcpy(zuma_prv_mac, &sdata_in, 2); - RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); + RET_IF_FAILED(zuma_mbox_do_one_mailbox(ZUMA_MBOXMSG_DONE, &data_in)); - return 0; + return 0; } -static void -zuma_mbox_dump(void) +static void zuma_mbox_dump(void) { - printf("ACC MAC=%04x%08x\n",*(unsigned short *)(&zuma_acc_mac),*(unsigned int *)((char *)&zuma_acc_mac+2)); - printf("PRV MAC=%04x%08x\n",*(unsigned short *)(&zuma_prv_mac),*(unsigned int *)((char *)&zuma_prv_mac+2)); - printf("slot:bac=%d:%d\n",(zuma_slot_bac>>2)&0xf, zuma_slot_bac & 0x3); - printf("BAUD1=%d BAUD2=%d\n",zuma_console_baud,zuma_debug_baud); + unsigned short s; + unsigned int i; + + memcpy(&s, &zuma_acc_mac, sizeof(s)); + memcpy(&i, &zuma_acc_mac[2], sizeof(i)); + printf("ACC MAC=%04x%08x\n", s, i); + + memcpy(&s, &zuma_prv_mac, sizeof(s)); + memcpy(&s, &zuma_prv_mac[2], sizeof(i)); + printf("PRV MAC=%04x%08x\n", s, i); + + printf("slot:bac=%d:%d\n", + (zuma_slot_bac >> 2) & 0xf, + zuma_slot_bac & 0x3); + + printf("BAUD1=%d BAUD2=%d\n", + zuma_console_baud, + zuma_debug_baud); } -static void -zuma_mbox_setenv(void) +static void zuma_mbox_setenv(void) { - char *data, buf[32]; - unsigned char save = 0; - - data = getenv("baudrate"); - - if(!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { - sprintf(buf, "%6d", zuma_console_baud); - setenv("baudrate", buf); - save=1; - printf("baudrate doesn't match from mbox\n"); - } - - ip_to_string(zuma_ip, buf); - setenv("ipaddr", buf); - - sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x", - zuma_prv_mac[0], - zuma_prv_mac[1], - zuma_prv_mac[2], - zuma_prv_mac[3], - zuma_prv_mac[4], - zuma_prv_mac[5]); - setenv("ethaddr", buf); - - sprintf(buf,"%02x",zuma_slot_bac); - setenv("bacslot", buf); - - if(save) - saveenv(); + char *data, buf[32]; + unsigned char save = 0; + + data = getenv("baudrate"); + + if (!data || (zuma_console_baud != simple_strtoul(data, NULL, 10))) { + sprintf(buf, "%6d", zuma_console_baud); + setenv("baudrate", buf); + save = 1; + printf("baudrate doesn't match from mbox\n"); + } + + ip_to_string(zuma_ip, buf); + setenv("ipaddr", buf); + + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x", + zuma_prv_mac[0], + zuma_prv_mac[1], + zuma_prv_mac[2], + zuma_prv_mac[3], zuma_prv_mac[4], zuma_prv_mac[5]); + setenv("ethaddr", buf); + + sprintf(buf, "%02x", zuma_slot_bac); + setenv("bacslot", buf); + + if (save) + saveenv(); } /** @@ -153,37 +170,39 @@ zuma_mbox_setenv(void) int zuma_mbox_init(void) { - unsigned int iobase; - memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); + unsigned int iobase; + + memset(&zuma_mbox_dev, 0, sizeof(struct _zuma_mbox_dev)); - zuma_mbox_dev.dev = pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); + zuma_mbox_dev.dev = + pci_find_device(VENDOR_ID_ZUMA, DEVICE_ID_ZUMA_PBB, 0); - if(zuma_mbox_dev.dev == -1) { - printf("no zuma pbb\n"); - return -1; - } + if (zuma_mbox_dev.dev == -1) { + printf("no zuma pbb\n"); + return -1; + } - pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); + pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - iobase &= PCI_BASE_ADDRESS_MEM_MASK; + iobase &= PCI_BASE_ADDRESS_MEM_MASK; - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase; + zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) iobase; - zuma_mbox_dev.sip->int_mask.word=0; + zuma_mbox_dev.sip->int_mask.word = 0; - printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, - zuma_mbox_dev.sip->version.pci_bits.rev_major, - zuma_mbox_dev.sip->version.pci_bits.rev_minor, - zuma_mbox_dev.sip->timestamp); + printf("pbb @ %p v%d.%d, timestamp %08x\n", zuma_mbox_dev.sip, + zuma_mbox_dev.sip->version.pci_bits.rev_major, + zuma_mbox_dev.sip->version.pci_bits.rev_minor, + zuma_mbox_dev.sip->timestamp); - if (zuma_mbox_do_all_mailbox() == -1) { - printf("mailbox failed.. no ACC?\n"); - return -1; - } + if (zuma_mbox_do_all_mailbox() == -1) { + printf("mailbox failed.. no ACC?\n"); + return -1; + } - zuma_mbox_dump(); + zuma_mbox_dump(); - zuma_mbox_setenv(); + zuma_mbox_setenv(); - return 0; + return 0; } diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c index 2578be4..dfd186b 100644 --- a/board/faraday/a320evb/a320evb.c +++ b/board/faraday/a320evb/a320evb.c @@ -31,7 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_FARADAY; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; ftsmc020_init(); /* initialize Flash */ diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 353d3c6..9077aaf 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_FSL_VIA) += cds_via.o COBJS-$(CONFIG_FMAN_ENET) += fman.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o +COBJS-$(CONFIG_FSL_QIXIS) += qixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o @@ -50,12 +51,14 @@ COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o +COBJS-$(CONFIG_P3060QDS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o # deal with common files for P-series corenet based devices SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P3060QDS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 6f221af..8a09f99 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -28,13 +28,12 @@ #if defined(CONFIG_OF_BOARD_SETUP) static void cds_pci_fixup(void *blob) { - int node, tmp[2]; + int node; const char *path; int len, slot, i; u32 *map = NULL; node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { path = fdt_getprop(blob, node, "pci0", NULL); if (path) { diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c index 89d8810..95a3cd7 100644 --- a/board/freescale/common/ics307_clk.c +++ b/board/freescale/common/ics307_clk.c @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,18 +25,92 @@ #include "ics307_clk.h" -#ifdef CONFIG_FSL_NGPIXIS +#if defined(CONFIG_FSL_NGPIXIS) #include "ngpixis.h" +#define fpga_reg pixis +#elif defined(CONFIG_FSL_QIXIS) +#include "qixis.h" +#define fpga_reg ((struct qixis *)QIXIS_BASE) #else #include "pixis.h" +#define fpga_reg pixis #endif +/* define for SYS CLK or CLK1Frequency */ +#define TTL 1 +#define CLK2 0 +#define CRYSTAL 0 +#define MAX_VDW (511 + 8) +#define MAX_RDW (127 + 2) +#define MIN_VDW (4 + 8) +#define MIN_RDW (1 + 2) +#define NUM_OD_SETTING 8 +/* + * These defines cover the industrial temperature range part, + * for commercial, change below to 400000 and 55000, respectively + */ +#define MAX_VCO 360000 +#define MIN_VCO 60000 + /* decode S[0-2] to Output Divider (OD) */ static u8 ics307_s_to_od[] = { 10, 2, 8, 4, 5, 7, 3, 6 }; /* + * Find one solution to generate required frequency for SYSCLK + * out_freq: KHz, required frequency to the SYSCLK + * the result will be retuned with component RDW, VDW, OD, TTL, + * CLK2 and crystal + */ +unsigned long ics307_sysclk_calculator(unsigned long out_freq) +{ + const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ; + unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od; + unsigned long tmp_out, diff, result = 0; + int found = 0; + + for (odp = 0; odp < NUM_OD_SETTING; odp++) { + od = ics307_s_to_od[odp]; + if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO) + continue; + for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) { + /* Calculate the VDW */ + vdw = out_freq * 1000 * od * rdw / (input_freq * 2); + if (vdw > MAX_VDW) + vdw = MAX_VDW; + if (vdw < MIN_VDW) + continue; + /* Calculate the temp out frequency */ + tmp_out = input_freq * 2 * vdw / (rdw * od * 1000); + diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out); + /* + * calculate the percent, the precision is 1/1000 + * If greater than 1/1000, continue + * otherwise, we think the solution is we required + */ + if (diff * 1000 / out_freq > 1) + continue; + else { + s_vdw = vdw; + s_rdw = rdw; + s_odp = odp; + found = 1; + break; + } + } + } + + if (found) + result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 | + CLK2 << 19 | TTL << 21 | CRYSTAL << 22; + + debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8, + ics307_s_to_od[s_odp]); + return result; +} + +/* * Calculate frequency being generated by ICS307-02 clock chip based upon * the control bytes being programmed into it. */ @@ -74,15 +148,15 @@ static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) unsigned long get_board_sys_clk(void) { return ics307_clk_freq( - in_8(&pixis->sclk[0]), - in_8(&pixis->sclk[1]), - in_8(&pixis->sclk[2])); + in_8(&fpga_reg->sclk[0]), + in_8(&fpga_reg->sclk[1]), + in_8(&fpga_reg->sclk[2])); } unsigned long get_board_ddr_clk(void) { return ics307_clk_freq( - in_8(&pixis->dclk[0]), - in_8(&pixis->dclk[1]), - in_8(&pixis->dclk[2])); + in_8(&fpga_reg->dclk[0]), + in_8(&fpga_reg->dclk[1]), + in_8(&fpga_reg->dclk[2])); } diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h index db3dbc4..3757912 100644 --- a/board/freescale/common/ics307_clk.h +++ b/board/freescale/common/ics307_clk.h @@ -1,5 +1,5 @@ /* - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,8 +23,10 @@ #define __ICS_CLK_H_ 1 #ifndef __ASSEMBLY__ + extern unsigned long get_board_sys_clk(void); extern unsigned long get_board_ddr_clk(void); +extern unsigned long ics307_sysclk_calculator(unsigned long out_freq); #endif #endif /* __ICS_CLK_H_ */ diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c index 765f035..276ae3c 100644 --- a/board/freescale/common/ngpixis.c +++ b/board/freescale/common/ngpixis.c @@ -156,9 +156,29 @@ static void pixis_dump_regs(void) } #endif +void pixis_sysclk_set(unsigned long sysclk) +{ + unsigned long freq_word; + u8 sclk0, sclk1, sclk2; + + freq_word = ics307_sysclk_calculator(sysclk); + sclk2 = freq_word & 0xff; + sclk1 = (freq_word >> 8) & 0xff; + sclk0 = (freq_word >> 16) & 0xff; + + /* set SYSCLK enable bit */ + PIXIS_WRITE(vcfgen0, 0x01); + + /* SYSCLK to required frequency */ + PIXIS_WRITE(sclk[0], sclk0); + PIXIS_WRITE(sclk[1], sclk1); + PIXIS_WRITE(sclk[2], sclk2); +} + int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { unsigned int i; + unsigned long sysclk; char *p_altbank = NULL; #ifdef DEBUG char *p_dump = NULL; @@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) continue; } #endif + if (strcmp(argv[i], "sysclk") == 0) { + sysclk = simple_strtoul(argv[i + 1], NULL, 0); + i += 1; + pixis_sysclk_set(sysclk); + continue; + } unknown_param = argv[i]; } @@ -219,4 +245,5 @@ U_BOOT_CMD( #ifdef DEBUG "pixis_reset dump - display the PIXIS registers\n" #endif + "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n" ); diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index a35b5cf..8d07061 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr) { int i, j; int mulconst; - int intarr_len, no_dec = 0; + int no_dec = 0; unsigned long intval = 0, decval = 0; char intarr[3], decarr[3]; @@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr) i++; } - /* Assign length of integer part to intarr_len. */ - intarr_len = i; intarr[i] = '\0'; if (no_dec) { diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c new file mode 100644 index 0000000..6cd7e51 --- /dev/null +++ b/board/freescale/common/qixis.c @@ -0,0 +1,151 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include "qixis.h" + +u8 qixis_read(unsigned int reg) +{ + void *p = (void *)QIXIS_BASE; + + return in_8(p + reg); +} + +void qixis_write(unsigned int reg, u8 value) +{ + void *p = (void *)QIXIS_BASE; + + out_8(p + reg, value); +} + +void qixis_reset(void) +{ + QIXIS_WRITE(rst_ctl, 0x83); +} + +void qixis_bank_reset(void) +{ + QIXIS_WRITE(rcfg_ctl, 0x20); + QIXIS_WRITE(rcfg_ctl, 0x21); +} + +/* Set the boot bank to the power-on default bank0 */ +void clear_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = reg & ~QIXIS_LBMAP_MASK; + QIXIS_WRITE(brdcfg[0], reg); +} + +/* Set the boot bank to the alternate bank */ +void set_altbank(void) +{ + u8 reg; + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_ALTBANK; + QIXIS_WRITE(brdcfg[0], reg); +} + +#ifdef DEBUG +static void qixis_dump_regs(void) +{ + int i; + + printf("id = %02x\n", QIXIS_READ(id)); + printf("arch = %02x\n", QIXIS_READ(arch)); + printf("scver = %02x\n", QIXIS_READ(scver)); + printf("model = %02x\n", QIXIS_READ(model)); + printf("rst_ctl = %02x\n", QIXIS_READ(rst_ctl)); + printf("aux = %02x\n", QIXIS_READ(aux)); + for (i = 0; i < 16; i++) + printf("brdcfg%02d = %02x\n", i, QIXIS_READ(brdcfg[i])); + for (i = 0; i < 16; i++) + printf("dutcfg%02d = %02x\n", i, QIXIS_READ(dutcfg[i])); + printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), + QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); + printf("dclk = %02x%02x%02x\n", QIXIS_READ(dclk[0]), + QIXIS_READ(dclk[1]), QIXIS_READ(dclk[2])); + printf("aux = %02x\n", QIXIS_READ(aux)); + printf("watch = %02x\n", QIXIS_READ(watch)); + printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys)); + printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl)); + printf("present = %02x\n", QIXIS_READ(present)); + printf("clk_spd = %02x\n", QIXIS_READ(clk_spd)); + printf("stat_dut = %02x\n", QIXIS_READ(stat_dut)); + printf("stat_sys = %02x\n", QIXIS_READ(stat_sys)); + printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm)); + printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2)); +} +#endif + +int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + + if (argc <= 1) { + clear_altbank(); + qixis_reset(); + } else if (strcmp(argv[1], "altbank") == 0) { + set_altbank(); + qixis_bank_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[9] = {"2s", "4s", "8s", "16s", "32s", + "1min", "2min", "4min", "8min"}; + u8 rcfg = QIXIS_READ(rcfg_ctl); + + if (argv[2] == NULL) { + printf("qixis watchdog <watchdog_period>\n"); + return 0; + } + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) { + /* disable watchdog */ + QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08); + QIXIS_WRITE(watch, ((i<<2) - 1)); + QIXIS_WRITE(rcfg_ctl, rcfg); + return 0; + } + } + } + +#ifdef DEBUG + else if (strcmp(argv[1], "dump") == 0) { + qixis_dump_regs(); + return 0; + } +#endif + + else { + printf("Invalid option: %s\n", argv[1]); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + qixis_reset, CONFIG_SYS_MAXARGS, 1, qixis_reset_cmd, + "Reset the board using the FPGA sequencer", + "- hard reset to default bank\n" + "qixis_reset altbank - reset to alternate bank\n" + "qixis watchdog <watchdog_period> - set the watchdog period\n" + " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n" +#ifdef DEBUG + "qixis_reset dump - display the QIXIS registers\n" +#endif + ); diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h new file mode 100644 index 0000000..7a0268a --- /dev/null +++ b/board/freescale/common/qixis.h @@ -0,0 +1,101 @@ +/* + * Copyright 2011 Freescale Semiconductor + * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the QIXIS of some Freescale reference boards. + */ + +#ifndef __QIXIS_H_ +#define __QIXIS_H_ + +struct qixis { + u8 id; /* ID value uniquely identifying each QDS board type */ + u8 arch; /* Board version information */ + u8 scver; /* QIXIS Version Register */ + u8 model; /* Information of software programming model version */ + u8 tagdata; + u8 ctl_sys; + u8 aux; /* Auxiliary Register,0x06 */ + u8 clk_spd; + u8 stat_dut; + u8 stat_sys; + u8 stat_alrm; + u8 present; + u8 ctl_sys2; + u8 rcw_ctl; + u8 ctl_led; + u8 i2cblk; + u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ + u8 rcfg_st; + u8 dcm_ad; + u8 dcm_da; + u8 dcmd; + u8 dmsg; + u8 gdc; + u8 gdd; /* DCM Debug Data Register,0x17 */ + u8 dmack; + u8 res1[6]; + u8 watch; /* Watchdog Register,0x1F */ + u8 pwr_ctl[2]; /* Power Control Register,0x20 */ + u8 res2[2]; + u8 pwr_stat[4]; /* Power Status Register,0x24 */ + u8 res3[8]; + u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ + u8 res4[2]; + u8 sclk[3]; /* Clock Configuration Registers,0x34 */ + u8 res5; + u8 dclk[3]; + u8 res6; + u8 clk_dspd[3]; + u8 res7; + u8 rst_ctl; /* Reset Control Register,0x40 */ + u8 rst_stat; /* Reset Status Register */ + u8 rst_rsn; /* Reset Reason Register */ + u8 rst_frc[2]; /* Reset Force Registers,0x43 */ + u8 res8[11]; + u8 brdcfg[16]; /* Board Configuration Register,0x50 */ + u8 dutcfg[16]; + u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ + u8 rcw_data; + u8 res9[5]; + u8 post_ctl; + u8 post_stat; + u8 post_dat[2]; + u8 pi_d[4]; + u8 gpio_io[4]; + u8 gpio_dir[4]; + u8 res10[20]; + u8 rjtag_ctl; + u8 rjtag_dat; + u8 res11[2]; + u8 trig_src[4]; + u8 trig_dst[4]; + u8 trig_stat; + u8 res12[3]; + u8 trig_ctr[4]; + u8 res13[48]; + u8 aux2[4]; /* Auxiliary Registers,0xE0 */ + u8 res14[10]; + u8 aux_ad; + u8 aux_da; + u8 res15[16]; +}; + +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 7 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_ALTBANK 0x04 + +u8 qixis_read(unsigned int reg); +void qixis_write(unsigned int reg, u8 value); + +#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) + +#endif diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a7a5e13..962f380 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 7ff00d1..1f00c14 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; @@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis) SLOT5, /* 17 - Bank 3:D */ }; - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) mdio_mux[i] = EMI_NONE; diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index be76774..bdd1293 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -172,10 +172,11 @@ int board_eth_init(bd_t *bd) if (board_handle_erratum2()) { int i; - for (i = 0; i < ARRAY_SIZE(uec_info); i++) + for (i = 0; i < ARRAY_SIZE(uec_info); i++) { uec_info[i].enet_interface_type = PHY_INTERFACE_MODE_RGMII_RXID; uec_info[i].speed = SPEED_1000; + } } return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info)); } diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a8d57cd..e5563f7 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,6 +33,9 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> +#include <fsl_mdio.h> +#include <netdev.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -81,12 +84,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -115,7 +116,6 @@ void lbc_sdram_init(void) uint idx; volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; - uint cpu_board_rev; uint lsdmr_common; puts("LBC SDRAM: "); @@ -137,7 +137,6 @@ void lbc_sdram_init(void) /* * MPC8548 uses "new" 15-16 style addressing. */ - cpu_board_rev = get_cpu_board_revision(); lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common |= LSDMR_BSMA1516; @@ -287,7 +286,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } -int last_stage_init(void) +void configure_rgmii(void) { unsigned short temp; @@ -295,29 +294,77 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_TSEC1_NAME, + miiphy_read(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_TSEC1_NAME, + miiphy_write(DEFAULT_MII_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } - return 0; + return; } +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif +#ifdef CONFIG_TSEC4 + /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ + if (get_board_version() >= 0x13) { + SET_STD_TSEC_INFO(tsec_info[num], 4); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; + num++; + } +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + configure_rgmii(); + + return pci_eth_init(bis); +} +#endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_pci_setup(void *blob, bd_t *bd) diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index 225c5d8..6e3945e 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -147,12 +147,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; gur->lbiuiplldcr1 = 0x00078080; if (clkdiv == 16) { @@ -302,6 +300,7 @@ pib_init(void) i2c_write(0x27, 0x3, 1, &val8, 1); asm("eieio"); + i2c_set_bus_num(orig_i2c_bus); } #ifdef CONFIG_PCI diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 89557d2..d119c65 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -303,12 +303,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 575bdb5..6d60513 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_NAND_SPL /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, @@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), +#endif /* *I*G - NAND */ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 5b3b560..2bcd5e6 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -235,12 +235,11 @@ void pci_init_board(void) volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; struct fsl_pci_info pci_info; - u32 devdisr, pordevsr; + u32 devdisr; int first_free_busno; int pci_agent; devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); first_free_busno = fsl_pcie_init_board(0); diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 37e6e4d..e5b0929 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -265,6 +265,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(0); else diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index be32aee..e5a1142 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -87,6 +87,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(1); /*GPIO1_1*/ else diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 335661f..aa4a2c9 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -212,6 +212,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index b4c7f33..3cf4195 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -140,6 +140,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) *cd = gpio_get_value(77); /*GPIO3_13*/ else diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 87fa7fa..55af4e4 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -134,6 +134,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { + mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1); *cd = gpio_get_value(77); /*GPIO3_13*/ return 0; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 03e9da1..b9e66f7 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif /* P1014 and it's derivatives don't support CAN and eTSEC3 */ if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) { diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 864b3ce..cfbae69 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) /* Delete eLBC node as it is muxed with USB2 controller */ diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 5ff6ea6..7968919 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -25,15 +25,17 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifndef CONFIG_NAND_SPL SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -#endif #ifdef CONFIG_VSC7385_ENET SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#endif + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 4671128..a60c5a2 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_board_fixup_qe_pins(blob); #endif #endif + +#if defined(CONFIG_HAS_FSL_DR_USB) fdt_fixup_dr_usb(blob, bd); +#endif } #endif diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile new file mode 100644 index 0000000..ba87904 --- /dev/null +++ b/board/freescale/p2020come/Makefile @@ -0,0 +1,46 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c new file mode 100644 index 0000000..85f84c6 --- /dev/null +++ b/board/freescale/p2020come/ddr.c @@ -0,0 +1,45 @@ +/* + * Copyright 2009, 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + + if (!pdimm->n_ranks) + return; + + /* + * Set DDR_SDRAM_CLK_CNTL = 0x02800000 + * + * Clock is launched 5/8 applied cycle after address/command + */ + popts->clk_adjust = 5; +} diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c new file mode 100644 index 0000000..20ba36f --- /dev/null +++ b/board/freescale/p2020come/law.c @@ -0,0 +1,39 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * Create a dummy LAW entry for the DDR SDRAM which will be replaced when + * the DDR SPD setup code runs. + * + * This table would be empty, except that it is used before the BSS section is + * initialized, and therefore must have at least one entry to push it into + * the DATA section. + */ +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_SDRAM_BASE, LAW_SIZE_4K, LAW_TRGT_IF_DDR), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c new file mode 100644 index 0000000..8cf7bee --- /dev/null +++ b/board/freescale/p2020come/p2020come.c @@ -0,0 +1,287 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <hwconfig.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/mpc85xx_gpio.h> +#include <asm/fsl_serdes.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <vsc7385.h> +#include <netdev.h> +#include <mmc.h> +#include <malloc.h> +#include <i2c.h> + +#if defined(CONFIG_PCI) +#include <asm/fsl_pci.h> +#include <pci.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PCI) +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void ft_pci_board_setup(void *blob) +{ + FT_FSL_PCI_SETUP; +} +#endif + +#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \ + SGMII_PHY_RST_SET | PCIE_RST_SET | \ + RGMII_PHY_RST_SET) + +#define SYSCLK_MASK 0x00200000 +#define BOARDREV_MASK 0x10100000 +#define BOARDREV_B 0x10100000 +#define BOARDREV_C 0x00100000 +#define BOARDREV_D 0x00000000 + +#define SYSCLK_66 66666666 +#define SYSCLK_50 50000000 +#define SYSCLK_100 100000000 + +unsigned long get_board_sys_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + return SYSCLK_66; + case 0x0A: + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +unsigned long get_board_ddr_clk(ulong dummy) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO; + + ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; + switch (ddr_ratio) { + case 0x0C: + case 0x0A: + return SYSCLK_66; + case 0x08: + return SYSCLK_100; + default: + puts("ERROR: unknown DDR ratio\n"); + return SYSCLK_100; + } +} + +#ifdef CONFIG_MMC +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->pmuxcr, + (MPC85xx_PMUXCR_SDHC_CD | + MPC85xx_PMUXCR_SDHC_WP)); + + /* All the device are enable except for SRIO12 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); + return 0; +} +#endif + +#define GPIO_DIR 0x0f3a0000 +#define GPIO_ODR 0x00000000 +#define GPIO_DAT 0x001a0000 + +int checkboard(void) +{ + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00); + + /* + * GPIO + * 0 - 3: CarryBoard Input; + * 4 - 7: CarryBoard Output; + * 8 : Mux as SDHC_CD (card detection) + * 9 : Mux as SDHC_WP + * 10 : Clear Watchdog timer + * 11 : LED Input + * 12 : Output to 1 + * 13 : Open Drain + * 14 : LED Output + * 15 : Switch Input + * + * Set GPIOs 11, 12, 14 to 1. + */ + out_be32(&pgpio->gpodr, GPIO_ODR); + mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT); + + puts("Board: Freescale COM Express P2020\n"); + return 0; +} + +#define M41ST85W_I2C_BUS 1 +#define M41ST85W_I2C_ADDR 0x68 +#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args) + +static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name) +{ + u8 data; + + if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to read %s bit\n", name); + return; + } + + if (data & mask) { + data &= ~mask; + if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) { + M41ST85W_ERROR("unable to clear %s bit\n", name); + return; + } + } +} + +#define M41ST85W_REG_SEC2 0x01 +#define M41ST85W_REG_SEC2_ST 0x80 + +#define M41ST85W_REG_ALHOUR 0x0c +#define M41ST85W_REG_ALHOUR_HT 0x40 + +/* + * The P2020COME board has a STMicro M41ST85W RTC/watchdog + * at i2c bus 1 address 0x68. + */ +static void start_rtc(void) +{ + unsigned int bus = i2c_get_bus_num(); + + if (i2c_set_bus_num(M41ST85W_I2C_BUS)) { + M41ST85W_ERROR("unable to set i2c bus\n"); + goto out; + } + + /* ensure ST (stop) and HT (halt update) bits are cleared */ + m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST"); + m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT"); + +out: + /* reset the i2c bus */ + i2c_set_bus_num(bus); +} + +int board_early_init_r(void) +{ + start_rtc(); + return 0; +} + +#define M41ST85W_REG_WATCHDOG 0x09 +#define M41ST85W_REG_WATCHDOG_WDS 0x80 +#define M41ST85W_REG_WATCHDOG_BMB0 0x04 + +void board_reset(void) +{ + u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0; + + /* set the hardware watchdog timeout to 1/16 second, then hang */ + i2c_set_bus_num(M41ST85W_I2C_BUS); + i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1); + + while (1) + /* hang */; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (is_serdes_configured(SGMII_TSEC3)) { + puts("eTSEC3 is in sgmii mode."); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + ft_pci_board_setup(blob); +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c new file mode 100644 index 0000000..d787ac3 --- /dev/null +++ b/board/freescale/p2020come/tlb.c @@ -0,0 +1,99 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_PCI) + /* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI1 0xD000,0000 - 0xDFFF,FFFF, size = 256M */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * *I*G* - PCI I/O + * + * PCI3 => 0xFFC10000 + * PCI2 => 0xFFC2,0000 + * PCI1 => 0xFFC3,0000 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256K, 1), +#endif /* #if defined(CONFIG_PCI) */ + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - DDR3 2G Part 1: 0 - 0x3fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* DDR3 2G Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c index 0a1dfa7..4b0d577 100644 --- a/board/freescale/p2041rdb/eth.c +++ b/board/freescale/p2041rdb/eth.c @@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 6461bd7..1f6a34b 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -83,10 +83,12 @@ int checkboard(void) puts("SERDES Reference Clocks: "); sw = in_8(&CPLD_SW(2)) >> 2; for (i = 0; i < 2; i++) { - static const char * const freq[] = {"0", "100", "125"}; + static const char * const freq[][3] = {{"0", "100", "125"}, + {"100", "156.25", "125"} + }; unsigned int clock = (sw >> (2 * i)) & 3; - printf("Bank%u=%sMhz ", i+1, freq[clock]); + printf("Bank%u=%sMhz ", i+1, freq[i][clock]); } puts("\n"); @@ -166,22 +168,25 @@ int misc_init_r(void) u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw; + static const int freq[][3] = { + {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125}, + {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25, + SRDS_PLLCR0_RFCK_SEL_125} + }; sw = in_8(&CPLD_SW(2)) >> 2; for (i = 0; i < NUM_SRDS_BANKS; i++) { unsigned int clock = (sw >> (2 * i)) & 3; - switch (clock) { - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - default: + if (clock == 0x3) { printf("Warning: SDREFCLK%u switch setting of '11' is " "unsupported\n", i + 1); break; } + if (i == 0 && clock == 0) + puts("Warning: SDREFCLK1 switch setting of" + "'00' is unsupported\n"); + else + actual[i] = freq[i][clock]; } for (i = 0; i < NUM_SRDS_BANKS; i++) { diff --git a/board/cerf250/Makefile b/board/freescale/p3060qds/Makefile index cf4742e..ae136f4 100644 --- a/board/cerf250/Makefile +++ b/board/freescale/p3060qds/Makefile @@ -1,5 +1,6 @@ # -# (C) Copyright 2000-2006 +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -25,14 +26,24 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := cerf250.o flash.o +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += eth.o +COBJS-y += fixed_ddr.o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + ######################################################################### # defines $(obj).depend target diff --git a/board/freescale/p3060qds/ddr.c b/board/freescale/p3060qds/ddr.c new file mode 100644 index 0000000..9affbf0 --- /dev/null +++ b/board/freescale/p3060qds/ddr.c @@ -0,0 +1,248 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +#include "p3060qds.h" + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ + +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + unsigned int lawbar1_target_id; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, + fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + /* + * setup laws for DDR. If not interleaving, presuming half memory on + * DDR1 and the other half on DDR2 + */ + if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) { + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + LAW_TRGT_IF_DDR_INTRLV) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } else { + lawbar1_target_id = LAW_TRGT_IF_DDR_1; + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + ddr_size, + lawbar1_target_id) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + } + return ddr_size; +} + +struct board_specific_params { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_params udimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 5, 6, 0xff, 2, 0}, + {2, 950, 5, 7, 0xff, 2, 0}, + {2, 1250, 4, 6, 0xff, 2, 0}, + {2, 1350, 5, 7, 0xff, 2, 0}, + {2, 1666, 5, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_params rdimm[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | |delay | + */ + {4, 850, 4, 6, 0xff, 2, 0}, + {4, 950, 5, 7, 0xff, 2, 0}, + {4, 1050, 5, 8, 0xff, 2, 0}, + {4, 1250, 5, 10, 0xff, 2, 0}, + {4, 1350, 5, 11, 0xff, 2, 0}, + {4, 1666, 5, 12, 0xff, 2, 0}, + {2, 850, 4, 6, 0xff, 2, 0}, + {2, 1050, 4, 7, 0xff, 2, 0}, + {2, 1666, 4, 8, 0xff, 2, 0}, + {1, 850, 4, 5, 0xff, 2, 0}, + {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1666, 4, 8, 0xff, 2, 0}, + {} +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_params *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num) { + printf("Wrong parameter for controller number %d", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + if (popts->registered_dimm_en) + pbsp = rdimm; + else + pbsp = udimm; + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s!\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } + + +found: + + /* + * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered. + * However SPD still claims CL=7 is supported. Extensive tests + * confirmed this board cannot work stably with CL=7 with this + * particular DIMM. + */ + if (ddr_freq >= 800 && ddr_freq < 1066 && \ + !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) { + popts->cas_latency_override = 1; + popts->cas_latency_override_value = 8; + debug("Override CL to 8\n"); + } + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("using fixed parameters\n"); + dram_size = fixed_sdram(); + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + debug(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p3060qds/eth.c b/board/freescale/p3060qds/eth.c new file mode 100644 index 0000000..3f812db --- /dev/null +++ b/board/freescale/p3060qds/eth.c @@ -0,0 +1,482 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <malloc.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <miiphy.h> +#include <phy.h> +#include <asm/fsl_dtsec.h> + +#include "../common/qixis.h" +#include "../common/fman.h" + +#include "p3060qds_qixis.h" + +#define EMI_NONE 0xffffffff +#define EMI1_RGMII1 0 +#define EMI1_SLOT1 1 +#define EMI1_SLOT2 2 +#define EMI1_SLOT3 3 +#define EMI1_RGMII2 4 + +static int mdio_mux[NUM_FM_PORTS]; + +static char *mdio_names[5] = { + "P3060QDS_MDIO0", + "P3060QDS_MDIO1", + "P3060QDS_MDIO2", + "P3060QDS_MDIO3", + "P3060QDS_MDIO4", +}; + +/* + * Mapping of all 18 SERDES lanes to board slots. + * A value of '0' here means that the mapping must be determined + * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug + */ +static u8 lane_to_slot[] = { + 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0 +}; + +static char *p3060qds_mdio_name_for_muxval(u32 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u32 muxval) +{ + struct mii_dev *bus; + char *name = p3060qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct p3060qds_mdio { + u32 muxval; + struct mii_dev *realbus; +}; + +static void p3060qds_mux_mdio(u32 muxval) +{ + u8 brdcfg4; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << 4); + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct p3060qds_mdio *priv = bus->priv; + + p3060qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int p3060qds_mdio_reset(struct mii_dev *bus) +{ + struct p3060qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int p3060qds_mdio_init(char *realbusname, u32 muxval) +{ + struct p3060qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate P3060QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate P3060QDS private data\n"); + free(bus); + return -1; + } + + bus->read = p3060qds_mdio_read; + bus->write = p3060qds_mdio_write; + bus->reset = p3060qds_mdio_reset; + sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, + enum fm_port port, int offset) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + if (mdio_mux[port] == EMI1_RGMII1) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1"); + + if (mdio_mux[port] == EMI1_RGMII2) + fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2"); + + if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3) + || (srds_prtcl == 0x6))) { + switch (port) { + case FM2_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy2_slot1"); + break; + case FM1_DTSEC4: + fdt_set_phy_handle(blob, prop, pa, "phy3_slot1"); + break; + default: + break; + } + } + + if (mdio_mux[port] == EMI1_SLOT3) { + switch (port) { + case FM2_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy0_slot3"); + break; + case FM1_DTSEC3: + fdt_set_phy_handle(blob, prop, pa, "phy1_slot3"); + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) { + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + fdt_status_disabled_by_alias(fdt, + "emi1_slot1_bk1"); + } else { + fdt_status_disabled_by_alias(fdt, + "emi1_slot1"); + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + } + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + + if (i == FM1_DTSEC2) + fdt_status_okay_by_alias(fdt, "emi1_rgmii2"); + break; + default: + break; + } + } +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + idx = i - FM2_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + switch (mdio_mux[i]) { + case EMI1_SLOT1: + if (lane >= 14) + fdt_status_okay_by_alias(fdt, + "emi1_slot1"); + else + fdt_status_okay_by_alias(fdt, + "emi1_slot1_bk1"); + break; + case EMI1_SLOT2: + fdt_status_okay_by_alias(fdt, + "emi1_slot2"); + break; + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, + "emi1_slot3"); + break; + } + } + break; + default: + break; + } + } +#endif +} + +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int sdprtl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (sdprtl) { + case 0x03: + case 0x06: + lane_to_slot[8] = 1; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 5; + lane_to_slot[17] = lane_to_slot[16]; + break; + case 0x16: + case 0x19: + case 0x1C: + lane_to_slot[8] = 5; + lane_to_slot[9] = lane_to_slot[8]; + lane_to_slot[16] = 1; + lane_to_slot[17] = lane_to_slot[16]; + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + int i; + struct fsl_pq_mdio_info dtsec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + initialize_lane_to_slot(); + + /* + * Set TBIPA on FM1@DTSEC1. This is needed for configurations + * where FM1@DTSEC1 isn't used directly, since it provides + * MDIO for other ports. + */ + out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + /* Register the 5 muxing front-ends to the MDIO buses */ + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + + if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */ + else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR); + + if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII) + fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */ + else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII) + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + + fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR); + + switch (srds_cfg) { + case 0x03: + case 0x06: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x16: + case 0x19: + case 0x1C: + fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC1) { + mdio_mux[i] = EMI1_RGMII1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } else if (i == FM1_DTSEC2) { + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + } + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1, lane, slot; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + if (QIXIS_READ(present) & (1 << (slot - 1))) + fm_disable_port(i); + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + mdio_mux[i] = EMI1_SLOT3; + fm_info_set_mdio(i, + mii_dev_for_muxval(mdio_mux[i])); + break; + }; + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/p3060qds/fixed_ddr.c b/board/freescale/p3060qds/fixed_ddr.c new file mode 100644 index 0000000..125988d --- /dev/null +++ b/board/freescale/p3060qds/fixed_ddr.c @@ -0,0 +1,214 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 +#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 +#define CONFIG_SYS_DDR_TIMING_1_1200 0x868FAA45 +#define CONFIG_SYS_DDR_TIMING_2_1200 0x0FB8A912 +#define CONFIG_SYS_DDR_MODE_1_1200 0x00441A40 +#define CONFIG_SYS_DDR_MODE_2_1200 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1200 0x12480100 +#define CONFIG_SYS_DDR_CLK_CTRL_1200 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_1000 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_1000 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_1000 0x727DF944 +#define CONFIG_SYS_DDR_TIMING_2_1000 0x0FB088CF +#define CONFIG_SYS_DDR_MODE_1_1000 0x00441830 +#define CONFIG_SYS_DDR_MODE_2_1000 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_1000 0x0F3C0100 +#define CONFIG_SYS_DDR_CLK_CTRL_1000 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_900 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_900 0xCC440104 +#define CONFIG_SYS_DDR_TIMING_1_900 0x616ba844 +#define CONFIG_SYS_DDR_TIMING_2_900 0x0fb088ce +#define CONFIG_SYS_DDR_MODE_1_900 0x00441620 +#define CONFIG_SYS_DDR_MODE_2_900 0x00080000 +#define CONFIG_SYS_DDR_INTERVAL_900 0x0db60100 +#define CONFIG_SYS_DDR_CLK_CTRL_900 0x02800000 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0xcc330104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b4744 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cc +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS0_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR2_CS2_BNDS 0x000000FF +#define CONFIG_SYS_DDR2_CS3_BNDS 0x000000FF +#define CONFIG_SYS_DDR_CS0_CONFIG 0xA0044202 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS0_CONFIG 0x80044202 +#define CONFIG_SYS_DDR2_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 +#define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80004202 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8675F607 +#define CONFIG_SYS_DDR_SDRAM_CFG 0xE7044000 +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x24401031 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_900 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_900, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_900, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_900, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_900, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_900, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_900, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1000 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1000, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1000, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1000, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1000, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1000, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1000, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1200 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, + .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS, + .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, + .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG, + .cs[3].config = CONFIG_SYS_DDR_CS3_CONFIG, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1200, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1200, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200, + .ddr_sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_SDRAM_CFG2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1200, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1200, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1200, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1200, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {850, 950, &ddr_cfg_regs_900}, + {950, 1050, &ddr_cfg_regs_1000}, + {1050, 1250, &ddr_cfg_regs_1200}, + {0, 0, NULL} +}; diff --git a/board/freescale/p3060qds/p3060qds.c b/board/freescale/p3060qds/p3060qds.c new file mode 100644 index 0000000..c6c74f2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.c @@ -0,0 +1,341 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> +#include <configs/P3060QDS.h> +#include <libfdt.h> +#include <fdt_support.h> + +#include "../common/qixis.h" +#include "p3060qds.h" +#include "p3060qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %s", cpu->name); + puts("QDS, "); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + static const char * const freq[] = {"100", "125", "Reserved", + "156.25"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* only single DDR controller on QDS board, disable DDR1_MCK4/5 */ + setbits_be32(&gur->ddrclkdr, 0x00030000); + + return 0; +} + +void board_config_serdes_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int cfg = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + switch (cfg) { + case 0x03: + case 0x06: + /* set Lane I,J as SGMII */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_B | BRDCFG6_SD3MX_A | + BRDCFG6_SD2MX_B | BRDCFG6_SD1MX_A); + break; + case 0x16: + case 0x19: + case 0x1c: + /* set Lane I,J as Aurora Debug */ + QIXIS_WRITE(brdcfg[6], BRDCFG6_SD4MX_A | BRDCFG6_SD3MX_B | + BRDCFG6_SD2MX_A | BRDCFG6_SD1MX_B); + break; + default: + puts("Invalid SerDes protocol for P3060QDS\n"); + break; + } +} + +void board_config_usb_mux(void) +{ + u8 brdcfg4, brdcfg5, brdcfg7; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + u32 ec1 = rcwsr11 & FSL_CORENET_RCWSR11_EC1; + u32 ec2 = rcwsr11 & FSL_CORENET_RCWSR11_EC2; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EC_MODE_MASK; + if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_USB1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_USB; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + (ec2 == FSL_CORENET_RCWSR11_EC2_USB2)) { + brdcfg4 |= BRDCFG4_EC2_USB_EC1_RGMII; + + } else if ((ec1 == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1) && + ((ec2 == FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2) || + (ec2 == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))) { + brdcfg4 |= BRDCFG4_EC2_RGMII_EC1_RGMII; + } else { + brdcfg4 |= BRDCFG4_EC2_MII_EC1_MII; + } + QIXIS_WRITE(brdcfg[4], brdcfg4); + + brdcfg5 = QIXIS_READ(brdcfg[5]); + brdcfg5 &= ~(BRDCFG5_USB1ID_MASK | BRDCFG5_USB2ID_MASK); + brdcfg5 |= (BRDCFG5_USB1ID_CTRL | BRDCFG5_USB2ID_CTRL); + QIXIS_WRITE(brdcfg[5], brdcfg5); + + brdcfg7 = BRDCFG7_JTAGMX_COP_JTAG | BRDCFG7_IQ1MX_IRQ_EVT | + BRDCFG7_G1MX_USB1 | BRDCFG7_D1MX_TSEC3USB | BRDCFG7_I3MX_USB1; + QIXIS_WRITE(brdcfg[7], brdcfg7); +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + board_config_serdes_mux(); + board_config_usb_mux(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 3 + +int misc_init_r(void) +{ + serdes_corenet_t *srds_regs; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = QIXIS_READ(brdcfg[2]); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 3: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '10' is " + "unsupported\n", i + 1); + break; + } + } + + srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = in_be32(&srds_regs->bank[i].pllcr0); + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +/* + * This is map of CVDD values. 33 means CVDD is 3.3v, 25 means CVDD is 2.5v, + * 18 means CVDD is 1.8v. + */ +static u8 IO_VSEL[] = { + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 25, 25, 25, 18, 18, 18, + 33, 33, 33, 33, 33 +}; + +#define IO_VSEL_MASK 0x1f + +/* + * different CVDD selects diffenert spi flashs, read dutcfg[3] to get CVDD, + * then set status of spi flash nodes to 'disabled' according to CVDD. + * CVDD '33' will select spi flash0 and flash1, CVDD '25' will select spi + * flash2, CVDD '18' will select spi flash3. + */ +void fdt_fixup_board_spi(void *blob) +{ + u8 sw5 = QIXIS_READ(dutcfg[3]); + + switch (IO_VSEL[sw5 & IO_VSEL_MASK]) { + /* 3.3v */ + case 33: + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 2.5v */ + case 25: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,sst25wf040", "status", + "disabled", strlen("disabled") + 1, 1); + break; + /* 1.8v */ + case 18: + do_fixup_by_compat(blob, "spansion,s25sl12801", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "spansion,en25q32", "status", + "disabled", strlen("disabled") + 1, 1); + do_fixup_by_compat(blob, "atmel,at45db081d", "status", + "disabled", strlen("disabled") + 1, 1); + break; + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + fdt_fixup_board_spi(blob); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/p3060qds/p3060qds.h b/board/freescale/p3060qds/p3060qds.h new file mode 100644 index 0000000..3da6815 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds.h @@ -0,0 +1,30 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_H__ +#define __P3060QDS_H__ + +#include <asm/fsl_ddr_sdram.h> +#include <asm/u-boot.h> + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); +extern fixed_ddr_parm_t fixed_ddr_parm_0[]; + +#endif diff --git a/board/freescale/p3060qds/p3060qds_qixis.h b/board/freescale/p3060qds/p3060qds_qixis.h new file mode 100644 index 0000000..4d5d6a2 --- /dev/null +++ b/board/freescale/p3060qds/p3060qds_qixis.h @@ -0,0 +1,74 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __P3060QDS_QIXIS_H__ +#define __P3060QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for P3060QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EC_MODE_MASK 0x0F +#define BRDCFG4_EC2_MII_EC1_MII 0x00 +#define BRDCFG4_EC2_MII_EC1_USB 0x03 +#define BRDCFG4_EC2_USB_EC1_MII 0x0C +#define BRDCFG4_EC2_USB_EC1_USB 0x0F +#define BRDCFG4_EC2_USB_EC1_RGMII 0x0E +#define BRDCFG4_EC2_RGMII_EC1_USB 0x0B +#define BRDCFG4_EC2_RGMII_EC1_RGMII 0x0A +#define BRDCFG4_EMISEL_MASK 0xF0 + +#define BRDCFG5_ECLKS_MASK 0x80 +#define BRDCFG5_USB1ID_MASK 0x40 +#define BRDCFG5_USB2ID_MASK 0x20 +#define BRDCFG5_GC2MX_MASK 0x0C +#define BRDCFG5_T15MX_MASK 0x03 +#define BRDCFG5_ECLKS_IEEE1588_CM 0x80 +#define BRDCFG5_USB1ID_CTRL 0x40 +#define BRDCFG5_USB2ID_CTRL 0x20 + +#define BRDCFG6_SD1MX_A 0x01 +#define BRDCFG6_SD1MX_B 0x00 +#define BRDCFG6_SD2MX_A 0x02 +#define BRDCFG6_SD2MX_B 0x00 +#define BRDCFG6_SD3MX_A 0x04 +#define BRDCFG6_SD3MX_B 0x00 +#define BRDCFG6_SD4MX_A 0x08 +#define BRDCFG6_SD4MX_B 0x00 + +#define BRDCFG7_JTAGMX_MASK 0xC0 +#define BRDCFG7_IQ1MX_MASK 0x20 +#define BRDCFG7_G1MX_MASK 0x10 +#define BRDCFG7_D1MX_MASK 0x0C +#define BRDCFG7_I3MX_MASK 0x03 +#define BRDCFG7_JTAGMX_AURORA 0x00 +#define BRDCFG7_JTAGMX_FPGA 0x80 +#define BRDCFG7_JTAGMX_COP_JTAG 0xC0 +#define BRDCFG7_IQ1MX_IRQ_EVT 0x00 +#define BRDCFG7_IQ1MX_USB2 0x20 +#define BRDCFG7_G1MX_USB1 0x00 +#define BRDCFG7_G1MX_TSEC3 0x10 +#define BRDCFG7_D1MX_DMA 0x00 +#define BRDCFG7_D1MX_TSEC3USB 0x04 +#define BRDCFG7_D1MX_HDLC2 0x08 +#define BRDCFG7_I3MX_UART2_I2C34 0x00 +#define BRDCFG7_I3MX_GPIO_EVT 0x01 +#define BRDCFG7_I3MX_USB1 0x02 +#define BRDCFG7_I3MX_TSEC3 0x03 + +#endif diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index ecba66e..f55afbd 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -87,7 +87,6 @@ static void print_fpga_info(unsigned dev) u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; - unsigned feature_compression; unsigned feature_rs232; unsigned feature_audio; unsigned feature_sysclock; @@ -111,7 +110,6 @@ static void print_fpga_info(unsigned dev) unit_type = (versions >> 4) & 0x000f; hardware_version = versions & 0x000f; - feature_compression = (fpga_features >> 13) & 0x0003; feature_rs232 = fpga_features & (1<<11); feature_audio = (fpga_features >> 9) & 0x0003; feature_sysclock = (fpga_features >> 7) & 0x0003; diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c new file mode 100644 index 0000000..0d25214 --- /dev/null +++ b/board/gdsys/405ex/405ex.c @@ -0,0 +1,250 @@ +#include <common.h> +#include <asm/ppc4xx.h> +#include <asm/ppc405.h> +#include <asm/processor.h> +#include <asm/io.h> + +#include <gdsys_fpga.h> + +#include "405ex.h" + +#define REFLECTION_TESTPATTERN 0xdede +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) + +DECLARE_GLOBAL_DATA_PTR; + +int get_fpga_state(unsigned dev) +{ + return gd->fpga_state[dev]; +} + +void print_fpga_state(unsigned dev) +{ + if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); +} + +int board_early_init_f(void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ + mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ + + mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ + mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */ + mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* + * Configure PFC (Pin Function Control) registers + */ + val = SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; + + /* + * reset FPGA + */ + gd405ex_init(); + + gd405ex_set_fpga_reset(1); + + gd405ex_setup_hw(); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ctr = 0; + while (!gd405ex_get_fpga_done(k)) { + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; + break; + } + } + } + + udelay(10); + + gd405ex_set_fpga_reset(0); + + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI + u16 *reflection_target = &fpga->reflection_low; +#else + u16 *reflection_target = &fpga->reflection_high; +#endif + /* + * wait for fpga out of reset + */ + ctr = 0; + while (1) { + out_le16(&fpga->reflection_low, + REFLECTION_TESTPATTERN); + + if (in_le16(reflection_target) == + REFLECTION_TESTPATTERN_INV) + break; + + udelay(100000); + if (ctr++ > 5) { + gd->fpga_state[k] |= + FPGA_STATE_REFLECTION_FAILED; + break; + } + } + } + + return 0; +} diff --git a/board/gdsys/405ex/405ex.h b/board/gdsys/405ex/405ex.h new file mode 100644 index 0000000..b15623f --- /dev/null +++ b/board/gdsys/405ex/405ex.h @@ -0,0 +1,10 @@ +#ifndef __405EX_H_ +#define __405EX_H_ + +/* functions to be provided by board implementation */ +void gd405ex_init(void); +void gd405ex_set_fpga_reset(unsigned state); +void gd405ex_setup_hw(void); +int gd405ex_get_fpga_done(unsigned fpga); + +#endif /* __405EX_H_ */ diff --git a/board/csb226/Makefile b/board/gdsys/405ex/Makefile index 6fe9bec..4549705 100644 --- a/board/csb226/Makefile +++ b/board/gdsys/405ex/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -25,14 +25,24 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := csb226.o flash.o +COBJS-$(CONFIG_IO64) += io64.o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +COBJS-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o + +COBJS := $(BOARD).o $(COBJS-y) + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/gdsys/405ex/chip_config.c b/board/gdsys/405ex/chip_config.c new file mode 100644 index 0000000..12cb3bf --- /dev/null +++ b/board/gdsys/405ex/chip_config.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/ppc4xx_config.h> + +/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ + +struct ppc4xx_config ppc4xx_config_val[] = { + { + "333-nor", "NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-133-nor", "NOR CPU: 400 PLB: 133 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-200-66-nor", "NOR CPU: 400 PLB: 200 OPB: 66 EBC: 66", + { + 0x8e, 0x0e, 0xe8, 0x12, 0xd8, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "400-nor", "NOR CPU: 400 PLB: 200 OPB: 100 EBC: 100", + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, + { + "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, +}; + +int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val); diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c new file mode 100644 index 0000000..a997571 --- /dev/null +++ b/board/gdsys/405ex/io64.c @@ -0,0 +1,384 @@ +/* + * (C) Copyright 2010 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on kilauea.c + * by Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/ppc4xx.h> +#include <asm/ppc405.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/ppc4xx-gpio.h> +#include <flash.h> + +#include <pca9698.h> + +#include "405ex.h" +#include <gdsys_fpga.h> + +#include <miiphy.h> +#include <i2c.h> +#include <dtt.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define PHYREG_CONTROL 0 +#define PHYREG_PAGE_ADDRESS 22 +#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 +#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26 +#define PHYREG_PG2_MAC_SPECIFIC_STATUS_1 17 +#define PHYREG_PG2_MAC_SPECIFIC_CONTROL 21 + +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) +#define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) + +enum { + UNITTYPE_CCD_SWITCH = 1, +}; + +enum { + HWVER_100 = 0, + HWVER_110 = 1, +}; + +static inline void blank_string(int size) +{ + int i; + + for (i = 0; i < size; i++) + putc('\b'); + for (i = 0; i < size; i++) + putc(' '); + for (i = 0; i < size; i++) + putc('\b'); +} + +/* + * Board early initialization function + */ +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + +#ifdef CONFIG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +static void print_fpga_info(unsigned dev) +{ + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); + int fpga_state = get_fpga_state(dev); + + unsigned unit_type; + unsigned hardware_version; + unsigned feature_channels; + unsigned feature_expansion; + + printf("FPGA%d: ", dev); + if (fpga_state & FPGA_STATE_PLATFORM) + printf("(legacy) "); + + if (fpga_state & FPGA_STATE_DONE_FAILED) { + printf(" done timed out\n"); + return; + } + + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { + printf(" refelectione test failed\n"); + return; + } + + unit_type = (versions & 0xf000) >> 12; + hardware_version = versions & 0x000f; + feature_channels = fpga_features & 0x007f; + feature_expansion = fpga_features & (1<<15); + + switch (unit_type) { + case UNITTYPE_CCD_SWITCH: + printf("CCD-Switch"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (hardware_version) { + case HWVER_100: + printf(" HW-Ver 1.00\n"); + break; + + case HWVER_110: + printf(" HW-Ver 1.10\n"); + break; + + default: + printf(" HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d, features:", + fpga_version / 100, fpga_version % 100); + + printf(" %d channel(s)", feature_channels); + + printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: CATCenter Io64\n"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + return 0; +} + +int configure_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch to powerdown */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value | 0x0004)) + goto err_out; + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* disable SGMII autonegotiation */ + if (miiphy_write(bus, addr, PHYREG_PG2_MAC_SPECIFIC_CONTROL, 48)) + goto err_out; + /* select page 0 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0000)) + goto err_out; + /* switch from powerdown to normal operation */ + if (miiphy_read(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + &value)) + goto err_out; + if (miiphy_write(bus, addr, PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, + value & ~0x0004)) + goto err_out; + /* reset phy so settings take effect */ + if (miiphy_write(bus, addr, PHYREG_CONTROL, 0x9140)) + goto err_out; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int verify_gbit_phy(char *bus, unsigned char addr) +{ + unsigned short value; + + /* select page 2 */ + if (miiphy_write(bus, addr, PHYREG_PAGE_ADDRESS, 0x0002)) + goto err_out; + /* verify SGMII link status */ + if (miiphy_read(bus, addr, PHYREG_PG2_MAC_SPECIFIC_STATUS_1, &value)) + goto err_out; + if (!(value & (1 << 10))) + return -2; + + return 0; + +err_out: + printf("Error writing to the PHY addr=%02x\n", addr); + return -1; +} + +int last_stage_init(void) +{ + unsigned int k; + unsigned int fpga; + ihs_fpga_t *fpga0 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + ihs_fpga_t *fpga1 = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(1); + int failed = 0; + char str_phys[] = "Setup PHYs -"; + char str_serdes[] = "Start SERDES blocks"; + char str_channels[] = "Start FPGA channels"; + char str_locks[] = "Verify SERDES locks"; + char str_status[] = "Verify PHY status -"; + char slash[] = "\\|/-\\|/-"; + + print_fpga_info(0); + print_fpga_info(1); + + /* setup Gbit PHYs */ + puts("TRANS: "); + puts(str_phys); + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + + miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, + bb_miiphy_read, bb_miiphy_write); + + for (k = 0; k < 32; ++k) { + configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_phys)); + + /* take fpga serdes blocks out of reset */ + puts(str_serdes); + udelay(500000); + out_le16(&fpga0->quad_serdes_reset, 0); + out_le16(&fpga1->quad_serdes_reset, 0); + blank_string(strlen(str_serdes)); + + /* take channels out of reset */ + puts(str_channels); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int; + for (k = 0; k < 32; ++k) + out_le16(ch0_config_int + 4 * k, 0); + } + blank_string(strlen(str_channels)); + + /* verify channels serdes lock */ + puts(str_locks); + udelay(500000); + for (fpga = 0; fpga < 2; ++fpga) { + u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int; + for (k = 0; k < 32; ++k) { + u16 status = in_le16(ch0_status_int + 4*k); + if (!(status & (1 << 4))) { + failed = 1; + printf("fpga %d channel %d: no serdes lock\n", + fpga, k); + } + /* reset events */ + out_le16(ch0_status_int + 4*k, status); + } + } + blank_string(strlen(str_locks)); + + /* verify phy status */ + puts(str_status); + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k)) { + printf("verify baseboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + for (k = 0; k < 32; ++k) { + if (verify_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k)) { + printf("verify extensionboard phy %d failed\n", k); + failed = 1; + } + putc('\b'); + putc(slash[k % 8]); + } + blank_string(strlen(str_status)); + + printf("Starting 64 channels %s\n", failed ? "failed" : "ok"); + + return 0; +} + +void gd405ex_init(void) +{ + unsigned int k; + + if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */ + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] |= FPGA_STATE_PLATFORM; + } else { + pca9698_direction_output(0x22, 39, 1); + } +} + +void gd405ex_set_fpga_reset(unsigned state) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) { + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } + } else { + pca9698_set_value(0x22, 39, state ? 0 : 1); + } +} + +void gd405ex_setup_hw(void) +{ + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED_N, 0); + gpio_write_bit(CONFIG_SYS_GPIO_STARTUP_FINISHED, 1); +} + +int gd405ex_get_fpga_done(unsigned fpga) +{ + int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; + + if (legacy) + return in_le16((void *)LATCH3_BASE) + & CONFIG_SYS_FPGA_DONE(fpga); + else + return pca9698_get_value(0x22, fpga ? 9 : 8); +} diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 2868cc8..05dd65d 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -30,6 +30,7 @@ endif LIB = $(obj)lib$(VENDOR).o COBJS-$(CONFIG_IO) += miiphybb.o +COBJS-$(CONFIG_IO64) += miiphybb.o COBJS-$(CONFIG_IOCON) += osd.o COBJS-$(CONFIG_DLVISION_10G) += osd.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c index e56e966..46f1a1e 100644 --- a/board/gdsys/common/miiphybb.c +++ b/board/gdsys/common/miiphybb.c @@ -26,6 +26,11 @@ #include <asm/io.h> +struct io_bb_pinset { + int mdio; + int mdc; +}; + static int io_bb_mii_init(struct bb_miiphy_bus *bus) { return 0; @@ -33,47 +38,57 @@ static int io_bb_mii_init(struct bb_miiphy_bus *bus) static int io_bb_mdio_active(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) | pins->mdio); return 0; } static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) { + struct io_bb_pinset *pins = bus->priv; + out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_TCR) & ~pins->mdio); return 0; } static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) | pins->mdio); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdio); return 0; } static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) { - *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0); + struct io_bb_pinset *pins = bus->priv; + + *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); return 0; } static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) { + struct io_bb_pinset *pins = bus->priv; + if (v) out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) | pins->mdc); else out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN); + in_be32((void *)GPIO0_OR) & ~pins->mdc); return 0; } @@ -85,6 +100,19 @@ static int io_bb_delay(struct bb_miiphy_bus *bus) return 0; } +struct io_bb_pinset io_bb_pinsets[] = { + { + .mdio = CONFIG_SYS_MDIO_PIN, + .mdc = CONFIG_SYS_MDC_PIN, + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .mdio = CONFIG_SYS_MDIO1_PIN, + .mdc = CONFIG_SYS_MDC1_PIN, + }, +#endif +}; + struct bb_miiphy_bus bb_miiphy_buses[] = { { .name = CONFIG_SYS_GBIT_MII_BUSNAME, @@ -95,7 +123,21 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { .get_mdio = io_bb_get_mdio, .set_mdc = io_bb_set_mdc, .delay = io_bb_delay, - } + .priv = &io_bb_pinsets[0], + }, +#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME + { + .name = CONFIG_SYS_GBIT_MII1_BUSNAME, + .init = io_bb_mii_init, + .mdio_active = io_bb_mdio_active, + .mdio_tristate = io_bb_mdio_tristate, + .set_mdio = io_bb_set_mdio, + .get_mdio = io_bb_get_mdio, + .set_mdc = io_bb_set_mdc, + .delay = io_bb_delay, + .priv = &io_bb_pinsets[1], + }, +#endif }; int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / diff --git a/board/hymod/input.c b/board/hymod/input.c index 1a2b8d2..0a58015 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -23,9 +23,6 @@ #include <common.h> -/* imports from common/main.c */ -extern char console_buffer[CONFIG_SYS_CBSIZE]; - int hymod_get_serno (const char *prompt) { diff --git a/board/innokom/flash.c b/board/innokom/flash.c deleted file mode 100644 index ed4b987..0000000 --- a/board/innokom/flash.c +++ /dev/null @@ -1,421 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> - * - * (C) Copyright 2002 - * Auerswald GmbH & Co KG, Germany - * Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/pxa-regs.h> - -/* Debugging macros ------------------------------------------------------ */ - -#undef FLASH_DEBUG - -/* Some debug macros */ -#if (FLASH_DEBUG > 2 ) -#define PRINTK3(args...) printf(args) -#else -#define PRINTK3(args...) -#endif - -#if FLASH_DEBUG > 1 -#define PRINTK2(args...) printf(args) -#else -#define PRINTK2(args...) -#endif - -#ifdef FLASH_DEBUG -#define PRINTK(args...) printf(args) -#else -#define PRINTK(args...) -#endif - -/* ------------------------------------------------------------------------ */ - -/* Development system: we have only 16 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_16MB -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB (during development) */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -/* Production system: we have 64 MB Flash */ -#ifdef CONFIG_MTD_INNOKOM_64MB -#define FLASH_BANK_SIZE 0x04000000 /* 64 MB */ -#define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/** - * flash_init: - initialize data structures for flash chips - * - * @return: size of the flash - */ - -ulong flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F128J3 & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect u-boot sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (256*1024) - 1, - &flash_info[0]); - -#ifdef CONFIG_ENV_IS_IN_FLASH - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - - -/** - * flash_print_info: - print information about the flash situation - * - * @param info: - */ - -void flash_print_info (flash_info_t *info) -{ - int i, j; - - for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { - - switch (info->flash_id & FLASH_VENDMASK) { - - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf("Intel: "); - break; - default: - printf("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf("28F128J3 (128Mbit)\n"); - break; - default: - printf("Unknown Chip Type\n"); - return; - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) printf ("\n "); - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - info++; - } -} - - -/** - * flash_erase: - erase flash sectors - * - */ - -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - ulong start; - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) - return ERR_UNKNOWN_FLASH_VENDOR; - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) prot++; - } - - if (prot) return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - flag = disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { - - printf("Erasing sector %2d ... ", sect); - - PRINTK("\n"); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - u16 * volatile addr = (u16 * volatile)(info->start[sect]); - - PRINTK("unlocking sector\n"); - *addr = 0x0060; - *addr = 0x00d0; - *addr = 0x00ff; - - PRINTK("erasing sector\n"); - *addr = 0x0020; - PRINTK("confirming erase\n"); - *addr = 0x00D0; - - while ((*addr & 0x0080) != 0x0080) { - PRINTK("."); - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = 0x00B0; /* suspend erase*/ - *addr = 0x00FF; /* read mode */ - rc = ERR_TIMOUT; - goto outahere; - } - } - - PRINTK("clearing status register\n"); - *addr = 0x0050; - PRINTK("resetting to read mode"); - *addr = 0x00FF; - } - - printf("ok.\n"); - } - - if (ctrlc()) printf("User Interrupt!\n"); - - outahere: - - /* allow flash to settle - wait 10 ms */ - udelay_masked(10000); - - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_word: - copy memory to flash - * - * @param info: - * @param dest: - * @param data: - * @return: - */ - -static int write_word (flash_info_t *info, ulong dest, ushort data) -{ - volatile u16 *addr = (u16 *)dest, val; - int rc = ERR_OK; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts(); - - /* clear status register command */ - *addr = 0x50; - - /* program set-up command */ - *addr = 0x40; - - /* latch address/data */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while(((val = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = ERR_TIMOUT; - *addr = 0xB0; /* suspend program command */ - goto outahere; - } - } - - if(val & 0x1A) { /* check for error */ - printf("\nFlash write error %02x at address %08lx\n", - (int)val, (unsigned long)dest); - if(val & (1<<3)) { - printf("Voltage range error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - if(val & (1<<1)) { - printf("Device protect error.\n"); - rc = ERR_PROTECTED; - goto outahere; - } - if(val & (1<<4)) { - printf("Programming error.\n"); - rc = ERR_PROG_ERROR; - goto outahere; - } - rc = ERR_PROG_ERROR; - goto outahere; - } - - outahere: - - *addr = 0xFF; /* read array command */ - if (flag) enable_interrupts(); - - return rc; -} - - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - for (; i<2 && cnt>0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt==0 && i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((ushort*)src); - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i<2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *)cp << 8); - } - - return write_word(info, wp, data); -} diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c deleted file mode 100644 index 22de7e3..0000000 --- a/board/innokom/innokom.c +++ /dev/null @@ -1,190 +0,0 @@ -/* - * (C) Copyright 2002 - * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de - * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net - * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/pxa-regs.h> -#include <asm/mach-types.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - -/** - * i2c_init_board - reset i2c bus. When the board is powercycled during a - * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. - * The Innokom board has GPIO70 connected to SCLK which can be toggled - * until all chips think that their current cycles are finished. - */ -int i2c_init_board(void) -{ - int i; - - /* set gpio pin low _before_ we change direction to output */ - writel(GPIO_bit(70), GPCR(70)); - - /* now toggle between output=low and high-impedance */ - for (i = 0; i < 20; i++) { - writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */ - udelay(10); - writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */ - udelay(10); - } - - return 0; -} - - -/** - * misc_init_r: - misc initialisation routines - */ - -int misc_init_r(void) -{ - char *str; - - /* determine if the software update key is pressed during startup */ - if (readl(GPLR0) & 0x00000800) { - printf("using bootcmd_normal (sw-update button not pressed)\n"); - str = getenv("bootcmd_normal"); - } else { - printf("using bootcmd_update (sw-update button pressed)\n"); - str = getenv("bootcmd_update"); - } - - setenv("bootcmd",str); - - return 0; -} - - -/** - * board_init: - setup some data structures - * - * @return: 0 in case of success - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; - gd->bd->bi_boot_params = 0xa0000100; - gd->bd->bi_baudrate = CONFIG_BAUDRATE; - - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -/** - * innokom_set_led: - switch LEDs on or off - * - * @param led: LED to switch (0,1,2) - * @param state: switch on (1) or off (0) - */ - -void innokom_set_led(int led, int state) -{ - switch(led) { -/* - case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; - } - break; - - case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; - } - break; - - case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; - } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; - } - break; -*/ - } - - return; -} - - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - * The CSB226 does only have 3 LEDs, so we switch them on at the most - * important states (1, 5, 15). - */ - -void show_boot_progress (int status) -{ - switch(status) { -/* - case 1: csb226_set_led(0,1); break; - case 5: csb226_set_led(1,1); break; - case 15: csb226_set_led(2,1); break; -*/ - } - - return; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/keymile/km83xx/km83xx_i2c.c b/board/keymile/km83xx/km83xx_i2c.c index be17775..8df92d8 100644 --- a/board/keymile/km83xx/km83xx_i2c.c +++ b/board/keymile/km83xx/km83xx_i2c.c @@ -41,7 +41,6 @@ int i2c_make_abort(void) { struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - uchar dummy; uchar last; int nbr_read = 0; int i = 0; @@ -52,7 +51,7 @@ int i2c_make_abort(void) udelay(DELAY_ABORT_SEQ); out_8(&dev->cr, (I2C_CR_MEN | I2C_CR_MSTA)); udelay(DELAY_ABORT_SEQ); - dummy = in_8(&dev->dr); + in_8(&dev->dr); udelay(DELAY_ABORT_SEQ); last = in_8(&dev->dr); nbr_read++; diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index c0a006a..0a105bf 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -76,7 +76,7 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index 3d74ef1..68d746c 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -31,46 +31,6 @@ const omap3_sysinfo sysinfo = { "AM3517EVM Board", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk deleted file mode 100644 index 71ec5d0..0000000 --- a/board/logicpd/am3517evm/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Author: Vaibhav Hiremath <hvaibhav@ti.com> -# -# Based on ti/evm/config.mk -# -# Copyright (C) 2010 -# Texas Instruments Incorporated - http://www.ti.com/ -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index e1e7807..bf8f0c9 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -220,7 +220,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type, start; int rcode = 0; @@ -255,7 +255,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -389,7 +389,6 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) { FPWV *addr = (FPWV *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -398,7 +397,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = (FPW) 0x00400040; /* write setup */ *addr = data; diff --git a/board/lubbock/lubbock.c b/board/lubbock/lubbock.c index f791c5b..437f944 100644 --- a/board/lubbock/lubbock.c +++ b/board/lubbock/lubbock.c @@ -27,6 +27,7 @@ #include <common.h> #include <netdev.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,10 +57,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c index 404c8b4..acb72c5 100644 --- a/board/matrix_vision/common/mv_common.c +++ b/board/matrix_vision/common/mv_common.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_ENV_IS_NOWHERE static char* entries_to_keep[] = { "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", @@ -38,7 +39,6 @@ static char* entries_to_keep[] = { #define MV_MAX_ENV_ENTRY_LENGTH 64 #define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) -#ifndef CONFIG_ENV_IS_NOWHERE void mv_reset_environment(void) { int i; diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile index 01cb517..f519a5d 100644 --- a/board/matrix_vision/mvblx/Makefile +++ b/board/matrix_vision/mvblx/Makefile @@ -37,12 +37,6 @@ CFLAGS += -Werror $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) -clean: - rm -f $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - ######################################################################### # defines $(obj).depend target diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c index 726366d..d8f754c 100644 --- a/board/mcc200/lcd.c +++ b/board/mcc200/lcd.c @@ -55,6 +55,9 @@ #define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */ #define PSOC_WAIT_TIME 10 /* usec */ +#include <video_font.h> +#define FONT_WIDTH VIDEO_FONT_WIDTH + DECLARE_GLOBAL_DATA_PTR; /* @@ -185,7 +188,6 @@ void lcd_enable (void) } #ifdef CONFIG_PROGRESSBAR -#define FONT_WIDTH 8 /* the same as VIDEO_FONT_WIDTH in video_font.h */ void show_progress (int size, int tot) { int cnt; diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 81d7271..d5b63c0 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -157,7 +157,7 @@ unsigned long flash_init (void) int i; #if !defined(CONFIG_PATI) - unsigned long size_b1,flashcr,size_reg; + unsigned long flashcr,size_reg; int mode; extern char version_string; char *p = &version_string; @@ -197,7 +197,6 @@ unsigned long flash_init (void) #if !defined(CONFIG_PATI) /* protect reset vector */ flash_info[0].protect[flash_info[0].sector_count-1] = 1; - size_b1 = 0 ; flash_info[0].size = size_b0; /* set up flash cs according to the size */ size_reg=(flash_info[0].size >>20); diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index e93d994..9d0db64 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -246,8 +246,7 @@ int init_sdram (void) unsigned char trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, - tctp_clocks; + trc_clocks; unsigned char cal_val; unsigned char bc; unsigned long sdram_tim, sdram_bank; @@ -345,7 +344,6 @@ int init_sdram (void) trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */ tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */ /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ - tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */ /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ @@ -626,10 +624,9 @@ phys_size_t initdram (int board_type) { unsigned long bank_reg[4], tmp, bank_size; - int i, ds; + int i; unsigned long TotalSize; - ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); @@ -646,8 +643,7 @@ phys_size_t initdram (int board_type) tmp = (bank_reg[i] >> 17) & 0x7; bank_size = 4 << tmp; TotalSize += bank_size; - } else - ds = 1; + } } mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG); tmp = mfdcr (SDRAM0_CFGDATA); diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 7b48c06..a1f0b65 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -179,7 +179,6 @@ void write_4hex (unsigned long val) int board_early_init_f (void) { - unsigned char dataout[1]; unsigned char datain[128]; unsigned long sdram_size = 0; SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; @@ -189,9 +188,13 @@ int board_early_init_f (void) unsigned short i; unsigned char rows, cols, banks, sdram_banks, density; unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, - trc_clocks, tctp_clocks; + trc_clocks; unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; +#ifdef SDRAM_DEBUG + unsigned char tctp_clocks; +#endif + /* set up the config port */ mtdcr (EBC0_CFGADDR, PB7AP); mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); @@ -210,7 +213,6 @@ int board_early_init_f (void) /* Read Serial Presence Detect Information */ i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - dataout[0] = 0; for (i = 0; i < 128; i++) datain[i] = 127; i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); @@ -307,12 +309,13 @@ int board_early_init_f (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; + +#ifdef SDRAM_DEBUG /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ tctp_clocks = ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + (tmemclk - 1)) / tmemclk; -#ifdef SDRAM_DEBUG serial_puts ("c_RP: "); write_hex (trp_clocks); serial_puts ("\nc_RCD: "); diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index e63625b..9f259c2 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -72,9 +72,6 @@ int board_early_init_f(void) int board_init(void) { - /* arch number of VCMA9-Board */ - gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index 86b49fb..da9e21d 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -27,6 +27,7 @@ #include <netdev.h> /*#include <mc9328.h>*/ #include <asm/arch/imx-regs.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -80,8 +81,6 @@ static u32 mc9328sid; int board_early_init_f(void) { - volatile unsigned int tmp; - mc9328sid = SIDR; GPCR = 0x000003AB; /* I/O pad driving strength */ @@ -107,8 +106,8 @@ int board_early_init_f(void) GIUS (0) &= 0xFF3FFFFF; GPR (0) &= 0xFF3FFFFF; - tmp = *(unsigned int *) (0x1500000C); - tmp = *(unsigned int *) (0x1500000C); + readl(0x1500000C); + readl(0x1500000C); SetAsynchMode (); diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index 7331efa..61a882e 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -57,7 +57,7 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips /* Get Status register */ u32 SF_SR(void) { - u32 tmp,tmp1; + u32 tmp; reg_SFCTL = CMD_PROGRAM; tmp = __REG(CONFIG_SYS_FLASH_BASE); @@ -65,7 +65,7 @@ u32 SF_SR(void) { reg_SFCTL = CMD_NORMAL; reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - tmp1 = __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); + __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); return tmp; } @@ -93,10 +93,10 @@ u8 SF_Ready(void) { /* Issue the precharge all command */ void SF_PrechargeAll(void) { - u32 tmp; - - reg_SFCTL = CMD_PREC; /* Set Precharge Command */ - tmp = __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ + /* Set Precharge Command */ + reg_SFCTL = CMD_PREC; + /* Issue Precharge All Command */ + __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); } /* set SyncFlash to normal mode */ @@ -109,13 +109,12 @@ void SF_Normal(void) { /* Erase SyncFlash */ void SF_Erase(u32 RowAddress) { - u32 tmp; reg_SFCTL = CMD_NORMAL; - tmp = __REG(RowAddress); + __REG(RowAddress); reg_SFCTL = CMD_PREC; - tmp = __REG(RowAddress); + __REG(RowAddress); reg_SFCTL = CMD_LCR; /* Set LCR mode */ __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ @@ -152,7 +151,6 @@ void SF_NvmodeWrite(void) { ulong flash_init(void) { int i, j; - u32 tmp; /* Turn on CSD1 for negating RESETSF of SyncFLash */ @@ -160,7 +158,7 @@ ulong flash_init(void) { udelay(200); reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ - tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ + __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ SF_Normal(); diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c index 5588fe7..2f1ad20 100644 --- a/board/palmld/palmld.c +++ b/board/palmld/palmld.c @@ -23,6 +23,7 @@ #include <command.h> #include <serial.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/pxa.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,10 +57,9 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c index 25186ae..4adf152 100644 --- a/board/palmtc/palmtc.c +++ b/board/palmtc/palmtc.c @@ -23,6 +23,7 @@ #include <command.h> #include <serial.h> #include <asm/io.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,10 +56,9 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c deleted file mode 100644 index 2406c5f..0000000 --- a/board/pleb2/flash.c +++ /dev/null @@ -1,814 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> -/* environment.h defines the various CONFIG_ENV_... values in terms - * of whichever ones are given in the configuration file. - */ -#include <environment.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static void flash_reset (flash_info_t * info); -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); - -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect (flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size_b; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - flash_info[0].size = size_b; - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n", - size_b); - } - - /* Do this again (was done already in flast_get_size), just - * in case we move it when remap the FLASH. - */ - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#ifdef CONFIG_SYS_FLASH_PROTECTION - /* read the hardware protection status (if any) into the - * protection array in flash_info. - */ - flash_sync_real_protect (&flash_info[0]); -#endif - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return (size_b); -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset (flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM800T) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (top boot sector type) */ - for (i = 0; i < info->sector_count - 3; i++) - info->start[i] = base + (i * sect_size); - i = info->sector_count - 1; - info->start[i--] = - base + (info->size - 0x00004000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00006000) * (sizeof (FPW) / 2); - info->start[i--] = - base + (info->size - 0x00008000) * (sizeof (FPW) / 2); - } -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - fmt = "29LV800B%s (8 Mbit, %s)\n"; - break; - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MiB */ - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets ((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset (info); - - return (info->size); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void flash_sync_real_protect (flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - case FLASH_AM800T: - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - start = get_timer(0); - last = 0; - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = - get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset (info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */ - putc ('.'); - last = now; - } - } - - flash_reset (info); /* reset to read mode */ - } - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ -#ifdef CONFIG_SYS_LITTLE_ENDIAN - for (i = 0; i < sizeof (data); i++) { - data >>= 8; - if (i < bytes || i - bytes >= left) - data += (*((uchar *) addr + i)) << 24; - else - data += (*src++) << 24; - } -#else - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } -#endif - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd (info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel (info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - - base = (FPWV *) (info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) -{ - int flag; - int res = 0; /* result, assume success */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int flash_real_protect (flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset (info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset (info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect (info); - break; - - case FLASH_AM640U: - case FLASH_AM800T: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/pleb2/pleb2.c b/board/pleb2/pleb2.c deleted file mode 100644 index 5a16cc7..0000000 --- a/board/pleb2/pleb2.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mach-types.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of Lubbock-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PLEB2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -int board_late_init(void) -{ - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index e7686ad..1cce798 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -85,9 +85,6 @@ static unsigned long regval; /* PROGRAM_SEL_DPR = LOW */ int fpga_pre_fn(int cookie) { - unsigned long reg; - - reg = in32(GPIO0_IR); /* Enable the FPGA Chain */ SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index b18c96b..d35cfed 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -122,12 +122,10 @@ static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len static int alpr_nand_dev_ready(struct mtd_info *mtd) { - volatile u_char val; - /* * Blocking read to wait for NAND to be ready */ - val = readb(&(alpr_ndfc->addr_wait)); + (void)readb(&(alpr_ndfc->addr_wait)); /* * Return always true diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 804d09c..877e8d9 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -34,6 +34,7 @@ #include <netdev.h> #include <command.h> #include <asm/io.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -83,10 +84,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/xm250/Makefile b/board/renesas/ecovec/Makefile index 6a0cca0..8fdc0c9 100644 --- a/board/xm250/Makefile +++ b/board/renesas/ecovec/Makefile @@ -1,9 +1,6 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. +# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as @@ -19,19 +16,17 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA -# -include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).o +include $(TOPDIR)/config.mk -COBJS := xm250.o flash.o +LIB = $(obj)lib$(BOARD).o -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) +COBJS := ecovec.o +SOBJS := lowlevel_init.o -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(call cmd_link_o_target, $(COBJS) $(SOBJS)) ######################################################################### diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c new file mode 100644 index 0000000..275b0ba --- /dev/null +++ b/board/renesas/ecovec/ecovec.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2009, 2011 Renesas Solutions Corp. + * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> + * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <i2c.h> +#include <netdev.h> + +/* USB power management register */ +#define UPONCR0 0xA40501D4 + +int checkboard(void) +{ + puts("BOARD: ecovec\n"); + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +static void debug_led(u8 led) +{ + /* PDGR[0-4] is debug LED */ + outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR); +} + +int board_late_init(void) +{ + u8 mac[6]; + char env_mac[17]; + int i; + + udelay(1000); + + /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/ + outw(inw(PLCR) & ~0xFFF0, PLCR); + outw(inw(PNCR) & ~0x000F, PNCR); + outw(inw(PXCR) & ~0x0FC0, PXCR); + outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB); + outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); + outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); + + debug_led(1 << 3); + + outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */ + + /* Read MAC address */ + i2c_read(0x50, 0x10, 0, mac, 6); + + /* Set MAC address */ + sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + setenv("ethaddr", env_mac); + + debug_led(0x0F); + + return 0; +} + +int board_init(void) +{ + + /* LED (PTG) */ + outw((inw(PGCR) & ~0xFF) | 0x66, PGCR); + outw((inw(HIZCRA) & ~0x02), HIZCRA); + + debug_led(1 << 0); + + /* SCIF0 (PTF, PTM) */ + outw(inw(PFCR) & ~0x30, PFCR); + outw(inw(PMCR) & ~0x0C, PMCR); + outw((inw(PSELA) & ~0x40) | 0x40, PSELA); + + debug_led(1 << 1); + + /* RMII (PTA) */ + outw((inw(PACR) & ~0x0C) | 0x04, PACR); + outb((inb(PADR) & ~0x02) | 0x02, PADR); + + debug_led(1 << 2); + + /* USB host */ + outw((inw(PBCR) & ~0x300) | 0x100, PBCR); + outb((inb(PBDR) & ~0x10) | 0x10, PBDR); + outl(inl(MSTPCR2) & 0x100000, MSTPCR2); + outw(0x0600, UPONCR0); + + debug_led(1 << 3); + + /* debug switch */ + outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); + + return 0; +} diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S new file mode 100644 index 0000000..9fc63e0 --- /dev/null +++ b/board/renesas/ecovec/lowlevel_init.S @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> + * + * board/renesas/ecovec/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> +#include <configs/ecovec.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + /* jump to 0xA0020000 if bit 1 of PVDR_A */ + mov.l PVDR_A, r1 + mov.l PVDR_D, r2 + mov.b @r1, r0 + tst r0, r2 + bt 1f + mov.l JUMP_A, r1 + jmp @r1 + nop + +1: + /* Disable watchdog */ + write16 RWTCSR_A, RWTCSR_D + + /* MMU Disable */ + write32 MMUCR_A, MMUCR_D + + /* Setup clocks */ + write32 PLLCR_A, PLLCR_D + write32 FRQCRA_A, FRQCRA_D + write32 FRQCRB_A, FRQCRB_D + + wait_timer TIMER_D + + write32 MMSELR_A, MMSELR_D + + /* Srtup BSC */ + write32 CMNCR_A, CMNCR_D + write32 CS0BCR_A, CS0BCR_D + write32 CS0WCR_A, CS0WCR_D + + wait_timer TIMER_D + + /* Setup SDRAM */ + write32 DBPDCNT0_A, DBPDCNT0_D0 + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBKIND_A, DBKIND_D + write32 DBCKECNT_A, DBCKECNT_D + + wait_timer TIMER_D + + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBMRCNT_A, DBMRCNT_D0 + write32 DBMRCNT_A, DBMRCNT_D1 + write32 DBMRCNT_A, DBMRCNT_D2 + write32 DBMRCNT_A, DBMRCNT_D3 + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBMRCNT_A, DBMRCNT_D4 + write32 DBMRCNT_A, DBMRCNT_D5 + write32 DBMRCNT_A, DBMRCNT_D6 + + wait_timer TIMER_D + + write32 DBEN_A, DBEN_D + write32 DBRFPDN1_A, DBRFPDN1_D + write32 DBRFPDN2_A, DBRFPDN2_D + write32 DBCMDCNT_A, DBCMDCNT_D0 + + + /* Dummy read */ + mov.l DUMMY_A ,r1 + synco + mov.l @r1, r0 + synco + + mov.l SDRAM_A ,r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBPDCNT0_A, DBPDCNT0_D1 + write32 DBRFPDN0_A, DBRFPDN0_D + + wait_timer TIMER_D + + write32 CCR_A, CCR_D + + stc sr, r0 + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + + .align 2 + +PVDR_A: .long PVDR +PVDR_D: .long 0x00000001 +JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR +TIMER_D: .long 64 +RWTCSR_A: .long RWTCSR +RWTCSR_D: .long 0x0000A507 +MMUCR_A: .long MMUCR +MMUCR_D: .long 0x00000004 +PLLCR_A: .long PLLCR +PLLCR_D: .long 0x00004000 +FRQCRA_A: .long FRQCRA +FRQCRA_D: .long 0x8E003508 +FRQCRB_A: .long FRQCRB +FRQCRB_D: .long 0x0 +MMSELR_A: .long MMSELR +MMSELR_D: .long 0xA5A50000 +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x00000013 +CS0BCR_A: .long CS0BCR +CS0BCR_D: .long 0x11110400 +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000440 +DBPDCNT0_A: .long DBPDCNT0 +DBPDCNT0_D0: .long 0x00000181 +DBPDCNT0_D1: .long 0x00000080 +DBCONF_A: .long DBCONF +DBCONF_D: .long 0x015B0002 +DBTR0_A: .long DBTR0 +DBTR0_D: .long 0x03061502 +DBTR1_A: .long DBTR1 +DBTR1_D: .long 0x02020102 +DBTR2_A: .long DBTR2 +DBTR2_D: .long 0x01090305 +DBTR3_A: .long DBTR3 +DBTR3_D: .long 0x00000002 +DBKIND_A: .long DBKIND +DBKIND_D: .long 0x00000005 +DBCKECNT_A: .long DBCKECNT +DBCKECNT_D: .long 0x00000001 +DBCMDCNT_A: .long DBCMDCNT +DBCMDCNT_D0:.long 0x2 +DBCMDCNT_D1:.long 0x4 +DBMRCNT_A: .long DBMRCNT +DBMRCNT_D0: .long 0x00020000 +DBMRCNT_D1: .long 0x00030000 +DBMRCNT_D2: .long 0x00010040 +DBMRCNT_D3: .long 0x00000532 +DBMRCNT_D4: .long 0x00000432 +DBMRCNT_D5: .long 0x000103C0 +DBMRCNT_D6: .long 0x00010040 +DBEN_A: .long DBEN +DBEN_D: .long 0x01 +DBRFPDN0_A: .long DBRFPDN0 +DBRFPDN1_A: .long DBRFPDN1 +DBRFPDN2_A: .long DBRFPDN2 +DBRFPDN0_D: .long 0x00010000 +DBRFPDN1_D: .long 0x00000613 +DBRFPDN2_D: .long 0x238C003A +SDRAM_A: .long 0xa8000000 +DUMMY_A: .long 0x0c400000 +CCR_A: .long CCR +CCR_D: .long 0x0000090B +SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S index ab1aa49..5090fd0 100644 --- a/board/renesas/sh7757lcr/lowlevel_init.S +++ b/board/renesas/sh7757lcr/lowlevel_init.S @@ -326,12 +326,13 @@ PC_MASK: .long 0x20000000 /* step 26 */ wait_DBCMD +#if defined(CONFIG_SH7757LCR_DDR_ECC) /* enable DDR-ECC */ write32 ECD_ECDEN_A, ECD_ECDEN_D write32 ECD_INTSR_A, ECD_INTSR_D write32 ECD_SPACER_A, ECD_SPACER_D write32 ECD_MCR_A, ECD_MCR_D - +#endif bra exit_ddr nop diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile index 0abca0d..a288b28 100644 --- a/board/ronetix/pm9261/Makefile +++ b/board/ronetix/pm9261/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # Ilko Iliev <www.ronetix.at> # diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index f659870..1a2a81d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Ilko Iliev <www.ronetix.at> * diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 871b94a..c6b582d 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> @@ -248,9 +248,6 @@ int board_init(void) 1 << ATMEL_ID_PIOC, &pmc->pcer); - /* arch number of PM9261-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9261; - /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile index 68baec7..db8de82 100644 --- a/board/ronetix/pm9263/Makefile +++ b/board/ronetix/pm9263/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # Ilko Iliev <www.ronetix.at> # diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index d6eb69f..e6883a3 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Ilko Iliev <www.ronetix.at> * diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index cfc9847..59cca87 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> @@ -164,7 +164,6 @@ void lcd_disable(void) /* Initialize the PSRAM memory */ static int pm9263_lcd_hw_psram_init(void) { - volatile uint16_t x; unsigned long csa; struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; @@ -196,14 +195,14 @@ static int pm9263_lcd_hw_psram_init(void) at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */ /* PSRAM: write BCR */ - x = readw(PSRAM_CTRL_REG); - x = readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ /* write RCR of the PSRAM */ - x = readw(PSRAM_CTRL_REG); - x = readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ /* set RCR; 0x10-async mode,0x90-page mode */ writew(0x90, PSRAM_CTRL_REG); @@ -222,8 +221,8 @@ static int pm9263_lcd_hw_psram_init(void) at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */ /* write RCR of the PSRAM */ - x = readw(PSRAM_CTRL_REG); - x = readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); + readw(PSRAM_CTRL_REG); writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ /* set RCR;0x10-async mode,0x90-page mode */ writew(0x90, PSRAM_CTRL_REG); @@ -349,9 +348,6 @@ int board_init(void) (1 << ATMEL_ID_PIOB), &pmc->pcer); - /* arch number of AT91SAM9263EK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9263; - /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/ronetix/pm9g45/Makefile b/board/ronetix/pm9g45/Makefile index e586964..bebc5b4 100644 --- a/board/ronetix/pm9g45/Makefile +++ b/board/ronetix/pm9g45/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index f3374a4..d29d076 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -5,7 +5,7 @@ * Ronetix GmbH <www.ronetix.at> * * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> + * Stelian Pop <stelian@popies.net> * Lead Tech Design <www.leadtechdesign.com> * * See file CREDITS for list of people who contributed to this @@ -139,8 +139,6 @@ int board_init(void) (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIODE), &pmc->pcer); - /* arch number of AT91SAM9M10G45EK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index c65cb96..818a7c3 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -304,7 +304,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); volatile FLASH_WORD_SIZE *addr2; - int flag, prot, sect, l_sect; + int flag, prot, sect; int i; if ((s_first < 0) || (s_first > s_last)) { @@ -335,8 +335,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) printf ("\n"); } - l_sect = -1; - /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -363,7 +361,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ } - l_sect = sect; /* * Wait for each sector to complete, it's more * reliable. According to AMD Spec, you must diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c index e5863d6..b0d3c6c 100644 --- a/board/sbc405/strataflash.c +++ b/board/sbc405/strataflash.c @@ -670,14 +670,11 @@ static ulong flash_get_size (ulong base, int banknum) static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) { - cfiptr_t ctladdr; cfiptr_t cptr; int flag; - ctladdr.cp = flash_make_addr(info, 0, 0); cptr.cp = (uchar *)dest; - /* Check if Flash is (sufficiently) erased */ switch(info->portwidth) { case FLASH_CFI_8BIT: diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e1a3ea3..26095a5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -77,12 +77,10 @@ local_bus_init(void) volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; uint clkdiv; - uint lbc_hz; sys_info_t sysinfo; get_sys_info(&sysinfo); clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index c5fe92e..98bc7df 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void) void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; + int node; #ifdef CONFIG_PCI const char *path; #endif @@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; if (node >= 0) { #ifdef CONFIG_PCI path = fdt_getprop(blob, node, "pci0", NULL); diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile index c99252c..a2951a4 100644 --- a/board/syteco/jadecpu/Makefile +++ b/board/syteco/jadecpu/Makefile @@ -3,7 +3,7 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> +# Stelian Pop <stelian@popies.net> # Lead Tech Design <www.leadtechdesign.com> # # See file CREDITS for list of people who contributed to this diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index a89ee1a..c56b195 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -128,7 +128,6 @@ int board_late_init(void) #ifdef CONFIG_FEC_MXC struct iomuxc_mux_ctl *muxctl; - struct iomuxc_pad_ctl *padctl; u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); @@ -144,7 +143,6 @@ int board_late_init(void) * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 */ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; - padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index cd5683d..436645a 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -75,7 +75,7 @@ void set_muxconf_regs(void) MUX_AM3517CRANE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/ti/am3517crane/am3517crane.h b/board/ti/am3517crane/am3517crane.h index 41db972..71335a3 100644 --- a/board/ti/am3517crane/am3517crane.h +++ b/board/ti/am3517crane/am3517crane.h @@ -30,45 +30,6 @@ const omap3_sysinfo sysinfo = { "CraneBoard", "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226 /* * IEN - Input Enable diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk deleted file mode 100644 index c6a18b5..0000000 --- a/board/ti/am3517crane/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Author: Srinath R <srinath@mistralsolutions.com> -# -# Based on logicpd/am3517evm/config.mk -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9482c5e..6a457cb 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -34,9 +34,11 @@ #include <status_led.h> #endif #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> @@ -135,6 +137,69 @@ int get_board_revision(void) return revision; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. If we can't identify it then + * we know it's an xM. To map the ID values please see nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_C4: + if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { + /* Beagleboard Rev C5, 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + } + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + if (pop_mfr == 0) { + /* 256MB DDR */ + *mcfg = MICRON_V_MCFG_200(256 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 512MB DDR */ + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } + break; + default: + /* Assume 128MB and Micron/165MHz timings to be safe */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_expansion_id * Description: This function checks for expansion board by checking I2C @@ -367,7 +432,7 @@ void set_muxconf_regs(void) MUX_BEAGLE(); } -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -476,6 +541,7 @@ int ehci_hcd_init(void) #endif /* CONFIG_USB_EHCI */ +#ifndef CONFIG_SPL_BUILD /* * This command returns the status of the user button on beagle xM * Input - none @@ -528,3 +594,4 @@ U_BOOT_CMD( "Return the status of the BeagleBoard USER button", "" ); +#endif diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk deleted file mode 100644 index cf055db..0000000 --- a/board/ti/beagle/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, <www.ti.com> -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8c43463..8497aee 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -37,6 +37,7 @@ #include <asm/gpio.h> #include <i2c.h> #include <asm/mach-types.h> +#include <linux/mtd/nand.h> #include "evm.h" #define OMAP3EVM_GPIO_ETH_RST_GEN1 64 @@ -119,6 +120,42 @@ int board_init(void) return 0; } +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. To map the ID values please see + * nand_ids.c + */ + identify_nand_chip(&pop_mfr, &pop_id); + + if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) { + /* 256MB DDR */ + *mcfg = HYNIX_V_MCFG_200(256 << 20); + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + } else { + /* 128MB DDR */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + } + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -238,7 +275,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */ -#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/pleb2/Makefile b/board/ti/omap5_evm/Makefile index bc29610..fa81d64 100644 --- a/board/pleb2/Makefile +++ b/board/ti/omap5_evm/Makefile @@ -1,6 +1,5 @@ - # -# (C) Copyright 2000-2006 +# (C) Copyright 2000, 2001, 2002 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -13,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -26,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := pleb2.o flash.o +COBJS := evm.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -34,6 +33,12 @@ OBJS := $(addprefix $(obj),$(COBJS)) $(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c new file mode 100644 index 0000000..ea0cb13 --- /dev/null +++ b/board/ti/omap5_evm/evm.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * Aneesh V <aneesh@ti.com> + * Steve Sakoman <steve@sakoman.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <twl6030.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> + +#include "mux_data.h" + +DECLARE_GLOBAL_DATA_PTR; + +const struct omap_sysinfo sysinfo = { + "Board: OMAP5430 EVM\n" +}; + +/** + * @brief board_init + * + * @return 0 + */ +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM; + gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return 0; +} + +/** + * @brief misc_init_r - Configure EVM board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ +#ifdef CONFIG_TWL6030_POWER + twl6030_init_battery_charging(); +#endif + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); +} + +void set_muxconf_regs_non_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, + sizeof(core_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, + sizeof(wkup_padconf_array_non_essential) / + sizeof(struct pad_conf_entry)); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + omap_mmc_init(1); + return 0; +} +#endif diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h new file mode 100644 index 0000000..18f4729 --- /dev/null +++ b/board/ti/omap5_evm/mux_data.h @@ -0,0 +1,275 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated, <www.ti.com> + * + * Balaji Krishnamoorthy <balajitk@ti.com> + * Aneesh V <aneesh@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EVM5430_MUX_DATA_H +#define _EVM5430_MUX_DATA_H + +#include <asm/arch/mux_omap5.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry core_padconf_array_non_essential[] = { + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48 */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (M1)}, /* dsi1_te0 */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ + {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ + {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ + {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ + {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ + {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ + {UART2_RTS, (M0)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ + {UART2_TX, (M0)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ + {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ + {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M3)}, /* gpio_27 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ +}; + +const struct pad_conf_entry wkup_padconf_array_non_essential[] = { + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ + {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ + {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ + {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ +}; + +#endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/panda/Makefile b/board/ti/panda/Makefile index ec493f5..b299e2f 100644 --- a/board/ti/panda/Makefile +++ b/board/ti/panda/Makefile @@ -25,9 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -ifndef CONFIG_SPL_BUILD COBJS := panda.o -endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index 97320cb..b4271fb 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -65,6 +65,23 @@ int misc_init_r(void) return 0; } +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + if (omap_revision() >= OMAP4460_ES1_0) + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_essential_4460, + sizeof(wkup_padconf_array_essential_4460) / + sizeof(struct pad_conf_entry)); +} + void set_muxconf_regs_non_essential(void) { do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, @@ -93,10 +110,18 @@ void set_muxconf_regs_non_essential(void) sizeof(struct pad_conf_entry)); } -#ifdef CONFIG_GENERIC_MMC +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); return 0; } #endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 83d0c3f..2970ccd 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -28,6 +28,58 @@ #include <asm/arch/mux_omap4.h> + +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ +{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ +{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ +{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ +{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ +{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ +{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ +{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { + +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ + +}; + const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ @@ -219,7 +271,7 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ diff --git a/board/ti/sdp4430/Makefile b/board/ti/sdp4430/Makefile index 806fdf4..72ad3eb 100644 --- a/board/ti/sdp4430/Makefile +++ b/board/ti/sdp4430/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS := sdp.o + ifndef CONFIG_SPL_BUILD -COBJS := sdp.o cmd_bat.o +COBJS += cmd_bat.o endif SRCS := $(COBJS:.o=.c) diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index a5ea682..9ae9e2c 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -70,6 +70,23 @@ int misc_init_r(void) return 0; } +void set_muxconf_regs_essential(void) +{ + do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, + sizeof(core_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, + sizeof(wkup_padconf_array_essential) / + sizeof(struct pad_conf_entry)); + + if (omap_revision() >= OMAP4460_ES1_0) + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_essential_4460, + sizeof(wkup_padconf_array_essential_4460) / + sizeof(struct pad_conf_entry)); +} + void set_muxconf_regs_non_essential(void) { do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential, @@ -79,9 +96,16 @@ void set_muxconf_regs_non_essential(void) do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential, sizeof(wkup_padconf_array_non_essential) / sizeof(struct pad_conf_entry)); + + if (omap_revision() < OMAP4460_ES1_0) { + do_set_mux(CONTROL_PADCONF_WKUP, + wkup_padconf_array_non_essential_4430, + sizeof(wkup_padconf_array_non_essential_4430) / + sizeof(struct pad_conf_entry)); + } } -#ifdef CONFIG_GENERIC_MMC +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -89,3 +113,11 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +/* + * get_board_rev() - get board revision + */ +u32 get_board_rev(void) +{ + return 0x20; +} diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 06efaea..0a20968 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -28,6 +28,49 @@ #include <asm/arch/mux_omap4.h> +const struct pad_conf_entry core_padconf_array_essential[] = { + +{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ +{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ +{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ +{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ +{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ +{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ +{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ +{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ +{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ +{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ +{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ +{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ +{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ +{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ +{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ +{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ +{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ +{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ +{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ +{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ +{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ +{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ +{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ +{UART3_TX_IRTX, (M0)} /* uart3_tx */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential[] = { + +{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ +{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ +{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + +}; + +const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { + +{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ + +}; + const struct pad_conf_entry core_padconf_array_non_essential[] = { {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ @@ -200,6 +243,15 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ + }; const struct pad_conf_entry wkup_padconf_array_non_essential[] = { @@ -214,7 +266,6 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 - Debug led-1 */ {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 - Debug led-2 */ {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 - Debug led-3 */ {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ @@ -224,4 +275,8 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = { {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ }; +const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = { + {PAD1_FREF_CLK4_REQ, (M3)} /* gpio_wk7 - Debug led-2 */ +}; + #endif /* _SDP4430_MUX_DATA_H */ diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff..b06aab6 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. We have either one or two banks of 128MB DDR. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + + *mr = MICRON_V_MR_165; +} diff --git a/board/colibri_pxa270/Makefile b/board/toradex/colibri_pxa270/Makefile index 854b19b..854b19b 100644 --- a/board/colibri_pxa270/Makefile +++ b/board/toradex/colibri_pxa270/Makefile diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/toradex/colibri_pxa270/colibri_pxa270.c index 191fb33..d72e5d6 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/toradex/colibri_pxa270/colibri_pxa270.c @@ -21,26 +21,20 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <asm/io.h> +#include <serial.h> DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ - -/* - * Miscelaneous platform dependent initialisations - */ -extern struct serial_device serial_ffuart_device; -extern struct serial_device serial_btuart_device; -extern struct serial_device serial_stuart_device; - -struct serial_device *default_serial_console (void) +struct serial_device *default_serial_console(void) { return &serial_ffuart_device; } -int board_init (void) +int board_init(void) { /* We have RAM, disable cache */ dcache_disable(); @@ -55,20 +49,13 @@ int board_init (void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - #ifdef CONFIG_CMD_USB int usb_board_init(void) { @@ -78,7 +65,8 @@ int usb_board_init(void) writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (UHCHR & UHCHR_FSBIR) + ; writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); @@ -126,3 +114,11 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 99f665b..1291195 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -33,6 +33,7 @@ #include <common.h> #include <asm/arch/pxa-regs.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <asm/io.h> @@ -139,10 +140,9 @@ struct serial_device *default_serial_console (void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index b5c60fd..5967055 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -23,7 +23,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifndef CONFIG_SPL_BUILD COBJS := vpac270.o +else +COBJS := onenand.o +endif SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/vpac270/onenand.c b/board/vpac270/onenand.c new file mode 100644 index 0000000..c2ae9a7 --- /dev/null +++ b/board/vpac270/onenand.c @@ -0,0 +1,65 @@ +/* + * Voipac PXA270 OneNAND SPL + * + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <onenand_uboot.h> +#include <asm/arch/pxa.h> + +void board_init_f(unsigned long unused) +{ + extern uint32_t _end; + uint32_t tmp; + + asm volatile("mov %0, pc" : "=r"(tmp)); + tmp >>= 24; + + /* The code runs from OneNAND RAM, copy SPL to SRAM and execute it. */ + if (tmp == 0) { + tmp = (uint32_t)&_end - CONFIG_SPL_TEXT_BASE; + onenand_spl_load_image(0, tmp, (void *)CONFIG_SPL_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SPL_TEXT_BASE)); + } + + /* Hereby, the code runs from (S)RAM, copy U-Boot and execute it. */ + arch_cpu_init(); + pxa2xx_dram_init(); + onenand_spl_load_image(CONFIG_SPL_ONENAND_LOAD_ADDR, + CONFIG_SPL_ONENAND_LOAD_SIZE, + (void *)CONFIG_SYS_TEXT_BASE); + asm volatile("mov pc, %0" : : "r"(CONFIG_SYS_TEXT_BASE)); + + for (;;) + ; +} + +void __attribute__((noreturn)) hang(void) +{ + for (;;) + ; +} + +void icache_disable(void) {} +void dcache_disable(void) {} diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds new file mode 100644 index 0000000..1958c2f --- /dev/null +++ b/board/vpac270/u-boot-spl.lds @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> + * on behalf of DENX Software Engineering GmbH + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = CONFIG_SPL_TEXT_BASE; + .text.0 : + { + arch/arm/cpu/pxa/start.o (.text*) + board/vpac270/libvpac270.o (.text*) + drivers/mtd/onenand/libonenand.o (.text*) + } + + + /* Start of the rest of the SPL */ + . = CONFIG_SPL_TEXT_BASE + 0x800; + + .text.1 : + { + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data) + } + + . = ALIGN(4); + + .rel.dyn : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + } + + .dynsym : { + __dynsym_start = .; + *(.dynsym) + } + + . = ALIGN(0x800); + + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 43bbdff..dfdab9b 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -21,6 +21,8 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/regs-mmc.h> +#include <asm/arch/pxa.h> #include <netdev.h> #include <serial.h> #include <asm/io.h> @@ -53,10 +55,11 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); +#ifndef CONFIG_ONENAND + pxa2xx_dram_init(); +#endif gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } @@ -72,6 +75,14 @@ void dram_init_banksize(void) #endif } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_USB int usb_board_init(void) { diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c index 6cb0aca..836c87e 100644 --- a/board/xaeniax/flash.c +++ b/board/xaeniax/flash.c @@ -220,7 +220,7 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - int flag, prot, sect; + int prot, sect; ulong type, start; int rcode = 0; @@ -255,7 +255,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { @@ -389,7 +389,6 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) { FPWV *addr = (FPWV *) dest; ulong status; - int flag; ulong start; /* Check if Flash is (sufficiently) erased */ @@ -398,7 +397,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) return (2); } /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + disable_interrupts(); *addr = (FPW) 0x00400040; /* write setup */ *addr = data; diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 40b0f3b..a4acf6c 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -30,6 +30,7 @@ #include <common.h> #include <netdev.h> +#include <asm/arch/pxa.h> DECLARE_GLOBAL_DATA_PTR; @@ -59,10 +60,9 @@ int board_late_init(void) return 0; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/board/xm250/flash.c b/board/xm250/flash.c deleted file mode 100644 index e825aba..0000000 --- a/board/xm250/flash.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/byteorder/swab.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -/* Intel-compatible flash ID */ -#define INTEL_COMPAT 0x00890089 -#define INTEL_ALT 0x00B000B0 - -/* Intel-compatible flash commands */ -#define INTEL_PROGRAM 0x00100010 -#define INTEL_ERASE 0x00200020 -#define INTEL_CLEAR 0x00500050 -#define INTEL_LOCKBIT 0x00600060 -#define INTEL_PROTECT 0x00010001 -#define INTEL_STATUS 0x00700070 -#define INTEL_READID 0x00900090 -#define INTEL_CONFIRM 0x00D000D0 -#define INTEL_RESET 0xFFFFFFFF - -/* Intel-compatible flash status bits */ -#define INTEL_FINISHED 0x00800080 -#define INTEL_OK 0x00800080 - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info); -static int write_data (flash_info_t *info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t *info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_2, &flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0] ); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - - case FLASH_28F640J3A: - printf ("28F640J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW *addr, flash_info_t *info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - - switch (value) { - - case (FPW) INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = (FPW) 0x00B000B0; /* suspend erase */ - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x00500050; /* clear status register cmd. */ - *addr = 0x00FF00FF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t *info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} - -/*----------------------------------------------------------------------- - * Set/Clear sector's lock bit, returns: - * 0 - OK - * 1 - Error (timeout, voltage problems, etc.) - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int i; - int rc = 0; - vu_long *addr = (vu_long *)(info->start[sector]); - int flag = disable_interrupts(); - ulong start; - - *addr = INTEL_CLEAR; /* Clear status register */ - if (prot) { /* Set sector lock bit */ - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - } - else { /* Clear sector lock bit */ - *addr = INTEL_LOCKBIT; /* All sectors lock bits */ - *addr = INTEL_CONFIRM; /* clear */ - } - - start = get_timer(0); - - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - - if (*addr != INTEL_OK) { - printf("Flash lock bit operation failed at %08X, CSR=%08X\n", - (uint)addr, (uint)*addr); - rc = 1; - } - - if (!rc) - info->protect[sector] = prot; - - /* - * Clear lock bit command clears all sectors lock bits, so - * we have to restore lock bits of protected sectors. - */ - if (!prot) - { - for (i = 0; i < info->sector_count; i++) - { - if (info->protect[i]) - { - start = get_timer(0); - addr = (vu_long *)(info->start[i]); - *addr = INTEL_LOCKBIT; /* Sector lock bit */ - *addr = INTEL_PROTECT; /* set */ - while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) - { - if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) - { - printf("Flash lock bit operation timed out\n"); - rc = 1; - break; - } - } - } - } - } - - if (flag) - enable_interrupts(); - - *addr = INTEL_RESET; /* Reset to read array mode */ - - return rc; -} diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c deleted file mode 100644 index 3188cf2..0000000 --- a/board/xm250/xm250.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/arch/pxa-regs.h> -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* local prototypes */ - -inline void sleep (int i); - -inline void -/**********************************************************/ -sleep (int i) -/**********************************************************/ -{ - while (i--) { - udelay (1000000); - } -} - -/* - * Miscelaneous platform dependent initialisations - */ - -int -/**********************************************************/ -board_init (void) -/**********************************************************/ -{ - /* We have RAM, disable cache */ - dcache_disable(); - icache_disable(); - - /* arch number of MicroSys XM250 */ - gd->bd->bi_arch_number = MACH_TYPE_XM250; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xa0000100; - - return 0; -} - -extern void pxa_dram_init(void); -int dram_init(void) -{ - pxa_dram_init(); - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 18cb85f..272e59b 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -40,7 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern env_t *env_ptr; -extern uchar default_environment[]; ulong flash_get_size(ulong base, int banknum); void env_crc_update(void); diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 9e6a0d5..b093c2f 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -27,6 +27,7 @@ #include <command.h> #include <serial.h> #include <asm/arch/hardware.h> +#include <asm/arch/pxa.h> #include <spi.h> #include <asm/io.h> @@ -65,10 +66,9 @@ struct serial_device *default_serial_console (void) return &serial_stuart_device; } -extern void pxa_dram_init(void); int dram_init(void) { - pxa_dram_init(); + pxa2xx_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } |