20 files changed, 228 insertions, 83 deletions

diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c
index 776226f..e98244b 100644
--- a/board/BuS/eb_cpux9k2/cpux9k2.c
+++ b/board/BuS/eb_cpux9k2/cpux9k2.c
@@ -267,9 +267,9 @@ int drv_video_init(void)
 		display_height = 256;
 	printf("%ld x %ld pixel matrix\n", display_width, display_height);
 
-	/* RWH = 7 | RWS =7  | TDF = 15 | NWS = 0x7F */
-	csr =	AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
-		AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
+	/* RWH = 2 | RWS =2  | TDF = 4 | NWS = 0x6 */
+	csr =	AT91_SMC_CSR_RWHOLD(2) | AT91_SMC_CSR_RWSETUP(2) |
+		AT91_SMC_CSR_TDF(4) | AT91_SMC_CSR_NWS(6) |
 		AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
 		AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
 	writel(csr, &mc->smc.csr[2]);
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index ae408bc..06028aa 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void)
 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
 	/* NAND flash on D16 */
 	csa |= AT91_MATRIX_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
 	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index a0a4d1d..93f12ea 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -78,7 +78,7 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0, SD slot, with 4-bit bus */
-	tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
 	return 0;
 }
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts
index 9faebd8..bb3851b 100644
--- a/board/avionic-design/dts/tegra20-tec.dts
+++ b/board/avionic-design/dts/tegra20-tec.dts
@@ -55,4 +55,15 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index cd684f2..0f8f167 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -70,11 +70,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init eMMC\n");
 	/* init dev 0, eMMC chip, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, -1, -1);
+	tegra_mmc_init(0, 4, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 3, SD slot, with 4-bit bus */
-	tegra20_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
+	tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
 
 	return 0;
 }
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 5dae15b..893cca8 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -69,10 +69,10 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
-	tegra20_mmc_init(0, 4, -1, GPIO_PP1);
+	tegra_mmc_init(0, 4, -1, GPIO_PP1);
 
 	/* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
-	tegra20_mmc_init(3, 4, -1, -1);
+	tegra_mmc_init(3, 4, -1, -1);
 
 	return 0;
 }
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 7ab2040..afe832a 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-const struct tegra20_sysinfo sysinfo = {
-	CONFIG_TEGRA20_BOARD_STRING
+const struct tegra_sysinfo sysinfo = {
+	CONFIG_TEGRA_BOARD_STRING
 };
 
 #ifndef CONFIG_SPL_BUILD
@@ -79,7 +79,7 @@ void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
 static void power_det_init(void)
 {
 #if defined(CONFIG_TEGRA20)
-	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+	struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
 	/* turn off power detects */
 	writel(0, &pmc->pmc_pwr_det_latch);
@@ -132,7 +132,7 @@ int board_init(void)
 	board_usb_init(gd->fdt_blob);
 #endif
 
-#ifdef CONFIG_TEGRA20_LP0
+#ifdef CONFIG_TEGRA_LP0
 	/* save Sdram params to PMC 2, 4, and 24 for WB0 */
 	warmboot_save_sdram_params();
 
diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts
index c351954..ca5facb 100644
--- a/board/nvidia/dts/tegra20-harmony.dts
+++ b/board/nvidia/dts/tegra20-harmony.dts
@@ -54,4 +54,14 @@
 	usb@c5004000 {
 		status = "disabled";
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 23 0>;		/* PC7 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts
index 3352539..25a63a0 100644
--- a/board/nvidia/dts/tegra20-seaboard.dts
+++ b/board/nvidia/dts/tegra20-seaboard.dts
@@ -153,4 +153,14 @@
 			0x1f04008a>;
 		linux,fn-keymap = <0x05040002>;
 	};
+
+	nand-controller@70008000 {
+		nvidia,wp-gpios = <&gpio 59 0>;		/* PH3 */
+		nvidia,width = <8>;
+		nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+		nand@0 {
+			reg = <0>;
+			compatible = "hynix,hy27uf4g2b", "nand-flash";
+		};
+	};
 };
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index b6efa1c..88b9dcf 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 44977c7..b4a811d 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -73,11 +73,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init SD slot J26\n");
 	/* init dev 0, SD slot J26, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+	tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
 
 	debug("board_mmc_init: init SD slot J5\n");
 	/* init dev 2, SD slot J5, with 4-bit bus */
-	tegra20_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
+	tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
 
 	return 0;
 }
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index b6efa1c..88b9dcf 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 3298a6b..667f60a 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -81,11 +81,11 @@ int board_mmc_init(bd_t *bd)
 	debug("board_mmc_init: init eMMC\n");
 	/* init dev 0, eMMC chip, with 4-bit bus */
 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
-	tegra20_mmc_init(0, 4, -1, -1);
+	tegra_mmc_init(0, 4, -1, -1);
 
 	debug("board_mmc_init: init SD slot\n");
 	/* init dev 1, SD slot, with 4-bit bus */
-	tegra20_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
+	tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
 
 	return 0;
 }
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index e3b7435..147d0bc 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -24,9 +24,7 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common $(obj)../seaboard)
-endif
+$(shell mkdir -p $(obj)../seaboard)
 
 LIB	= $(obj)lib$(BOARD).o
 
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/whistler/Makefile
index a910577..913f1ce 100644
--- a/board/nvidia/whistler/Makefile
+++ b/board/nvidia/whistler/Makefile
@@ -24,10 +24,6 @@
 
 include $(TOPDIR)/config.mk
 
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
index c0a114d..598b2e5 100644
--- a/board/nvidia/whistler/whistler.c
+++ b/board/nvidia/whistler/whistler.c
@@ -81,10 +81,10 @@ int board_mmc_init(bd_t *bd)
 	pin_mux_mmc();
 
 	/* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
-	tegra20_mmc_init(0, 8, -1, -1);
+	tegra_mmc_init(0, 8, -1, -1);
 
 	/* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
-	tegra20_mmc_init(1, 8, -1, -1);
+	tegra_mmc_init(1, 8, -1, -1);
 
 	return 0;
 }
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
index 5e07bf8..06df0af 100644
--- a/board/taskit/stamp9g20/stamp9g20.c
+++ b/board/taskit/stamp9g20/stamp9g20.c
@@ -159,15 +159,28 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int board_init(void)
+int board_postclk_init(void)
 {
-	/* Adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	/*
+	 * Initialize the serial interface here, because be need a running
+	 * timer to set PC9 to high and wait for some time to enable the
+	 * level converter of the RS232 interface on the PortuxG20 board.
+	 */
 
-	/* Enable the serial interface */
+#ifdef CONFIG_PORTUXG20
 	at91_set_gpio_output(AT91_PIN_PC9, 1);
+	mdelay(1);
+#endif
 	at91_seriald_hw_init();
 
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
 	stamp9G20_nand_hw_init();
 #ifdef CONFIG_MACB
 	stamp9G20_macb_hw_init();
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
index c2b10ac..7429e93 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -100,8 +100,18 @@ int board_init(void)
 
 int misc_init_r(void)
 {
+	char *eth_addr;
+
 	dieid_num_r();
 
+	eth_addr = getenv("ethaddr");
+	if (eth_addr)
+		return 0;
+
+#ifndef CONFIG_SPL_BUILD
+	TAM3517_READ_MAC_FROM_EEPROM;
+#endif
+
 	return 0;
 }
 
diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c
index 9fbaedd..b8ad447 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.c
+++ b/board/teejet/mt_ventoux/mt_ventoux.c
@@ -21,13 +21,17 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <malloc.h>
 #include <fpga.h>
+#include <video_fb.h>
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_gpio.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/dss.h>
+#include <asm/arch/clocks.h>
 #include <i2c.h>
 #include <spartan3.h>
 #include <asm/gpio.h>
@@ -39,6 +43,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define BUZZER		140
+#define SPEAKER		141
+
 #ifndef CONFIG_FPGA
 #error "The Teejet mt_ventoux must have CONFIG_FPGA enabled"
 #endif
@@ -50,6 +57,42 @@ DECLARE_GLOBAL_DATA_PTR;
 #define FPGA_INIT	119
 #define FPGA_DONE	154
 
+#define LCD_PWR		138
+#define LCD_PON_PIN	139
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+static struct {
+	u32 xres;
+	u32 yres;
+} panel_resolution[] = {
+	{ 480, 272 },
+	{ 800, 480 }
+};
+
+static struct panel_config lcd_cfg[] = {
+	{
+	.timing_h       = PANEL_TIMING_H(4, 8, 41),
+	.timing_v       = PANEL_TIMING_V(2, 4, 10),
+	.pol_freq       = 0x00000000, /* Pol Freq */
+	.divisor        = 0x0001000d, /* 33Mhz Pixel Clock */
+	.panel_type     = 0x01, /* TFT */
+	.data_lines     = 0x03, /* 24 Bit RGB */
+	.load_mode      = 0x02, /* Frame Mode */
+	.panel_color	= 0,
+	},
+	{
+	.timing_h       = PANEL_TIMING_H(20, 192, 4),
+	.timing_v       = PANEL_TIMING_V(2, 20, 10),
+	.pol_freq       = 0x00004000, /* Pol Freq */
+	.divisor        = 0x0001000E, /* 36Mhz Pixel Clock */
+	.panel_type     = 0x01, /* TFT */
+	.data_lines     = 0x03, /* 24 Bit RGB */
+	.load_mode      = 0x02, /* Frame Mode */
+	.panel_color	= 0,
+	}
+};
+#endif
+
 /* Timing definitions for FPGA */
 static const u32 gpmc_fpga[] = {
 	FPGA_GPMC_CONFIG1,
@@ -193,6 +236,33 @@ int board_init(void)
 
 	mt_ventoux_init_fpga();
 
+	/* GPIO_140: speaker #mute */
+	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4))
+	/* GPIO_141: Buzz Hi */
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4))
+
+	/* Turning off the buzzer */
+	gpio_request(BUZZER, "BUZZER_MUTE");
+	gpio_request(SPEAKER, "SPEAKER");
+	gpio_direction_output(BUZZER, 0);
+	gpio_direction_output(SPEAKER, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *eth_addr;
+
+	dieid_num_r();
+
+	eth_addr = getenv("ethaddr");
+	if (eth_addr)
+		return 0;
+
+#ifndef CONFIG_SPL_BUILD
+	TAM3517_READ_MAC_FROM_EEPROM;
+#endif
 	return 0;
 }
 
@@ -224,3 +294,46 @@ int board_mmc_init(bd_t *bis)
 	return omap_mmc_init(0, 0, 0);
 }
 #endif
+
+#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
+int board_video_init(void)
+{
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct panel_config *panel = &lcd_cfg[0];
+	char *s;
+	u32 index = 0;
+
+	void *fb;
+
+	fb = (void *)0x88000000;
+
+	s = getenv("panel");
+	if (s) {
+		index = simple_strtoul(s, NULL, 10);
+		if (index < ARRAY_SIZE(lcd_cfg))
+			panel = &lcd_cfg[index];
+		else
+			return 0;
+	}
+
+	panel->frame_buffer = fb;
+	printf("Panel: %dx%d\n", panel_resolution[index].xres,
+		panel_resolution[index].yres);
+	panel->lcd_size = (panel_resolution[index].yres - 1) << 16 |
+		(panel_resolution[index].xres - 1);
+
+	gpio_request(LCD_PWR, "LCD Power");
+	gpio_request(LCD_PON_PIN, "LCD Pon");
+	gpio_direction_output(LCD_PWR, 0);
+	gpio_direction_output(LCD_PON_PIN, 1);
+
+
+	setbits_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
+	setbits_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
+
+	omap3_dss_panel_config(panel);
+	omap3_dss_enable();
+
+	return 0;
+}
+#endif
diff --git a/board/teejet/mt_ventoux/mt_ventoux.h b/board/teejet/mt_ventoux/mt_ventoux.h
index 9b2e43e..1cd7ec2 100644
--- a/board/teejet/mt_ventoux/mt_ventoux.h
+++ b/board/teejet/mt_ventoux/mt_ventoux.h
@@ -142,7 +142,8 @@ const omap3_sysinfo sysinfo = {
 			/*GPIO_62: FPGA_RESET */ \
 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) \
-	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/ \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) \
+			/* GPIO_64*/ \
 	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)) \
 	/* DSS */\
 	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
@@ -174,26 +175,6 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
 	/* CAMERA */\
-	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
-	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
-	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
 	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
@@ -209,6 +190,7 @@ const omap3_sysinfo sysinfo = {
 			/* GPIO_126: CardDetect */\
 	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+			/*GPIO_128 */ \
 	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
 	\
 	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN | M0)) /*MMC2_CLK*/\
@@ -221,7 +203,7 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MMC2_DAT5),		(IDIS  | PTU | EN  | M4)) \
 	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | EN  | M4)) \
 			/* GPIO_138: LCD_ENVD */\
-	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTD | EN  | M4)) \
 			/* GPIO_139: LCD_PON */\
 	/* McBSP */\
 	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
@@ -241,16 +223,12 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCBSP2_DX),		(IEN | PTD | EN | M4)) \
 			/* GPIO_119: FPGA_INIT */ \
 	\
-	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4)) \
-			/* GPIO_140: speaker #mute */\
-	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4)) \
-			/* GPIO_141: Buzz Hi */\
 	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN | M4)) \
 	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN | M4)) \
 	\
 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN | PTD | DIS | M4)) \
 			/*GPIO_152: Ignition Sense */ \
-	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) \
+	MUX_VAL(CP(MCBSP4_DR),		(IEN | PTD | DIS | M4)) \
 			/*GPIO_153: Power Button Sense */ \
 	MUX_VAL(CP(MCBSP4_DX),		(IEN | PTU | DIS | M4)) \
 			/* GPIO_154: FPGA_DONE */ \
@@ -264,10 +242,14 @@ const omap3_sysinfo sysinfo = {
 			/* GPIO_150: USB status 1 */\
 	\
 	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
-	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M2)) \
+			/* gpt9_pwm */\
+	MUX_VAL(CP(UART2_RTS),		(IEN | PTD | DIS | M2)) \
+			/* gpt10_pwm */\
+	MUX_VAL(CP(UART2_TX),		(IEN | PTD | DIS | M2)) \
+			/* gpt8_pwm */\
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M2)) \
+			/* gpt11_pwm */\
 	\
 	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS  | PTD | DIS | M4)) \
 			/*GPIO_163 : TS_PENIRQ*/ \
@@ -299,22 +281,24 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
 	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M0)) \
 	/* CCDC */\
-	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M4)) \
+			/* GPIO94 */\
 	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO95: #Enable Output */\
-	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
-	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M4)) \
 	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO 99: #SOM_PWR_OFF */\
-	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M4)) \
 	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M4)) \
 			/* GPIO_100: #power out */\
-	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M4)) \
+			/* GPIO_102 */\
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M4)) \
 	/* RMII */\
 	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
 	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
@@ -363,7 +347,8 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
 	\
 	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
-	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IDIS | PTD | DIS | M4)) \
+			/* gpio_10 */\
 	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
 	/* JTAG */\
 	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
@@ -387,12 +372,15 @@ const omap3_sysinfo sysinfo = {
 	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M3)) \
 	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)) \
 	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)) \
-	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IDIS | PTD | EN  | M4)) \
+					/* gpio_24 */\
 	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) \
-	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M3)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M4)) \
+					/* gpio_26 */\
 	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M3)) \
-	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M3)) \
-	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M3)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
+					/* gpio_29 */\
 	/* Die to Die */\
 	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
 	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \