diff options
Diffstat (limited to 'board')
49 files changed, 1093 insertions, 504 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 803995a..7c98920 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -277,7 +277,7 @@ int board_early_init_f(void) } #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; /*----------------------------------------------------------------------------+ diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index 35cb655..433429b 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -32,3 +32,6 @@ endif ifeq ($(dbcr),1) PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 endif + +# legacy nand support +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 6e03b72..1dc635f 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -27,5 +27,8 @@ # Reserve 320 kB for Monitor TEXT_BASE = 0xFFFB0000 -# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) +# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined) BOARDLIBS = drivers/nand/libnand.a + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c index 16c67cd..40a827c 100644 --- a/board/dave/PPChameleonEVB/nand.c +++ b/board/dave/PPChameleonEVB/nand.c @@ -22,9 +22,8 @@ #include <common.h> + #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#ifdef CONFIG_NEW_NAND_CODE -/* new NAND handling */ #include <nand.h> @@ -82,7 +81,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) break; } - if (in32(GPIO0_IR) & rb_gpio_pin) + if (in32(GPIO0_IR) & rb_gpio_pin) return 1; return 0; } @@ -90,7 +89,7 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) /* * Board-specific NAND initialization. The following members of the - * argument are board-specific (per include/linux/mtd/nand_new.h): + * argument are board-specific (per include/linux/mtd/nand.h): * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device * - hwcontrol: hardwarespecific function for accesing control-lines @@ -115,33 +114,4 @@ void board_nand_init(struct nand_chip *nand) nand->chip_delay = NAND_BIG_DELAY_US; nand->options = NAND_SAMSUNG_LP_OPTIONS; } - -#else - -/* old NAND handling */ -extern ulong -nand_probe(ulong physadr); - -void -nand_init(void) -{ - ulong totlen = 0; - -/* - The HI model is equipped with a large block NAND chip not supported yet - by U-Boot - (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) -*/ - -#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); -#endif /* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */ - - debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE); - totlen += nand_probe (CFG_NAND1_BASE); - - printf ("%3lu MB\n", totlen >>20); -} -#endif -#endif +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ diff --git a/board/delta/config.mk b/board/delta/config.mk index b269b6e..9564625 100644 --- a/board/delta/config.mk +++ b/board/delta/config.mk @@ -6,4 +6,3 @@ TEXT_BASE = 0xa3008000 # Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) BOARDLIBS = drivers/nand/libnand.a - diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S index 66e7575..498cf7f 100644 --- a/board/delta/lowlevel_init.S +++ b/board/delta/lowlevel_init.S @@ -16,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -32,33 +32,33 @@ DRAM_SIZE: .long CFG_DRAM_SIZE /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm .macro wait time - ldr r2, =OSCR - mov r3, #0 - str r3, [r2] + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] 0: - ldr r3, [r2] - cmp r3, \time - bls 0b + ldr r3, [r2] + cmp r3, \time + bls 0b .endm /* - * Memory setup + * Memory setup */ .globl lowlevel_init lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ - mov r10, lr - - /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ + mov r10, lr + + /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ ldr r0, =GPIO97 ldr r1, =0x801 str r1, [r0] @@ -66,24 +66,24 @@ lowlevel_init: ldr r0, =GPIO98 ldr r1, =0x801 str r1, [r0] - - /* tebrandt - ASCR, clear the RDH bit */ - ldr r0, =ASCR - ldr r1, [r0] - bic r1, r1, #0x80000000 - str r1, [r0] - + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + /* ---------------------------------------------------------------- */ - /* Enable memory interface */ + /* Enable memory interface */ /* ---------------------------------------------------------------- */ /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ /* ---------------------------------------------------------------- */ -; wait #300 - +; wait #300 + mem_init: #define NEW_SDRAM_INIT 1 @@ -99,11 +99,11 @@ mem_init: /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ ldr r0, =MDCNFG ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) - /* ldr r1, =0x80000403 */ + /* ldr r1, =0x80000403 */ str r1, [r0] ldr r1, [r0] /* delay until written */ - /* 3. wait nop power up waiting period (200ms) + /* 3. wait nop power up waiting period (200ms) * optimization: Steps 4+6 can be done during this */ wait #300 @@ -127,7 +127,7 @@ mem_init: ldr r1, =0x60000033 str r1, [r0] wait #300 - + /* Configure MDREFR */ ldr r0, =MDREFR ldr r1, =0x00000006 @@ -142,48 +142,48 @@ mem_init: #else /* NEW_SDRAM_INIT */ - + /* configure the MEMCLKCFG register */ - ldr r1, =MEMCLKCFG - ldr r2, =0x00010001 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[0] to data flash SRAM mode */ - ldr r1, =CSADRCFG0 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[1] to data flash SRAM mode */ - ldr r1, =CSADRCFG1 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set MSC 0 register for SRAM memory */ - ldr r1, =MSC0 - ldr r2, =0x11191119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[2] to data flash SRAM mode */ - ldr r1, =CSADRCFG2 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[3] to VLIO mode */ - ldr r1, =CSADRCFG3 - ldr r2, =0x0032080B - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN /* set MSC 1 register for VLIO memory */ - ldr r1, =MSC1 - ldr r2, =0x123C1119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN #if 0 /* This does not work in Zylonite. -SC */ @@ -240,11 +240,11 @@ mem_init: ldr r2, [r1] /* Hardware DDR Read-Strobe Delay Calibration */ - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] wait #5 - ldr r1, [r0] + ldr r1, [r0] /* Here we assume the hardware calibration alwasy be successful. -SC */ /* Set DMCEN bit in MDCNFG Register */ @@ -254,20 +254,20 @@ mem_init: str r1, [r0] #endif /* NEW_SDRAM_INIT */ - + #ifndef CFG_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 - mov r2, #0 + mov r2, #0 mov r3, #0 - mov r4, #0 + mov r4, #0 mov r5, #0 - mov r6, #0 + mov r6, #0 mov r7, #0 -10: /* fastScrubLoop */ +10: /* fastScrubLoop */ subs r9, r9, #32 /* 8 words/line */ stmia r8!, {r0-r7} beq 15f @@ -281,25 +281,25 @@ mem_init: /* Disable software and data breakpoints */ mov r0, #0 - mcr p15,0,r0,c14,c8,0 // ibcr0 - mcr p15,0,r0,c14,c9,0 // ibcr1 - mcr p15,0,r0,c14,c4,0 // dbcon + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ /* Enable all debug functionality */ mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 // dcsr + mcr p14,0,r0,c10,c0,0 /* dcsr */ endlowlevel_init: - mov pc, lr + mov pc, lr /* @******************************************************************************** @ DDR calibration -@ +@ @ This function is used to calibrate DQS delay lines. -@ Monahans supports three ways to do it. One is software +@ Monahans supports three ways to do it. One is software @ calibration. Two is hardware calibration. Three is hybrid @ calibration. @ @@ -308,15 +308,15 @@ endlowlevel_init: ddr_calibration: @ Case 1: Write the correct delay value once - @ Configure DDR_SCAL Register - ldr r0, =DDR_SCAL @ DDR_SCAL -q ldr r1, =0xaf2f2f2f - str r1, [r0] - ldr r1, [r0] + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] */ /* @ Case 2: Software Calibration @ Write test pattern to memory - ldr r5, =0x0faf0faf @ Data Pattern + ldr r5, =0x0faf0faf @ Data Pattern ldr r4, =0xa0000000 @ DDR ram str r5, [r4] @@ -328,11 +328,11 @@ ddr_loop1: cmp r1, =0xf ble end_loop mov r3, r1 - mov r0, r1, lsl #30 + mov r0, r1, lsl #30 orr r3, r3, r0 - mov r0, r1, lsl #22 + mov r0, r1, lsl #22 orr r3, r3, r0 - mov r0, r1, lsl #14 + mov r0, r1, lsl #14 orr r3, r3, r0 orr r3, r3, =0x80000000 ldr r2, =DDR_SCAL @@ -346,16 +346,16 @@ ddr_loop2: add r1, r1, =0x1 cmp r1, =0xf ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] ldr r2, [r4] cmp r2, r5 @@ -364,22 +364,22 @@ ddr_loop2: add r3, r6, r7 lsr r3, r3, =0x1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + end_loop: @ Case 3: Hardware Calibratoin - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] wait #5 - ldr r1, [r0] - mov pc, lr + ldr r1, [r0] + mov pc, lr */ diff --git a/board/delta/nand.c b/board/delta/nand.c index 5876727..50def59 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -95,7 +95,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) unsigned long rest = len & 0x3; unsigned long *long_buf; int i; - + DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf)); if(bytes_multi) { for(i=0; i<bytes_multi; i+=4) { @@ -110,7 +110,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) } -/* +/* * These functions are quite problematic for the DFC. Luckily they are * not used in the current nand code, except for nand_command, which * we've defined our own anyway. The problem is, that we always need @@ -152,7 +152,7 @@ static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len) *long_buf = NDDB; } } - + /* ...then the rest */ if(rest) { unsigned long rest_data = NDDB; @@ -176,7 +176,7 @@ static u16 dfc_read_word(struct mtd_info *mtd) static unsigned long read_buf = 0; static int bytes_read = -1; -/* +/* * read a byte from NDDB Because we can only read 4 bytes from NDDB at * a time, we buffer the remaining bytes. The buffer is reset when a * new command is sent to the chip. @@ -196,7 +196,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) if(bytes_read < 0) { read_buf = NDDB; - dummy = NDDB; + dummy = NDDB; bytes_read = 0; } byte = (unsigned char) (read_buf>>(8 * bytes_read++)); @@ -211,7 +211,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) static unsigned long get_delta(unsigned long start) { unsigned long cur = OSCR; - + if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); else @@ -239,14 +239,14 @@ static void dfc_clear_nddb() static unsigned long dfc_wait_event(unsigned long event) { unsigned long ndsr, timeout, start = OSCR; - + if(!event) return 0xff000000; else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; else timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; - + while(1) { ndsr = NDSR; if(ndsr & event) { @@ -257,7 +257,7 @@ static unsigned long dfc_wait_event(unsigned long event) DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event); return 0xff000000; } - + } return ndsr; } @@ -271,13 +271,13 @@ static void dfc_new_cmd() while(retry++ <= CFG_NAND_SENDCMD_RETRY) { /* Clear NDSR */ NDSR = 0xFFF; - + /* set NDCR[NDRUN] */ if(!(NDCR & NDCR_ND_RUN)) NDCR |= NDCR_ND_RUN; - + status = dfc_wait_event(NDSR_WRCMDREQ); - + if(status & NDSR_WRCMDREQ) return; @@ -303,7 +303,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) } else if(state == FL_ERASING) { event = NDSR_CS0_CMDD | NDSR_CS0_BBD; } - + ndsr = dfc_wait_event(event); if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000)) @@ -312,7 +312,7 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) } /* cmdfunc send commands to the DFC */ -static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, +static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, int column, int page_addr) { /* register struct nand_chip *this = mtd->priv; */ @@ -404,7 +404,7 @@ static void dfc_gpio_init() /* no idea what is done here, see zylonite.c */ GPIO4 = 0x1; - + DF_ALE_WE1 = 0x00000001; DF_ALE_WE2 = 0x00000001; DF_nCS0 = 0x00000001; @@ -464,10 +464,10 @@ void board_nand_init(struct nand_chip *nand) CKENA |= (CKENA_4_NAND | CKENA_9_SMC); #undef CFG_TIMING_TIGHT -#ifndef CFG_TIMING_TIGHT - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), +#ifndef CFG_TIMING_TIGHT + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), DFC_MAX_tCH); - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), DFC_MAX_tCS); tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1), DFC_MAX_tWH); @@ -485,9 +485,9 @@ void board_nand_init(struct nand_chip *nand) DFC_MAX_tAR); #else /* this is the tight timing */ - tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), + tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)), DFC_MAX_tCH); - tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), + tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)), DFC_MAX_tCS); tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)), DFC_MAX_tWH); @@ -523,13 +523,11 @@ void board_nand_init(struct nand_chip *nand) (tRP_high << 6) | (tRH << 3) | (tRP << 0); - + NDTR1CS0 = (tR << 16) | (tWHR << 4) | (tAR << 0); - - /* If it doesn't work (unlikely) think about: * - ecc enable * - chip select don't care @@ -544,7 +542,7 @@ void board_nand_init(struct nand_chip *nand) * - ND_RDY : clears command buffer */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - + NDCR = (NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ @@ -557,17 +555,17 @@ void board_nand_init(struct nand_chip *nand) NDCR_CS1_CMDDM | NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */ NDCR_CS1_BBDM | - NDCR_DBERRM | /* double bit error ir masked */ + NDCR_DBERRM | /* double bit error ir masked */ NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ NDCR_WRCMDREQM); /* write command request ir masked */ - + /* wait 10 us due to cmd buffer clear reset */ /* wait(10); */ - - + + nand->hwcontrol = dfc_hwcontrol; /* nand->dev_ready = dfc_device_ready; */ nand->eccmode = NAND_ECC_SOFT; diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 03ae7fd..84fc3a0 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/ash405/config.mk +++ b/board/esd/ash405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index e4cfe14..e283a92 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -238,7 +238,7 @@ U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk index 5c3c01c..0c56c40 100644 --- a/board/esd/cms700/config.mk +++ b/board/esd/cms700/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 1decc0e..cad8211 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -23,10 +23,15 @@ */ #include <common.h> + +#ifndef CFG_NAND_LEGACY +#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#endif + #include <command.h> #include <image.h> #include <asm/byteorder.h> -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> #include <fat.h> #include "auto_update.h" @@ -76,9 +81,9 @@ extern block_dev_desc_t *get_dev (char*, int); #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); -extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; @@ -259,9 +264,9 @@ int au_do_update(int i, long sz) } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) printf("Updating NAND FLASH with image %s\n", au_image[i].name); - debug ("nand_erase(%lx, %lx);\n", start, end); - rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); - debug ("nand_erase returned %x\n", rc); + debug ("nand_legacy_erase(%lx, %lx);\n", start, end); + rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -286,10 +291,10 @@ int au_do_update(int i, long sz) rc = flash_write((char *)addr, start, nbytes); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, + debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); + rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); #endif } if (rc != 0) { @@ -304,7 +309,7 @@ int au_do_update(int i, long sz) rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { #if (CONFIG_COMMANDS & CFG_CMD_NAND) - rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, + rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, start, nbytes, (size_t *)&total, (uchar *)addr); rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); #endif diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index 3478f82..bf796ff 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -120,4 +120,3 @@ U_BOOT_CMD( ); #endif - diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 2800420..1a27ca0 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -36,9 +36,9 @@ int board_early_init_f (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); - /* set output pins to high */ + /* set output pins to high */ out32(GPIO0_OR, CFG_EEPROM_WP); - /* setup for output (LED=off) */ + /* setup for output (LED=off) */ out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); /* diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 0be45c7..ceff4c4 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -38,3 +38,6 @@ TEXT_BASE = 0xFFFD0000 endif endif endif + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index fd0f904..dbed597 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -378,7 +378,6 @@ int misc_init_r () CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[3]); - } return 0; } diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index 37c7150..c335ebf 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -46,8 +46,8 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = { #ifdef CONFIG_USE_CPCIDVI typedef struct { - unsigned int base; - unsigned int init; + unsigned int base; + unsigned int init; } GT_CPCIDVI_ROM_T; static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0}; @@ -133,20 +133,20 @@ static const unsigned int pci_p2p_configuration[] = { /******************************************************************** * pciWriteConfigReg - Write to a PCI configuration register -* - Make sure the GT is configured as a master before writing -* to another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before writing +* to another device on the PCI. +* - The function takes care of Big/Little endian conversion. * * * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec -* (or any other PCI device spec) -* pciDevNum: The device number needs to be addressed. +* (or any other PCI device spec) +* pciDevNum: The device number needs to be addressed. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, @@ -180,20 +180,20 @@ void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciReadConfigReg - Read from a PCI0 configuration register -* - Make sure the GT is configured as a master before reading -* from another device on the PCI. -* - The function takes care of Big/Little endian conversion. +* - Make sure the GT is configured as a master before reading +* from another device on the PCI. +* - The function takes care of Big/Little endian conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec) -* pciDevNum: The device number needs to be addressed. +* spec) +* pciDevNum: The device number needs to be addressed. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|00| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, @@ -228,21 +228,21 @@ unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset, /******************************************************************** * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where -* the agent is placed on another Bus. For more -* information read P2P in the PCI spec. +* the agent is placed on another Bus. For more +* information read P2P in the PCI spec. * * Inputs: unsigned int regOffset - The register offset as it apears in the -* GT spec (or any other PCI device spec). -* unsigned int pciDevNum - The device number needs to be addressed. -* unsigned int busNum - On which bus does the Target agent connect -* to. -* unsigned int data - data to be written. +* GT spec (or any other PCI device spec). +* unsigned int pciDevNum - The device number needs to be addressed. +* unsigned int busNum - On which bus does the Target agent connect +* to. +* unsigned int data - data to be written. * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * * The configuration Address is configure as type-I (bits[1:0] = '01') due to * PCI spec referring to P2P. @@ -273,23 +273,23 @@ void pciOverBridgeWriteConfigReg (PCI_HOST host, /******************************************************************** * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where -* the agent target locate on another PCI bus. -* - Make sure the GT is configured as a master -* before reading from another device on the PCI. -* - The function takes care of Big/Little endian -* conversion. +* the agent target locate on another PCI bus. +* - Make sure the GT is configured as a master +* before reading from another device on the PCI. +* - The function takes care of Big/Little endian +* conversion. * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI -* spec). (configuration register offset.) -* pciDevNum: The device number needs to be addressed. -* busNum: the Bus number where the agent is place. +* spec). (configuration register offset.) +* pciDevNum: The device number needs to be addressed. +* busNum: the Bus number where the agent is place. * RETURNS: data , if the data == 0xffffffff check the master abort bit in the -* cause register to make sure the data is valid +* cause register to make sure the data is valid * * Configuration Address 0xCF8: * -* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number +* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number * |congif|Reserved| Bus |Device|Function|Register|01| -* |Enable| |Number|Number| Number | Number | | <=field Name +* |Enable| |Number|Number| Number | Number | | <=field Name * *********************************************************************/ unsigned int pciOverBridgeReadConfigReg (PCI_HOST host, @@ -393,7 +393,7 @@ static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region) /******************************************************************** * pciGetBaseAddress - Gets the base address of a PCI. -* - If the PCI size is 0 then this base address has no meaning!!! +* - If the PCI size is 0 then this base address has no meaning!!! * * * INPUT: Bus, Region - The bus and region we ask for its base address. @@ -501,13 +501,13 @@ void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank, /******************************************************************** * pciSetRegionFeatures - This function modifys one of the 8 regions with -* feature bits given as an input. -* - Be advised to check the spec before modifying them. +* feature bits given as an input. +* - Be advised to check the spec before modifying them. * Inputs: PCI_PROTECT_REGION region - one of the eight regions. -* unsigned int features - See file: pci.h there are defintion for those -* region features. -* unsigned int baseAddress - The region base Address. -* unsigned int topAddress - The region top Address. +* unsigned int features - See file: pci.h there are defintion for those +* region features. +* unsigned int baseAddress - The region base Address. +* unsigned int topAddress - The region top Address. * Returns: false if one of the parameters is erroneous true otherwise. *********************************************************************/ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, @@ -541,7 +541,7 @@ bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region, /******************************************************************** * pciDisableAccessRegion - Disable The given Region by writing MAX size -* to its low Address and MIN size to its high Address. +* to its low Address and MIN size to its high Address. * * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled. * Returns: N/A. @@ -588,12 +588,12 @@ bool pciArbiterDisable (PCI_HOST host) * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low) * * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent. -* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. -* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. -* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. -* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. -* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. -* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. +* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent. +* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent. +* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent. +* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent. +* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent. +* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent. * Returns: true *********************************************************************/ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, @@ -619,17 +619,17 @@ bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent, /******************************************************************** * pciParkingDisable - Park on last option disable, with this function you can -* disable the park on last mechanism for each agent. -* disabling this option for all agents results parking -* on the internal master. +* disable the park on last mechanism for each agent. +* disabling this option for all agents results parking +* on the internal master. * * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent. -* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. -* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. -* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. -* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. -* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. -* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. +* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent. +* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent. +* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent. +* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent. +* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent. +* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent. * Returns: true *********************************************************************/ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, @@ -655,11 +655,11 @@ bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent, /******************************************************************** * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to -* respond to grant assertion within a window specified in -* the input value: 'brokenValue'. +* respond to grant assertion within a window specified in +* the input value: 'brokenValue'. * * Inputs: unsigned char brokenValue - A value which limits the Master to hold the -* grant without asserting frame. +* grant without asserting frame. * Returns: Error for illegal broken value otherwise true. *********************************************************************/ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) @@ -678,9 +678,9 @@ bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue) /******************************************************************** * pciDisableBrokenAgentDetection - This function disable the Broken agent -* Detection mechanism. -* NOTE: This operation may cause a dead lock on the -* pci0 arbitration. +* Detection mechanism. +* NOTE: This operation may cause a dead lock on the +* pci0 arbitration. * * Inputs: N/A * Returns: true. @@ -697,15 +697,15 @@ bool pciDisableBrokenAgentDetection (PCI_HOST host) /******************************************************************** * pciP2PConfig - This function set the PCI_n P2P configurate. -* For more information on the P2P read PCI spec. +* For more information on the P2P read PCI spec. * * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower -* Boundry. -* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper -* Boundry. -* unsigned int busNum - The CPI bus number to which the PCI interface -* is connected. -* unsigned int devNum - The PCI interface's device number. +* Boundry. +* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper +* Boundry. +* unsigned int busNum - The CPI bus number to which the PCI interface +* is connected. +* unsigned int devNum - The PCI interface's device number. * * Returns: true. *********************************************************************/ @@ -723,15 +723,15 @@ bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow, /******************************************************************** * pciSetRegionSnoopMode - This function modifys one of the 4 regions which -* supports Cache Coherency in the PCI_n interface. +* supports Cache Coherency in the PCI_n interface. * Inputs: region - One of the four regions. -* snoopType - There is four optional Types: -* 1. No Snoop. -* 2. Snoop to WT region. -* 3. Snoop to WB region. -* 4. Snoop & Invalidate to WB region. -* baseAddress - Base Address of this region. -* regionLength - Region length. +* snoopType - There is four optional Types: +* 1. No Snoop. +* 2. Snoop to WT region. +* 3. Snoop to WB region. +* 4. Snoop & Invalidate to WB region. +* baseAddress - Base Address of this region. +* regionLength - Region length. * Returns: false if one of the parameters is wrong otherwise return true. *********************************************************************/ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, @@ -754,7 +754,7 @@ bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region, GT_REG_WRITE (snoopXtopAddress, 0); return true; } - baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ + baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */ data = (baseAddress >> 20) | snoopType << 12; GT_REG_WRITE (snoopXbaseAddress, data); snoopHigh = (snoopHigh & 0xfff00000) >> 20; @@ -827,7 +827,7 @@ static void gt_setup_ide (struct pci_controller *hose, static void gt_setup_cpcidvi (struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *entry) { - u32 bar_value, pci_response; + u32 bar_value, pci_response; pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); @@ -843,30 +843,30 @@ static void gt_setup_cpcidvi (struct pci_controller *hose, unsigned char gt_cpcidvi_in8(unsigned int offset) { - unsigned char data; + unsigned char data; if (gt_cpcidvi_rom.init == 0) { - return(0); - } - data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); - return(data); + return(0); + } + data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base); + return(data); } void gt_cpcidvi_out8(unsigned int offset, unsigned char data) { - unsigned int off; - + unsigned int off; + if (gt_cpcidvi_rom.init == 0) { - return; - } + return; + } off = data; off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base; - in8(off); - return; + in8(off); + return; } #endif -/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ +/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */ /* and is curently not called *. */ #if 0 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev) diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk index 7129ad5..798a3fa 100644 --- a/board/esd/hh405/config.mk +++ b/board/esd/hh405/config.mk @@ -29,3 +29,6 @@ TEXT_BASE = 0xFFF80000 #TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 958af8f..99fd556 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -697,7 +697,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk index a6d31aa..4c60c35 100644 --- a/board/esd/hub405/config.mk +++ b/board/esd/hub405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index e77dba8..0c6771f 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -265,7 +265,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 25b2105..916b285 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -27,3 +27,6 @@ TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 5b9d063..37b92fb 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -269,7 +269,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk index 219a4eb..72e8103 100644 --- a/board/esd/voh405/config.mk +++ b/board/esd/voh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFF80000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index eda3fd9..22995b5 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -343,7 +343,7 @@ void ide_set_reset(int on) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk index 1d743a9..3cf5dd8 100644 --- a/board/esd/wuh405/config.mk +++ b/board/esd/wuh405/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xFFFC0000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index db24122..5a1a3f3 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -239,7 +239,7 @@ int testdram (void) /* ------------------------------------------------------------------------- */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 3f78753..39b5c70 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -185,7 +185,7 @@ int testdram (void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; void nand_init(void) diff --git a/board/mcc200/Makefile b/board/mcc200/Makefile new file mode 100644 index 0000000..7fdc088 --- /dev/null +++ b/board/mcc200/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/mcc200/config.mk b/board/mcc200/config.mk new file mode 100644 index 0000000..fa55673 --- /dev/null +++ b/board/mcc200/config.mk @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# MCC200 board: +# +# Valid values for TEXT_BASE are: +# +# 0xFFF00000 boot high (standard configuration) +# 0xFE000000 boot low +# 0x00100000 boot from RAM (for testing only) +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +## Standard: boot high +TEXT_BASE = 0xFFF00000 +## For testing: boot from RAM +# TEXT_BASE = 0x00100000 +endif + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c new file mode 100644 index 0000000..d1c99fd --- /dev/null +++ b/board/mcc200/mcc200.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc5xxx.h> +#include <pci.h> + +#include "mt48lc8m32b2-6-7.h" + +extern flash_info_t flash_info[]; /* FLASH chips info */ + +ulong flash_get_size (ulong base, int banknum); + +#ifndef CFG_RAMBOOT +static void sdram_start (int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set mode register: extended mode */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; + __asm__ volatile ("sync"); + + /* set mode register: reset DLL */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; + __asm__ volatile ("sync"); +#endif + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; + __asm__ volatile ("sync"); + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + __asm__ volatile ("sync"); + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; + __asm__ volatile ("sync"); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * is something else than 0x00000000. + */ + +long int initdram (int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* setup SDRAM chip selects */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ + __asm__ volatile ("sync"); + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + __asm__ volatile ("sync"); + +#if SDRAM_DDR + /* set tap delay */ + *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; + __asm__ volatile ("sync"); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) { + dramsize = 0; + } + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; + } else { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ + } + + /* let SDRAM CS1 start right after CS0 */ + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ + + /* find RAM size using SDRAM CS1 only */ + if (!dramsize) + sdram_start(0); + test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + if (!dramsize) { + sdram_start(1); + test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + } + if (test1 > test2) { + sdram_start(0); + dramsize2 = test1; + } else { + dramsize2 = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize2 < (1 << 20)) { + dramsize2 = 0; + } + + /* set SDRAM CS1 size according to the amount of RAM found */ + if (dramsize2 > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); + } else { + *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ + } + +#else /* CFG_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) { + dramsize = (1 << (dramsize - 0x13)) << 20; + } else { + dramsize = 0; + } + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; + if (dramsize2 >= 0x13) { + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + } else { + dramsize2 = 0; + } + +#endif /* CFG_RAMBOOT */ + + return dramsize + dramsize2; +} + +int checkboard (void) +{ + puts ("Board: MCC200\n"); + return 0; +} + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* + * Adjust flash start and offset to detected values + */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* + * Check if boot FLASH isn't max size + */ + if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { + /* adjust mapping */ + *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = + START_REG(gd->bd->bi_flashstart); + *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + } + + return (0); +} + +#ifdef CONFIG_PCI +static struct pci_controller hose; + +extern void pci_mpc5xxx_init(struct pci_controller *); + +void pci_init_board(void) +{ + pci_mpc5xxx_init(&hose); +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) + +void init_ide_reset (void) +{ + debug ("init_ide_reset\n"); + +} + +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + +#if (CONFIG_COMMANDS & CFG_CMD_DOC) +extern void doc_probe (ulong physadr); +void doc_init (void) +{ + doc_probe (CFG_DOC_BASE); +} +#endif diff --git a/board/mcc200/mt46v16m16-75.h b/board/mcc200/mt46v16m16-75.h new file mode 100644 index 0000000..f650faa --- /dev/null +++ b/board/mcc200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/mcc200/mt48lc16m16a2-75.h b/board/mcc200/mt48lc16m16a2-75.h new file mode 100644 index 0000000..ffdf039 --- /dev/null +++ b/board/mcc200/mt48lc16m16a2-75.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 0 /* is SDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xD2322800 +#define SDRAM_CONFIG2 0x8AD70000 + +#elif defined(CONFIG_MGT5100) +/* Settings for XLB = 66 MHz */ +#define SDRAM_MODE 0x008D0000 +#define SDRAM_CONTROL 0x504F0000 +#define SDRAM_CONFIG1 0xC2222600 +#define SDRAM_CONFIG2 0x88B70004 +#define SDRAM_ADDRSEL 0x02000000 + +#else +#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined +#endif diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000..13aebbd --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ diff --git a/board/mcc200/u-boot.lds b/board/mcc200/u-boot.lds new file mode 100644 index 0000000..4fdea6b --- /dev/null +++ b/board/mcc200/u-boot.lds @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2003-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/netphone/config.mk b/board/netphone/config.mk index 8497ebc..de179c2 100644 --- a/board/netphone/config.mk +++ b/board/netphone/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index dd03e4b..297de97 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -599,7 +599,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netstar/config.mk b/board/netstar/config.mk index 57a34c4..50d647a 100644 --- a/board/netstar/config.mk +++ b/board/netstar/config.mk @@ -10,6 +10,5 @@ # XXX TEXT_BASE = 0x20012000 TEXT_BASE = 0x13FC0000 -# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) +# Compile the new NAND code BOARDLIBS = drivers/nand/libnand.a - diff --git a/board/netstar/setup.S b/board/netstar/setup.S index 82c0342..f67786d 100644 --- a/board/netstar/setup.S +++ b/board/netstar/setup.S @@ -129,8 +129,8 @@ MUX_CONFIG_OFFSETS: .byte 0x0c @ COMP_MODE_CTRL_0 .byte 0xff -.globl platformsetup -platformsetup: +.globl lowlevel_init +lowlevel_init: /* Improve performance a bit... */ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register diff --git a/board/netta2/config.mk b/board/netta2/config.mk index 8497ebc..de179c2 100644 --- a/board/netta2/config.mk +++ b/board/netta2/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index c9b4051..3ca7bd3 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -597,7 +597,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netvia/config.mk b/board/netvia/config.mk index 9dddaad..583174a 100644 --- a/board/netvia/config.mk +++ b/board/netvia/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0x40000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index fb7f770..3e6c616 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -418,7 +418,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 6ae1a49..2387176 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -32,7 +32,7 @@ #include <i2c.h> #include <asm/mach-types.h> #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk index 0cd8f44..8e73d2f 100644 --- a/board/sixnet/config.mk +++ b/board/sixnet/config.mk @@ -26,3 +26,6 @@ # TEXT_BASE = 0xF8000000 + +# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) +BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index 867589f..a25dffd 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -34,7 +34,7 @@ #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; #endif diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index aa3d129..7caf06a 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -576,7 +576,7 @@ int board_early_init_f(void) #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#include <linux/mtd/nand.h> +#include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/tqm85xx/tqm85xx.c b/board/tqm85xx/tqm85xx.c index 13ea6f4..c03b60d 100644 --- a/board/tqm85xx/tqm85xx.c +++ b/board/tqm85xx/tqm85xx.c @@ -296,7 +296,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, 0xffffffff, + CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S index 4d62be5..c3bb4eb 100644 --- a/board/zylonite/lowlevel_init.S +++ b/board/zylonite/lowlevel_init.S @@ -16,7 +16,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -32,140 +32,140 @@ DRAM_SIZE: .long CFG_DRAM_SIZE /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm +.macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 +.endm .macro wait time - ldr r2, =OSCR - mov r3, #0 - str r3, [r2] + ldr r2, =OSCR + mov r3, #0 + str r3, [r2] 0: - ldr r3, [r2] - cmp r3, \time - bls 0b + ldr r3, [r2] + cmp r3, \time + bls 0b .endm - + /* - * Memory setup + * Memory setup */ .globl lowlevel_init lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ - mov r10, lr - - /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */ - ldr r0, =0x40E10438 @ GPIO41 FFRXD - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E1043C @ GPIO42 FFTXD - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E10440 @ GPIO43 FFCTS - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E10444 @ GPIO 44 FFDCD - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E10448 @ GPIO 45 FFDSR - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E1044C @ GPIO 46 FFRI - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E10450 @ GPIO 47 FFDTR - ldr r1, =0x802 - str r1, [r0] - - ldr r0, =0x40E10454 @ GPIO 48 - ldr r1, =0x802 - str r1, [r0] - - /* tebrandt - ASCR, clear the RDH bit */ - ldr r0, =ASCR - ldr r1, [r0] - bic r1, r1, #0x80000000 - str r1, [r0] - + mov r10, lr + + /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */ + ldr r0, =0x40E10438 @ GPIO41 FFRXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1043C @ GPIO42 FFTXD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10440 @ GPIO43 FFCTS + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10444 @ GPIO 44 FFDCD + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10448 @ GPIO 45 FFDSR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E1044C @ GPIO 46 FFRI + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10450 @ GPIO 47 FFDTR + ldr r1, =0x802 + str r1, [r0] + + ldr r0, =0x40E10454 @ GPIO 48 + ldr r1, =0x802 + str r1, [r0] + + /* tebrandt - ASCR, clear the RDH bit */ + ldr r0, =ASCR + ldr r1, [r0] + bic r1, r1, #0x80000000 + str r1, [r0] + /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ + /* Chapter 10. */ /* ---------------------------------------------------------------- */ /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ /* ---------------------------------------------------------------- */ /* mk: replaced with wait macro */ -/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */ -/* mov r2, #0 */ -/* str r2, [r3] */ -/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */ -/* /\* so 0x300 should be plenty *\/ */ +/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */ +/* mov r2, #0 */ +/* str r2, [r3] */ +/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */ +/* /\* so 0x300 should be plenty *\/ */ /* 1: */ -/* ldr r2, [r3] */ -/* cmp r4, r2 */ -/* bgt 1b */ +/* ldr r2, [r3] */ +/* cmp r4, r2 */ +/* bgt 1b */ wait #300 - + mem_init: /* configure the MEMCLKCFG register */ - ldr r1, =MEMCLKCFG - ldr r2, =0x00010001 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MEMCLKCFG + ldr r2, =0x00010001 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[0] to data flash SRAM mode */ - ldr r1, =CSADRCFG0 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG0 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[1] to data flash SRAM mode */ - ldr r1, =CSADRCFG1 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG1 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set MSC 0 register for SRAM memory */ - ldr r1, =MSC0 - ldr r2, =0x11191119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =MSC0 + ldr r2, =0x11191119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[2] to data flash SRAM mode */ - ldr r1, =CSADRCFG2 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - + ldr r1, =CSADRCFG2 + ldr r2, =0x00320809 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN + /* set CSADRCFG[3] to VLIO mode */ - ldr r1, =CSADRCFG3 - ldr r2, =0x0032080B - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =CSADRCFG3 + ldr r2, =0x0032080B + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN /* set MSC 1 register for VLIO memory */ - ldr r1, =MSC1 - ldr r2, =0x123C1119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN + ldr r1, =MSC1 + ldr r2, =0x123C1119 + str r2, [r1] @ WRITE + ldr r2, [r1] @ DELAY UNTIL WRITTEN #if 0 /* This does not work in Zylonite. -SC */ @@ -222,11 +222,11 @@ mem_init: ldr r2, [r1] /* Hardware DDR Read-Strobe Delay Calibration */ - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] wait #5 - ldr r1, [r0] + ldr r1, [r0] /* Here we assume the hardware calibration alwasy be successful. -SC */ /* Set DMCEN bit in MDCNFG Register */ @@ -236,21 +236,21 @@ mem_init: str r1, [r0] /* scrub/init SDRAM if enabled/present */ -/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ -/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ -/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ - ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ - ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ +/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ +/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ +/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ + ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ + ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 - mov r2, #0 + mov r2, #0 mov r3, #0 - mov r4, #0 + mov r4, #0 mov r5, #0 - mov r6, #0 + mov r6, #0 mov r7, #0 -10: /* fastScrubLoop */ - subs r9, r9, #32 // 32 bytes/line +10: /* fastScrubLoop */ + subs r9, r9, #32 /* 32 bytes/line */ stmia r8!, {r0-r7} beq 15f b 10b @@ -262,34 +262,30 @@ mem_init: /* Disable software and data breakpoints */ mov r0, #0 - mcr p15,0,r0,c14,c8,0 // ibcr0 - mcr p15,0,r0,c14,c9,0 // ibcr1 - mcr p15,0,r0,c14,c4,0 // dbcon + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ /* Enable all debug functionality */ mov r0,#0x80000000 - mcr p14,0,r0,c10,c0,0 // dcsr - + mcr p14,0,r0,c10,c0,0 /* dcsr */ - /* We are finished with Intel's memory controller initialisation */ - /* ---------------------------------------------------------------- */ - /* End lowlevel_init */ + /* End lowlevel_init */ /* ---------------------------------------------------------------- */ endlowlevel_init: - mov pc, lr - + mov pc, lr /* @******************************************************************************** @ DDR calibration -@ +@ @ This function is used to calibrate DQS delay lines. -@ Monahans supports three ways to do it. One is software +@ Monahans supports three ways to do it. One is software @ calibration. Two is hardware calibration. Three is hybrid @ calibration. @ @@ -298,78 +294,78 @@ endlowlevel_init: ddr_calibration: @ Case 1: Write the correct delay value once - @ Configure DDR_SCAL Register - ldr r0, =DDR_SCAL @ DDR_SCAL -q ldr r1, =0xaf2f2f2f - str r1, [r0] - ldr r1, [r0] + @ Configure DDR_SCAL Register + ldr r0, =DDR_SCAL @ DDR_SCAL +q ldr r1, =0xaf2f2f2f + str r1, [r0] + ldr r1, [r0] */ /* @ Case 2: Software Calibration @ Write test pattern to memory - ldr r5, =0x0faf0faf @ Data Pattern - ldr r4, =0xa0000000 @ DDR ram - str r5, [r4] + ldr r5, =0x0faf0faf @ Data Pattern + ldr r4, =0xa0000000 @ DDR ram + str r5, [r4] - mov r1, =0x0 @ delay count - mov r6, =0x0 - mov r7, =0x0 + mov r1, =0x0 @ delay count + mov r6, =0x0 + mov r7, =0x0 ddr_loop1: - add r1, r1, =0x1 - cmp r1, =0xf - ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] - - ldr r2, [r4] - cmp r2, r5 - bne ddr_loop1 - mov r6, r1 + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + bne ddr_loop1 + mov r6, r1 ddr_loop2: - add r1, r1, =0x1 - cmp r1, =0xf - ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] - - ldr r2, [r4] - cmp r2, r5 - be ddr_loop2 - mov r7, r2 - - add r3, r6, r7 - lsr r3, r3, =0x1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - + add r1, r1, =0x1 + cmp r1, =0xf + ble end_loop + mov r3, r1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + str r3, [r2] + + ldr r2, [r4] + cmp r2, r5 + be ddr_loop2 + mov r7, r2 + + add r3, r6, r7 + lsr r3, r3, =0x1 + mov r0, r1, lsl #30 + orr r3, r3, r0 + mov r0, r1, lsl #22 + orr r3, r3, r0 + mov r0, r1, lsl #14 + orr r3, r3, r0 + orr r3, r3, =0x80000000 + ldr r2, =DDR_SCAL + end_loop: @ Case 3: Hardware Calibratoin - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] - wait #5 - ldr r1, [r0] - mov pc, lr + ldr r0, =DDR_HCAL @ DDR_HCAL + ldr r1, =0x803ffc07 @ the offset is correct? -SC + str r1, [r0] + wait #5 + ldr r1, [r0] + mov pc, lr */ |