diff options
Diffstat (limited to 'board')
-rw-r--r-- | board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 11 | ||||
-rw-r--r-- | board/freescale/mx6qsabreauto/mx6q.cfg | 20 | ||||
-rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 26 | ||||
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 9 |
4 files changed, 50 insertions, 16 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 93d6209..51a7cbd 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. * Jason Liu <r64343@freescale.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -16,9 +16,14 @@ IMAGE_VERSION 2 /* - * Boot Device : one of - * spi, sd (the board has no nand neither onenand) + * Boot Device : one of spi, sd, sata + * the board has no nand and eimnor + * spinor: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 */ + +/* the same flash_offset as sd */ BOOT_FROM sd #ifdef CONFIG_USE_PLUGIN diff --git a/board/freescale/mx6qsabreauto/mx6q.cfg b/board/freescale/mx6qsabreauto/mx6q.cfg index 075d51a..c05d1df 100644 --- a/board/freescale/mx6qsabreauto/mx6q.cfg +++ b/board/freescale/mx6qsabreauto/mx6q.cfg @@ -114,16 +114,16 @@ DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 /* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0xFFFFF300 -DATA 4 0x020c407c 0x0F0000F3 -DATA 4 0x020c4080 0x00000FFF +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF /* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF +DATA 4, 0x020e0010, 0xF00000CF /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index aca2c60..2bf0c74 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -57,6 +57,10 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024); @@ -359,6 +363,25 @@ void board_late_mmc_env_init(void) #endif +#ifdef CONFIG_SYS_USE_SPINOR +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Steer logic */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + gpio_direction_output(IMX_GPIO_NR(3, 19), 0); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -440,6 +463,9 @@ int board_early_init_f(void) { setup_iomux_uart(); +#ifdef CONFIG_SYS_USE_SPINOR + setup_spinor(); +#endif return 0; } diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 2800b57..2889b6c 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -164,6 +164,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#ifdef CONFIG_SYS_USE_SPINOR iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -171,10 +172,12 @@ iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_spi(void) +static void setup_spinor(void) { imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(4, 9), 0); } +#endif iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ @@ -758,8 +761,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_MXC_SPI - setup_spi(); +#ifdef CONFIG_SYS_USE_SPINOR + setup_spinor(); #endif #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |