diff options
Diffstat (limited to 'board')
-rw-r--r-- | board/a3m071/README | 2 | ||||
-rw-r--r-- | board/a3m071/a3m071.c | 147 | ||||
-rw-r--r-- | board/a3m071/is46r16320d.h | 35 | ||||
-rw-r--r-- | board/davedenx/aria/aria.c | 64 | ||||
-rw-r--r-- | board/esd/mecp5123/mecp5123.c | 54 | ||||
-rw-r--r-- | board/freescale/mpc5121ads/mpc5121ads.c | 52 | ||||
-rw-r--r-- | board/ifm/ac14xx/Makefile | 34 | ||||
-rw-r--r-- | board/ifm/ac14xx/ac14xx.c | 617 | ||||
-rw-r--r-- | board/pdm360ng/pdm360ng.c | 58 |
9 files changed, 826 insertions, 237 deletions
diff --git a/board/a3m071/README b/board/a3m071/README index 7698614..a0fe832 100644 --- a/board/a3m071/README +++ b/board/a3m071/README @@ -62,7 +62,7 @@ the following command: All this can be integrated into an environment command: => setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \ - fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \ + fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \ cp.b 1800000 fc060000 10000' => saveenv diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index 89ced82..0f9f883 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -24,10 +24,15 @@ #include <mpc5xxx.h> #include <pci.h> #include <miiphy.h> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/io.h> +#ifdef CONFIG_A4M2K +#include "is46r16320d.h" +#else #include "mt46v16m16-75.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -63,6 +68,12 @@ static void sdram_start(int hi_addr) /* normal operation */ out_be32((void *)MPC5XXX_SDRAM_CTRL, control); + + /* + * Wait a short while for the DLL to lock before accessing + * the SDRAM + */ + udelay(100); } #endif @@ -157,12 +168,6 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; u8 val; - /* - * Figure out failsavelevel - * see ticket dsvk#59 - */ - *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ - /* read digitalboard-version from TMR[2..4] */ val = 0; val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; @@ -170,6 +175,17 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; *digiboardversion = val; + /* + * A4M2K only supports digiboardversion. No failsavelevel and + * fpgaversion here. + */ +#if !defined(CONFIG_A4M2K) + /* + * Figure out failsavelevel + * see ticket dsvk#59 + */ + *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ + if (*digiboardversion == 0) { *failsavelevel = 1; /* digiboard-version ok */ @@ -183,6 +199,7 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, if (*fpgaversion == 1) *failsavelevel = 2; /* fpga-version ok */ } +#endif } /* @@ -196,6 +213,11 @@ void spl_board_init(void) struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + +#if defined(CONFIG_A4M2K) + /* enable CS3 and CS5 (FPGA) */ + setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); +#else int digiboardversion; int failsavelevel; int fpgaversion; @@ -219,6 +241,7 @@ void spl_board_init(void) /* And write new value back to register */ out_be32(&mm->ipbi_ws_ctrl, val); +#endif /* * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG) @@ -232,8 +255,57 @@ void spl_board_init(void) * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT) * set bit 0(msb) to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN); + +#if defined(CONFIG_A4M2K) + /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */ + + /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 15); + gpio->simple_ddr |= 1 << (31 - 14); + gpio->simple_ddr |= 1 << (31 - 13); + gpio->simple_ddr |= 1 << (31 - 12); + + /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 15); + gpio->simple_gpioe |= 1 << (31 - 14); + gpio->simple_gpioe |= 1 << (31 - 13); + gpio->simple_gpioe |= 1 << (31 - 12); + + /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */ + + /* set PSC2[0..2] (STSLED[0..2]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 27); + gpio->simple_ddr |= 1 << (31 - 26); + gpio->simple_ddr |= 1 << (31 - 25); + + /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 27); + gpio->simple_gpioe |= 1 << (31 - 26); + gpio->simple_gpioe |= 1 << (31 - 25); + + /* Setup PSC6[2] as MRST2 self reset GPIO output */ + + /* set PSC6[2]/IRDA_TX (MRST2) direction to output */ + gpio->simple_ddr |= 1 << (31 - 3); + + /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */ + gpio->simple_ode |= 1 << (31 - 3); + /* set PSC6[2]/IRDA_TX (MRST2) output as default high */ + gpio->simple_dvo |= 1 << (31 - 3); + + /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 3); + + /* Setup PSC6[3] as HARNSSCD harness code GPIO input */ + + /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */ + gpio->simple_ddr |= 0 << (31 - 2); + + /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 2); +#else /* setup GPIOs for status-leds if needed - see ticket #57 */ if (failsavelevel > 0) { /* digiboard-version is OK */ @@ -267,7 +339,7 @@ void spl_board_init(void) * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above */ } - +#endif } int checkboard(void) @@ -278,11 +350,16 @@ int checkboard(void) get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); +#ifdef CONFIG_A4M2K + puts("Board: A4M2K\n"); + printf(" digiboard IO version %u\n", digiboardversion); +#else puts("Board: A3M071\n"); printf("Rev: failsave level %u\n", failsavelevel); printf(" digiboard IO version %u\n", digiboardversion); if (failsavelevel > 0) /* only if fpga-version red */ printf(" fpga IO version %u\n", fpgaversion); +#endif return 0; } @@ -333,3 +410,57 @@ int spl_start_uboot(void) return 1; } #endif + +#if defined(CONFIG_HW_WATCHDOG) +static int watchdog_toggle; + +void hw_watchdog_reset(void) +{ + int val; + + /* + * Check if watchdog is enabled via user command + */ + if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) { + /* Set direction to output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN); + + /* + * Toggle watchdog output + */ + val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & + CONFIG_WDOG_GPIO_PIN); + if (val) { + clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, + CONFIG_WDOG_GPIO_PIN); + } else { + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, + CONFIG_WDOG_GPIO_PIN); + } + } +} + +int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + goto usage; + + if (strncmp(argv[1], "on", 2) == 0) + watchdog_toggle = 1; + else if (strncmp(argv[1], "off", 3) == 0) + watchdog_toggle = 0; + else + goto usage; + + return 0; +usage: + printf("Usage: wdogtoggle %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle, + "toggle GPIO pin to service watchdog", + "[on/off] - Switch watchdog toggling via GPIO pin on/off" +); +#endif diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h new file mode 100644 index 0000000..8183d81 --- /dev/null +++ b/board/a3m071/is46r16320d.h @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SDRAM_DDR /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ + +/* SDRAM Config Standard timing */ +#define SDRAM_MODE 0x008d0000 +#define SDRAM_EMODE 0x40010000 +#define SDRAM_CONTROL 0x70430f00 +#define SDRAM_CONFIG1 0x33622930 +#define SDRAM_CONFIG2 0x46670000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index 31b079b..2290257 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -35,70 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; - - /* - * Initialize Local Window for the On Board FPGA access - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) | - CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - sync_law(&im->sysconf.lpcs2aw); - - /* - * Initialize Local Window for the On Board SRAM access - */ - out_be32(&im->sysconf.lpcs6aw, - CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) | - CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE) - ); - out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); - sync_law(&im->sysconf.lpcs6aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - spridr = in_be32(&im->sysconf.spridr); - - if (SVR_MJREV(spridr) >= 2) - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - return 0; -} - phys_size_t initdram (int board_type) { return fixed_sdram(NULL, NULL, 0); diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 748ad7c..e38678f 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -33,20 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_I2C_EN) - int eeprom_write_enable(unsigned dev_addr, int state) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -65,18 +51,9 @@ int eeprom_write_enable(unsigned dev_addr, int state) int board_early_init_f(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; int i; /* - * Initialize Local Window for NOR FLASH access - */ - out_be32(&im->sysconf.lpcs0aw, - CSAW_START(CONFIG_SYS_FLASH_BASE) | - CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); - sync_law(&im->sysconf.lpcs0aw); - - /* * Initialize Local Window for boot access */ out_be32(&im->sysconf.lpbaw, @@ -84,37 +61,6 @@ int board_early_init_f(void) sync_law(&im->sysconf.lpbaw); /* - * Initialize Local Window for VPC3 access - */ - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(CONFIG_SYS_VPC3_BASE) | - CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE)); - sync_law(&im->sysconf.lpcs1aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - /* - * Configure VPC3 Speed - */ - out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); - - spridr = in_be32(&im->sysconf.spridr); - if (SVR_MJREV(spridr) >= 2) - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - /* * Configure MSCAN clocks */ for (i=0; i<4; ++i) { diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 97eeab3..33a8aa5 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -38,25 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN | \ - CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_USB1_EN | \ - CLOCK_SCCR2_USB2_EN) - void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ @@ -83,20 +64,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) int board_early_init_f(void) { - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 spridr; - - /* - * Initialize Local Window for the CPLD registers access (CS2 selects - * the CPLD chip) - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_CPLD_BASE) | - CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - sync_law(&im->sysconf.lpcs2aw); - /* * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control * @@ -114,25 +81,6 @@ int board_early_init_f(void) out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); } #endif - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - spridr = in_be32(&im->sysconf.spridr); - - if (SVR_MJREV (spridr) >= 2) - out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - return 0; } diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile new file mode 100644 index 0000000..9a76f32 --- /dev/null +++ b/board/ifm/ac14xx/Makefile @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c new file mode 100644 index 0000000..7442591 --- /dev/null +++ b/board/ifm/ac14xx/ac14xx.c @@ -0,0 +1,617 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009 Dave Srl www.dave.eu + * (C) Copyright 2010 ifm ecomatic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/bitops.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mpc512x.h> +#include <fdt_support.h> +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_configure(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + + im = (immap_t *) CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ + out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ + + /* + * out_be32(&gpioregs->gpdir, 0xC2293020); + * workaround for a hardware affect: configure direction in pieces, + * setting all outputs at once drops the reset line too low and + * makes us lose the MII connection (breaks ethernet for us) + */ + out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ + setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ + + /* to turn from red to yellow when U-Boot runs */ + setbits_be32(&gpioregs->gpdat, 0x00002020); + out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ + out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ + out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ + out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ +} + +/* the physical location of the pins */ +#define GPIOKEY_ROW_BITMASK 0x40000000 +#define GPIOKEY_ROW_UPPER 0 +#define GPIOKEY_ROW_LOWER 1 + +#define GPIOKEY_COL0_BITMASK 0x20000000 +#define GPIOKEY_COL1_BITMASK 0x10000000 +#define GPIOKEY_COL2_BITMASK 0x08000000 + +/* the logical presentation of pressed keys */ +#define GPIOKEY_BIT_FNLEFT (1 << 5) +#define GPIOKEY_BIT_FNRIGHT (1 << 4) +#define GPIOKEY_BIT_DIRUP (1 << 3) +#define GPIOKEY_BIT_DIRLEFT (1 << 2) +#define GPIOKEY_BIT_DIRRIGHT (1 << 1) +#define GPIOKEY_BIT_DIRDOWN (1 << 0) + +/* the hotkey combination which starts recovery */ +#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ + GPIOKEY_BIT_DIRDOWN) + +static void gpio_selectrow(gpio512x_t *gpioregs, u32 row) +{ + + if (row) + setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + else + clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + udelay(10); +} + +static u32 gpio_querykbd(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + u32 keybits; + u32 input; + + im = (immap_t *)CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + keybits = 0; + + /* query upper row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRUP; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNRIGHT; + + /* query lower row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRRIGHT; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRDOWN; + + /* return bit pattern for keys */ + return keybits; +} + +/* excerpt from the recovery's hw_info.h */ + +static int eeprom_diag = 1; + +struct __attribute__ ((__packed__)) eeprom_layout { + char magic[3]; /** 'ifm' */ + u8 len[2]; /** content length without magic/len fields */ + u8 version[3]; /** structure version */ + u8 type; /** type of PCB */ + u8 reserved[0x37]; /** padding up to offset 0x40 */ + u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */ +}; + +#define HW_COMP_MAINCPU 2 + +static struct eeprom_layout eeprom_content; +static int eeprom_was_read; /* has_been_read */ +static int eeprom_is_valid; +static int eeprom_version; + +#define get_eeprom_field_int(name) ({ \ + int value; \ + int idx; \ + value = 0; \ + for (idx = 0; idx < sizeof(name); idx++) { \ + value <<= 8; \ + value |= name[idx]; \ + } \ + value; \ +}) + +static int read_eeprom(void) +{ + int eeprom_datalen; + int ret; + + if (eeprom_was_read) + return 0; + + eeprom_is_valid = 0; + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *)&eeprom_content, sizeof(eeprom_content)); + if (eeprom_diag) { + printf("DIAG: %s() read rc[%d], size[%d]\n", + __func__, ret, sizeof(eeprom_content)); + } + + if (ret != 0) + return -1; + + eeprom_was_read = 1; + + /* + * check validity of EEPROM content + * (check version, length, optionally checksum) + */ + eeprom_is_valid = 1; + eeprom_datalen = get_eeprom_field_int(eeprom_content.len); + eeprom_version = get_eeprom_field_int(eeprom_content.version); + + if (eeprom_diag) { + printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n", + __func__, eeprom_content.magic[0], + eeprom_content.magic[1], eeprom_content.magic[2], + eeprom_datalen, eeprom_version, eeprom_content.type); + } + if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0) + eeprom_is_valid = 0; + if (eeprom_datalen < sizeof(struct eeprom_layout) - 5) + eeprom_is_valid = 0; + if ((eeprom_version != 1) && (eeprom_version != 2)) + eeprom_is_valid = 0; + if (eeprom_content.type != HW_COMP_MAINCPU) + eeprom_is_valid = 0; + + if (eeprom_diag) + printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid); + + return ret; +} + +int mac_read_from_eeprom(void) +{ + const u8 *mac; + + if (read_eeprom()) { + printf("I2C EEPROM read failed.\n"); + return -1; + } + + if (!eeprom_is_valid) { + printf("I2C EEPROM content not valid\n"); + return -1; + } + + mac = NULL; + switch (eeprom_version) { + case 1: + case 2: + mac = (const u8 *)&eeprom_content.macaddress; + break; + } + + if (mac && is_valid_ether_addr(mac)) { + eth_setenv_enetaddr("ethaddr", mac); + printf("DIAG: %s() MAC value [%s]\n", + __func__, getenv("ethaddr")); + } + + return 0; +} + +/* + * BEWARE! + * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2 + * which the ADS, Aria or PDM360NG boards are using + * (the steps outlined here refer to the Micron datasheet) + */ +u32 sdram_init_seq[] = { + /* item 6, at least one NOP after CKE went high */ + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 7, precharge all; item 8, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* item 9, extended mode register; item 10, tMRD 10ns) */ + CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 11, (base) mode register _with_ reset DLL; + * item 12, tMRD (10ns) + */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL | + CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* item 13, precharge all; item 14, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 15, auto refresh (i.e. refresh with CKE held high); + * item 16, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 17, auto refresh (i.e. refresh with CKE held high); + * item 18, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 21, "actually done", but make sure 200 DRAM clock cycles + * have passed after DLL reset before READ requests are issued + * (200 cycles at 160MHz -> 1.25 usec) + */ + /* EMPTY, optional, we don't do it */ +}; + +phys_size_t initdram(int board_type) +{ + return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq)); +} + +int misc_init_r(void) +{ + u32 keys; + char *s; + int want_recovery; + + /* we use bus I2C-0 for the on-board eeprom */ + i2c_set_bus_num(0); + + /* setup GPIO directions and initial values */ + gpio_configure(); + + /* + * check the GPIO keyboard, + * enforced start of the recovery when + * - the appropriate keys were pressed + * - a previous installation was aborted or has failed + * - "some" external software told us to + */ + want_recovery = 0; + keys = gpio_querykbd(); + printf("GPIO keyboard status [0x%08X]\n", keys); + /* XXX insist in the _exact_ combination? */ + if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) { + printf("GPIO keyboard requested RECOVERY\n"); + /* XXX TODO + * refine the logic to detect the first keypress, and + * wait to recheck IF it was the recovery combination? + */ + want_recovery = 1; + } + s = getenv("install_in_progress"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation aborted, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("install_failed"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation FAILED, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("want_recovery"); + if ((s != NULL) && (*s != '\0')) { + printf("running RECOVERY according to the request\n"); + want_recovery = 1; + } + + if (want_recovery) + setenv("bootcmd", "run recovery"); + + /* + * boot the recovery system without waiting; boot the + * production system without waiting by default, only + * insert a pause (to provide a chance to get a prompt) + * when GPIO keys were pressed during power on + */ + if (want_recovery) + setenv("bootdelay", "0"); + else if (!keys) + setenv("bootdelay", "0"); + else + setenv("bootdelay", "2"); + + /* get the ethernet MAC from I2C EEPROM */ + mac_read_from_eeprom(); + + return 0; +} + +/* setup specific IO pad configuration */ +static iopin_t ioregs_init[] = { + { /* LPC CS3 */ + offsetof(struct ioctrl512x, io_control_nfc_ce0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* LPC CS1 */ + offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS2 */ + offsetof(struct ioctrl512x, io_control_lpc_cs2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS4, CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce1), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* SDHC CLK, CMD, D0, D1, D2, D3 */ + offsetof(struct ioctrl512x, io_control_pata_ior), 6, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO keyboard */ + offsetof(struct ioctrl512x, io_control_pci_ad30), 4, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO DN1 PF, LCD power, DN2 PF */ + offsetof(struct ioctrl512x, io_control_pci_ad26), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset AS-i */ + offsetof(struct ioctrl512x, io_control_pci_ad21), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset safety */ + offsetof(struct ioctrl512x, io_control_pci_ad19), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset netX */ + offsetof(struct ioctrl512x, io_control_pci_ad16), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO ma2 en */ + offsetof(struct ioctrl512x, io_control_pci_ad15), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO SD CD, SD WP */ + offsetof(struct ioctrl512x, io_control_pci_ad08), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* FEC RX DV */ + offsetof(struct ioctrl512x, io_control_pci_ad06), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* GPIO AS-i prog, AS-i done, LCD backlight */ + offsetof(struct ioctrl512x, io_control_pci_ad05), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i wdg */ + offsetof(struct ioctrl512x, io_control_pci_req2), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO safety wdg */ + offsetof(struct ioctrl512x, io_control_pci_req1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO netX wdg */ + offsetof(struct ioctrl512x, io_control_pci_req0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ powerfail */ + offsetof(struct ioctrl512x, io_control_pci_inta), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i PWRD */ + offsetof(struct ioctrl512x, io_control_pci_frame), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO LED0, LED1 */ + offsetof(struct ioctrl512x, io_control_pci_idsel), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */ + offsetof(struct ioctrl512x, io_control_pci_irdy), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* DIU clk */ + offsetof(struct ioctrl512x, io_control_spdif_txclk), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* FEC TX ER, CRS */ + offsetof(struct ioctrl512x, io_control_spdif_tx), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */ + offsetof(struct ioctrl512x, io_control_irq0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* + * FEC col, tx en, tx clk, txd 0-3, mdc, rx er, + * rdx 3-0, mdio, rx clk + */ + offsetof(struct ioctrl512x, io_control_psc0_0), 15, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* optional: make sure PSC3 remains the serial console */ + { /* LPC CS6 */ + offsetof(struct ioctrl512x, io_control_psc3_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* make sure PSC4 remains available for SPI, + *BUT* PSC4_1 is a GPIO kind of SS! */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc4_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { + offsetof(struct ioctrl512x, io_control_psc4_1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + /* optional: make sure PSC5 remains available for SPI */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc5_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(1), + }, + { /* LPC TSIZ1 */ + offsetof(struct ioctrl512x, io_control_psc6_0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* DIU hsync */ + offsetof(struct ioctrl512x, io_control_psc6_1), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU vsync */ + offsetof(struct ioctrl512x, io_control_psc6_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, part of DIU RGB */ + offsetof(struct ioctrl512x, io_control_psc7_0), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, safety UART */ + offsetof(struct ioctrl512x, io_control_psc7_2), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(0) | IO_PIN_DS(1), + }, + { /* DIU (part of) RGB[] */ + offsetof(struct ioctrl512x, io_control_psc8_3), 16, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU data enable */ + offsetof(struct ioctrl512x, io_control_psc11_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + /* reduce LPB drive strength for improved EMI */ + { /* LPC OE, LPC RW */ + offsetof(struct ioctrl512x, io_control_lpc_oe), 2, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC AX03 through LPC AD00 */ + offsetof(struct ioctrl512x, io_control_lpc_ax03), 36, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC CLK */ + offsetof(struct ioctrl512x, io_control_nfc_wp), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC DATA */ + offsetof(struct ioctrl512x, io_control_nfc_ale), 4, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, +}; + +int checkboard(void) +{ + puts("Board: ifm AC14xx\n"); + + /* initialize function mux & slew rate IO inter alia on IO Pins */ + iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init)); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index a2a1323..3048acd 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -44,63 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; ulong flash_get_size (phys_addr_t base, int banknum); -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Initialize Local Window for FLASH-Bank1 access (CS1) - */ - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(CONFIG_SYS_FLASH1_BASE) | - CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE) - ); - out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); - - /* - * Local Window for MRAM access (CS2) - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_MRAM_BASE) | - CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - - sync_law(&im->sysconf.lpcs2aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - return 0; -} - sdram_conf_t mddrc_config[] = { { (512 << 20), /* 512 MB RAM configuration */ @@ -557,7 +500,6 @@ void ft_board_setup(void *blob, bd_t *bd) int rc, i = 0; ft_cpu_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #ifdef CONFIG_FDT_FIXUP_PARTITIONS fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif |