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-rw-r--r--board/delta/Makefile48
-rw-r--r--board/delta/config.mk8
-rw-r--r--board/delta/delta.c75
-rw-r--r--board/delta/lowlevel_init.S385
-rw-r--r--board/delta/nand.c590
-rw-r--r--board/delta/u-boot.lds56
-rw-r--r--board/mcc200/mt48lc8m32b2-6-7.h8
-rw-r--r--board/zylonite/Makefile48
-rw-r--r--board/zylonite/config.mk4
-rw-r--r--board/zylonite/flash.c434
-rw-r--r--board/zylonite/lowlevel_init.S371
-rw-r--r--board/zylonite/u-boot.lds56
-rw-r--r--board/zylonite/zylonite.c75
13 files changed, 2154 insertions, 4 deletions
diff --git a/board/delta/Makefile b/board/delta/Makefile
new file mode 100644
index 0000000..e744eec
--- /dev/null
+++ b/board/delta/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := delta.o nand.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/delta/config.mk b/board/delta/config.mk
new file mode 100644
index 0000000..9564625
--- /dev/null
+++ b/board/delta/config.mk
@@ -0,0 +1,8 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+#TEXT_BASE = 0x9ffe0000
+TEXT_BASE = 0xa3008000
+
+# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
+BOARDLIBS = drivers/nand/libnand.a
diff --git a/board/delta/delta.c b/board/delta/delta.c
new file mode 100644
index 0000000..3ffcc2a
--- /dev/null
+++ b/board/delta/delta.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board mk@tbd: fix this! */
+ gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
new file mode 100644
index 0000000..498cf7f
--- /dev/null
+++ b/board/delta/lowlevel_init.S
@@ -0,0 +1,385 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+.endm
+
+
+.macro wait time
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, \time
+ bls 0b
+.endm
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
+ mov r10, lr
+
+ /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */
+ ldr r0, =GPIO97
+ ldr r1, =0x801
+ str r1, [r0]
+
+ ldr r0, =GPIO98
+ ldr r1, =0x801
+ str r1, [r0]
+
+ /* tebrandt - ASCR, clear the RDH bit */
+ ldr r0, =ASCR
+ ldr r1, [r0]
+ bic r1, r1, #0x80000000
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+; wait #300
+
+mem_init:
+
+#define NEW_SDRAM_INIT 1
+#ifdef NEW_SDRAM_INIT
+
+ /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
+ ldr r0, =ACCR
+ ldr r1, [r0]
+ orr r1, r1, #0x3000
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
+ ldr r0, =MDCNFG
+ ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
+ /* ldr r1, =0x80000403 */
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+
+ /* 3. wait nop power up waiting period (200ms)
+ * optimization: Steps 4+6 can be done during this
+ */
+ wait #300
+
+ /* 4. Perform an initial Rcomp-calibration cycle */
+ ldr r0, =RCOMP
+ ldr r1, =0x80000000
+ str r1, [r0]
+ ldr r1, [r0] /* delay until written */
+ /* missing: program for automatic rcomp evaluation cycles */
+
+ /* 5. DDR DRAM strobe delay calibration */
+ ldr r0, =DDR_HCAL
+ ldr r1, =0x88000007
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0] /* delay until written */
+
+ /* Set MDMRS */
+ ldr r0, =MDMRS
+ ldr r1, =0x60000033
+ str r1, [r0]
+ wait #300
+
+ /* Configure MDREFR */
+ ldr r0, =MDREFR
+ ldr r1, =0x00000006
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Enable the dynamic memory controller */
+ ldr r0, =MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #MDCNFG_DMCEN
+ str r1, [r0]
+
+
+#else /* NEW_SDRAM_INIT */
+
+ /* configure the MEMCLKCFG register */
+ ldr r1, =MEMCLKCFG
+ ldr r2, =0x00010001
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[0] to data flash SRAM mode */
+ ldr r1, =CSADRCFG0
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[1] to data flash SRAM mode */
+ ldr r1, =CSADRCFG1
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 0 register for SRAM memory */
+ ldr r1, =MSC0
+ ldr r2, =0x11191119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[2] to data flash SRAM mode */
+ ldr r1, =CSADRCFG2
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[3] to VLIO mode */
+ ldr r1, =CSADRCFG3
+ ldr r2, =0x0032080B
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
+ ldr r1, =MSC1
+ ldr r2, =0x123C1119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+#endif /* NEW_SDRAM_INIT */
+
+#ifndef CFG_SKIP_DRAM_SCRUB
+ /* scrub/init SDRAM if enabled/present */
+ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */
+ ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
+ mov r2, #0
+ mov r3, #0
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+10: /* fastScrubLoop */
+ subs r9, r9, #32 /* 8 words/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+#endif /* CFG_SKIP_DRAM_SCRUB */
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+endlowlevel_init:
+
+ mov pc, lr
+
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@ This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
+ @ Configure DDR_SCAL Register
+ ldr r0, =DDR_SCAL @ DDR_SCAL
+q ldr r1, =0xaf2f2f2f
+ str r1, [r0]
+ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
+ ldr r5, =0x0faf0faf @ Data Pattern
+ ldr r4, =0xa0000000 @ DDR ram
+ str r5, [r4]
+
+ mov r1, =0x0 @ delay count
+ mov r6, =0x0
+ mov r7, =0x0
+ddr_loop1:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ bne ddr_loop1
+ mov r6, r1
+ddr_loop2:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ be ddr_loop2
+ mov r7, r2
+
+ add r3, r6, r7
+ lsr r3, r3, =0x1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+ mov pc, lr
+*/
diff --git a/board/delta/nand.c b/board/delta/nand.c
new file mode 100644
index 0000000..50def59
--- /dev/null
+++ b/board/delta/nand.c
@@ -0,0 +1,590 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#ifdef CONFIG_NEW_NAND_CODE
+
+#include <nand.h>
+#include <asm/arch/pxa-regs.h>
+
+#ifdef CFG_DFC_DEBUG1
+# define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG1(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG2
+# define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG2(fmt, args...)
+#endif
+
+#ifdef CFG_DFC_DEBUG3
+# define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
+#else
+# define DFC_DEBUG3(fmt, args...)
+#endif
+
+#define MIN(x, y) ((x < y) ? x : y)
+
+/* These really don't belong here, as they are specific to the NAND Model */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr delta_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 2,
+ .pattern = scan_ff_pattern
+};
+
+static struct nand_oobinfo delta_oob = {
+ .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */
+ .eccbytes = 6,
+ .eccpos = {2, 3, 4, 5, 6, 7},
+ .oobfree = { {8, 2}, {12, 4} }
+};
+
+
+/*
+ * not required for Monahans DFC
+ */
+static void dfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+{
+ return;
+}
+
+#if 0
+/* read device ready pin */
+static int dfc_device_ready(struct mtd_info *mtdinfo)
+{
+ if(NDSR & NDSR_RDY)
+ return 1;
+ else
+ return 0;
+ return 0;
+}
+#endif
+
+/*
+ * Write buf to the DFC Controller Data Buffer
+ */
+static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
+{
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+ int i;
+
+ DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ NDDB = *long_buf;
+ }
+ }
+ if(rest) {
+ printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
+ }
+ return;
+}
+
+
+/*
+ * These functions are quite problematic for the DFC. Luckily they are
+ * not used in the current nand code, except for nand_command, which
+ * we've defined our own anyway. The problem is, that we always need
+ * to write 4 bytes to the DFC Data Buffer, but in these functions we
+ * don't know if to buffer the bytes/half words until we've gathered 4
+ * bytes or if to send them straight away.
+ *
+ * Solution: Don't use these with Mona's DFC and complain loudly.
+ */
+static void dfc_write_word(struct mtd_info *mtd, u16 word)
+{
+ printf("dfc_write_word: WARNING, this function does not work with the Monahans DFC!\n");
+}
+static void dfc_write_byte(struct mtd_info *mtd, u_char byte)
+{
+ printf("dfc_write_byte: WARNING, this function does not work with the Monahans DFC!\n");
+}
+
+/* The original:
+ * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
+ *
+ * Shouldn't this be "u_char * const buf" ?
+ */
+static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
+{
+ int i=0, j;
+
+ /* we have to be carefull not to overflow the buffer if len is
+ * not a multiple of 4 */
+ unsigned long bytes_multi = len & 0xfffffffc;
+ unsigned long rest = len & 0x3;
+ unsigned long *long_buf;
+
+ DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
+ /* if there are any, first copy multiple of 4 bytes */
+ if(bytes_multi) {
+ for(i=0; i<bytes_multi; i+=4) {
+ long_buf = (unsigned long*) &buf[i];
+ *long_buf = NDDB;
+ }
+ }
+
+ /* ...then the rest */
+ if(rest) {
+ unsigned long rest_data = NDDB;
+ for(j=0;j<rest; j++)
+ buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
+ }
+
+ return;
+}
+
+/*
+ * read a word. Not implemented as not used in NAND code.
+ */
+static u16 dfc_read_word(struct mtd_info *mtd)
+{
+ printf("dfc_write_byte: UNIMPLEMENTED.\n");
+ return 0;
+}
+
+/* global var, too bad: mk@tbd: move to ->priv pointer */
+static unsigned long read_buf = 0;
+static int bytes_read = -1;
+
+/*
+ * read a byte from NDDB Because we can only read 4 bytes from NDDB at
+ * a time, we buffer the remaining bytes. The buffer is reset when a
+ * new command is sent to the chip.
+ *
+ * WARNING:
+ * This function is currently only used to read status and id
+ * bytes. For these commands always 8 bytes need to be read from
+ * NDDB. So we read and discard these bytes right now. In case this
+ * function is used for anything else in the future, we must check
+ * what was the last command issued and read the appropriate amount of
+ * bytes respectively.
+ */
+static u_char dfc_read_byte(struct mtd_info *mtd)
+{
+ unsigned char byte;
+ unsigned long dummy;
+
+ if(bytes_read < 0) {
+ read_buf = NDDB;
+ dummy = NDDB;
+ bytes_read = 0;
+ }
+ byte = (unsigned char) (read_buf>>(8 * bytes_read++));
+ if(bytes_read >= 4)
+ bytes_read = -1;
+
+ DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
+ return byte;
+}
+
+/* calculate delta between OSCR values start and now */
+static unsigned long get_delta(unsigned long start)
+{
+ unsigned long cur = OSCR;
+
+ if(cur < start) /* OSCR overflowed */
+ return (cur + (start^0xffffffff));
+ else
+ return (cur - start);
+}
+
+/* delay function, this doesn't belong here */
+static void wait_us(unsigned long us)
+{
+ unsigned long start = OSCR;
+ us *= OSCR_CLK_FREQ;
+
+ while (get_delta(start) < us) {
+ /* do nothing */
+ }
+}
+
+static void dfc_clear_nddb()
+{
+ NDCR &= ~NDCR_ND_RUN;
+ wait_us(CFG_NAND_OTHER_TO);
+}
+
+/* wait_event with timeout */
+static unsigned long dfc_wait_event(unsigned long event)
+{
+ unsigned long ndsr, timeout, start = OSCR;
+
+ if(!event)
+ return 0xff000000;
+ else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
+ timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+ else
+ timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+
+ while(1) {
+ ndsr = NDSR;
+ if(ndsr & event) {
+ NDSR |= event;
+ break;
+ }
+ if(get_delta(start) > timeout) {
+ DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%x.\n", event);
+ return 0xff000000;
+ }
+
+ }
+ return ndsr;
+}
+
+/* we don't always wan't to do this */
+static void dfc_new_cmd()
+{
+ int retry = 0;
+ unsigned long status;
+
+ while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+ /* Clear NDSR */
+ NDSR = 0xFFF;
+
+ /* set NDCR[NDRUN] */
+ if(!(NDCR & NDCR_ND_RUN))
+ NDCR |= NDCR_ND_RUN;
+
+ status = dfc_wait_event(NDSR_WRCMDREQ);
+
+ if(status & NDSR_WRCMDREQ)
+ return;
+
+ DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
+ dfc_clear_nddb();
+ }
+ DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
+}
+
+/* this function is called after Programm and Erase Operations to
+ * check for success or failure */
+static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
+{
+ unsigned long ndsr=0, event=0;
+
+ /* mk@tbd set appropriate timeouts */
+ /* if (state == FL_ERASING) */
+ /* timeo = CFG_HZ * 400; */
+ /* else */
+ /* timeo = CFG_HZ * 20; */
+ if(state == FL_WRITING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ } else if(state == FL_ERASING) {
+ event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
+ }
+
+ ndsr = dfc_wait_event(event);
+
+ if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
+ return(0x1); /* Status Read error */
+ return 0;
+}
+
+/* cmdfunc send commands to the DFC */
+static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
+ int column, int page_addr)
+{
+ /* register struct nand_chip *this = mtd->priv; */
+ unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
+
+ /* clear the ugly byte read buffer */
+ bytes_read = -1;
+ read_buf = 0;
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (NAND_CMD_READ0 | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_READ1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
+ goto end;
+ case NAND_CMD_READOOB:
+ DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
+ goto end;
+ case NAND_CMD_READID:
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
+ ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_PAGEPROG:
+ /* sent as a multicommand in NAND_CMD_SEQIN */
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_ERASE1:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ dfc_new_cmd();
+ ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
+ ndcb1 = (page_addr & 0x00ffffff);
+ goto write_cmd;
+ case NAND_CMD_ERASE2:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
+ goto end;
+ case NAND_CMD_SEQIN:
+ /* send PAGE_PROG command(0x1080) */
+ dfc_new_cmd();
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
+ ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
+ column >>= 1; /* adjust for 16 bit bus */
+ ndcb1 = (((column>>1) & 0xff) |
+ ((page_addr<<8) & 0xff00) |
+ ((page_addr<<8) & 0xff0000) |
+ ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
+ event = NDSR_WRDREQ;
+ goto write_cmd;
+ case NAND_CMD_STATUS:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
+ dfc_new_cmd();
+ ndcb0 = NAND_CMD_STATUS | (4<<21);
+ event = NDSR_RDDREQ;
+ goto write_cmd;
+ case NAND_CMD_RESET:
+ DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
+ ndcb0 = NAND_CMD_RESET | (5<<21);
+ event = NDSR_CS0_CMDD;
+ goto write_cmd;
+ default:
+ printk("dfc_cmdfunc: error, unsupported command.\n");
+ goto end;
+ }
+
+ write_cmd:
+ NDCB0 = ndcb0;
+ NDCB0 = ndcb1;
+ NDCB0 = ndcb2;
+
+ /* wait_event: */
+ dfc_wait_event(event);
+ end:
+ return;
+}
+
+static void dfc_gpio_init()
+{
+ DFC_DEBUG2("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see zylonite.c */
+ GPIO4 = 0x1;
+
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+ unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
+
+ /* set up GPIO Control Registers */
+ dfc_gpio_init();
+
+ /* turn on the NAND Controller Clock (104 MHz @ D0) */
+ CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
+
+#undef CFG_TIMING_TIGHT
+#ifndef CFG_TIMING_TIGHT
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
+ DFC_MAX_tAR);
+#else /* this is the tight timing */
+
+ tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
+ DFC_MAX_tCH);
+ tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
+ DFC_MAX_tCS);
+ tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
+ DFC_MAX_tWH);
+ tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
+ DFC_MAX_tWP);
+ tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
+ DFC_MAX_tRH);
+ tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
+ DFC_MAX_tRP);
+ tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tR);
+ tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
+ DFC_MAX_tWHR);
+ tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
+ DFC_MAX_tAR);
+#endif /* CFG_TIMING_TIGHT */
+
+
+ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
+
+ /* tRP value is split in the register */
+ if(tRP & (1 << 4)) {
+ tRP_high = 1;
+ tRP &= ~(1 << 4);
+ } else {
+ tRP_high = 0;
+ }
+
+ NDTR0CS0 = (tCH << 19) |
+ (tCS << 16) |
+ (tWH << 11) |
+ (tWP << 8) |
+ (tRP_high << 6) |
+ (tRH << 3) |
+ (tRP << 0);
+
+ NDTR1CS0 = (tR << 16) |
+ (tWHR << 4) |
+ (tAR << 0);
+
+ /* If it doesn't work (unlikely) think about:
+ * - ecc enable
+ * - chip select don't care
+ * - read id byte count
+ *
+ * Intentionally enabled by not setting bits:
+ * - dma (DMA_EN)
+ * - page size = 512
+ * - cs don't care, see if we can enable later!
+ * - row address start position (after second cycle)
+ * - pages per block = 32
+ * - ND_RDY : clears command buffer
+ */
+ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
+
+ NDCR = (NDCR_SPARE_EN | /* use the spare area */
+ NDCR_DWIDTH_C | /* 16bit DFC data bus width */
+ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
+ (2 << 16) | /* read id count = 7 ???? mk@tbd */
+ NDCR_ND_ARB_EN | /* enable bus arbiter */
+ NDCR_RDYM | /* flash device ready ir masked */
+ NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
+ NDCR_CS1_PAGEDM |
+ NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
+ NDCR_CS1_CMDDM |
+ NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
+ NDCR_CS1_BBDM |
+ NDCR_DBERRM | /* double bit error ir masked */
+ NDCR_SBERRM | /* single bit error ir masked */
+ NDCR_WRDREQM | /* write data request ir masked */
+ NDCR_RDDREQM | /* read data request ir masked */
+ NDCR_WRCMDREQM); /* write command request ir masked */
+
+
+ /* wait 10 us due to cmd buffer clear reset */
+ /* wait(10); */
+
+
+ nand->hwcontrol = dfc_hwcontrol;
+/* nand->dev_ready = dfc_device_ready; */
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->chip_delay = NAND_DELAY_US;
+ nand->options = NAND_BUSWIDTH_16;
+ nand->waitfunc = dfc_wait;
+ nand->read_byte = dfc_read_byte;
+ nand->write_byte = dfc_write_byte;
+ nand->read_word = dfc_read_word;
+ nand->write_word = dfc_write_word;
+ nand->read_buf = dfc_read_buf;
+ nand->write_buf = dfc_write_buf;
+
+ nand->cmdfunc = dfc_cmdfunc;
+ nand->autooob = &delta_oob;
+ nand->badblock_pattern = &delta_bbt_descr;
+}
+
+#else
+ #error "U-Boot legacy NAND support not available for Monahans DFC."
+#endif
+#endif
diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds
new file mode 100644
index 0000000..f010239
--- /dev/null
+++ b/board/delta/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h
index 73dcd5c..13aebbd 100644
--- a/board/mcc200/mt48lc8m32b2-6-7.h
+++ b/board/mcc200/mt48lc8m32b2-6-7.h
@@ -6,7 +6,7 @@
/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x008d0000 // CL-3 BURST-8 -> Mode Register—MBAR + 0x0100
-#define SDRAM_CONTROL 0x504f0000 // Control Register—MBAR + 0x0104
-#define SDRAM_CONFIG1 0xc2222900 // Delays between commands -> Configuration Register 1—MBAR + 0x0108
-#define SDRAM_CONFIG2 0x88c70000 // Delays between commands -> Configuration Register 2—MBAR + 0x010C
+#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
+#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
+#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
+#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
diff --git a/board/zylonite/Makefile b/board/zylonite/Makefile
new file mode 100644
index 0000000..999647f
--- /dev/null
+++ b/board/zylonite/Makefile
@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := zylonite.o flash.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/zylonite/config.mk b/board/zylonite/config.mk
new file mode 100644
index 0000000..09b0f71
--- /dev/null
+++ b/board/zylonite/config.mk
@@ -0,0 +1,4 @@
+#TEXT_BASE = 0x0
+#TEXT_BASE = 0xa1700000
+#TEXT_BASE = 0xa3080000
+TEXT_BASE = 0xa3008000
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
new file mode 100644
index 0000000..883c1ba
--- /dev/null
+++ b/board/zylonite/flash.c
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH ushort
+#define FLASH_PORT_WIDTHV vu_short
+#define SWAP(x) __swab16(x)
+#else
+#define FLASH_PORT_WIDTH ulong
+#define FLASH_PORT_WIDTHV vu_long
+#define SWAP(x) __swab32(x)
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+#if 0
+ int i;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ switch (i) {
+ case 0:
+ flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+ break;
+ case 1:
+ flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+ flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+ break;
+ default:
+ panic ("configured too many flash banks!\n");
+ break;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors
+ */
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0] );
+
+ flash_protect ( FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+ return size;
+#endif
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+ info->protect[i] = 0;
+ }
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL:
+ printf ("INTEL ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F128J3A:
+ printf ("28F128J3A\n");
+ break;
+ default:
+ printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+ return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+ volatile FPW value;
+
+ /* Write auto select command: read Manufacturer ID */
+ addr[0x5555] = (FPW) 0x00AA00AA;
+ addr[0x2AAA] = (FPW) 0x00550055;
+ addr[0x5555] = (FPW) 0x00900090;
+
+ mb ();
+ value = addr[0];
+
+ switch (value) {
+
+ case (FPW) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+ return (0); /* no or unknown flash */
+ }
+
+ mb ();
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+
+ case (FPW) INTEL_ID_28F128J3A:
+ info->flash_id += FLASH_28F128J3A;
+ info->sector_count = 128;
+ info->size = 0x02000000;
+ break; /* => 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ break;
+ }
+
+ if (info->sector_count > CFG_MAX_FLASH_SECT) {
+ printf ("** ERROR: sector count %d > max (%d) **\n",
+ info->sector_count, CFG_MAX_FLASH_SECT);
+ info->sector_count = CFG_MAX_FLASH_SECT;
+ }
+
+ addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong type, start, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ type = (info->flash_id & FLASH_VENDMASK);
+ if ((type != FLASH_MAN_INTEL)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+ last = start;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ FPWV *addr = (FPWV *) (info->start[sect]);
+ FPW status;
+
+ printf ("Erasing sector %2d ... ", sect);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = (FPW) 0x00B000B0; /* suspend erase */
+ *addr = (FPW) 0x00FF00FF; /* reset to read mode */
+ rcode = 1;
+ break;
+ }
+ }
+
+ *addr = 0x00500050; /* clear status register cmd. */
+ *addr = 0x00FF00FF; /* resest to read mode */
+
+ printf (" done\n");
+ }
+ }
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int count, i, l, rc, port_width;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ return 4;
+ }
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+ wp = (addr & ~1);
+ port_width = 2;
+#else
+ wp = (addr & ~3);
+ port_width = 4;
+#endif
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+ for (; i < port_width && cnt > 0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ count = 0;
+ while (cnt >= port_width) {
+ data = 0;
+ for (i = 0; i < port_width; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+ return (rc);
+ }
+ wp += port_width;
+ cnt -= port_width;
+ if (count++ > 0x800) {
+ spin_wheel ();
+ count = 0;
+ }
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i < port_width; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *) cp);
+ }
+
+ return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+ FPWV *addr = (FPWV *) dest;
+ ulong status;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts ();
+
+ *addr = (FPW) 0x00400040; /* write setup */
+ *addr = data;
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+
+ /* wait while polling the status register */
+ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+ return (1);
+ }
+ }
+
+ *addr = (FPW) 0x00FF00FF; /* restore read mode */
+
+ return (0);
+}
+
+void inline spin_wheel (void)
+{
+ static int p = 0;
+ static char w[] = "\\/-";
+
+ printf ("\010%c", w[p]);
+ (++p == 3) ? (p = 0) : 0;
+}
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
new file mode 100644
index 0000000..c3bb4eb
--- /dev/null
+++ b/board/zylonite/lowlevel_init.S
@@ -0,0 +1,371 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE: .long CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+.macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+.endm
+
+
+.macro wait time
+ ldr r2, =OSCR
+ mov r3, #0
+ str r3, [r2]
+0:
+ ldr r3, [r2]
+ cmp r3, \time
+ bls 0b
+.endm
+
+/*
+ * Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Set up GPIO pins first ----------------------------------------- */
+ mov r10, lr
+
+ /* Configure GPIO Pins 41 - 48 as UART1 / altern. Fkt. 2 */
+ ldr r0, =0x40E10438 @ GPIO41 FFRXD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E1043C @ GPIO42 FFTXD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10440 @ GPIO43 FFCTS
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10444 @ GPIO 44 FFDCD
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10448 @ GPIO 45 FFDSR
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E1044C @ GPIO 46 FFRI
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10450 @ GPIO 47 FFDTR
+ ldr r1, =0x802
+ str r1, [r0]
+
+ ldr r0, =0x40E10454 @ GPIO 48
+ ldr r1, =0x802
+ str r1, [r0]
+
+ /* tebrandt - ASCR, clear the RDH bit */
+ ldr r0, =ASCR
+ ldr r1, [r0]
+ bic r1, r1, #0x80000000
+ str r1, [r0]
+
+ /* ---------------------------------------------------------------- */
+ /* Enable memory interface */
+ /* */
+ /* The sequence below is based on the recommended init steps */
+ /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+ /* Chapter 10. */
+ /* ---------------------------------------------------------------- */
+
+ /* ---------------------------------------------------------------- */
+ /* Step 1: Wait for at least 200 microsedonds to allow internal */
+ /* clocks to settle. Only necessary after hard reset... */
+ /* FIXME: can be optimized later */
+ /* ---------------------------------------------------------------- */
+
+ /* mk: replaced with wait macro */
+/* ldr r3, =OSCR /\* reset the OS Timer Count to zero *\/ */
+/* mov r2, #0 */
+/* str r2, [r3] */
+/* ldr r4, =0x300 /\* really 0x2E1 is about 200usec, *\/ */
+/* /\* so 0x300 should be plenty *\/ */
+/* 1: */
+/* ldr r2, [r3] */
+/* cmp r4, r2 */
+/* bgt 1b */
+ wait #300
+
+mem_init:
+
+ /* configure the MEMCLKCFG register */
+ ldr r1, =MEMCLKCFG
+ ldr r2, =0x00010001
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[0] to data flash SRAM mode */
+ ldr r1, =CSADRCFG0
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[1] to data flash SRAM mode */
+ ldr r1, =CSADRCFG1
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 0 register for SRAM memory */
+ ldr r1, =MSC0
+ ldr r2, =0x11191119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[2] to data flash SRAM mode */
+ ldr r1, =CSADRCFG2
+ ldr r2, =0x00320809
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set CSADRCFG[3] to VLIO mode */
+ ldr r1, =CSADRCFG3
+ ldr r2, =0x0032080B
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+ /* set MSC 1 register for VLIO memory */
+ ldr r1, =MSC1
+ ldr r2, =0x123C1119
+ str r2, [r1] @ WRITE
+ ldr r2, [r1] @ DELAY UNTIL WRITTEN
+
+#if 0
+ /* This does not work in Zylonite. -SC */
+ ldr r0, =0x15fffff0
+ ldr r1, =0xb10b
+ str r1, [r0]
+ str r1, [r0, #4]
+#endif
+
+ /* Configure ACCR Register */
+ ldr r0, =ACCR @ ACCR
+ ldr r1, =0x0180b108
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Configure MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, =0x403
+ str r1, [r0]
+ ldr r1, [r0]
+
+ /* Perform Resistive Compensation by configuring RCOMP register */
+ ldr r1, =RCOMP @ RCOMP
+ ldr r2, =0x000000ff
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS0 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0x60000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDMRS Register for SDCS1 */
+ ldr r1, =MDMRS @ MDMRS
+ ldr r2, =0xa0000023
+ ldr r3, [r1]
+ orr r2, r2, r3
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure MDREFR */
+ ldr r1, =MDREFR @ MDREFR
+ ldr r2, =0x00000006
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Configure EMPI */
+ ldr r1, =EMPI @ EMPI
+ ldr r2, =0x80000000
+ str r2, [r1]
+ ldr r2, [r1]
+
+ /* Hardware DDR Read-Strobe Delay Calibration */
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+
+ /* Here we assume the hardware calibration alwasy be successful. -SC */
+ /* Set DMCEN bit in MDCNFG Register */
+ ldr r0, =MDCNFG @ MDCNFG
+ ldr r1, [r0]
+ orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access
+ str r1, [r0]
+
+ /* scrub/init SDRAM if enabled/present */
+/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
+/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */
+ ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */
+ ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */
+ mov r0, #0 /* scrub with 0x0000:0000 */
+ mov r1, #0
+ mov r2, #0
+ mov r3, #0
+ mov r4, #0
+ mov r5, #0
+ mov r6, #0
+ mov r7, #0
+10: /* fastScrubLoop */
+ subs r9, r9, #32 /* 32 bytes/line */
+ stmia r8!, {r0-r7}
+ beq 15f
+ b 10b
+
+15:
+ /* Mask all interrupts */
+ mov r1, #0
+ mcr p6, 0, r1, c1, c0, 0 @ ICMR
+
+ /* Disable software and data breakpoints */
+ mov r0, #0
+ mcr p15,0,r0,c14,c8,0 /* ibcr0 */
+ mcr p15,0,r0,c14,c9,0 /* ibcr1 */
+ mcr p15,0,r0,c14,c4,0 /* dbcon */
+
+ /* Enable all debug functionality */
+ mov r0,#0x80000000
+ mcr p14,0,r0,c10,c0,0 /* dcsr */
+
+ /* We are finished with Intel's memory controller initialisation */
+
+ /* ---------------------------------------------------------------- */
+ /* End lowlevel_init */
+ /* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+ mov pc, lr
+
+/*
+@********************************************************************************
+@ DDR calibration
+@
+@ This function is used to calibrate DQS delay lines.
+@ Monahans supports three ways to do it. One is software
+@ calibration. Two is hardware calibration. Three is hybrid
+@ calibration.
+@
+@ TBD
+@ -SC
+ddr_calibration:
+
+ @ Case 1: Write the correct delay value once
+ @ Configure DDR_SCAL Register
+ ldr r0, =DDR_SCAL @ DDR_SCAL
+q ldr r1, =0xaf2f2f2f
+ str r1, [r0]
+ ldr r1, [r0]
+*/
+/* @ Case 2: Software Calibration
+ @ Write test pattern to memory
+ ldr r5, =0x0faf0faf @ Data Pattern
+ ldr r4, =0xa0000000 @ DDR ram
+ str r5, [r4]
+
+ mov r1, =0x0 @ delay count
+ mov r6, =0x0
+ mov r7, =0x0
+ddr_loop1:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ bne ddr_loop1
+ mov r6, r1
+ddr_loop2:
+ add r1, r1, =0x1
+ cmp r1, =0xf
+ ble end_loop
+ mov r3, r1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+ str r3, [r2]
+
+ ldr r2, [r4]
+ cmp r2, r5
+ be ddr_loop2
+ mov r7, r2
+
+ add r3, r6, r7
+ lsr r3, r3, =0x1
+ mov r0, r1, lsl #30
+ orr r3, r3, r0
+ mov r0, r1, lsl #22
+ orr r3, r3, r0
+ mov r0, r1, lsl #14
+ orr r3, r3, r0
+ orr r3, r3, =0x80000000
+ ldr r2, =DDR_SCAL
+
+end_loop:
+
+ @ Case 3: Hardware Calibratoin
+ ldr r0, =DDR_HCAL @ DDR_HCAL
+ ldr r1, =0x803ffc07 @ the offset is correct? -SC
+ str r1, [r0]
+ wait #5
+ ldr r1, [r0]
+ mov pc, lr
+*/
diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds
new file mode 100644
index 0000000..f010239
--- /dev/null
+++ b/board/zylonite/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/pxa/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c
new file mode 100644
index 0000000..e618ab9
--- /dev/null
+++ b/board/zylonite/zylonite.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of Lubbock-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setenv("stdout", "serial");
+ setenv("stderr", "serial");
+ return 0;
+}
+
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+ return 0;
+}
generated by cgit v1.1 at 2024-12-22 15:58:40 +0000