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-rw-r--r--board/amcc/common/flash.c10
-rw-r--r--board/amcc/taihu/flash.c10
-rw-r--r--board/amcc/yucca/flash.c10
-rw-r--r--board/esd/common/xilinx_jtag/micro.c2
-rw-r--r--board/esd/dasa_sim/flash.c3
-rw-r--r--board/renesas/ecovec/Makefile38
-rw-r--r--board/renesas/ecovec/ecovec.c124
-rw-r--r--board/renesas/ecovec/lowlevel_init.S211
-rw-r--r--board/renesas/sh7757lcr/lowlevel_init.S3
9 files changed, 381 insertions, 30 deletions
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index 8f23375..1960fc1 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -396,7 +396,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -427,8 +427,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -454,7 +452,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -825,7 +822,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -856,8 +853,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -883,7 +878,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
index e9fbbb1..63968a4 100644
--- a/board/amcc/taihu/flash.c
+++ b/board/amcc/taihu/flash.c
@@ -511,7 +511,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -542,8 +542,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -569,7 +567,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -953,7 +950,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -984,8 +981,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
printf("\n");
}
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -1011,7 +1006,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index 20b6af9..ab513f9 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -422,7 +422,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -449,8 +449,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -476,7 +474,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
@@ -831,7 +828,7 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
- int flag, prot, sect, l_sect;
+ int flag, prot, sect;
int i;
if ((s_first < 0) || (s_first > s_last)) {
@@ -858,8 +855,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
printf("\n");
- l_sect = -1;
-
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
@@ -885,7 +880,6 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
}
- l_sect = sect;
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c
index 9823e5e..cba33b8 100644
--- a/board/esd/common/xilinx_jtag/micro.c
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -1831,7 +1831,6 @@ int xsvfExecute(void)
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int iErrorCode;
- char* pzXsvfFileName;
unsigned long duration;
unsigned long long startClock, endClock;
@@ -1847,7 +1846,6 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE );
- pzXsvfFileName = 0;
xsvf_iDebugLevel = 0;
printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION);
diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c
index d6a7737..e2f2aac 100644
--- a/board/esd/dasa_sim/flash.c
+++ b/board/esd/dasa_sim/flash.c
@@ -44,7 +44,6 @@ unsigned long flash_init (void)
{
unsigned long size_b0;
int i;
- unsigned long base_b0;
/* Init: no FLASHes known */
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
@@ -63,8 +62,6 @@ unsigned long flash_init (void)
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
- base_b0 = -size_b0;
-
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-monitor_flash_len,
diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile
new file mode 100644
index 0000000..8fdc0c9
--- /dev/null
+++ b/board/renesas/ecovec/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := ecovec.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(obj).depend $(COBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
new file mode 100644
index 0000000..275b0ba
--- /dev/null
+++ b/board/renesas/ecovec/ecovec.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2009, 2011 Renesas Solutions Corp.
+ * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <netdev.h>
+
+/* USB power management register */
+#define UPONCR0 0xA40501D4
+
+int checkboard(void)
+{
+ puts("BOARD: ecovec\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ return 0;
+}
+
+static void debug_led(u8 led)
+{
+ /* PDGR[0-4] is debug LED */
+ outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
+}
+
+int board_late_init(void)
+{
+ u8 mac[6];
+ char env_mac[17];
+ int i;
+
+ udelay(1000);
+
+ /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
+ outw(inw(PLCR) & ~0xFFF0, PLCR);
+ outw(inw(PNCR) & ~0x000F, PNCR);
+ outw(inw(PXCR) & ~0x0FC0, PXCR);
+ outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
+ outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
+ outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
+
+ debug_led(1 << 3);
+
+ outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
+
+ /* Read MAC address */
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ /* Set MAC address */
+ sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ setenv("ethaddr", env_mac);
+
+ debug_led(0x0F);
+
+ return 0;
+}
+
+int board_init(void)
+{
+
+ /* LED (PTG) */
+ outw((inw(PGCR) & ~0xFF) | 0x66, PGCR);
+ outw((inw(HIZCRA) & ~0x02), HIZCRA);
+
+ debug_led(1 << 0);
+
+ /* SCIF0 (PTF, PTM) */
+ outw(inw(PFCR) & ~0x30, PFCR);
+ outw(inw(PMCR) & ~0x0C, PMCR);
+ outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
+
+ debug_led(1 << 1);
+
+ /* RMII (PTA) */
+ outw((inw(PACR) & ~0x0C) | 0x04, PACR);
+ outb((inb(PADR) & ~0x02) | 0x02, PADR);
+
+ debug_led(1 << 2);
+
+ /* USB host */
+ outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
+ outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
+ outl(inl(MSTPCR2) & 0x100000, MSTPCR2);
+ outw(0x0600, UPONCR0);
+
+ debug_led(1 << 3);
+
+ /* debug switch */
+ outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
+
+ return 0;
+}
diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S
new file mode 100644
index 0000000..9fc63e0
--- /dev/null
+++ b/board/renesas/ecovec/lowlevel_init.S
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
+ *
+ * board/renesas/ecovec/lowlevel_init.S
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+#include <configs/ecovec.h>
+
+ .global lowlevel_init
+
+ .text
+ .align 2
+
+lowlevel_init:
+
+ /* jump to 0xA0020000 if bit 1 of PVDR_A */
+ mov.l PVDR_A, r1
+ mov.l PVDR_D, r2
+ mov.b @r1, r0
+ tst r0, r2
+ bt 1f
+ mov.l JUMP_A, r1
+ jmp @r1
+ nop
+
+1:
+ /* Disable watchdog */
+ write16 RWTCSR_A, RWTCSR_D
+
+ /* MMU Disable */
+ write32 MMUCR_A, MMUCR_D
+
+ /* Setup clocks */
+ write32 PLLCR_A, PLLCR_D
+ write32 FRQCRA_A, FRQCRA_D
+ write32 FRQCRB_A, FRQCRB_D
+
+ wait_timer TIMER_D
+
+ write32 MMSELR_A, MMSELR_D
+
+ /* Srtup BSC */
+ write32 CMNCR_A, CMNCR_D
+ write32 CS0BCR_A, CS0BCR_D
+ write32 CS0WCR_A, CS0WCR_D
+
+ wait_timer TIMER_D
+
+ /* Setup SDRAM */
+ write32 DBPDCNT0_A, DBPDCNT0_D0
+ write32 DBCONF_A, DBCONF_D
+ write32 DBTR0_A, DBTR0_D
+ write32 DBTR1_A, DBTR1_D
+ write32 DBTR2_A, DBTR2_D
+ write32 DBTR3_A, DBTR3_D
+ write32 DBKIND_A, DBKIND_D
+ write32 DBCKECNT_A, DBCKECNT_D
+
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D0
+ write32 DBMRCNT_A, DBMRCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D2
+ write32 DBMRCNT_A, DBMRCNT_D3
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBMRCNT_A, DBMRCNT_D4
+ write32 DBMRCNT_A, DBMRCNT_D5
+ write32 DBMRCNT_A, DBMRCNT_D6
+
+ wait_timer TIMER_D
+
+ write32 DBEN_A, DBEN_D
+ write32 DBRFPDN1_A, DBRFPDN1_D
+ write32 DBRFPDN2_A, DBRFPDN2_D
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+
+
+ /* Dummy read */
+ mov.l DUMMY_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+
+ mov.l SDRAM_A ,r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ add #4, r1
+ synco
+ mov.l @r1, r0
+ synco
+ wait_timer TIMER_D
+
+ write32 DBCMDCNT_A, DBCMDCNT_D0
+ write32 DBCMDCNT_A, DBCMDCNT_D1
+ write32 DBPDCNT0_A, DBPDCNT0_D1
+ write32 DBRFPDN0_A, DBRFPDN0_D
+
+ wait_timer TIMER_D
+
+ write32 CCR_A, CCR_D
+
+ stc sr, r0
+ mov.l SR_MASK_D, r1
+ and r1, r0
+ ldc r0, sr
+
+ rts
+
+ .align 2
+
+PVDR_A: .long PVDR
+PVDR_D: .long 0x00000001
+JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
+TIMER_D: .long 64
+RWTCSR_A: .long RWTCSR
+RWTCSR_D: .long 0x0000A507
+MMUCR_A: .long MMUCR
+MMUCR_D: .long 0x00000004
+PLLCR_A: .long PLLCR
+PLLCR_D: .long 0x00004000
+FRQCRA_A: .long FRQCRA
+FRQCRA_D: .long 0x8E003508
+FRQCRB_A: .long FRQCRB
+FRQCRB_D: .long 0x0
+MMSELR_A: .long MMSELR
+MMSELR_D: .long 0xA5A50000
+CMNCR_A: .long CMNCR
+CMNCR_D: .long 0x00000013
+CS0BCR_A: .long CS0BCR
+CS0BCR_D: .long 0x11110400
+CS0WCR_A: .long CS0WCR
+CS0WCR_D: .long 0x00000440
+DBPDCNT0_A: .long DBPDCNT0
+DBPDCNT0_D0: .long 0x00000181
+DBPDCNT0_D1: .long 0x00000080
+DBCONF_A: .long DBCONF
+DBCONF_D: .long 0x015B0002
+DBTR0_A: .long DBTR0
+DBTR0_D: .long 0x03061502
+DBTR1_A: .long DBTR1
+DBTR1_D: .long 0x02020102
+DBTR2_A: .long DBTR2
+DBTR2_D: .long 0x01090305
+DBTR3_A: .long DBTR3
+DBTR3_D: .long 0x00000002
+DBKIND_A: .long DBKIND
+DBKIND_D: .long 0x00000005
+DBCKECNT_A: .long DBCKECNT
+DBCKECNT_D: .long 0x00000001
+DBCMDCNT_A: .long DBCMDCNT
+DBCMDCNT_D0:.long 0x2
+DBCMDCNT_D1:.long 0x4
+DBMRCNT_A: .long DBMRCNT
+DBMRCNT_D0: .long 0x00020000
+DBMRCNT_D1: .long 0x00030000
+DBMRCNT_D2: .long 0x00010040
+DBMRCNT_D3: .long 0x00000532
+DBMRCNT_D4: .long 0x00000432
+DBMRCNT_D5: .long 0x000103C0
+DBMRCNT_D6: .long 0x00010040
+DBEN_A: .long DBEN
+DBEN_D: .long 0x01
+DBRFPDN0_A: .long DBRFPDN0
+DBRFPDN1_A: .long DBRFPDN1
+DBRFPDN2_A: .long DBRFPDN2
+DBRFPDN0_D: .long 0x00010000
+DBRFPDN1_D: .long 0x00000613
+DBRFPDN2_D: .long 0x238C003A
+SDRAM_A: .long 0xa8000000
+DUMMY_A: .long 0x0c400000
+CCR_A: .long CCR
+CCR_D: .long 0x0000090B
+SR_MASK_D: .long 0xEFFFFF0F
diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S
index ab1aa49..5090fd0 100644
--- a/board/renesas/sh7757lcr/lowlevel_init.S
+++ b/board/renesas/sh7757lcr/lowlevel_init.S
@@ -326,12 +326,13 @@ PC_MASK: .long 0x20000000
/* step 26 */
wait_DBCMD
+#if defined(CONFIG_SH7757LCR_DDR_ECC)
/* enable DDR-ECC */
write32 ECD_ECDEN_A, ECD_ECDEN_D
write32 ECD_INTSR_A, ECD_INTSR_D
write32 ECD_SPACER_A, ECD_SPACER_D
write32 ECD_MCR_A, ECD_MCR_D
-
+#endif
bra exit_ddr
nop
generated by cgit v1.1 at 2024-12-27 17:02:58 +0000